Semiconductor device

Abstract

To provide a semiconductor device that can easily extract carriers through a contact portion at the end of an active region and improve a withstand voltage.SOLUTION: A semiconductor device having an active region 101 and a voltage-withstanding region 102 provided outside the active region 101, includes a first conductivity type semiconductor layer 12 provided across the active region 101 and the voltage-withstanding region 102, a second conductivity type semiconductor region 18 provided on an upper surface of the semiconductor layer 12 at an end 103 of the active region 101 on the voltage-withstanding region 102 side, and a contact portion 5 provided on the upper surface of the semiconductor region 18, and the contact portion 5 includes a first stripe portion 51a extending in a first direction along the end 103 of the active region 101 on the voltage-withstanding region 102 side, and a plurality of first connection portions 52a connected to the first stripe portion 51a and spaced apart from each other in the first direction.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent document 1 discloses a configuration in which an active termination portion is provided within an active region and is in contact with a voltage-resistant region, and a second p-type region and multiple trench contact portions are provided in the active termination portion, a configuration in which a conductor embedded in the trench contact portion is formed integrally with a source electrode, and a configuration in which a plug metal is embedded in the trench contact portion via a barrier metal layer.

[0003] In Patent Document 2, an outer region is provided between an element forming region and a voltage-resistance holding region, and the outer region is provided with p + A structure in which a type termination region is provided and a third contact recess for an emitter lead-out portion is formed, and a p + p + The disclosed configuration has a contact region, and the emitter routing portion recovers avalanche current generated in a region outside the element formation region, and the recovered avalanche current is taken out from the emitter pad via the emitter connection portion.

[0004] In Patent Document 3, the fourth doping region is 2×10 13 cm -3 ~5×10 13 cm -3 The sixth doping region is formed with an impurity concentration of 1×10 15 cm -3 ~5×10 15 cm -3 The structure disclosed has an impurity concentration of 0.5 μm to 1.5 μm in depth. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2020-170807 A [Patent Document 2] JP 2018-120990 A [Patent Document 3] Special Publication No. 2019-521529 Summary of the Invention [Problem to be solved by the invention]

[0006] As described in Patent Documents 1 and 2, in a configuration in which carriers are extracted by a contact portion provided at the end of the active region in contact with the voltage-resistant region, current concentration occurs outside the contact portion, making it difficult to improve the withstand voltage.

[0007] An object of the present disclosure is to provide a semiconductor device that can facilitate the extraction of carriers by contact portions at the ends of active regions and improve the withstand voltage. [Means for solving the problem]

[0008] In order to achieve the above-mentioned object, one aspect of the present disclosure is a semiconductor device having an active region and a voltage-withstanding region provided outside the active region, the semiconductor device comprising: a first conductivity type semiconductor layer provided across the active region and the voltage-withstanding region; a second conductivity type semiconductor region provided on an upper surface side of the semiconductor layer at an end of the active region on the voltage-withstanding region side; and a contact portion provided on the upper surface side of the semiconductor region, the contact portion comprising: a first stripe portion extending in a first direction along the end of the active region on the voltage-withstanding region side in a plan view; and a plurality of first connection portions connected to the first stripe portion and spaced apart from each other in the first direction. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a semiconductor device that can facilitate the extraction of carriers by contact portions at the ends of the active region and improve the withstand capability. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is an enlarged plan view of the semiconductor device according to the first embodiment of the present invention in which a region A in FIG. [Diagram 3] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line AA' in FIG. 2. [Figure 4] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line BB' in FIG. 2. [Diagram 5] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line CC' in FIG. 2. [Figure 6] 3 is an enlarged plan view of the semiconductor device according to the first embodiment of the present invention, showing a region D in FIG. 2. [Figure 7] 7 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line AA' in FIG. 6. [Figure 8] 7 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line BB' in FIG. 6. [Figure 9] FIG. 2 is a plan view of a portion of a semiconductor device according to a first comparative example. [Figure 10] 10 is a perspective view of a semiconductor device according to a first comparative example corresponding to FIG. 9. FIG. [Figure 11] FIG. 11 is a plan view of a portion of a semiconductor device according to a second comparative example. [Figure 12] 12 is a perspective view of a semiconductor device according to a second comparative example corresponding to FIG. 11. FIG. [Figure 13] FIG. 7 is a perspective view of the semiconductor device according to the first embodiment, corresponding to FIG. 6. [Figure 14] FIG. 11 is a plan view of a portion of a semiconductor device according to a second embodiment. [Figure 15] 15 is a cross-sectional view of the semiconductor device according to the second embodiment taken along the line AA′ in FIG. [Figure 16] FIG. 11 is a plan view of a portion of a semiconductor device according to a third embodiment. [Figure 17] 17 is a cross-sectional view of the semiconductor device according to the third embodiment taken along the line AA′ in FIG. 16 [Figure 18] FIG. 13 is a plan view of a portion of a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 13 is a plan view of a portion of a semiconductor device according to a fifth embodiment. [Figure 20] 20 is an enlarged plan view of the semiconductor device according to the fifth embodiment of the present invention, showing a region A in FIG. 19. [Figure 21] 21 is a cross-sectional view of the semiconductor device according to the fifth embodiment taken along the line AA' in FIG. 20. [Figure 22] FIG. 13 is a plan view of a portion of a semiconductor device according to a sixth embodiment. [Diagram 23] FIG. 13 is a cross-sectional view of a portion of a semiconductor device according to a seventh embodiment. [Figure 24] 13 is a cross-sectional view of another portion of the semiconductor device according to the seventh embodiment. FIG. [Diagram 25] FIG. 13 is a cross-sectional view of a portion of a semiconductor device according to an eighth embodiment. [Figure 26A] 1 is a graph showing reverse recovery characteristics of a diode. [Figure 26B] 13 is a graph showing the relationship between the dose in the contact region and the rate of change of the reverse recovery current in the semiconductor device according to the ninth embodiment. [Figure 27] FIG. 23 is a plan view of a portion of the semiconductor device according to the tenth embodiment. [Figure 28] 28 is a cross-sectional view taken along the line AA' in FIG. 27. [Figure 29] 28 is a cross-sectional view taken along line BB' in FIG. 27. [Figure 30A] 28 is a cross-sectional view taken along line CC' in FIG. 27. [Figure 30B] 28 is a cross-sectional view taken along the line DD' in FIG. 27. [Diagram 31] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to an eleventh embodiment. [Diagram 32] FIG. 23 is a cross-sectional view of another portion of the semiconductor device according to the eleventh embodiment. [Diagram 33] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to a twelfth embodiment. [Diagram 34] FIG. 23 is a cross-sectional view of another portion of the semiconductor device according to the twelfth embodiment. [Diagram 35] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to a thirteenth embodiment. [Diagram 36] FIG. 23 is a cross-sectional view of another portion of the semiconductor device according to the thirteenth embodiment. [Figure 37] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to a fourteenth embodiment. [Figure 38] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to a fifteenth embodiment. [Figure 39] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to a sixteenth embodiment. [Diagram 40] FIG. 23 is a cross-sectional view of a portion of a semiconductor device according to a seventeenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the first to seventeenth embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are given the same or similar symbols. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0012] In the following description, the "first main electrode region" and the "second main electrode region" are main electrode regions of a semiconductor element into which a main current flows in or out. The "first main electrode region" means a semiconductor region that becomes either a source region or a drain region in the case of a field effect transistor (FET) or a static induction transistor (SIT). The "first main electrode region" means a semiconductor region that becomes either an emitter region or a collector region in the case of an insulated gate bipolar transistor (IGBT). The "second main electrode region" means a semiconductor region that becomes either an anode region or a cathode region in the case of a static induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO). The "second main electrode region" means a semiconductor region that becomes either a source region or a drain region that is not the first main electrode region in the case of a FET or a SIT. The "second main electrode region" means a region that becomes either an emitter region or a collector region that is not the first main electrode region in the case of an IGBT. The "second main electrode region" means a region that becomes either an anode region or a cathode region that is not the first main electrode region in the case of an SI thyristor or a GTO. That is, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. Note that when the term "main electrode region" is simply used, it comprehensively means either the first main electrode region or the second main electrode region, whichever is technically and contextually appropriate.

[0013] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical ideas of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are of course read as reversed up and down. In addition, the "top surface" may be read as the "front surface" and the "bottom surface" may be read as the "reverse surface."

[0014] In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the semiconductor regions have the same "n" and "n" attached, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0015] (First embodiment) Fig. 1 is a plan view of the semiconductor device according to the first embodiment. As shown in Fig. 1, the semiconductor device according to the first embodiment has a substantially rectangular planar shape. The semiconductor device according to the first embodiment includes an active region 101 provided inside the semiconductor device according to the first embodiment, and a voltage-resistant region (termination region) 102 provided outside the active region 101 so as to surround the periphery of the active region 101.

[0016] The active region 101 has a substantially rectangular planar shape. The active region 101 includes an active element (switching element), and is a region through which a main current flows when the active element is turned on. The active element may be, for example, a vertical switching element. In the semiconductor device according to the first embodiment, the active element included in the active region 101 is illustrated as a MOSFET having a planar gate structure. A surface electrode (source electrode) 3 is provided in the active region 101.

[0017] The voltage-resistant region 102 has an annular (frame-shaped) planar shape so as to surround the periphery of the active region 101. The voltage-resistant region 102 is a region that relieves the electric field and maintains the voltage resistance.

[0018] A gate pad 1 is provided in a portion between the active region 101 and the voltage withstand region 102. The gate pad 1 has a substantially rectangular planar shape. A wiring layer (gate runner 2) is electrically connected to the gate pad 1. The gate runner 2 is provided in the voltage withstand region 102 so as to surround the periphery of the active region 101. The gate pad 1 is electrically connected to a gate electrode of an active element in the active region 101 via the gate runner 2.

[0019] 2 is an enlarged plan view of a region A including corners of a rectangle formed by a planar shape of the semiconductor device according to the first embodiment of FIG. 1. As shown in FIG. 2, an active region 101 includes gate electrodes 31a-31d of MOSFETs as active elements and contact portions (plug portions) 61a-61c sandwiched between the gate electrodes 31a-31d. In the semiconductor device according to the first embodiment, the contact portions 61a-61c are trench contact portions at least partially embedded in trenches provided on the upper surface side of the semiconductor device according to the first embodiment. The gate electrodes 31a-31d and the trench contact portions 61a-61c have linear (striped) planar shapes extending parallel to each other in one direction (the vertical direction in FIG. 2). Here, in a planar view of the semiconductor device of the first embodiment, the extension direction of the gate electrodes 31a to 31d and the trench contact portions 61a to 61c (the up-down direction in FIG. 2) is defined as the "first direction", and the direction perpendicular to the extension direction of the gate electrodes 31a to 31d and the trench contact portions 61a to 61c (the left-right direction in FIG. 2) is defined as the "second direction".

[0020] A contact portion (plug portion) 5 is provided at an end portion (active termination portion) 103 of the active region 101 on the voltage-resistant region 102 side. In the semiconductor device according to the first embodiment, the contact portion 5 is a trench contact portion at least partially embedded in a trench provided on the upper surface side of the semiconductor device according to the first embodiment. The active termination portion 103 is provided inside the source electrode 3 in a plan view. In FIG. 2, the gate electrodes 31a to 31d, trench contact portions 61a to 61c, and trench contact portion 5 hidden on the lower surface side of the source electrode 3 are diagrammatically shown by dashed lines.

[0021] 2 is shown in FIG 3, a cross section along line BB' in FIG 2 is shown in FIG 4, and a cross section along line CC' in FIG 2 is shown in FIG 5. As shown in FIG 3 to FIG 5, the semiconductor device according to the first embodiment has a first conductivity type (n + A main electrode region (drain region) 11 of n-type (type) is provided on the upper surface side of the drain region 11 and has a lower impurity concentration than the drain region 11. - The semiconductor layer (drift layer) 12 is a semiconductor layer having a thickness of 100 nm.

[0022] The drain region 11 is made of a semiconductor substrate such as a silicon (Si) substrate. The semiconductor substrate constituting the drain region 11 is not limited to a Si substrate, and may be, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 The semiconductor substrate may be made of a wide band gap semiconductor such as SiO2 (C), diamond (C) or aluminum nitride (AlN).

[0023] The drift layer 12 is composed of an epitaxially grown layer made of Si. The drift layer 12 is composed of an n-type semiconductor substrate, and n is introduced into the back surface of the semiconductor substrate by ion implantation or thermal diffusion. + A drain region 11 of the type may be formed.

[0024] In the active region 101, second conductive type (p-type) semiconductor regions (base regions) 13a and 13b are provided on the upper surface side of the drift layer 12 in contact with the drift layer 12. A parasitic diode is formed by the base regions 13a and 13b and the drift layer 12. A n-type semiconductor region (base region) 13a is provided on the upper surface side of the base region 13a in contact with the base region 13a. + The n-type main electrode regions (source regions) 14a and 14b are provided on the upper surface side of the base region 13b. + A source region 14c is provided.

[0025] A gate electrode 31a is provided on the upper surface side of the drift layer 12 and the base region 13a with a gate insulating film 71a interposed therebetween. The gate insulating film 71a and the gate electrode 31a form an insulated gate electrode structure (31a, 71a). A gate electrode 31b is provided on the upper surface side of the drift layer 12 and the base region 13b with a gate insulating film 71b interposed therebetween. The gate insulating film 71b and the gate electrode 31b form an insulated gate electrode structure (31b, 71b).

[0026] The gate insulating films 71a and 71b are, for example, silicon dioxide films (SiO 2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si 3 N 4 ) film, aluminum oxide (Al 2 O 3 ) film, magnesium oxide (MgO) film, yttrium oxide (Y 2 O 3 ) film, hafnium oxide (HfO 2 ) film, zirconium oxide (ZrO 2 ) film, tantalum oxide (Ta 2 O 5 ) film, bismuth oxide (Bi 2 O 3 ) membrane or a composite membrane in which a plurality of these membranes are laminated can be used.

[0027] The gate electrodes 31a and 31b may be made of a polysilicon film (doped polysilicon film) doped with a high concentration of n-type impurities such as phosphorus (P) or arsenic (As) or p-type impurities such as boron (B).

[0028] An interlayer insulating film 73 is provided on the upper surfaces of the drift layer 12 and the insulated gate electrode structures (31a, 71a), (31b, 71b). The interlayer insulating film 73 is, for example, a non-doped silicon oxide film (SiO 2 film), high temperature oxide film (HTO film), silicon nitride film (Si 3 N 4It is composed of single layer films such as silicon oxide film doped with boron (PSG film), silicon oxide film doped with phosphorus (BSG film), silicon oxide film doped with boron and phosphorus (BPSG film), or laminated films of these.

[0029] The interlayer insulating film 73 is provided with a contact hole penetrating the interlayer insulating film 73. The epitaxial growth layer constituting the drift layer 12 is provided with trenches (contact trenches) 20a, 20b so as to continue to the contact hole of the interlayer insulating film 73. The contact trenches 20a, 20b are provided in the depth direction, which is the direction perpendicular to the upper surface of the epitaxial growth layer constituting the drift layer 12.

[0030] The left side surface of the contact trench 20a is in contact with the source region 14a, and the right side surface of the contact trench 20a is in contact with the source region 14b. + A p-type contact region 16a is provided. The contact region 16a is in contact with the base region 13a. The impurity concentration of the contact region 16a is higher than the impurity concentration of the base region 13a. The left side surface of the contact trench 20b is in contact with the source region 14c. A p-type contact region 16a is provided at the bottom of the contact trench 20b in contact with the contact trench 20b. + A contact region 16b is provided in the base region 13b. The contact region 16b is in contact with the base region 13b. The impurity concentration of the contact region 16b is higher than the impurity concentration of the base region 13b.

[0031] At least a part of trench contact parts (plug parts) 61a, 61b is buried in the contact trenches 20a, 20b. The trench contact parts 61a, 61b have a barrier metal film provided in contact with the contact trenches 20a, 20b, and a contact plug buried inside the contact trenches 20a, 20b via the barrier metal film. For example, a single layer film of titanium (Ti) or titanium nitride (TiN), or a laminated film of Ti and TiN, can be used as the barrier metal film. For the contact plug, a metal made of a high melting point metal such as tungsten (W) can be used.

[0032] A source electrode 3 is provided on the interlayer insulating film 73. The source electrode 3 can be made of metal such as aluminum (Al), an Al alloy, or copper (Cu). Examples of the Al alloy include Al-silicon (Si), Al-Si-copper (Cu), and Al-Cu. The source electrode 3 is electrically connected to the source regions 14a to 14c and the contact regions 16a and 16b via trench contact portions 61a and 61b.

[0033] A back electrode (drain electrode) 6 is provided on the lower surface of the drain region 11. The drain electrode 6 can be composed of, for example, a single layer film made of gold (Au) or a metal film laminated in this order of titanium (Ti), nickel (Ni), and gold (Au).

[0034] During operation of the MOSFET, which is an active element included in the active region 101 of the semiconductor device according to the first embodiment, when the source electrode 3 is at ground potential, a positive voltage is applied to the drain electrode 6, and a positive voltage equal to or greater than a threshold is applied to the gate electrodes 31a and 31b, an inversion layer (channel) is formed in the base regions 13a and 13b, and the MOSFET is turned on. In the on state, a current flows from the drain electrode 6 to the source electrode 3 via the drain region 11, the drift layer 12, the inversion layers in the base regions 13a and 13b, and the source regions 14a to 14c. On the other hand, when the voltage applied to the gate electrodes 31a and 31b is less than the threshold, no inversion layer is formed in the base regions 13a and 13b, so that the MOSFET is turned off and no current flows from the drain electrode 6 to the source electrode 3.

[0035] In the active termination portion 103 provided at the end of the active region 101 on the side of the breakdown voltage region 102, a p-type semiconductor region (well region) 18 is provided on the upper surface side of the drift layer 12, separated from the base region 13a of the active region 101. The well region 18 is formed in the same process as the base regions 13a, 13b of the active region 101. The depth of the well region 18 is approximately the same as the depth of the base regions 13a, 13b of the active region 101, and is, for example, about 1 μm or more and 2 μm or less.

[0036] Trenches (contact trenches) 21a to 21c are provided in the upper part of the well region 18. The contact trenches 21a to 21c are formed in the same process as the contact trenches 20a, 20b in the active region 101. The depth of the contact trenches 21a to 21c is approximately the same as the depth of the contact trenches 20a, 20b in the active region 101, and is, for example, about 0.4 μm or more and 0.8 μm or less.

[0037] The side and bottom surfaces of the contact trenches 21a to 21c are provided with p +A contact region 17, which is a high-concentration, low-resistance region of the type, is provided on each of the active regions 101 and 102. The contact region 17 is in contact with a well region 18. The impurity concentration of the contact region 17 is higher than the impurity concentration of the well region 18. The contact region 17 is formed in the same process as the contact regions 16a and 16b of the active region 101. The impurity concentration of the contact region 17 is approximately the same as the impurity concentration of the contact regions 16a and 16b of the active region 101. The depth of the contact region 17 is approximately the same as the depth of the contact regions 16a and 16b of the active region 101.

[0038] At least a part of a trench contact portion (plug portion) 5 is buried in the contact trenches 21a to 21c. The trench contact portion 5 is formed in the same process as the trench contact portions 61a and 61b in the active region 101, and is made of the same material as the trench contact portions 61a and 61b in the active region 101. The trench contact portion 5 has a barrier metal film provided in contact with the contact trenches 21a to 21c, and a contact plug made of a high melting point metal such as W buried inside the contact trenches 21a to 21c with the barrier metal film interposed therebetween. The trench contact portion 5 is electrically connected to the source electrode 3.

[0039] Fig. 6 shows an enlarged plan view of region D including a part of trench contact portion 5 of active termination portion 103 in Fig. 2. Source electrode 3, interlayer insulating film 73, gate electrode 31a, and gate insulating film 71a are omitted in Fig. 6. Also, in Fig. 6, arrows 201 typically indicate the flow of carriers during switching operation of the semiconductor device according to the first embodiment. Fig. 7 shows a cross section taken along line AA' in Fig. 6, and Fig. 8 shows a cross section taken along line BB' in Fig. 6.

[0040] 6 to 8, the trench contact portion 5 has a lattice-like planar shape. The trench contact portion 5 includes a plurality of (three) stripe portions 51a to 51c extending linearly (in stripes) in a first direction (the vertical direction in FIG. 6), a plurality of connection portions 52a provided between the stripe portions 51a and 51b and spaced apart from each other in the first direction, and a plurality of connection portions 52b provided between the stripe portions 51b and 51c and spaced apart from each other in the first direction.

[0041] The stripe portions 51a to 51c are embedded in the contact trenches 21a to 21c, respectively. The widths W1 to W3 of the stripe portions 51a to 51c in the second direction (the left-right direction in FIG. 6) are, for example, about 0.3 μm or more and 1 μm or less. The widths W1 to W3 of the stripe portions 51a to 51c may be the same as each other or may be different from each other.

[0042] The multiple connection parts 52a are embedded in the contact trenches 22a. The multiple connection parts 52a have a substantially rectangular planar shape. One end of each of the multiple connection parts 52a in the second direction is connected to the stripe portion 51a, and the other end of each of the multiple connection parts 52a in the second direction is connected to the stripe portion 51b. The length L1 of each of the multiple connection parts 52a in the second direction is, for example, about 0.3 μm or more and 1 μm or less.

[0043] The multiple connection parts 52b are embedded in the contact trenches 22b. One end of each of the multiple connection parts 52b in the second direction is connected to the stripe portion 51b, and the other end of each of the multiple connection parts 52b in the second direction is connected to the stripe portion 51c. The length L2 of each of the multiple connection parts 52b in the second direction is, for example, about 0.3 μm or more and 1 μm or less. The length L2 of each of the multiple connection parts 52b in the second direction may be the same as or different from the length L1 of each of the multiple connection parts 52a in the second direction.

[0044] The multiple connection parts 52a and the multiple connection parts 52b are provided at the same pitch in the first direction. The width W4 of the multiple connection parts 52a and the multiple connection parts 52b in the first direction is, for example, about 0.3 μm or more and 1 μm or less. The width W4 of the multiple connection parts 52a and the multiple connection parts 52b in the first direction may be the same as the length L1 of the multiple connection parts 52a in the second direction or the length L2 of the multiple connection parts 52b in the second direction, and may be larger or smaller than the length L1 of the multiple connection parts 52a in the second direction or the length L2 of the multiple connection parts 52b in the second direction.

[0045] The interval S1 between the multiple connection parts 52a and the multiple connection parts 52b in the first direction is, for example, about 0.3 μm or more and 1 μm or less. The interval S1 between the multiple connection parts 52a and the multiple connection parts 52b in the first direction may be the same as the width W4 of the multiple connection parts 52a and the multiple connection parts 52b in the first direction, or may be larger or smaller than the width W4 of the multiple connection parts 52a and the multiple connection parts 52b in the first direction. The number of the multiple connection parts 52a and the multiple connection parts 52b is not particularly limited.

[0046] The lattice-like planar shape of the trench contact portion 5 can also be regarded as a planar shape in which multiple (three) stripe portions 51a to 51c extending linearly (striped) in the first direction intersect with multiple stripe portions extending linearly (striped) in the second direction, including multiple connection portions 52a and multiple connection portions 52b in a continuous manner.

[0047] As shown in FIG. 2, at the corners of the rectangle formed by the planar shape of the active region 101, the corners of the active region 101 have a curved shape, and the corners of the source electrode 3 also have a curved shape. The lengths of the stripes 51a-51c of the trench contact portion 5 of the active termination portion 103 change along the curved shape of the corners of the active region 101. The length in the first direction of the outermost stripe portion 51a is shorter than the length in the first direction of the stripe portion 51b located more inward than the stripe portion 51a. The length in the first direction of the stripe portion 51b is shorter than the length in the first direction of the stripe portion 51c located more inward than the stripe portion 51b.

[0048] The trench contact portion 5 of the active termination portion 103 further has a plurality of connection portions 53a-53d at the corners of the active region 101. One end in the second direction of the connection portions 53a-53c is connected to the stripe portion 51b. The length in the second direction of the connection portions 53a-53c changes along the curved shape of the corners of the active region 101. The length in the second direction of the connection portions 53a-53c becomes shorter toward the corners of the active region 101. One end in the second direction of the connection portion 53d is connected to the stripe portion 51c.

[0049] When the semiconductor device according to the first embodiment is turned off, the p-type well region 18 and the n-type - A depletion layer is formed at the pn junction with drift layer 12 of the semiconductor device, and carriers are accumulated in the depletion layer. When the semiconductor device according to the first embodiment is turned on, the carriers accumulated in the depletion layer flow from the withstand voltage region 102 side to the active region 101 side as shown by arrow 201 in FIG. 6 and are extracted to source electrode 3 via trench contact portion 5.

[0050] 3 to 5, in the voltage-resistant region 102, a p-type well region 18 is provided on the upper surface side of the drift layer 12, continuing from the active region 101. On the upper surface side of the drift layer 12, a p-type well region 18 having a lower impurity concentration than the well region 18 is provided so as to cover the outer lower surface and side surfaces of the well region 18. -A type semiconductor region (resurf region) 15 is provided. A gate runner 2 is provided on the upper surface side of the well region 18 and the resurf region 15 via a field insulating film 72 and an interlayer insulating film 73 made of a local oxide film (LOCOS film) or the like. - A type semiconductor region (channel stopper) 19 is provided on the upper surface side of the channel stopper 19. A field plate 32 made of polysilicon is provided on the upper surface side of the channel stopper 19 with an interlayer insulating film 73 interposed therebetween.

[0051] In the semiconductor device according to the first embodiment, the on-resistance (on-voltage) of the active element itself included in the active region 101 is reduced with improved design and processing accuracy due to miniaturization, etc., but the withstand voltage tends to decrease with an increase in current density. In order to improve the withstand voltage, when forming the contacts in the active region 101, the semiconductor layer is dug down to a region deeper than the source regions 14a to 14c to form contact trenches 20a, 20b, and trench contact parts (plug parts) 61a, 61b are embedded in the contact trenches 20a, 20b to form p-type base regions 13a, 13b and n-type - The parasitic transistor operation is suppressed by directly extracting carriers from the parasitic diode region formed by the drift layer 12 of the semiconductor substrate 10. At this time, a high melting point metal is filled in the contact trenches 20a and 20b and flattened so that the increase in resistance is small even with a small contact area.

[0052] Moreover, by forming the active element included in the active region 101 into a stripe-shaped cell (stripe cell) including the gate electrodes 31a, 31b each extending in a stripe shape, it is possible to improve uniformity within the cell and increase the figure of merit of breakdown voltage and on-resistance (on-voltage). When the active element included in the active region 101 is a stripe cell, it is common to form a contact parallel to the stripe cell in the active termination section 103, which is the end section of the active region 101 on the breakdown voltage region 102 side. In this case, it is preferable that the contact area of ​​the active termination section 103 is large in order to improve the extraction of current during switching, etc. Also, in order to improve the breakdown voltage, the semiconductor layer is dug down to form contact trenches 21a to 21c, 22a, 22b, and trench contact sections 5 are embedded in the contact trenches 21a to 21c, 22a, 22b, thereby forming a p-type well region 18 and a p-type well region 19. - Type RESURF region 15 and n - By this, carriers can be directly extracted from the parasitic diode region formed by the n-type drift layer 12 and the n-type drift layer 12, and the parasitic transistor operation can be suppressed.

[0053] <First Comparative Example> 9 is a plan view of a portion of a semiconductor device according to a first comparative example, and corresponds to the plan view of the semiconductor device according to the first embodiment shown in FIG. 6. As shown in FIG. 9, the semiconductor device according to the first comparative example is different from the semiconductor device according to the first embodiment shown in FIG. 6 in that the trench contact portion 5x is composed of only three stripe portions 51a-51c extending in a first direction (the vertical direction in FIG. 9). The stripe portions 51a-51c are embedded in the contact trenches 21a-21c. In the semiconductor device according to the first comparative example, the width of the contact trenches 21a-21c is narrowed because the contact trenches 21a-21c need to be embedded with a high melting point metal, and a structure in which a plurality of stripe-shaped contact trenches 21a-21c are arranged in order to increase the contact area is used.

[0054] Fig. 10 is a perspective view of a semiconductor device according to a first comparative example corresponding to Fig. 9. In Fig. 10, the stripe portions 51a-51c embedded in the contact trenches 21a-21c are not shown, and the side and bottom surfaces of the contact trenches 21a-21c are exposed. In Fig. 10, the portions of the contact trenches 21a-21c where the amount of carriers extracted is relatively large are typically indicated by oblique hatching.

[0055] 10, in the semiconductor device according to the first comparative example, the extraction current is concentrated on the outer side surface and bottom surface of the outermost contact trench 21a among the contact trenches 21a to 21c, and the amount of carrier extraction is relatively large. On the other hand, the amount of carrier extraction is relatively small on the inner side surface of the contact trench 21a and on the outer and inner side surfaces and bottom surfaces of the contact trenches 21b and 21c that are more on the inside than the contact trench 21a. Therefore, the contact area from which carriers are easily extracted is small compared to the entire contact area of ​​the contact trenches 21a to 21c, and improvement in the withstand current cannot be expected.

[0056] <Second Comparative Example> FIG. 11 is a plan view of a part of a semiconductor device according to a second comparative example, and corresponds to the plan view of the semiconductor device according to the first embodiment shown in FIG. 6. As shown in FIG. 11, the semiconductor device according to the second comparative example is different from the semiconductor device according to the first embodiment shown in FIG. 6 in that the trench contact portion 5y is composed of a plurality of island portions 51x provided at a distance from each other in a first direction (the vertical direction in FIG. 11), a plurality of island portions 51y provided at a distance from each other in the first direction on the inner side of the plurality of island portions 51x, and one stripe portion 51c extending in the first direction on the inner side of the plurality of island portions 51y. The plurality of island portions 51x and 51y are embedded in the contact trenches 21x and 21y. The stripe portion 51c is embedded in the contact trench 21c.

[0057] In the semiconductor device according to the second comparative example, the current concentration is alleviated by shifting the positions of the island portions 51x and the island portions 51y. However, since the resistance of the metal constituting the island portions 51x, 51y and the stripe portion 51c is three or more orders of magnitude lower than the resistance in the semiconductor, even if the island portions 51x and 51y are divided and shifted, the current flows through the portions with low resistance, so that the current concentrates on the outer island portions 51x and 51y, and the withstand current decreases.

[0058] Fig. 12 is a perspective view of a semiconductor device according to a second comparative example corresponding to Fig. 11. In Fig. 12, the island portions 51x, the island portions 51y, and the stripe portion 51c embedded in the contact trenches 21x, 21y, and 21c are not shown, and the side and bottom surfaces of the contact trenches 21x, 21y, and 21c are exposed. In Fig. 12, the portions of the contact trenches 21x, 21y, and 21c where a large amount of carriers are extracted are typically hatched.

[0059] 12, in the semiconductor device according to the second comparative example, the amount of carriers pulled out is relatively large in the outer side surface, two side surfaces facing each other in the first direction, and bottom surface of the outermost contact trench 21x among the contact trenches 21x, 21y, and 21c, and in the outer side surface, two side surfaces facing each other in the first direction, and bottom surface of the contact trench 21y located inside the contact trench 21x and shifted from the contact trench 21x. On the other hand, the amount of carriers pulled out is relatively small in the outer and inner side surfaces and bottom surface of the contact trench 21c located inside the contact trenches 21x and 21y. Therefore, the contact area from which carriers are easily pulled out is small, and the improvement in the withstand current is not sufficient.

[0060] <Effects of the Semiconductor Device According to the First Embodiment> In contrast to the first and second comparative examples, the semiconductor device according to the first embodiment has a structure in which the stripes 51a to 51c are connected by a plurality of connecting portions 52a, 52b in the trench contact portion 5 as shown in Fig. 6. This makes it easier to extract current not only from the outermost stripe 51a but also from the entire trench contact portion 5, and makes it difficult for current to concentrate on the outermost stripe 51a. For example, in addition to the outer side and bottom surface of the outermost stripe 51a, carriers are easily extracted evenly at least from two side surfaces and bottom surfaces facing each other in the first direction of the plurality of connecting portions 52a connected to the stripe 51a, and further from the bottom surface of the stripe 51b connected to the plurality of connecting portions 52a on the inner side of the plurality of connecting portions 52a.

[0061] In addition, fine contact trenches 21a-21c, 22a, 22b can be formed at a pitch smaller than the cell pitch, and by arranging the contact trenches 21a-21c, 22a, 22b evenly, the current can be easily dispersed, and the contact area effective for evenly extracting carriers can be expanded. The contact area of ​​the trench contact portion 5 in the semiconductor device according to the first embodiment and the semiconductor devices according to the second to eighth embodiments described below is, for example, about 1 to 4 times larger than the contact area of ​​the semiconductor device according to the first and second comparative examples. However, the contact area of ​​the trench contact portion 5 in the semiconductor device according to the first embodiment and the semiconductor devices according to the second to eighth embodiments described below that is effective for evenly extracting carriers is larger than the contact area of ​​the semiconductor device according to the first and second comparative examples, and can be, for example, twice or more larger than the contact area of ​​the semiconductor device according to the first and second comparative examples.

[0062] Fig. 13 is a perspective view of the semiconductor device according to the first embodiment corresponding to Fig. 6. In Fig. 13, the stripe portions 51a-51c embedded in the contact trenches 21a-21c and the multiple connection portions 52a, 52b embedded in the contact trenches 22a, 22b are omitted, and the side and bottom surfaces of the contact trenches 21a-21c, 22a, 22b are exposed. In Fig. 13, the portions of the contact trenches 21a-21c, 22a, 22b where a large amount of carriers are extracted are typically indicated by oblique hatching.

[0063] 13, in the semiconductor device according to the first embodiment, the stripe-shaped contact trenches 21a to 21c are connected by the contact trenches 22a and 22b, so that carriers can be easily extracted evenly not only from the outer side and bottom of the outermost contact trench 21a but also from two side and bottom surfaces of the contact trench 22a connected to the contact trench 21a that face each other in the first direction, and further from the bottom surface of the contact trench 21b connected to the contact trench 22a, etc. Therefore, the contact area effective for extracting carriers evenly can be expanded, and thus the withstand capability can be improved.

[0064] Furthermore, according to the semiconductor device of the first embodiment, as shown in FIG. 2, at the corners of the rectangle formed by the planar shape of the active region 101, the active termination portion 103 has multiple connection portions 53a-53d shaped to follow the curved shape of the corners of the active region 101, making it easier to extract carriers evenly even at the corners of the active region 101.

[0065] Second embodiment Fig. 14 is a plan view of a portion of the semiconductor device according to the second embodiment, and corresponds to the plan view of the semiconductor device according to the first embodiment shown in Fig. 6. Fig. 15 is a cross-sectional view taken along line AA' in Fig. 14. As shown in Figs. 14 and 15, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in the configuration of trench contact portion 5 of active termination portion 103.

[0066] The trench contact portion 5 shown in FIGS. 14 and 15 has a ladder-like planar shape. The trench contact portion 5 includes two stripe portions 51a, 51c extending in a first direction (vertical direction in FIG. 14) and a plurality of connecting portions 52a provided between the stripe portions 51a, 51c and extending in a second direction (horizontal direction in FIG. 14) perpendicular to the first direction. One end of each of the connecting portions 52a in the second direction is connected to the stripe portion 51a, and the other end of each of the connecting portions 52a in the second direction is connected to the stripe portion 51c. The length L1 of each of the connecting portions 52a in the second direction is longer than the length L1 of each of the connecting portions 52a shown in FIG. 6. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore, repeated explanations will be omitted.

[0067] In the semiconductor device according to the second embodiment, in the trench contact portion 5 of the active termination portion 103, the stripes 51a, 51c extending in the first direction are connected by a plurality of connecting portions 52a, so that the amount of carrier extraction is increased at the outer side and bottom surface of the outermost stripe 51a, the bottom surfaces of the plurality of connecting portions 52a connected to the stripe 51a, and two opposing side surfaces in the first direction, and the like, and the carriers can be extracted evenly. Therefore, the contact area effective for extracting the carriers evenly can be expanded, and the withstand capability can be improved.

[0068] Third embodiment Fig. 16 is a plan view of a portion of the semiconductor device according to the third embodiment, and corresponds to the plan view of the semiconductor device according to the first embodiment shown in Fig. 6. Fig. 17 is a cross-sectional view taken along line AA' in Fig. 16. As shown in Figs. 16 and 17, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in the configuration of trench contact portion 5 of active termination portion 103.

[0069] The trench contact portion 5 shown in FIG. 16 and FIG. 17 includes two stripe portions 51b, 51c extending in a first direction (vertical direction in FIG. 16), a plurality of connecting portions 52a provided outside the stripe portion 51b and extending in a second direction (horizontal direction in FIG. 16) perpendicular to the first direction, and a plurality of connecting portions 52b provided between the stripe portions 51b, 51c. One end of the plurality of connecting portions 52a in the second direction is connected to the stripe portion 51b. One end of the plurality of connecting portions 52b in the second direction is connected to the stripe portion 51b, and the other end of the plurality of connecting portions 52b in the second direction is connected to the stripe portion 51c. The length L1 of the plurality of connecting portions 52a in the second direction is longer than the length L2 of the plurality of connecting portions 52b. Other configurations of the semiconductor device according to the third embodiment are similar to those of the semiconductor device according to the first embodiment, so that a duplicated description will be omitted.

[0070] In the semiconductor device according to the third embodiment, in the trench contact portion 5 of the active termination 103, a plurality of connection portions 52b are connected to the stripe portion 51b, and the stripe portions 51b, 51c are connected by a plurality of connection portions 52a, so that the amount of carrier extraction is increased at the outer side surface and bottom surface in the second direction and two opposing side surfaces in the first direction of the outermost plurality of connection portions 52a, and at the outer side surface and bottom surface of the stripe portion 51b connected to the plurality of connection portions 52a, and the like, and the carriers can be extracted evenly. Therefore, the contact area effective for extracting the carriers evenly can be expanded, and the withstand capability can be improved.

[0071] (Fourth embodiment) Fig. 18 is a plan view of a portion of the semiconductor device according to the fourth embodiment, and corresponds to the plan view of the semiconductor device according to the first embodiment shown in Fig. 6. As shown in Fig. 18, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in the configuration of trench contact portion 5 of active termination portion 103.

[0072] The trench contact portion 5 shown in FIG. 18 has a structure obtained by flipping the trench contact portion 5 of the semiconductor device according to the third embodiment shown in FIG. 16 from left to right. The trench contact portion 5 includes two stripes 51a and 51b extending in a first direction (vertical direction in FIG. 18), a plurality of connecting portions 52a provided between the stripes 51a and 51b, and a plurality of connecting portions 52b provided inside the stripes 51b and extending in a second direction (horizontal direction in FIG. 18) perpendicular to the first direction. One end of each of the connecting portions 52a in the second direction is connected to the stripes 51a, and the other end of each of the connecting portions 52a in the second direction is connected to the stripes 51b. One end of each of the connecting portions 52b in the second direction is connected to the stripes 51b. The length L2 of each of the connecting portions 52b in the second direction is longer than the length L1 of each of the connecting portions 52a. Other configurations of the semiconductor device according to the fourth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore, a duplicated description will be omitted.

[0073] In the semiconductor device according to the fourth embodiment, in the trench contact portion 5 of the active termination 103, the stripes 51a and 51b are connected by a plurality of connecting portions 52a, and a plurality of connecting portions 52b are connected to the stripe 51b, so that the amount of carrier extraction is increased at the outer side and bottom surface of the outermost stripe 51a, the bottom surfaces of the plurality of connecting portions 52a connected to the stripe 51a, and two opposing side surfaces in the first direction, and the like, and the carriers can be extracted evenly. Therefore, the contact area effective for extracting the carriers evenly can be expanded, and the withstand capability can be improved.

[0074] Fifth embodiment Fig. 19 is a plan view of a portion of the semiconductor device according to the fifth embodiment, and corresponds to the plan view of the semiconductor device according to the first embodiment shown in Fig. 2. Fig. 20 is an enlarged plan view of region A in Fig. 19. Fig. 21 is a cross-sectional view taken along line AA' in Fig. 20. As shown in Figs. 19 to 21, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment in the configuration of trench contact portion 5 of active termination portion 103.

[0075] The trench contact portion 5 shown in FIGS. 19 to 21 has a comb-like planar shape. The trench contact portion 5 includes one stripe portion 51c extending in a first direction (the vertical direction in FIG. 20) and a plurality of connecting portions 52a provided outside the stripe portion 51c and extending in a second direction (the horizontal direction in FIG. 20) perpendicular to the first direction. The stripe portion 51c corresponds to a handle portion of the comb-like shape, and the plurality of connecting portions 52a correspond to teeth portions of the comb-like shape. One end of the plurality of connecting portions 52a in the second direction is connected to the stripe portion 51c. The length L1 of the plurality of connecting portions 52a in the second direction is longer than the length L1 of the plurality of connecting portions 52a shown in FIG. 6.

[0076] 19, the source electrode 3 has a curved shape at the corners of the rectangle formed by the planar shape of the active region 101. The lengths in the second direction (left-right direction in FIG. 19) of the multiple connection portions 52a included in the trench contact portion 5 of the active termination portion 103 change along the curved shape of the corners of the active region 101, and become shorter as they approach the corners of the active region 101. Other configurations of the semiconductor device according to the fifth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0077] In the semiconductor device according to the fifth embodiment, by configuring the trench contact portion 5 of the active termination 103 so that the multiple connection portions 52a are connected to the outside of the stripe portion 51c, the amount of carrier extraction is increased at the outer side surface and bottom surface in the second direction and two opposing side surfaces in the first direction of the outermost multiple connection portions 52a, and the outer side surface and bottom surface of the stripe portion 51b connected to the multiple connection portions 52a, and the like, and the carriers can be extracted evenly. Therefore, the contact area effective for extracting the carriers evenly can be expanded, and the withstand capability can be improved.

[0078] Furthermore, according to the semiconductor device of the fifth embodiment, at the corner portions (corner portions) of the rectangular planar shape of the active region 101, the lengths in the second direction of the multiple connection portions 52a included in the trench contact portion 5 of the active termination portion 103 are changed to conform to the curved shape of the corner portions of the active region 101, making it easier to extract carriers evenly even at the corner portions of the active region 101.

[0079] Sixth embodiment Fig. 22 is a plan view of a portion of the semiconductor device according to the sixth embodiment, which corresponds to the plan view of the semiconductor device according to the first embodiment shown in Fig. 6. As shown in Fig. 22, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment in the configuration of trench contact portion 5.

[0080] The trench contact portion 5 shown in FIG. 22 has a structure obtained by flipping the trench contact portion 5 of the semiconductor device according to the fifth embodiment shown in FIG. 20 from left to right. The trench contact portion 5 includes one stripe portion 51a extending in a first direction (vertical direction in FIG. 22) and a plurality of connecting portions 52a provided inside the stripe portion 51a and extending in a second direction (horizontal direction in FIG. 22) perpendicular to the first direction. One end of each of the connecting portions 52a in the second direction is connected to the stripe portion 51a. The length L1 of each of the connecting portions 52a in the second direction is longer than the length L1 of each of the connecting portions 52a shown in FIG. 6. Other configurations of the semiconductor device according to the sixth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0081] In the semiconductor device according to the sixth embodiment, by configuring the trench contact portion 5 of the active termination portion 103 so that a plurality of connection portions 52a are connected to the stripe portion 51a, the amount of carrier extraction is increased at the outer side surface and bottom surface of the outermost stripe portion 51a, the bottom surfaces of the plurality of connection portions 52a connected to the stripe portion 51a, and two opposing side surfaces in the first direction, and the like, and the carriers can be extracted evenly. Therefore, the contact area effective for extracting the carriers evenly can be expanded, and the withstand capability can be improved.

[0082] Seventh embodiment Fig. 23 is a cross-sectional view of a portion of the semiconductor device according to the seventh embodiment, which corresponds to the cross-sectional view of the portion of the semiconductor device according to the first embodiment shown in Fig. 3. Fig. 24 is a cross-sectional view of another portion of the semiconductor device according to the seventh embodiment, which corresponds to the cross-sectional view of the portion of the semiconductor device according to the first embodiment shown in Fig. 4. As shown in Figs. 23 and 24, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment in that the active element in the active region 101 is a vertical MOSFET with a trench gate structure.

[0083] n - A plurality of trenches (gate trenches) 30a, 30b are provided in parallel and spaced apart from each other in the upper portion of the drift layer 12. The right side surface of the gate trench 30a is provided with an n + The n-type source region 14a and the p-type base region 13a are in contact with each other. + The n-type source region 14b and the p-type base region 13a are in contact with each other. + 23 and 24. The side surfaces of the p-type source region 14c and the p-type base region 13b are in contact with each other. The bottoms of the gate trenches 30a, 30b are in contact with the drift layer 12. The gate trenches 30a, 30b have linear (striped) planar shapes extending parallel to each other in the depth direction in FIG. 23 and in the left-right direction in FIG. 24.

[0084] Between adjacent gate trenches 30a, 30b, there is provided a mesa portion constituted by an upper portion of the drift layer 12. The mesa portion is a region of the drift layer 12 sandwiched between adjacent gate trenches 30a, 30b, and is a region above the deepest positions of the gate trenches 30a, 30b.

[0085] A gate insulating film 71a is provided so as to cover the bottom and side surfaces of the gate trench 30a. A gate electrode 31a is embedded inside the gate trench 30a via the gate insulating film 71a. The gate insulating film 71a and the gate electrode 31a form an insulated gate electrode structure (31a, 71a). A gate insulating film 71b is provided so as to cover the bottom and side surfaces of the gate trench 30b. A gate electrode 31b is embedded inside the gate trench 30b via the gate insulating film 71b. The gate insulating film 71b and the gate electrode 31b form an insulated gate electrode structure (31b, 71b).

[0086] An interlayer insulating film 73 is provided on the mesa portion of the drift layer 12 and on the upper surfaces of the insulated gate electrode structures (31a, 71a), (31b, 71b). The interlayer insulating film 73 located on the mesa portion of the drift layer 12 is provided with contact holes penetrating the interlayer insulating film 73. Trenches (contact trenches) 20a, 20b are provided in the mesa portion of the drift layer 12 so as to be continuous with the contact holes.

[0087] The side surface of the contact trench 20a contacts the source regions 14a and 14b. + The contact trench 20b is in contact with the source region 14c. The contact trench 20b has a side surface in contact with the source region 14c. The bottom of the contact trench 20b is in contact with the p-type contact region 16a. A trench contact portion (plug portion) 61a is buried in the contact trench 20a. + The contact trench 20b is in contact with a contact region 16b of the mold. A trench contact portion (plug portion) 61b is buried in the contact trench 20b.

[0088] A surface electrode (source electrode) 3 is provided on the interlayer insulating film 73. The source electrode 3 is electrically connected to the source regions 14a to 14c and the contact regions 16a and 16b via trench contact portions 61a and 61b.

[0089] The lower surface side of the drift layer 12 is provided with an n-type semiconductor layer having a higher impurity concentration than the drift layer 12.+ A back surface electrode (drain electrode) 6 is provided on the lower surface of the drain region 11.

[0090] Other configurations of the semiconductor device according to the seventh embodiment, such as the breakdown voltage region 102 and the active termination portion 103, are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0091] According to the semiconductor device of the seventh embodiment, even when the active element in the active region 101 is a vertical MOSFET with a trench gate structure, the contact area effective for evenly extracting carriers can be enlarged in the active termination 103, as in the semiconductor device of the first embodiment, thereby improving the withstand capability. Note that the trench contact 5 of the active termination 103 of the semiconductor device of the seventh embodiment can have a configuration similar to any of the trench contact 5 of the active termination 103 of the semiconductor devices of the first to sixth embodiments.

[0092] Eighth embodiment Fig. 25 is a cross-sectional view of a portion of the semiconductor device according to the eighth embodiment, which corresponds to the cross-sectional view of the portion of the semiconductor device according to the first embodiment shown in Fig. 3. As shown in Fig. 25, the semiconductor device according to the eighth embodiment differs from the semiconductor device according to the first embodiment in that the active element in the active region 201 is a MOSFET with a super junction (SJ) structure.

[0093] The semiconductor device according to the eighth embodiment includes an active region 201 and a voltage-withstanding region 202 provided outside the active region 201 so as to surround the active region 201. An active termination portion 203 is provided at the end of the active region 201 on the voltage-withstanding region 202 side.

[0094] The semiconductor device according to the eighth embodiment is + A drain electrode 306 is provided on the lower surface side of the semiconductor substrate 311. An n-type semiconductor substrate 311 having a lower impurity concentration than the semiconductor substrate 311 is provided on the upper surface side of the semiconductor substrate 311. -A buffer layer 312 of a type, and a n-type - The semiconductor device further includes a drift layer 313 of the same type.

[0095] In the active region 201, p-type semiconductor regions (p-type columns) 314 and n-type semiconductor regions (n-type columns) 315 are alternately and periodically provided on the upper surface side of the buffer layer 312. The p-type columns 314 and n-type columns 315 have a cross-sectional shape extending in the vertical direction of FIG. 23. The p-type columns 314 and n-type columns 315 have a planar shape extending in the depth direction of FIG. 23. A p-type base region 316 is provided on the upper surface side of the p-type columns 314 and n-type columns 315. An n-type semiconductor region 315 is provided on the upper surface side of the base region 316. + A mold source region 317 is provided.

[0096] A trench (gate trench) 341 is provided in the depth direction from the upper surface of the source region 317. The lower end of the gate trench 341 reaches the n-type column 315. A gate insulating film 371 and a gate electrode 331 are buried in the gate trench 341. An interlayer insulating film 373 is provided on the upper surface side of the gate electrode 331. A source electrode 303 is provided on the upper surface side of the interlayer insulating film 373.

[0097] A trench (contact trench) 342 is provided in a depth direction from the upper surface of the source region 317 at a position continuous with the contact hole provided in the interlayer insulating film 373. The lower end of the contact trench 342 reaches the n-type column 315. + A mold contact region 318 is provided. A trench contact portion (plug portion) 361 is buried in the contact trench 342. The source region 317 is electrically connected to the source electrode 303 via the trench contact portion 361.

[0098] When the semiconductor device according to the eighth embodiment is off, a depletion layer extends laterally from the pn junction between the p-type column 314 and the n-type column 315 into the p-type column 314 and the n-type column 315, making it easier for the depletion layers to connect, thereby achieving a high withstand voltage.

[0099] In the active termination 203, a trench (contact trench) 343 is provided in the depth direction from the top surface of the base region 316. + A p-type contact region 319 is provided. A trench contact portion (plug portion) 305 is embedded in the contact trench 343. The trench contact portion 305 is provided above the p-type column 314. The trench contact portion 305 has the same configuration as the trench contact portion 5 of the semiconductor device according to the first embodiment, and a duplicated description will be omitted.

[0100] In the voltage-resistant region 202, p-type semiconductor regions (p-type columns) 321 and n-type semiconductor regions (n-type columns) 322 are alternately and periodically provided on the upper surface side of the buffer layer 312. A repetition pitch P2 of the p-type columns 321 and the n-type columns 322 in the voltage-resistant region 202 is smaller than a repetition pitch P1 of the p-type columns 314 and the n-type columns 315 in the active region 201.

[0101] On the upper surface side of the p-type column 321 and the n-type column 322, a plurality of p - A type semiconductor region (resurf region) 324 is provided. A gate wiring 307 made of polysilicon is provided on the upper surface side of the resurf region 324 via a field insulating film 372. A gate runner 302 is provided on the upper surface side of the gate wiring 307 via an interlayer insulating film 373. The gate runner 302 is electrically connected to the gate wiring 307 via a trench contact portion 308 embedded in a contact hole provided in the interlayer insulating film 373.

[0102] An n-type column 323 is provided outside the p-type column 321 and the n-type column 322 via a drift layer 313. - A type semiconductor region (channel stopper) 325 is provided. A field plate 332 made of polysilicon is provided on the upper surface side of the channel stopper 325 via a field insulating film 372 made of a local insulating film (LOCOS film) or the like. Other configurations of the semiconductor device according to the eighth embodiment are similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0103] According to the semiconductor device of the eighth embodiment, even when the active element in active region 201 is a MOSFET with an SJ structure, the contact area effective for evenly extracting carriers can be enlarged in active termination 203, as in the semiconductor device of the first embodiment, thereby improving the withstand capability. Note that trench contact 305 of active termination 203 of the semiconductor device of the eighth embodiment can have a configuration similar to that of trench contact 5 of active termination 203 of the semiconductor devices of the first to sixth embodiments.

[0104] Ninth embodiment The semiconductor device according to the ninth embodiment has the same configuration as the semiconductor device according to the first embodiment. + The impurity concentrations (dosages) and positional relationship of the contact region 17, which is a high-concentration, low-resistance region, and the contact regions 16a and 16b will be described.

[0105] As shown in FIG. 3, the active termination section 103, which has a large reverse recovery current, has a diode structure to suppress the operation of a parasitic bipolar transistor (BJT). + A similar p-type contact region 17 is formed in the cell portion of the active region 101. +By forming the contact regions 16a and 16b, parasitic BJT operation is suppressed, avalanche resistance is improved, and forward voltage is reduced. In order to reduce resistance as much as possible, the impurity concentration of the contact region 17 and the contact regions 16a and 16b is increased, and the distances d1 and d2 between the contact region 17 and the contact regions 16a and 16b and the pn junction are shortened.

[0106] However, by forming the contact region 17 and the contact regions 16a and 16b, the peak value (Irp) of the reverse recovery current increases, and the reverse recovery withstand voltage decreases. In addition, the rate of change (dIr / dt) of the reverse recovery current increases due to the decrease in resistance, and the breakdown voltage (BVds) during reverse recovery jumps up, and the electric field becomes higher. In addition, the inflow of carriers from the contact region 17 and the contact regions 16a and 16b increases, and the electric field becomes higher due to the large number of carriers near the pn junction during reverse recovery, the avalanche voltage decreases, the avalanche current concentrates, and the withstand voltage decreases. In addition, if the distances d1 and d2 between the contact region 17 and the contact regions 16a and 16b and the pn junction are shortened in order to reduce the resistance, the high resistance region of the diode becomes shorter, the electric field becomes higher, the avalanche voltage decreases, the avalanche current concentrates, and the withstand voltage decreases.

[0107] Therefore, in the semiconductor device according to the ninth embodiment, the dose of a p-type impurity such as boron (B) during ion implantation for forming the contact region 17 and the contact regions 16a and 16b is set to, for example, 5×10 14 cm -2 That's it, 3 x 10 15 cm -2 The dose of the contact region 17 and the contact regions 16a and 16b is set to about 5×10 14 cm -2 By setting the dose amount of the contact region 17 and the contact regions 16a and 16b at 3×10 or more, the parasitic BJT operation can be effectively suppressed. 15 cm -2or less and not lowering the carrier extraction resistance during reverse recovery too much, it is possible to suppress the peak value (Irp) of the reverse recovery current and the rate of change (dIr / dt) of the current when the reverse recovery current recovers from the peak value (Irp), thereby improving the reverse recovery withstand capability.

[0108] Figure 26A shows the reverse recovery characteristics of the diode's forward current (IF) and source-drain voltage (Vds). As shown in Figure 26A, the rate of change (dIr / dt) of the reverse recovery current when it recovers from its peak value (Irp) indicates the slope of the time it takes for the peak value (Irp) of the reverse recovery current generated in the reverse recovery withstand capability test to reach 0. Note that if the rate of change (dIr / dt) of the current when the reverse recovery current recovers from its peak value (Irp) becomes large, the source-drain voltage (Vds) will rise sharply, resulting in larger switching losses and a tendency for the withstand capability to decrease.

[0109] 26B is a graph showing the relationship between the dose of the contact region 17 and the contact regions 16a and 16b and the rate of change (di / dt) of the reverse recovery current. As shown in FIG. 26B, in order to increase the rate of change (di / dt) of the reverse recovery current, the dose of the contact region 17 and the contact regions 16a and 16b is preferably 5×10 14 cm -2 , 2.5×10 15 cm -2 More preferably, it is about 5×10 14 cm -2 That's it, 2 x 10 15 cm -2 More preferably, it is about 1×10 15 cm -2 That's it, 2 x 10 15 cm -2 It is about the following.

[0110] Here, the rate of change of reverse recovery current (di / dt) indicates the conditions under which the reverse recovery withstand capability test is performed. The viewpoint of increasing the rate of change of reverse recovery current (di / dt) is to reduce switching loss. Note that as the rate of change of reverse recovery current (di / dt) increases, the peak value of reverse recovery current (Irp) also increases, making it easier for the withstand capability to decrease. Therefore, conditions are selected under which the withstand capability does not decrease even if the test is performed with an increased rate of change of reverse recovery current (di / dt).

[0111] The dose of p-type impurities such as boron (B) during ion implantation to form the well region 18 and base regions 13a and 13b in contact with the contact region 17 and the contact regions 16a and 16b, respectively, can be set appropriately depending on the static characteristics required for each element, such as breakdown voltage, on-resistance (Ron), gate threshold voltage (Vth), forward voltage (Vf), and switching characteristics. The dose of the well region 18 and the base regions 13a and 13b is, for example, 1×10 13 cm -2 That's it, 2 x 10 14 cm -2 The dose of the well region 18 and the base regions 13a and 13b is about 1×10 13 cm -2 By setting the dose amount of the well region 18 and the base regions 13a and 13b at 2×10 or more, it is possible to suppress a decrease in breakdown voltage, a decrease in gate threshold voltage (Vth), a decrease in forward transconductance (gfs), an increase in forward voltage (Vf), a decrease in avalanche resistance, and a decrease in switching characteristics. 14 cm -2 By setting the following, it is possible to suppress a decrease in breakdown voltage, a decrease in gate threshold voltage (Vth), a decrease in on-resistance (Ron), a decrease in forward transconductance (gfs), a decrease in reverse recovery withstand capability, and switching noise.

[0112] When the semiconductor device according to the ninth embodiment is of a low breakdown voltage class, the dose of the well region 18 and the base regions 13a and 13b is 1×10 13 cm -2 That's it, 3 x 1013 cm -2 In the case where the semiconductor device according to the ninth embodiment is of the medium to high breakdown voltage class, a barrier metal film is not provided in the contact region 17 and the contact regions 16a and 16b, and electron beam irradiation is not performed during the manufacture of the semiconductor device according to the ninth embodiment, the dose of the well region 18 and the base regions 13a and 13b is about 2×10 13 cm -2 That's it, 4 x 10 13 cm -2 In the case where the semiconductor device according to the ninth embodiment is of the medium to high breakdown voltage class, a barrier metal film is formed on the contact portions of the contact region 17 and the contact regions 16a and 16b, and electron beam irradiation is performed during the manufacture of the semiconductor device according to the ninth embodiment, the dose of the well region 18 and the base regions 13a and 13b may be about 4×10 13 cm -2 That's it, 2 x 10 14 cm -2 It may be about the following.

[0113] The ratio of the dose of the contact region 17 to the dose of the well region 18 is, for example, 5 times or more and 60 times or less. On the other hand, by making the ratio of the dose of the contact region 17 to the dose of the well region 18 5 times or more, the parasitic BJT operation can be effectively suppressed. On the other hand, by making the ratio of the dose of the contact region 17 to the dose of the well region 18 60 times or less and not lowering the carrier extraction resistance during reverse recovery too much, the reverse recovery withstand capability can be improved. The ratio of the dose of the contact regions 16a, 16b to the dose of the base regions 13a, 13b is approximately the same as the ratio of the dose of the contact region 17 to the dose of the well region 18.

[0114] In the semiconductor device according to the ninth embodiment, the distance d1 between the bottom surface of the contact region 17 and the pn junction of the well region 18 and the drift layer 11, and the distance d2 between the contact regions 16a, 16b and the pn junction of the base regions 13a, 13b and the drift layer 11 are set to, for example, about 0.5 μm or more and 2.0 μm or less. By setting the distances d1 and d2 between the contact region 17 and the contact regions 16a, 16b and the pn junction to 0.5 μm or more, it is possible to prevent the depletion layer extending from the pn junction from reaching the contact region 17 and the contact regions 16a, 16b, and to make it difficult for the breakdown voltage to decrease. Furthermore, it is possible to suppress the generation of excess carriers during reverse recovery, to relax the electric field in the well region 18 and the base regions 13a, 13b, and to suppress the decrease in the breakdown voltage due to the decrease in the breakdown voltage. On the other hand, by setting the distances d1, d2 between the contact region 17 and the pn junction and the contact regions 16a, 16b to 2.0 μm or less, it is possible to suppress a decrease in breakdown voltage, suppress an increase in on-resistance (Ron), suppress a decrease in forward transconductance (gfs), suppress an increase in forward voltage (Vf), suppress an increase in input capacitance (Ciss), and suppress a decrease in feedback capacitance (Crss).

[0115] The distances d1, d2 between the contact region 17 and the contact regions 16a, 16b and the pn junction can be appropriately set depending on the characteristics such as the breakdown voltage class required for the element and the associated acceleration voltage of ion implantation. In the case of low acceleration ion implantation (e.g., about 50 keV) such as when the contact region 17 and the contact regions 16a, 16b are formed at the bottom of the trench contact, the distances d1, d2 between the contact region 17 and the contact regions 16a, 16b and the pn junction are, for example, 0.5 μm or more and 1.0 μm or less. In the case of high acceleration ion implantation (e.g., about 120 keV) such as when the contact region 17 and the contact regions 16a, 16b are formed on the upper surface of the semiconductor substrate that is not a trench contact, the distances d1, d2 between the contact region 17 and the contact regions 16a, 16b and the pn junction are, for example, 1.0 μm or more and 2.0 μm or less. The other configurations of the semiconductor device according to the ninth embodiment are similar to those of the semiconductor device according to the first embodiment, so that the overlapping description will be omitted.

[0116] According to the semiconductor device of the ninth embodiment, the impurity concentration (dose) of the contact region 17 and the contact regions 16a, 16b is set within a predetermined range, thereby suppressing the reverse recovery current (Irp) and the rate of change of the reverse recovery current (dIr / dt), and improving the reverse recovery withstand voltage. In addition, the ratio of the dose of the contact region 17 to the dose of the well region 18 and the ratio of the dose of the contact regions 16a, 16b to the dose of the base regions 13a, 13b are set within a predetermined range, thereby improving the reverse recovery withstand voltage. In addition, the distances d1, d2 between the contact region 17 and the contact regions 16a, 16b and the pn junction are set within a predetermined range, thereby improving the reverse recovery withstand voltage. The same effect can be obtained not only in the configuration of the semiconductor device of the first embodiment, but also in the configurations of the semiconductor devices of the second to eighth embodiments.

[0117] Tenth embodiment Fig. 27 is a plan view of a portion of the semiconductor device according to the tenth embodiment. In Fig. 27, for the sake of convenience, the source electrode 3, gate wirings 2a-2c, and field plate 2d are indicated by solid lines, the gate electrodes 31a-31c and field plates 33a-33h are indicated by dashed lines, and the field insulating film 72 is indicated by dotted lines. The semiconductor device according to the tenth embodiment includes an active region 101 and a voltage-resistant region 102 provided outside the active region 101. In Fig. 27, the position of the end of the source electrode 3 is set to the boundary position between the active region 101 and the voltage-resistant region 102.

[0118] The gate electrodes 31a to 31c of the active elements included in the active region 101 extend in a stripe shape in a first direction (horizontal direction in FIG. 27) and are spaced apart from each other in a second direction (vertical direction in FIG. 27) perpendicular to the first direction. The gate electrodes 31a to 31c extend from the active region 101 to the voltage withstanding region 102. Ends of the gate electrodes 31a to 31c in the first direction are connected to the gate wiring 2a via contact parts 2x, 2y, and 2z. The gate electrodes 31a to 31c have a width w1 on the active region 101 side. Between the vicinity of the boundary between the active region 101 and the voltage withstanding region 102 and the contact parts 2x, 2y, and 2z with the gate wiring 2a, the gate electrodes 31a to 31c have a width w2 narrower than the width w1.

[0119] In the voltage-resistant region 102, metal gate wirings 2a-2c and metal field plate 2d extend in a stripe pattern in a second direction (vertical direction in FIG. 27) at a distance from each other in a first direction (horizontal direction in FIG. 27). A plurality of field insulating films 72 extend in a stripe pattern in the second direction (vertical direction in FIG. 27) at a distance from each other in the first direction (horizontal direction in FIG. 27). A plurality of polysilicon field plates 33a-33h extend in a stripe pattern in the second direction (vertical direction in FIG. 27) at a distance from each other in the first direction (horizontal direction in FIG. 27).

[0120] 28 is a cross-sectional view taken along the line AA′ passing through the gate electrode 31a in FIG. 27. As shown in FIG. - Two p-type well regions 13 are provided, spaced apart from each other, on the active region 101 side of the upper surface of the drift layer 12. Of the two p-type well regions 13, the inner well region 13 (left side in FIG. 28) is located directly under the narrow width w2 portion of the gate electrode 31a shown in FIG. 27. The depth of the outer well region 13 (right side in FIG. 28) is deeper than the depth of the inner well region 13. A p-type well region 13 having a higher impurity concentration than the well region 13 is provided at the end of the gate electrode 31a on the upper surface side of the outer well region 13. +27. The contact region 16 is provided so as to surround the periphery of the gate electrodes 31a to 31c in FIG. 27. Outside the outer well region 13, p-type RESURF regions 41a to 41d are provided. At the chip end on the upper surface side of the drift layer 12, p - A mold channel stopper 19 is provided.

[0121] A gate electrode 31a made of polysilicon or the like is provided on the upper surface of the drift layer 12 on the active region 101 side via a gate insulating film 71a. A field plate 33a-33h, 32 made of polysilicon or the like is provided on the upper surface of the drift layer 12 on the voltage-resistant region 102 side via a field insulating film 72. The field insulating film 72 has openings that expose the upper surfaces of the contact region 16, the resurf regions 41a-41d, and the channel stopper 19. The field insulating film 72, the gate electrode 31a, and the field plates 33a-33h, 32 are covered with an interlayer insulating film 73. A source electrode 3 and a gate wiring 2a are provided above the gate electrode 31a via the interlayer insulating film 73. The gate wiring 2a is connected to an end of the gate electrode 31a via a contact portion 2x. Gate wirings 2b, 2c are provided above the field plates 33a-33h via the interlayer insulating film 73. A field plate 2d is provided above the field plate 32 via the interlayer insulating film 73.

[0122] 29 is a cross-sectional view taken along line BB' passing between gate electrodes 31a and 31b in FIG. - A p-type well region 13 is provided on the upper surface side of the drift layer 12. The well region 13 is provided so as to extend from the active region 101 to the voltage-resistant region 102. + A contact region 16 of a n-type is provided. The contact region 16 is provided so as to extend from the active region 101 to the voltage-resistant region 102. +A source region 14 is provided on the contact region 16. The upper surfaces of the contact region 16 and the source region 14 are in contact with the source electrode 3.

[0123] 30A is a cross-sectional view taken along line CC′ passing through the wide width w1 portion of the gate electrodes 31a to 31c in FIG. - A plurality of p-type well regions 13 are provided at intervals on the upper surface side of the p-type drift layer 12. The well regions 13 function as base regions (channel formation regions) of active elements. + The contact region 16 and the n + A source region 14 is provided.

[0124] FIG. 30B is a cross-sectional view taken along line DD' passing through the narrow width w2 portion of the gate electrodes 31a to 31c in FIG. 27. As shown in FIG. 30B, a p-type well region 13 is provided on the upper surface side of the drift region 12. The well region 13 is divided into a plurality of regions in the position of FIG. 30A, but is connected to each other in the position of FIG. 30B. The depth of the well region 13 immediately below the gate electrodes 31a to 31c is shallower than the depth of the well region 13 located between the gate electrodes 31a to 31c. The impurity concentration of the well region 13 immediately below the gate electrodes 31a to 31c is lower than the impurity concentration of the well region 13 located between the gate electrodes 31a to 31c. In FIG. 28 and FIG. 30B, regions A1 to A3 of the well region 13 that are relatively shallow and have low impurity concentrations are typically shown by dashed lines.

[0125] As shown in FIG. 30B, the upper surface side of the well region 13 is provided with a plurality of p + The contact regions 16 are provided spaced apart from each other. The contact regions 16 are selectively provided in regions between the gate electrodes 31a to 31c where the well region 13 is deep and has a high impurity concentration. The contact regions 16 are not provided in regions A1 to A3 where the well region 13 directly below the gate electrodes 31a to 31c is shallow and has a low impurity concentration. Other configurations of the semiconductor device according to the tenth embodiment are similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0126] According to the semiconductor device of the tenth embodiment, in the narrow width w2 portion of the gate electrodes 31a to 31c, the depth of the well region 13 located directly below the gate electrodes 31a to 31c is shallow, and the p + By providing the contact region 16, it is possible to suppress the injection of excess carriers, prevent a further increase in the electric field and a decrease in the withstand voltage, and suppress a decrease in the reverse recovery withstand voltage.

[0127] Eleventh embodiment Fig. 31 is a cross-sectional view of a portion of the semiconductor device according to the 11th embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the first embodiment shown in Fig. 3. Fig. 32 is a cross-sectional view of another portion of the semiconductor device according to the 11th embodiment, and corresponds to the position of the cross section taken along line EE' in the plan view of the semiconductor device according to the first embodiment shown in Fig. 2.

[0128] As shown in Figures 31 and 32, the semiconductor device of the 11th embodiment differs from the semiconductor device of the first embodiment in that the contact portions 61a, 61b of the active elements in the active region 101 and the contact portion 5 of the active termination portion 103 are each normal contact portions (planar contact portions) that are not embedded in trenches.

[0129] The side surfaces of the contact portions 61a and 61b of the active element in the active region 101 are in contact with the interlayer insulating film 73. The lower surface of the contact portion 61a is in contact with the upper surfaces of the source regions 14a and 14b and the contact region 16a. The lower surface of the contact portion 61b is in contact with the upper surfaces of the source region 14c and the contact region 16b.

[0130] The contact portion 5 of the active termination portion 103 includes a plurality of (three) stripes 51a-51c, a plurality of connection portions 52a provided between the stripes 51a, 51b and spaced apart from each other in the first direction, and a plurality of connection portions 52b provided between the stripes 51b, 51c and spaced apart from each other in the first direction. Sides of the stripes 51a-51c and the connection portions 52a, 52b are in contact with the interlayer insulating film 73. Lower surfaces of the stripes 51a-51c and the connection portions 52a, 52b are in contact with the contact region 17. Other configurations of the semiconductor device according to the eleventh embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0131] According to the semiconductor device of the eleventh embodiment, the contact portions 61a, 61b of the active elements in the active region 101 and the contact portion 5 of the active termination portion 103 may each be a normal contact portion that is not embedded in a trench. Even in this case, as in the semiconductor device of the first embodiment, the contact area effective for evenly extracting carriers by the contact portion 5 can be enlarged in the active termination portion 103, thereby improving the withstand capability.

[0132] Furthermore, as in the semiconductor device according to the tenth embodiment, by setting the impurity concentration (dose) of the contact region 17 and the contact regions 16a, 16b within a predetermined range, the reverse recovery current (Irp) and the rate of change (dIr / dt) of the reverse recovery current can be suppressed and the reverse recovery withstand voltage can be improved. In addition, by setting the ratio of the dose of the contact region 17 to the dose of the well region 18 and the ratio of the dose of the contact regions 16a, 16b to the dose of the base regions 13a, 13b within a predetermined range, the reverse recovery withstand voltage can be improved. In addition, by setting the distances d1, d2 between the contact region 17 and the contact regions 16a, 16b and the pn junction within a predetermined range, the reverse recovery withstand voltage can be improved. The same effect can be achieved in the semiconductor devices according to the twelfth to seventeenth embodiments described below.

[0133] Twelfth embodiment Fig. 33 is a cross-sectional view of a portion of the semiconductor device according to the twelfth embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the eleventh embodiment shown in Fig. 31. Fig. 34 is a cross-sectional view of another portion of the semiconductor device according to the twelfth embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the eleventh embodiment shown in Fig. 32.

[0134] As shown in Figures 33 and 34, the semiconductor device of the 12th embodiment differs from the semiconductor device of the 11th embodiment shown in Figures 31 and 32 in that the active element in the active region 101 is a MOSFET with a super junction (SJ) structure.

[0135] An n-type buffer region 23 is provided on the upper surface side of the drain region 11. In the active region 101, p-type semiconductor regions (p-type columns) 24a to 24d and n-type semiconductor regions (n-type columns) 25a to 25d are alternately and periodically provided on the upper surface side of the buffer region 23. The upper surface of the p-type column 24a is in contact with the base region 13b. The upper surface of the p-type column 24b is in contact with the base region 13a. The upper surface of the p-type column 24c is in contact with the well region 18. The upper surface of the p-type column 24d is in contact with the well region 18 and the RESURF region 15.

[0136] In the withstand voltage region 102, p-type semiconductor regions (p-type columns) 24e-24g are provided at a distance from one another on the upper surface side of the buffer region 23, and an n-type semiconductor region 25e is provided to be sandwiched between the p-type columns 24e-24g. The upper surface of the p-type column 24e is in contact with the RESURF region 15. The upper surfaces of the p-type columns 24f, 24g are separated from the field insulating film 72 via the n-type semiconductor region 25e. Other configurations of the semiconductor device according to the twelfth embodiment are similar to those of the semiconductor device according to the eleventh embodiment, and therefore repeated explanations will be omitted.

[0137] According to the semiconductor device of the twelfth embodiment, the active element in the active region 101 may be a MOSFET with an SJ structure. Even in this case, the contact area effective for evenly extracting carriers by the contact portion 5 can be enlarged in the active termination portion 103, and therefore the withstand capability can be improved.

[0138] Thirteenth embodiment Fig. 35 is a cross-sectional view of a portion of the semiconductor device according to the 13th embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the 12th embodiment shown in Fig. 33. Fig. 36 is a cross-sectional view of another portion of the semiconductor device according to the 13th embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the 12th embodiment shown in Fig. 34.

[0139] As shown in Figures 35 and 36, the semiconductor device of the 13th embodiment differs from the semiconductor device of the 12th embodiment shown in Figures 33 and 34 in that the contact portions 61a, 61b of the active element in the active region 101 and the contact portion 5 of the active termination portion 103 are each integrally formed with the source electrode 3.

[0140] Contact portions 61a, 61b of the active elements in active region 101 and contact portion 5 of active termination portion 103 are made of the same metal material, such as aluminum, as source electrode 3. Other configurations of the semiconductor device according to the thirteenth embodiment are similar to those of the semiconductor device according to the twelfth embodiment, and therefore repeated explanations will be omitted.

[0141] According to the semiconductor device of the thirteenth embodiment, contact portions 61a, 61b of the active elements in active region 101 and contact portion 5 of active termination portion 103 may each be provided integrally with source electrode 3. Even in this case, the contact area effective for evenly extracting carriers by contact portion 5 can be enlarged in active termination portion 103, thereby improving the withstand capability.

[0142] Fourteenth embodiment Fig. 37 is a cross-sectional view of a portion of the semiconductor device according to the fourteenth embodiment, and corresponds to a position on the active termination portion 103 side of the cross section of the portion of the semiconductor device according to the first embodiment shown in Fig. 3. As shown in Fig. 37, the semiconductor device according to the fourteenth embodiment is similar to the semiconductor device according to the first embodiment shown in Fig. 3 in that the contact portion 5 of the active termination portion 103 is a trench contact portion buried in the trenches 21a-21c, but differs from the semiconductor device according to the first embodiment shown in Fig. 3 in that the contact portions 61a, 61b of the active elements in the active region 101 are normal contact portions that are not buried in trenches.

[0143] Contact portions 61a, 61b of the active element in the active region 101 are provided integrally with the source electrode 3. Contact portion 5 of the active termination portion 103 has multiple (three) stripe portions 51a-51c embedded in trenches 21a-21c via a barrier metal film 54. Other configurations of the semiconductor device in accordance with the fourteenth embodiment are similar to those of the semiconductor device in accordance with the first embodiment, and therefore repeated explanations will be omitted.

[0144] According to the semiconductor device of the fourteenth embodiment, contact portions 61a, 61b of the active elements in active region 101 may be normal contact portions that are not embedded in trenches, and contact portion 5 of active termination portion 103 may be a trench contact portion embedded in trenches 21a to 21c. Even in this case, the contact area effective for evenly extracting carriers by contact portion 5 can be enlarged in active termination portion 103, thereby improving the withstand capability.

[0145] Fifteenth embodiment Fig. 38 is a cross-sectional view of a portion of the semiconductor device according to the fifteenth embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the fourteenth embodiment shown in Fig. 37. As shown in Fig. 38, the semiconductor device according to the fifteenth embodiment differs from the semiconductor device according to the fourteenth embodiment shown in Fig. 37 in that contact portions 61a, 61b of the active elements in the active region 101 are plug portions provided separately from the source electrode 3.

[0146] Contact portions 61a, 61b of the active elements in the active region 101 are made of a metal such as tungsten (W). The contact portion 61 is provided on the upper surface side of the contact region 16a and the source regions 14a, 14b via a barrier metal film 62. The contact portion 61b is provided on the upper surface side of the contact region 16b and the source region 14c via a barrier metal film 62. Other configurations of the semiconductor device according to the fifteenth embodiment shown in FIG. 38 are similar to those of the semiconductor device according to the fourteenth embodiment shown in FIG. 37, and therefore repeated explanations will be omitted.

[0147] According to the semiconductor device of the fifteenth embodiment, the contact portions 61a, 61b of the active element in the active region 101 may be provided separately from the source electrode 3. Even in this case, the contact area effective for evenly extracting carriers by the contact portion 5 can be enlarged in the active termination portion 103, thereby improving the withstand capability.

[0148] Sixteenth embodiment Fig. 39 is a cross-sectional view of a portion of the semiconductor device according to the sixteenth embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the fourteenth embodiment shown in Fig. 37. As shown in Fig. 39, the semiconductor device according to the sixteenth embodiment differs from the semiconductor device according to the fourteenth embodiment shown in Fig. 37 in that the active element in the active region 101 is a MOSFET with a super junction (SJ) structure.

[0149] On the upper surface side of the drain region 11, p-type columns 24a to 24f and n-type columns 25a to 25d are alternately provided. The upper surface of the p-type column 24a contacts the base region 13b. The upper surface of the p-type column 24b contacts the base region 13a. The upper surface of the p-type column 24c contacts the well region 18 and the resurf region 15. The upper surfaces of the p-type columns 24d and 24e contact the resurf region 15. The upper surface of the p-type column 24f is separated from the field insulating film 72 via the n-type semiconductor region 25e. Other configurations of the semiconductor device according to the sixteenth embodiment are similar to those of the semiconductor device according to the fourteenth embodiment shown in FIG. 37, and therefore repeated explanations will be omitted.

[0150] According to the semiconductor device of the sixteenth embodiment, the active element in the active region 101 may be a MOSFET with an SJ structure. Even in this case, the contact area effective for evenly extracting carriers by the contact portion 5 can be enlarged in the active termination portion 103, and therefore the withstand capability can be improved.

[0151] Seventeenth embodiment Fig. 40 is a cross-sectional view of a portion of the semiconductor device according to the seventeenth embodiment, and corresponds to the position of the cross section of the portion of the semiconductor device according to the fifteenth embodiment shown in Fig. 38. As shown in Fig. 40, the semiconductor device according to the seventeenth embodiment differs from the semiconductor device according to the fifteenth embodiment shown in Fig. 38 in that the active element in the active region 101 is a MOSFET with a super junction (SJ) structure. The SJ structure is similar to that of the semiconductor device according to the sixteenth embodiment shown in Fig. 39, and therefore a duplicated description will be omitted. Other configurations of the semiconductor device according to the seventeenth embodiment are similar to those of the semiconductor device according to the fifteenth embodiment shown in Fig. 38, and therefore a duplicated description will be omitted.

[0152] According to the semiconductor device of the seventeenth embodiment, the active element in the active region 101 may be a MOSFET with an SJ structure. Even in this case, the contact area effective for evenly extracting carriers by the contact portion 5 can be enlarged in the active termination portion 103, and therefore the withstand capability can be improved.

[0153] (Other embodiments) Although the first to seventeenth embodiments have been described above, the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0154] For example, a MOSFET has been illustrated as an example of the semiconductor device according to the first to seventeenth embodiments. + The drain region is p +The present invention is also applicable to insulated gate bipolar transistors (IGBTs) with a collector region of a reverse-type insulated gate bipolar transistor (RB-IGBT) or reverse-conducting IGBT (RC-IGBT) in addition to the IGBT itself.

[0155] In addition, in the semiconductor devices according to the first to seventeenth embodiments, the contact portion 5 includes one to three stripes 51a to 51c, but may include four or more stripes. Stripes other than the outermost stripe do not necessarily need to be connected to multiple connection portions.

[0156] In addition, the configurations disclosed in the first to seventeenth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0157] 1…Gate pad 2. Gate Runner 2a~2c…Gate wiring 2d…Field plate 2x, 2y, 2z...Contact part 3…Source electrode 5,5x,5y…Contact part 6...Drain electrode 11…Drain region 12…Drift layer 13...Well area 13a, 13b...Base region 14a~14c…Source region 15…Resurf region 16, 16a, 16b...Contact area 17…Contact area 18...Well area 19...Channel stopper 20a, 20b, 21a to 21c, 21x, 21y, 22a, 22b...Contact trench 24a~24f...p-type columns 25a~25d...n-type columns 25e…Semiconductor region 30a, 30b...Gate trench 31a to 31d: gate electrodes 32,33a~33h...Field plate 41a~41d…Resurf area 51a~51c…Striped section 51x,51y…Shimabe 52a, 52b, 53a to 53d...Connections 54...Barrier metal film 61a~61c…Trench contact section 62...Barrier metal film 71a, 71b...gate insulating film 72...Field insulating film 73...Interlayer insulating film 101,201...active area 102, 202…Voltage range 103,203...Active termination part 201...Arrow 302...Gate Runner 303...Source electrode 305…Trench contact section 306...Drain electrode 307…Gate wiring 308…Trench contact section 311...Semiconductor substrate 312...Buffer layer 313…Drift layer 314,321...p-type column 315, 322, 323...n-type columns 316…Base area 317…Source area 318,319…Contact area 324…Resurf area 325…Channel stopper 331...gate electrode 332...Field plate 341…Gate trench 342,343…Contact trench 361…Trench contact section 371...Gate insulating film 372...Field insulating film 373...Interlayer insulating film

Claims

1. A semiconductor device having an active region and a voltage-resistant region provided outside the active region, a first conductivity type semiconductor layer provided across the active region and the voltage-withstanding region; a first semiconductor region of a second conductivity type provided on an upper surface side of the semiconductor layer at an end of the active region on the voltage withstanding region side; a contact portion provided on an upper surface side of the first semiconductor region; Equipped with The contact portion is a first stripe portion extending in a first direction along an end portion of the active region on the voltage-withstanding region side in a plan view; a plurality of first connection portions connected to the first stripe portion and spaced apart from each other in the first direction; A semiconductor device comprising:

2. The plurality of first connection portions are provided on the inner side of the first stripe portion. The semiconductor device according to claim 1 .

3. The plurality of first connection portions are provided outside the first stripe portion. The semiconductor device according to claim 1 .

4. a second stripe portion provided on the inner side of the first stripe portion and spaced apart from the first stripe portion, connected to the first connection portions, and extending in the first direction; The semiconductor device according to claim 2 .

5. a plurality of second connection parts provided on the inner side of the second stripe parts, connected to the second stripe parts, and spaced apart from each other in the first direction; The semiconductor device according to claim 4.

6. a third stripe portion provided on the inner side of the second stripe portion and spaced apart from the second stripe portion, connected to the plurality of second connection portions, and extending in the first direction; The semiconductor device according to claim 5 .

7. a plurality of second connection parts provided outside the first stripe parts, connected to the first stripe parts, and spaced apart from each other in the first direction; The semiconductor device according to claim 4.

8. In the plan view, corners of the active region have a curved shape, The lengths of the first to third stripe portions in the first direction vary along the curved shape. The semiconductor device according to claim 6.

9. The contact portion further includes a plurality of third connection portions that are provided outside the second stripe portion, are connected to the second stripe portion, and have a length that changes in a second direction perpendicular to the first direction along the curved shape. The semiconductor device according to claim 8.

10. In the plan view, corners of the active region have a curved shape, The length of the plurality of first connection portions in a second direction perpendicular to the first direction varies along the curved shape. The semiconductor device according to claim 3 .

11. A gate electrode of an active element included in the active region extends in the first direction. The semiconductor device according to claim 1 .

12. The active element included in the active region has a planar gate structure. The semiconductor device according to claim 1 .

13. The active element included in the active region has a trench gate structure. The semiconductor device according to claim 1 .

14. The active element included in the active region has a superjunction structure. The semiconductor device according to claim 1 .

15. The contact portion is electrically connected to a surface electrode of an active element included in the active region. The semiconductor device according to claim 1 .

16. The contact portion includes a barrier metal film and a contact plug. The semiconductor device according to claim 1 .

17. The contact plug includes a high melting point metal. The semiconductor device according to claim 16.

18. The contact portion is at least partially embedded inside a trench provided on an upper surface side of the first semiconductor region. The semiconductor device according to claim 1 .

19. The contact portion is provided on an upper surface of the first semiconductor region. The semiconductor device according to claim 1 .

20. a contact region of a second conductivity type having a higher impurity concentration than the first semiconductor region, the contact region being provided on an upper surface side of the first semiconductor region in contact with the contact portion; The semiconductor device according to claim 1 .

21. The dose of the contact region is 5×10 １４ cm －２ That's it, 3 x 10 １５ cm －２ is less than or equal to The semiconductor device according to claim 20.

22. The ratio of the dose of the contact region to the dose of the first semiconductor region is 5 times or more and 60 times or less. The semiconductor device according to claim 20.

23. The distance between the contact region and the pn junction formed by the semiconductor layer and the first semiconductor region is 0.5 μm or more. The semiconductor device according to claim 20.

24. A plurality of gate electrodes of active elements included in the active region are spaced apart from each other and extend in the first direction, a second semiconductor region of a second conductivity type provided on an upper surface side of the semiconductor layer, the second semiconductor region having a depth at a position overlapping with ends of the plurality of gate electrodes in the first direction shallower than a depth at a position overlapping with a gap between the ends of the plurality of gate electrodes; a third semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor region, the third semiconductor region being provided on an upper surface side of the deep portion of the second semiconductor region and separated from the shallow portion of the second semiconductor region; Further comprising The semiconductor device according to claim 1 .

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