Time measurement circuit, distance measurement device, and time measurement method

Abstract

To improve the accuracy of time measurement in a time measurement circuit using a ring oscillator-type TDC over the conventional accuracy.SOLUTION: A time measurement circuit 10 comprises: a ring oscillator 12 configured to generate a first clock from input of a time measurement start signal until input of a time measurement stop signal; a counter (high-speed counter) 14 for counting the first clock; an auxiliary circuit (delay line type TDC) 200 for outputting a time calculation signal for calculating an elapsed time from input of the start signal until the first rising edge of the first clock is detected from the start signal; and a time calculation circuit 18 for calculating an elapsed time from input of the start signal until input of the stop signal on the basis of the calculation result based on the time calculation signal outputted by the auxiliary circuit, or on the basis of the calculation result based on the time calculation signal outputted by the auxiliary circuit and the count result by the counter.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a time measurement circuit, a distance measuring device, and a time measurement method. [Background technology]

[0002] Conventionally, distance measuring devices that measure the distance to a target object (hereinafter also referred to as the "target") use a method called "Time of Flight (TOF)". This method measures the distance from the distance measuring device to the target by measuring the time it takes for light emitted from the distance measuring device to be reflected by the target and return. Here, if the speed of light in air is approximately 300,000 km / sec, the time measurement used in the distance measuring device requires a high-resolution time measurement circuit that uses a high-frequency signal.

[0003] Therefore, in order to measure time with a resolution higher than the period of the reference clock, the time measurement circuit prepares, for example, multiple signals with different phase values ​​of the reference clock, and uses the values ​​of these signals to measure time with a resolution higher than the period of the reference clock. A circuit that performs such time measurement is called a "Time To Digital Converter (TDC)," and an example of the configuration of a general time measurement device using this TDC is disclosed in, for example, Patent Document 1.

[0004] However, the high-frequency reference clock used in the above-mentioned time measurement device increases power consumption, so generating this reference clock constantly is disadvantageous in terms of power consumption. To solve this problem, a ring oscillator-type TDC (hereinafter also referred to as a "ring oscillator-type TDC") that can generate a reference clock intermittently may be used in the time measurement circuit.

[0005] A ring oscillator TDC is equipped with a ring oscillator that is made up of delay elements connected in a ring shape to give a time delay to the input signal. The ring oscillator oscillates by using the propagation delay of the delay elements, which enables a time measurement circuit using a ring oscillator TDC to intermittently generate a reference clock (intermittent operation) and to measure time based on the results of counting this reference clock. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2019-60670 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, when the above-mentioned ring oscillator type TDC is used as a time measurement circuit to reduce power consumption, there are two problems. For example, in a ring oscillator type TDC, a delay of a certain time (for example, about 0.5 to 1 ns) occurs from when the ring oscillator start signal is made active (High) until the ring oscillator starts oscillating. In other words, there is a time after the ring oscillator is started during which time measurement is not possible. In addition, when a reference clock is intermittently generated by the ring oscillator, the period of the generated reference clock does not immediately stabilize, and the period of the reference clock becomes unstable in the first cycle (for example, about 1.6 ns from the start of the ring oscillator oscillation when the frequency of the ring oscillator is 625 MHz).

[0008] Therefore, when a ring oscillator TDC is used in a time measurement circuit, it is more advantageous in terms of power consumption than other time measurement circuits, but due to the above two problems, accurate time measurement is not possible for the first specified time (for example, about 2 ns (= 0.5 ns + 1.6 ns)) after the ring oscillator is started. In other words, there was room for improvement in the accuracy of time measurement in time measurement circuits using conventional ring oscillator TDCs.

[0009] The present disclosure has been made to solve the above-mentioned problems, and aims to improve the accuracy of time measurement in a time measurement circuit using a ring oscillator type TDC compared to the conventional technology. [Means for solving the problem]

[0010] The time measurement circuit of the present disclosure is characterized by comprising: a ring oscillator configured to generate a first clock between input of a time measurement start signal and input of a time measurement stop signal; a counter that counts the first clock; an auxiliary circuit that outputs a signal for calculating the elapsed time from input of the start signal to detection of the first rising edge of the first clock; and a time calculation circuit that calculates the elapsed time from input of the start signal to input of the stop signal based on a calculation result based on the signal output by the auxiliary circuit, or based on a calculation result based on the signal output by the auxiliary circuit and a counting result by the counter. Effect of the Invention

[0011] According to the present disclosure, with the above-mentioned configuration, in a time measurement circuit using a ring oscillator type TDC, it is possible to improve the accuracy of time measurement compared to the conventional art. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram for explaining the concept of distance measurement using Time of Flight (TOF) in the first embodiment. [Diagram 2]1 is a diagram illustrating an example of the configuration of a distance measuring device according to a first embodiment. [Diagram 3] FIG. 1 is a diagram showing an example of the configuration of a time measurement circuit according to a conventional example. [Figure 4] 11 is a timing chart showing an example of the operation of a time measurement circuit according to a conventional example. [Diagram 5] 2 is a diagram illustrating a configuration example of a time measurement circuit according to the first embodiment; [Figure 6] 4 is a timing chart showing an example of the operation of the time measurement circuit in Pattern 1 according to the first embodiment. [Figure 7] 11 is a timing chart showing an example of the operation of the time measurement circuit in Pattern 2 according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Embodiment 1 First, a concept of distance measurement using "Time of Flight (TOF)" used in the embodiment of the present disclosure and a configuration example of a distance measuring device according to the embodiment that uses the concept of distance measurement using TOF will be briefly described.

[0014] In TOF, light from a light source consisting of a laser, LED, etc. is irradiated onto an object for distance measurement, and the light reflected by the object (reflected light) is received by a light receiving element, as shown in Figure 1. Then, the elapsed time (time difference) from when the light source irradiates the object to when the reflected light is received by the light receiving element is calculated, and the distance from the light source to the object is measured based on the calculated elapsed time and the speed of light.

[0015] <Distance measuring device 60> 2 is a diagram showing an example of the configuration of a distance measuring device 60 according to the first embodiment, which uses the concept of distance measurement by TOF as described above. The distance measuring device 60 includes a light source 1, a light receiving element 2, a timing control circuit 3, and a distance measuring circuit 50 including a time measurement circuit 10, as shown in FIG.

[0016] The light source 1 is composed of, for example, a laser and an LED, and irradiates light onto an object of distance measurement based on an irradiation instruction signal from a timing control circuit 3. The light receiving element 2 receives light (reflected light) that is irradiated from the light source 1 onto the object and reflected by the object, and notifies the timing control circuit 3 and the time measurement circuit 10 of the timing at which the reflected light is received.

[0017] The timing control circuit 3 outputs a signal (irradiation instruction signal) to the light source 1 to instruct the light source 1 to irradiate the target object with light, and notifies the time measurement circuit 10 of the timing at which the signal was output to the light source 1. The timing control circuit 3 also notifies the time measurement circuit 10 of the timing at which the reflected light was received, which is notified by the light receiving element 2.

[0018] The time measurement circuit 10 receives notifications from the light receiving element 2 and the timing control circuit 3, and measures the elapsed time from when the light source 1 irradiates the object with light to when the light receiving element 2 receives the reflected light.

[0019] The distance measurement circuit 50 measures the distance from the distance measuring device 60 (light source 1) to the object based on the elapsed time measured by the time measurement circuit 10 and the speed of light.

[0020] In the example of Figure 2, a configuration example in which the time measurement circuit 10 is included in the distance measurement circuit 50 is described, but the time measurement circuit 10 is not limited to this, and may be provided inside the distance measuring device 60 and outside the distance measurement circuit 50.

[0021] Next, a configuration example of the time measurement circuit 10 according to the embodiment 1 will be described. In order to easily understand the features of the time measurement circuit 10 according to the embodiment 1, a configuration example of a time measurement circuit 10b according to a conventional example will be described first as a comparative example, and then a configuration example of the time measurement circuit 10 according to the embodiment 1 will be described.

[0022] <Time measurement circuit 10b> 3 is a diagram showing an example of the configuration of a conventional time measurement circuit 10b, which includes a ring oscillator type TDC 100b.

[0023] The ring oscillator type TDC 100b includes a D flip-flop circuit 11b, a ring oscillator 12b, an OR circuit 13b, a high-speed counter 14b, an edge detection circuit 15b, a flip-flop circuit 16b, an encoder 17b, and a time calculation circuit 18b.

[0024] The D flip-flop circuit 11b receives a value "1" as an input to the D terminal (D input), receives a time measurement start signal EXT_START as a clock input, receives a time measurement stop signal EXT_STOP as a RESET input, and outputs an oscillation enable signal TDC_EN that becomes significant (High) (rises) in response to the input of the start signal EXT_START.

[0025] The ring oscillator 12b oscillates while the oscillation enable signal TDC_EN is active to generate an oscillation signal, and outputs the generated oscillation signal to the OR circuit 13b.

[0026] Specifically, as shown in FIG. 3, the ring oscillator 12b includes a NAND circuit 120b and delay circuits 120b-1 to 120b-3 as delay elements, and D flip-flop circuits 121b-1 to 121b-4.

[0027] The NAND circuit 120b performs a NAND operation on the oscillation enable signal TDC_EN output from the D flip-flop circuit 11b and the output signal of the delay circuit 120b-3, which is the final stage of the delay elements.

[0028] The delay circuits 120b-1 to 120b-3 are cascaded to the output of the NAND circuit 120b. The output signal of the delay circuit 120b-3, which is the final stage, is output to the OR circuit 13b as the oscillation signal, and is also returned to the NAND circuit 120b.

[0029] 3, the D flip-flop circuits 121b-1 to 121b-4 are connected to the output terminals of the NAND circuit 120 and the delay circuits 120b-1 to 120b-3, respectively. The D flip-flop circuits 121b-1 to 121b-4 receive the output signals of the NAND circuit 120 and the delay circuits 120b-1 to 120b-3 as their D inputs, receive the stop signal EXT_STOP as their clock input, and capture and hold the output signals of the NAND circuit 120 and the delay circuits 120b-1 to 120b-3 at the timing when the stop signal EXT_STOP becomes significant (High).

[0030] Although an example in which the ring oscillator 12b includes three delay circuits and four D flip-flop circuits has been described here, the numbers of the delay circuits and the D flip-flop circuits are not limited to the above example.

[0031] The OR circuit 13b generates a first clock ROSC_CLK by performing a logical OR operation on the oscillation signal output from the ring oscillator 12b and the stop signal EXT_STOP. The OR circuit 13b outputs the generated first clock ROSC_CLK to the high-speed counter 14b.

[0032] The high-speed counter 14b counts the first clock ROSC_CLK and generates a count signal HS_CNT indicating the count result. In addition, when the high-speed counter 14b receives a count clear signal HS_CNT_CLR output from an edge detection circuit 15b (described later), the high-speed counter 14b clears (to 0) the count signal HS_CNT indicating the count result.

[0033] 3, HS_CNT[15:0] indicates that the count signal HS_CNT is represented by 16 bits from bit 0 to bit 15. In the following explanation, for the sake of simplicity, the number of bits will be omitted and the signal will simply be referred to as HS_CNT.

[0034] The edge detection circuit 15b detects a rising edge, which is the timing when the stop signal EXT_STOP becomes significant (High), and generates an edge detection signal HS_CNT_TRG that rises in synchronization with the rising edge of the stop signal EXT_STOP, and a count clear signal HS_CNT_CLR that rises slightly after the rising edge of the stop signal EXT_STOP. The edge detection circuit 15b outputs the edge detection signal HS_CNT_TRG to the flip-flop circuit 16b, and the count clear signal HS_CNT_CLR to the high-speed counter 14b.

[0035] The flip-flop circuit 16b receives the count signal HS_CNT output from the high-speed counter 14b as an input, receives the edge detection signal HS_CNT_TRG as a clock input, and takes in and holds the count signal HS_CNT at the rising edge of the edge detection signal HS_CNT_TRG.

[0036] The encoder 17b generates a timing signal HS_PHASE indicating the timing at which the stop signal EXT_STOP is input based on the output signals from the NAND circuit 120 and the delay circuits 120b-1 to 120b-3, which are held in the D flip-flop circuits 121b-1 to 121b-4. The encoder 17b outputs the generated timing signal HS_PHASE to the time calculation circuit 18b.

[0037] The time calculation circuit 18b acquires the count signal HS_CNT held in the flip-flop circuit 16b as a count capture signal HS_CNT_LATCH. The time calculation circuit 18b also calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on the acquired count capture signal HS_CNT_LATCH and the timing signal HS_PHASE output from the encoder 17b.

[0038] In addition, in Fig. 3, HS_CNT_LATCH[15:0] indicates that the count capture signal HS_CNT_LATCH is represented by 16 bits from bit 0 to bit 15. In addition, in Fig. 3, HS_PHASE[2:0] indicates that the timing signal HS_PHASE is represented by 3 bits from bit 0 to bit 2. In the following explanation, for the sake of simplicity, the description of the number of bits will be omitted, and they will simply be referred to as HS_CNT_LATCH and HS_PHASE.

[0039] Next, an example of the operation of the conventional time measurement circuit 10b will be described below with reference to Fig. 4, which is a timing chart showing an example of the operation of the time measurement circuit 10b.

[0040] First, when a time measurement start signal EXT_START is input, the D flip-flop circuit 11b outputs an oscillation enable signal TDC_EN that becomes significant (High) at the rising edge of the start signal EXT_START, as shown in FIG.

[0041] The ring oscillator 12b starts oscillating when the oscillation permission signal TDC_EN output from the D flip-flop circuit 11b becomes active. rTAP[0] to rTAP[3] shown in Fig. 4 indicate the output signals of the NAND circuit 120b and the delay circuits 120b-1 to 120b-3 that constitute the ring oscillator 12b. Fig. 4 shows how the values ​​of rTAP[0] to rTAP[3] change to 0 or 1 over time, which indicates that the ring oscillator 12b is oscillating.

[0042] The OR circuit 13b generates the first clock ROSC_CLK as shown in FIG. 4 by calculating the logical sum of the oscillation signal generated by the ring oscillator 12b and the stop signal EXT_STOP.

[0043] The high-speed counter 14b counts up each time the first clock ROSC_CLK goes from insignificant (Low) to significant (High) (each time it rises), and outputs a count signal HS_CNT indicating the result.

[0044] Thereafter, when the stop signal EXT_STOP is input (becomes significant), the D flip-flop circuit 11b outputs the oscillation permission signal TDC_EN which becomes insignificant (Low) as shown in FIG.

[0045] Furthermore, when the stop signal EXT_STOP becomes active, the D flip-flop circuits 121b-1 to 121b-4 of the ring oscillator 12b capture and hold the output signals (rTAP[0] to rTAP[3] shown in FIG. 4) of the NAND circuit 120b and the delay circuits 120b-1 to 120b-3 at the time when the stop signal EXT_STOP becomes active.

[0046] Furthermore, when the stop signal EXT_STOP becomes active, the edge detection circuit 15b detects the rising edge of the stop signal EXT_STOP, and generates an edge detection signal HS_CNT_TRG that rises in synchronization with the rising edge of the stop signal EXT_STOP, as shown in FIG.

[0047] The flip-flop circuit 16b captures the count signal HS_CNT at the timing when the edge detection signal HS_CNT_TRG rises, and holds the captured signal. The encoder 17b generates a timing signal HS_PHASE indicating the timing when the stop signal EXT_STOP becomes significant, as shown in Fig. 4, based on the output signals (rTAP[0] to rTAP[3]) held in the D flip-flop circuits 121b-1 to 121b-4. The encoder 17b outputs the generated timing signal HS_PHASE to the time calculation circuit 18b.

[0048] The time calculation circuit 18b acquires the count signal HS_CNT held in the flip-flop circuit 16b as a count capture signal HS_CNT_LATCH. The time calculation circuit 18b also calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on the acquired count capture signal HS_CNT_LATCH and the timing signal HS_PHASE output from the encoder 17b.

[0049] For example, the time calculation circuit 18b can grasp how many first clocks ROSC_CLK have been counted between the input of the start signal EXT_START and the input of the stop signal EXT_STOP by referring to the count capture signal HS_CNT_LATCH output from the flip-flop circuit 16b. Therefore, the time calculation circuit 18b can obtain the elapsed time based on the count number by multiplying the count number by the total delay time of the delay elements (here, the NAND circuit 120b and the delay circuits 120b-1 to 120b-3) that constitute the ring oscillator 12b.

[0050] In addition, by referring to the timing signal HS_PHASE output from the encoder 17b, the time calculation circuit 18b can determine to what position among the multiple stages of delay elements that make up the ring oscillator 12b the falling edge of the first clock ROSC_CLK has advanced at the timing when the stop signal EXT_STOP is input.

[0051] For example, in the example of Fig. 4, the timing signal HS_PHASE is "1", which indicates that the rising edge of the first clock ROSC_CLK advances to the position of the output terminal of the second delay circuit 120b-1 from the beginning at the timing when the stop signal EXT_STOP is input. Therefore, the time calculation circuit 18b can obtain the elapsed time based on this position by multiplying the number of delay elements before this position, "2", by the delay time per delay element.

[0052] Therefore, the time calculation circuit 18b can calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP by adding together the elapsed time based on the count number and the elapsed time based on the position. Specifically, the time calculation circuit 18b can calculate the elapsed time by, for example, the following formula (1). Elapsed time=((HS_CNT_LATCH)×g+HS_PHASE)×h (1) Here, g is the total number of delay elements constituting the ring oscillator 12b, and h is the delay time per delay element.

[0053] However, in the conventional time measurement circuit 10b, as shown in Fig. 4, the period from input of the start signal EXT_START to input of the stop signal EXT_STOP (hereinafter, this period is also referred to as the "time measurement period T") includes a period t1 during which the ring oscillator 12b does not rise and time measurement is not possible, and a period t2 during which the ring oscillator 12b rises but the period of the first clock ROSC_CLK is unstable and the accuracy of the time measurement is low. Note that in the following explanation, the above two periods are collectively referred to as the "unstable period".

[0054] The cycle of the first clock ROSC_CLK is unstable until the first clock ROSC_CLK rises for the first time after the start signal EXT_START is input, but it is considered to be stable after the first clock ROSC_CLK rises for the first time after the start signal EXT_START is input. Therefore, here, the end of the period t2 is the timing when the first clock ROSC_CLK rises for the first time after the start signal EXT_START is input.

[0055] As described above, in the conventional time measurement circuit 10b, the time measurement period T includes the unstable period (t1+t2), so that there is a problem in that the final time measurement accuracy is not necessarily good.

[0056] Therefore, in order to solve such problems, the time measurement circuit 10 according to the first embodiment includes a delay line type TDC as an auxiliary circuit for measuring the elapsed time from when the start signal EXT_START is input, particularly during the above-mentioned unstable period of the cycle.

[0057] <Time measurement circuit 10> 5 is a diagram showing an example of the configuration of the time measurement circuit 10 according to the embodiment 1. The time measurement circuit 10 according to the embodiment 1 includes a ring oscillator type TDC 100 and a delay line type TDC 200.

[0058] The ring oscillator type TDC 100 includes a D flip-flop circuit 11, a ring oscillator 12, an OR circuit 13, a high-speed counter 14, an edge detection circuit 15, a flip-flop circuit 16, an encoder 17, and a time calculation circuit 18. Among these, the components other than the time calculation circuit 18 basically have the same functions as the corresponding components of the ring oscillator type TDC 100b in the conventional example, so a repeated description will be omitted. Note that, here, the ring oscillator 12 is configured to include 15 delay circuits and 16 D flip-flop circuits, as shown in FIG. 5.

[0059] The delay line type TDC 200 includes a ROSC detection circuit 21, a delay line 22, a selector 23, an encoder 24, and a memory 25 for storing calibration values.

[0060] The ROSC detection circuit 21 detects the timing at which the oscillation signal (i.e., the first clock ROSC_CLK) first rises after the start signal EXT_START is input, based on the oscillation signal output from the ring oscillator 12. The ROSC detection circuit 21 outputs a rise detection signal ROSC_DET indicating the detected timing to the selector 23 and the time calculation circuit 18.

[0061] As shown in FIG. 5, the delay line 22 is configured to include delay circuits 220-1 to 220-32 as delay elements and D flip-flop circuits 221-1 to 221-32.

[0062] Note that the total delay time by the delay circuits 220-1 to 220-32 is configured to be equal to or greater than the sum of the time for one cycle of the first clock ROSC_CLK generated by the ring oscillator 12 and the time from when the start signal EXT_START is input until the ring oscillator 12 starts oscillating.

[0063] The delay circuits 220-1 to 220-32 are connected to the output terminal of the start signal EXT_START. The output signal of the delay circuit 220-32, which is the last stage, is output to the time calculation circuit 18.

[0064] As shown in FIG. 5, the D flip-flop circuits 221-1 to 221-32 are connected to the respective output terminals of the delay circuits 220-1 to 220-32. The D flip-flop circuits 221-1 to 221-32 take the output signals of the delay circuits 220-1 to 220-32 as D inputs respectively, take the output signal from the selector 23 as a clock input, and capture and hold the output signals of the delay circuits 220-1 to 220-32 according to the output signal from the selector 23.

[0065] The selector 23 takes the stop signal EXT_STOP as the first input, the rising edge detection signal ROSC_DET output from the ROSC detection circuit 21 as the second input, and the externally input calibration permission signal CALIB_EN as a control input. When the control input is "0", it selects and outputs the first input side, and when the control input is "1", it selects and outputs the second input side. That is, the selector 23 outputs either the stop signal EXT_STOP or the rising edge detection signal ROSC_DET according to the control input.

[0066] The encoder 24 generates a time calculation signal DLY_ENC_PHASE for calculating the elapsed time from the input of the start signal EXT_START until the first rising edge of the first clock ROSC_CLK is detected, based on the output signal DLY_PHASE held in the D flip-flop circuits 221-1 to 221-32. The encoder 24 outputs the generated time calculation signal DLY_ENC_PHASE to the time calculation circuit 18.

[0067] The time calculation circuit 18 calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on the count capture signal HS_CNT_LATCH output from the flip-flop circuit 16, the timing signal HS_PHASE output from the encoder 17, the rising edge detection signal ROSC_DET output from the ROSC detection circuit 21, and the time calculation signal DLY_ENC_PHASE output from the encoder 24. In this calculation, the time calculation circuit 18 uses a calibration value stored in a calibration value storage memory 25, which will be described later.

[0068] The calibration value storage memory 25 is a memory circuit that stores the calibration values. The calibration values ​​will be described later.

[0069] Here, an example has been described in which the ring oscillator 12 is configured to include 15 delay circuits and 16 D flip-flop circuits, and the delay line 22 is configured to include 31 delay circuits and 31 D flip-flop circuits, but the numbers of each delay circuit and D flip-flop circuit are not limited to the above examples.

[0070] Next, a description will be given of an example of the operation of the time measurement circuit 10 according to the embodiment 1. The time measurement circuit 10 according to the embodiment 1 operates in, for example, the following two patterns. (Pattern 1) The timing at which the stop signal EXT_STOP is input is earlier than or the same as the timing at which the first clock ROSC_CLK first rises after the start signal EXT_START is input. (Pattern 2) When the timing at which the stop signal EXT_STOP is input is later than the timing at which the first clock ROSC_CLK first rises after the start signal EXT_START is input

[0071] In the case of pattern 1, the time measurement circuit 10 (time calculation circuit 18) uses the elapsed time calculated based on the signal (time calculation signal DLY_ENC_PHASE) output by the delay line type TDC 200 as the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP.

[0072] In the case of pattern 2, the time measurement circuit 10 (time calculation circuit 18) calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on both the elapsed time calculated based on the signal (time calculation signal DLY_ENC_PHASE) output by the delay line type TDC 200 and the elapsed time based on the counting result of the counter obtained by the ring oscillator type TDC 100. Below, an example of the operation of the time measurement circuit 10 in each pattern will be described while showing a timing chart for each pattern.

[0073] (Example of operation in Pattern 1) Fig. 6 is a timing chart showing an example of the operation of the time measurement circuit 10 in pattern 1. Note that Fig. 6 shows a timing chart in which the timing at which the stop signal EXT_STOP is input precedes the timing at which the first clock ROSC_CLK first rises after the start signal EXT_START is input, but the operation example in which the two timings are the same is also similar.

[0074] In the example shown in FIG. 6, the timing at which the stop signal EXT_STOP is input occurs before the timing at which the first clock ROSC_CLK first rises after the start signal EXT_START is input. Therefore, the time measurement period T2, which is the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP, measured by the delay line type TDC 200 is less than one period of the first clock ROSC_CLK.

[0075] When operation in pattern 1 is assumed, the selector 23 of the delay line type TDC 200 receives “0” as the control input (calibration enable signal CALIB_EN).

[0076] First, when a time measurement start signal EXT_START is input, measurement is started by both the ring oscillator type TDC 100 and the delay line type TDC 200. The measurement procedure by the ring oscillator type TDC 100 is basically the same as the measurement procedure by the ring oscillator type TDC 100b in the above-mentioned conventional example.

[0077] On the other hand, in the delay line type TDC 200, the start signal EXT_START is input to the delay line 22, and the start signal EXT_START passes through each of the delay circuits 220-1 to 220-32 in sequence. After that, before the first clock ROSC_CLK generated by the ring oscillator 12 rises, the stop signal EXT_STOP is input.

[0078] At this time, since the calibration enable signal CALIB_EN input to the selector 23 is "0", the selector 23 selects and outputs the stop signal EXT_STOP.

[0079] Upon receiving the output from the selector 23, the D flip-flop circuits 221-1 to 221-32 of the delay line 22 capture and hold the output signals (rTAP[0] to rTAP

[31] shown in FIG. 6) of the delay circuits 220-1 to 220-32 at the timing when the stop signal EXT_STOP becomes active (High).

[0080] Based on the output signals held in the D flip-flop circuits 221-1 to 221-32, the encoder 24 generates a time calculation signal DLY_ENC_PHASE for calculating the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP during the period from the input of the start signal EXT_START to the detection of the first rising edge of the first clock ROSC_CLK, as shown in FIG. 6, and outputs the generated signal to the time calculation circuit 18.

[0081] The time calculation circuit 18 calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on the time calculation signal DLY_ENC_PHASE output by the encoder 24. For example, in the example of Fig. 6, the time calculation signal DLY_ENC_PHASE output by the encoder 24 indicates "29". This indicates that at the timing when the stop signal EXT_STOP is input, the rising edge of the start signal EXT_START reaches the position of the output terminal of the 29th delay circuit 220-29 from the beginning among the multiple stages of delay circuits that make up the delay line 22.

[0082] Therefore, the time calculation circuit 18 can calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP by multiplying the delay time per delay circuit by "29." The time calculation circuit 18 then uses the elapsed time obtained as described above as the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP. In this case, the time calculation circuit 18 discards the elapsed time obtained based on the measurement result in the ring oscillator type TDC 100.

[0083] In this case, the time calculation circuit 18 may temporarily store the time calculation signal DLY_ENC_PHASE ("29" in the above example) output by the encoder 24 in the calibration value storage memory 25, read out the time calculation signal DLY_ENC_PHASE stored in the calibration value storage memory 25, and calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP.

[0084] In pattern 1, the time measurement period T2 by the delay line TDC 200 is included in the unstable period described above. However, since the delay line 22 in the delay line TDC 200 is configured by arranging delay circuits, which are delay elements, in series for the time to be measured, unlike the ring oscillator 12 in the ring oscillator TDC 100, there is no waiting time (oscillation start waiting time) until the ring oscillator 12 starts oscillating. Therefore, the delay line TDC 200 can start operating promptly when the start signal EXT_START is input. Therefore, there is no problem with the accuracy of the time calculation signal DLY_ENC_PHASE output from the delay line TDC 200 in pattern 1 even if it is output during the unstable period described above.

[0085] Therefore, even during the above-mentioned unstable period of cycles, the time calculation circuit 18 can accurately calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP by calculating the elapsed time using the time calculation signal DLY_ENC_PHASE output from the delay line type TDC 200, thereby making it possible to improve the accuracy of the calculation results compared to the conventional method.

[0086] (Example of operation in pattern 2) FIG. 7 is a timing chart showing an example of the operation of the time measurement circuit 10 in pattern 2. In FIG.

[0087] In the example shown in FIG. 7, the timing at which the stop signal EXT_STOP is input is later than the timing at which the first clock ROSC_CLK first rises after the start signal EXT_START is input. Therefore, the time measurement period T3 of the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP by the delay line type TDC 200 is longer than one period of the first clock ROSC_CLK.

[0088] When operation in pattern 2 is assumed, the selector 23 of the delay line type TDC 200 receives “1” as the control input (calibration enable signal CALIB_EN).

[0089] First, when a time measurement start signal EXT_START is input, measurement begins in both the ring oscillator type TDC 100 and the delay line type TDC 200. The measurement procedure by the ring oscillator type TDC 100 is basically the same as the measurement procedure by the ring oscillator type TDC 100b in the above-mentioned conventional example.

[0090] On the other hand, in the delay line type TDC 200, the start signal EXT_START is input to the delay line 22, and the start signal EXT_START passes through each of the delay circuits 220-1 to 220-32 in sequence. After that, before the stop signal EXT_STOP is input, the first clock ROSC_CLK generated by the ring oscillator 12 rises.

[0091] When the first clock ROSC_CLK rises, the ROSC detection circuit 21 detects the rising edge of the first clock ROSC_CLK, and outputs to the selector 23 a rising edge detection signal ROSC_DET indicating the detected timing.

[0092] At this time, since the calibration enable signal CALIB_EN input to the selector 23 is "1", the selector 23 selects and outputs the rising edge detection signal ROSC_DET output from the ROSC detection circuit 21.

[0093] Upon receiving the output from the selector 23, the D flip-flop circuits 221-1 to 221-32 of the delay line 22 capture and hold the output signals of the delay circuits 220-1 to 220-32 (rTAP[0] to rTAP

[31] shown in FIG. 7) at the timing when the first clock ROSC_CLK first rises.

[0094] Based on the output signals held in the D flip-flop circuits 221-1 to 221-32, the encoder 24 generates a time calculation signal DLY_ENC_PHASE for calculating the elapsed time from the input of the start signal EXT_START to the detection of the first rising edge of the first clock ROSC_CLK, as shown in FIG. 7, and outputs the generated signal to the time calculation circuit 18.

[0095] The time calculation circuit 18 calculates the elapsed time from the input of the start signal EXT_START to the first rising edge of the first clock ROSC_CLK based on the time calculation signal DLY_ENC_PHASE output by the encoder 24. For example, in the example of Fig. 7, the time calculation signal DLY_ENC_PHASE output by the encoder 24 indicates "31". This indicates that at the timing when the first rising edge of the first clock ROSC_CLK is detected, the rising edge of the start signal EXT_START has reached the position of the output terminal of the last delay circuit 220-32 among the multiple stages of delay circuits that make up the delay line 22.

[0096] Therefore, the time calculation circuit 18 can calculate the elapsed time from the input of the start signal EXT_START to the detection of the first rising edge of the first clock ROSC_CLK by multiplying the delay time per delay circuit by "31".

[0097] The time calculation circuit 18 stores the time calculation signal DLY_ENC_PHASE ("31" in the example of FIG. 7) output by the encoder 24 in the calibration value storage memory 25 as a calibration value.

[0098] After that, as shown in Fig. 7, the stop signal EXT_STOP is input, but as described above, it is considered that the period of the first clock ROSC_CLK is stabilized after the first rising edge of the first clock ROSC_CLK is detected. Therefore, during the period from when the first rising edge of the first clock ROSC_CLK is detected until the stop signal EXT_STOP is input (the "ring oscillator measurement period (2)" shown in Fig. 7), it is acceptable to use the measurement result based on the count result of the first clock ROSC_CLK counted by the ring oscillator type TDC 100.

[0099] For example, when a stop signal EXT_STOP is input, the time calculation circuit 18 calculates the elapsed time from the rising edge of the first clock ROSC_CLK to the input of the stop signal EXT_STOP based on the count capture signal HS_CNT_LATCH output from the flip-flop circuit 16 and the timing signal HS_PHASE output from the encoder 17.

[0100] In this case, however, the elapsed time from when the start signal EXT_START is input until the first clock ROSC_CLK first rises has already been calculated based on the time calculation signal DLY_ENC_PHASE output from the delay line type TDC 200. Therefore, the time calculation circuit 18 calculates the elapsed time in the ring oscillator measurement period (2) by using a value obtained by subtracting 1 from the count value indicated by the count capture signal HS_CNT_LATCH output from the flip-flop circuit 16.

[0101] Then, the time calculation circuit 18 can calculate the final elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP by adding together the elapsed time calculated based on the time calculation signal DLY_ENC_PHASE output from the delay line type TDC 200 (the elapsed time in the time measurement period T3) and the elapsed time calculated in the ring oscillator measurement period (2).

[0102] Specifically, the time calculation circuit 18 calculates the elapsed time, for example, by the following formula (2). Elapsed time=((HS_CNT_LATCH-1)×g+Cal+HS_PHASE)×h (2) Here, g is the total number of delay elements constituting the ring oscillator 12, h is the delay time per delay element, and Cal is the calibration value stored in the calibration value storage memory 25.

[0103] In addition, in pattern 2, the time measurement period T3 by the delay line TDC 200 is also included in the above-mentioned unstable period. However, since the delay line 22 in the delay line TDC 200 is configured by arranging delay circuits, which are delay elements, in series for the time to be measured, unlike the ring oscillator 12 in the ring oscillator TDC 100, there is no waiting time (oscillation start waiting time) until the ring oscillator 12 starts oscillating. Therefore, the delay line TDC 200 can start operating promptly when the start signal EXT_START is input. Therefore, in pattern 2, the accuracy of the time calculation signal DLY_ENC_PHASE output from the delay line TDC 200 does not matter even if it is output during the above-mentioned unstable period.

[0104] Therefore, by using the above-described calculation method, the time calculation circuit 18 can accurately calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP, and can improve the accuracy of the calculation result compared to the conventional method.

[0105] (Effects of the time measurement circuit 10 and the distance measuring device 60) Next, effects of the time measurement circuit 10 according to the first embodiment and the distance measuring device 60 including the time measurement circuit 10 will be described.

[0106] As described above, the time measurement circuit 10 according to the first embodiment includes a delay line TDC 200 as an auxiliary circuit for measuring the elapsed time from input of the start signal EXT_START, particularly during the unstable cycle period (the period from input of the start signal EXT_START to detection of the first rising edge of the first clock ROSC_CLK). The delay line TDC 200 outputs a time calculation signal DLY_ENC_PHASE for calculating the elapsed time from input of the start signal EXT_START during the unstable cycle period.

[0107] As described above, the delay line 22 in the delay line TDC 200 is configured by arranging delay circuits, which are delay elements, in series for the time to be measured, and therefore, unlike the ring oscillator 12 in the ring oscillator TDC 100, there is no waiting time (oscillation start waiting time) until the ring oscillator 12 starts oscillating. Therefore, even during the above-mentioned unstable period of the cycle, the time calculation circuit 18 can accurately calculate the elapsed time from the input of the start signal EXT_START by calculating the elapsed time using the time calculation signal DLY_ENC_PHASE output from the delay line TDC 200, and as a result, the calculation accuracy of the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP can be improved compared to the conventional method.

[0108] Furthermore, the time measurement circuit 10 and distance measuring device 60 according to the first embodiment have the following advantages. (1) It solves the problem of the minimum distance to a measurable object (minimum measurement distance) becoming long. (2) The maximum measurement distance can be extended without uniformly arranging a large number of delay elements. (3) It is not affected by the recovery time violation and removal time violation in the D flip-flop circuit.

[0109] For example, with respect to (1) above, in the distance measuring device 60 including the time measurement circuit 10, it is possible to solve the problem that the minimum distance to an object that can be measured (minimum measurement distance) becomes long.

[0110] For example, as already explained, in conventional time measurement circuits, the first certain period after starting the ring oscillator (for example, about 2 ns (=0.5 ns + 1.6 ns)) is a period of periodic instability, and accurate time measurement may not be possible. If the speed of light in air (speed of light) is 300,000 km / sec and the round trip time it takes for the light to return to the distance measuring device is 2 ns, then the one-way time from the distance measuring device to the target object is 1 ns, and therefore the distance from the distance measuring device to the target object can be calculated using the following formula (3). (1×10 -9 )×(30×10000×1000)=0.3m (3)

[0111] In other words, if accurate time measurement cannot be performed for the first approximately 2 ns after the ring oscillator is started, a distance measuring device equipped with a conventional time measurement circuit will be unable to perform accurate distance measurement when the distance between the distance measuring device (light source) and the target object is 0.3 m or less. Furthermore, the inability to perform accurate distance measurement when the distance to the target object is 0.3 m or less may hinder the expansion of applicable applications when the distance measuring device is used for object detection on a production line, dimensional measurement, robot control, and the like.

[0112] In this regard, as described above, the time measurement circuit 10 according to the first embodiment can perform accurate time measurement even during the first predetermined time period after starting the ring oscillator 12. Therefore, the distance measuring device 60 including the time measurement circuit 10 can also solve the problem that the minimum distance to a measurable object (minimum measurement distance) becomes long.

[0113] Regarding (2) above, in the distance measuring device 60 according to the first embodiment, the maximum distance to a measurable object (maximum measurement distance) can be extended without uniformly arranging a large number of delay elements in the time measurement circuit 10.

[0114] For example, although the minimum measurement distance was mentioned above, if the distance measuring device is to be used for object detection on a production line, a maximum measurement distance of about 10 m is required. In this case, the one-way time required for light to reach an object 10 m away is about 33 ns according to the following formula (4). (33×10 -9 )×(30×10000×1000)=9.9m (4)

[0115] Also, because the time needs to be measured both ways, doubling the approximately 33 ns results in a maximum measurement time of approximately 66 ns. Commonly known TDCs are configured with delay elements connected in series, but if a delay element with a delay time of 50 ps is selected to be able to measure a time difference of approximately 66 ns, the number of delay elements required will be 1200, according to the following equation (5). However, it is difficult to arrange 1200 delay elements so that each has a uniform delay value (delay time). 66ns / 50ps=1200 (5)

[0116] In this regard, in the time measurement circuit 10 according to the first embodiment, the number of delay elements required can be reduced by using the value obtained by counting the rising edges of the output signal of the final stage of the delay element as the time measurement value. For example, in the example shown in Fig. 5, the ring oscillator 12 includes 16 stages of delay elements including the NAND circuit 120. If the delay time of one stage of the delay element is 50 ps, ​​a signal with a period of 1600 ps (=50 ps x 2 x 16) can be obtained, such as the first clock ROSC_CLK in the timing chart shown in Fig. 6. Then, in the time measurement circuit 10, the rising edges of this signal can be counted to perform time measurement with a resolution of 1600 ps.

[0117] Furthermore, the time measurement circuit 10 can also measure time with a resolution of 50 ps by using the total 16-bit value of rTAP[0] to rTAP

[15] , which is the output signal of each delay element, for time measurement. In other words, by using a value obtained by combining the count number of the first clock ROSC_CLK and the value of rTAP[15:0] as the measurement value of the elapsed time, the distance measuring device 60 equipped with the time measurement circuit 10 can extend the maximum measurement distance without arranging many delay elements uniformly.

[0118] Regarding the above (3), the time measurement circuit 10 according to the first embodiment has the advantage that it is not affected by the recovery time violation and removal time violation in the D flip-flop circuit 11.

[0119] For example, in the conventional time measurement circuit 10b shown in FIG. 3, the oscillation enable signal TDC_EN is generated by the D flip-flop circuit 11b. In this case, as shown in FIG. 3, the time measurement start signal EXT_START is connected to the clock terminal of the D flip-flop circuit 11b, and the time measurement stop signal EXT_STOP is connected to the reset terminal of the D flip-flop circuit 11b.

[0120] However, when measuring a very short time, for example when the rising edge of the start signal EXT_START and the rising edge of the stop signal EXT_STOP are very close to each other, the time measurement circuit 10b may violate the restriction of the period during which the reset signal must not change with respect to the rising edge of the clock, called the removal time and recovery time. In this case, the value of the oscillation enable signal TDC_EN in the time measurement circuit 10b becomes indefinite, and as a result, the time measured by the ring oscillator 12b may become an unreliable value.

[0121] In this regard, in the time measurement circuit 10 of embodiment 1, as described in the above pattern 1, in a period equal to or less than one cycle of the first clock ROSC_CLK generated by the ring oscillator 12, the measurement time obtained based on the measurement result in the ring oscillator type TDC 100 is discarded, and the measurement time based on the time calculation signal DLY_ENC_PHASE output from the delay line type TDC 200 is used as the final measurement time, so that the circuit is not affected by violations of the recovery time and removal time as described above.

[0122] As described above, according to the first embodiment, the time measurement circuit 10 includes a ring oscillator 12 configured to generate a first clock ROSC_CLK during the period from input of the time measurement start signal EXT_START to input of the time measurement stop signal EXT_STOP, a counter 14 that counts the first clock ROSC_CLK, an auxiliary circuit (delay line type TDC) 200 that outputs a time calculation signal DLY_ENC_PHASE for calculating the elapsed time from input of the start signal EXT_START during the period from input of the start signal EXT_START to detection of the first rising edge of the first clock ROSC_CLK, and a time calculation circuit 18 that calculates the elapsed time from input of the start signal EXT_START to input of the stop signal EXT_STOP based on the calculation result based on the time calculation signal DLY_ENC_PHASE output by the auxiliary circuit 200, or based on the calculation result based on the time calculation signal DLY_ENC_PHASE output by the auxiliary circuit 200 and the counting result by the counter 14. As a result, the time measurement circuit 10 according to the first embodiment can improve the accuracy of time measurement in a time measurement circuit using a ring oscillator type TDC as compared to the conventional technology.

[0123] Further, when the input timing of the stop signal EXT_STOP is before the detection timing of the first rising edge of the first clock ROSC_CLK, the time calculation circuit 18 uses the calculation result based on the time calculation signal DLY_ENC_PHASE output by the auxiliary circuit 200 as the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP. When the input timing of the stop signal EXT_STOP is after the detection timing of the first rising edge of the first clock ROSC_CLK, the time calculation circuit 18 calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on the calculation result based on the time calculation signal DLY_ENC_PHASE output by the auxiliary circuit 200 and the counting result by the counter 14. Thereby, the time measurement circuit 10 according to the first embodiment can accurately calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP according to the input timing of the stop signal EXT_STOP.

[0124] Also, when the input timing of the stop signal EXT_STOP is after the detection timing of the first rising edge of the first clock ROSC_CLK, the time calculation circuit 18 adds the elapsed time from the input of the start signal EXT_START to the detection timing of the first rising edge of the first clock ROSC_CLK, calculated based on the time calculation signal DLY_ENC_PHASE output by the auxiliary circuit 200, and the elapsed time from the detection timing of the first rising edge of the first clock ROSC_CLK to the input timing of the stop signal EXT_STOP, calculated based on the counting result by the counter 14, to calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP. Thereby, the time measurement circuit 10 according to the first embodiment can accurately calculate the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP when the input timing of the stop signal EXT_STOP is after the detection timing of the first rising edge of the first clock ROSC_CLK.

[0125] The auxiliary circuit 200 is also configured to include a delay line 22 configured by connecting a plurality of delay elements 220 that delay the start signal EXT_START, a flip-flop circuit 221 connected to each of the plurality of delay elements 220 that configure the delay line 22, a selector 23 that outputs a clock to each flip-flop circuit 221 for holding an output signal from the corresponding delay element 220, and an encoder 24 that generates a time calculation signal DLY_ENC_PHASE based on the output signal held in each flip-flop circuit in response to the clock output from the selector 23. As a result, the time measurement circuit 10 according to the first embodiment can realize the auxiliary circuit 200 with a simple configuration.

[0126] Furthermore, the selector 23 outputs a clock to each flip-flop circuit 221 for holding an output signal from the corresponding delay element 220 at the timing when the stop signal EXT_STOP is input or at the timing when the first rising edge of the first clock ROSC_CLK is detected after the start signal EXT_START is input. This allows the time measurement circuit 10 according to the first embodiment to generate the time calculation signal DLY_ENC_PHASE both at the timing when the stop signal EXT_STOP is input or at the timing when the first rising edge of the first clock ROSC_CLK is detected after the start signal EXT_START is input.

[0127] Furthermore, the total delay time of the multiple delay elements 220 that make up the delay line 22 is equal to or greater than the sum of one cycle of the first clock ROSC_CLK and the time from when the start signal EXT_START is input until when the ring oscillator 12 starts oscillating. This allows the time measurement circuit 10 according to the first embodiment to accurately calculate the elapsed time from when the start signal EXT_START is input until when the first rising edge of the first clock ROSC_CLK is detected.

[0128] The auxiliary circuit 200 also includes a detection circuit 21 that detects the first rising edge of the first clock ROSC_CLK after the start signal EXT_START is input. This allows the time measurement circuit 10 according to the first embodiment to accurately detect the first rising edge of the first clock ROSC_CLK after the start signal EXT_START is input.

[0129] Moreover, the auxiliary circuit 200 includes a memory circuit (memory for storing calibration values) 25 for storing the time calculation signal DLY_ENC_PHASE, and the time calculation circuit 18 calculates the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP based on the calculation result based on the time calculation signal DLY_ENC_PHASE stored in the memory circuit 25, or based on the calculation result based on the time calculation signal DLY_ENC_PHASE stored in the memory circuit 25 and the counting result by the counter 14. This allows the time measurement circuit 10 according to the first embodiment to accurately calculate the elapsed time while storing the time calculation signal DLY_ENC_PHASE.

[0130] According to the first embodiment, the distance measuring device 60 includes a light source 1 that emits light to an object, a light receiving element 2 that receives the light emitted from the light source 1 and reflected by the object, the time measurement circuit 10 in which the input timing of the time measurement start signal EXT_START corresponds to the timing of light emission by the light source 1 and the input timing of the time measurement stop signal EXT_STOP corresponds to the timing of light reception by the light receiving element 2, and a distance measurement circuit 50 that measures the distance to the object using the elapsed time from the input of the start signal EXT_START to the input of the stop signal EXT_STOP calculated by the time measurement circuit 10 and the speed of light. Thus, the distance measuring device 60 according to the first embodiment can improve the distance measurement accuracy compared to the conventional art and can solve the problem that the minimum distance to the object that can be measured (minimum measurement distance) becomes long.

[0131] It should be noted that, within the scope of the present disclosure, any of the components of the embodiments may be modified or any of the components of the embodiments may be omitted. [Explanation of symbols]

[0132] 1 light source 2 Light receiving element 3 Timing control circuit 10, 10b Time measurement circuit 11, 11b D flip-flop circuit 12, 12b Ring Oscillator 13, 13b OR circuit 14, 14b High-speed counter (counter) 15, 15b Edge detection circuit 16, 16b flip-flop circuit 17, 17b Encoder 18, 18b Time calculation circuit 21 ROSC detection circuit 22 Delay Lines 23 Selector 24 Encoder 25 Memory for storing calibration values ​​(memory circuit) 50 Distance measurement circuit 60 Ranging device 100, 100b Ring oscillator type TDC 120, 120b NAND circuit 200 Delay line type TDC (auxiliary circuit) 220 Delay circuit (delay element) 221 D Flip-Flop Circuit

Claims

1. a ring oscillator configured to generate a first clock during a period from when a time measurement start signal is input to when a time measurement stop signal is input; a counter that counts the first clock; an auxiliary circuit that outputs a time calculation signal for calculating an elapsed time from the input of the start signal until the first rising edge of the first clock is detected; a time calculation circuit that calculates an elapsed time from the input of the start signal to the input of the stop signal based on a calculation result based on the time calculation signal output by the auxiliary circuit, or based on the calculation result based on the time calculation signal output by the auxiliary circuit and a counting result by the counter; A time measurement circuit comprising:

2. The time calculation circuit includes: when the input timing of the stop signal is before the detection timing of the first rising edge of the first clock, a calculation result based on the time calculation signal output by the auxiliary circuit is set as the elapsed time from the input of the start signal to the input of the stop signal; When the input timing of the stop signal is after the detection timing of the first rising edge of the first clock, the elapsed time from the input of the start signal to the input of the stop signal is calculated based on a calculation result based on the time calculation signal output by the auxiliary circuit and a counting result by the counter.

2. The time measurement circuit according to claim 1.

3. The time calculation circuit includes: When the input timing of the stop signal is after the detection timing of the first rising edge of the first clock, an elapsed time from the input of the start signal to the detection timing of the first rising edge of the first clock, the elapsed time being calculated based on the time calculation signal output by the auxiliary circuit; The time elapsed from the input of the start signal to the input of the stop signal is calculated by adding up the time elapsed from the detection timing of the first rising edge of the first clock to the input timing of the stop signal, the time elapsed from the input of the start signal to the input of the stop signal, which is calculated based on the counting result by the counter.

3. The time measurement circuit according to claim 2.

4. The auxiliary circuit includes: a delay line configured by connecting a plurality of delay elements that delay the start signal; a flip-flop circuit connected to each of the plurality of delay elements constituting the delay line; a selector that outputs a clock to each of the flip-flop circuits for holding an output signal from the corresponding delay element; an encoder that generates the time calculation signal based on the output signals held in the flip-flop circuits in response to the clock output from the selector; 4. The time measurement circuit according to claim 1, further comprising:

5. The selector: At the timing when the stop signal is input or at the timing when the first rising edge of the first clock is detected after the input of the start signal, a clock for holding an output signal from the corresponding delay element is output to each of the flip-flop circuits.

5. The time measurement circuit according to claim 4.

6. The total delay time of the plurality of delay elements constituting the delay line is is equal to or greater than the sum of the time for one cycle of the first clock and the time from when the start signal is input until when the ring oscillator starts oscillating.

5. The time measurement circuit according to claim 4.

7. The auxiliary circuit includes:

5. The time measurement circuit according to claim 4, further comprising a detection circuit for detecting the first rising edge of the first clock after the start signal is input.

8. the auxiliary circuit includes a memory circuit for storing the time calculation signal; The time calculation circuit includes: Calculates the elapsed time from the input of the start signal to the input of the stop signal based on a calculation result based on the time calculation signal stored in the memory circuit, or based on the calculation result based on the time calculation signal stored in the memory circuit and the counting result by the counter.

5. The time measurement circuit according to claim 4.

9. a light source that emits light onto an object; a light receiving element that receives light emitted from the light source and reflected by the object; a time measurement circuit according to any one of claims 1 to 3, wherein an input timing of a time measurement start signal corresponds to a timing of light emission by the light source, and an input timing of a time measurement stop signal corresponds to a timing of light reception by the light receiving element; a distance measurement circuit that measures a distance to the object using the elapsed time from the input of the start signal to the input of the stop signal, which is calculated by the time measurement circuit, and the speed of light; A distance measuring device comprising:

10. A time measurement method using a time measurement circuit, a ring oscillator generates a first clock during a period from when a time measurement start signal is input to when a time measurement stop signal is input; a counter counting the first clock; an auxiliary circuit outputs a time calculation signal for calculating an elapsed time from the input of the start signal until a first rising edge of the first clock is detected; A time calculation circuit calculates an elapsed time from the input of the start signal to the input of the stop signal based on a calculation result based on the time calculation signal output by the auxiliary circuit, or based on the calculation result based on the time calculation signal output by the auxiliary circuit and a counting result by the counter. A time measurement method comprising:

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