Delta sigma modulator and delta sigma modulation method

Abstract

To provide technology that makes is possible to suppress a computation error due to discontinuity by a simple configuration.SOLUTION: A delta sigma modulator (1000, 1400, 2000) comprises: a distribution unit (110, 2010) for dividing an input signal into a plurality of signal blocks; a parallel circuit unit (120, 2020) including two or more filter circuits, each of the two or more filter circuits including two or more delta sigma modulation circuits including different initial values; and a combining unit (130, 2030) for executing combining processing to combine a plurality of output signals. The combining unit executes combining processing by using the output selection signal of the delta sigma modulation circuit for processing a leading signal block among the plurality of signal blocks and the initial values.SELECTED DRAWING: Figure 20

Description

[Technical field]

[0001] The present disclosure relates to a delta-sigma modulation device and a delta-sigma modulation method. [Background technology]

[0002] In the field of wireless communication, technological developments are underway to achieve high-speed communication in order to cope with increasing traffic.

[0003] Usually, to realize high-speed communication, a wireless communication device needs to have a high-speed and high-precision digital-to-analog converter (DAC). However, since the price and power consumption of such a DAC are generally high, there is a problem that the manufacturing cost and power consumption of a wireless communication device equipped with a DAC are generally high.

[0004] In order to solve the above-mentioned problems, a delta-sigma modulation device can be used. The delta-sigma modulation device converts a multi-bit digital signal, which is an input signal, into a bit string of one bit, and outputs the bit string as an output signal. The output signal is passed through a band-pass filter having a pass band equal to the signal band of the input signal. This makes it possible to obtain an analog signal that is almost equivalent to the input signal.

[0005] The use of a delta-sigma modulator eliminates the need for a DAC, thereby reducing the manufacturing costs and power consumption of wireless communication devices. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2005-6273 A [Patent Document 2] Patent No. 7072734 Summary of the Invention [Problem to be solved by the invention]

[0007] For example, when processing a high-speed digital signal having a sampling frequency exceeding 1 G samples / second, it is difficult to process such a digital signal using only one delta-sigma modulation circuit. Patent Document 1 discloses multiple delta-sigma modulation circuits arranged in parallel. This configuration makes it possible to process high-speed digital signals.

[0008] On the other hand, in a plurality of delta-sigma modulation circuits arranged in parallel, there is a problem that a calculation error occurs near the boundary between signal blocks of the output signal. Patent Document 2 discloses a configuration for suppressing the calculation error. However, the configuration disclosed in Patent Document 2 has a plurality of conditional branches, and therefore the processing is complicated. The configuration disclosed in Patent Document 2 is not suitable for the above-mentioned plurality of delta-sigma modulation circuits arranged in parallel that are required to process high-speed digital signals.

[0009] The present disclosure provides a technique that can suppress calculation errors with a simpler configuration than the related techniques described above (for example, Patent Document 2). [Means for solving the problem]

[0010] The delta-sigma modulation device of the present disclosure includes a distribution unit that divides an input signal into a plurality of signal blocks, a parallel circuit unit including two or more filter circuits arranged in parallel and performing delta-sigma modulation processing on the plurality of signal blocks to output a plurality of output signals corresponding to the plurality of signal blocks, each of the two or more filter circuits including two or more delta-sigma modulation circuits having different initial values, and a combination unit that performs a combination process to combine the plurality of output signals. The two or more delta-sigma modulation circuits perform the delta-sigma modulation processing on the same signal block to output the output signal, and output an output selection signal for combining the plurality of output signals. The combination unit performs the combination process using the output selection signal of the delta-sigma modulation circuit that processes a preceding signal block of the plurality of signal blocks and the initial value.

[0011] A delta-sigma modulation method according to the present disclosure includes: dividing an input signal into a plurality of signal blocks; inputting the plurality of signal blocks to two or more filter circuits to output a plurality of output signals corresponding to the plurality of signal blocks; and performing a combining process to combine the plurality of output signals. The two or more filter circuits are arranged in parallel, and each of the two or more filter circuits includes two or more delta-sigma modulation circuits including different initial values. The delta-sigma modulation method further includes: performing a delta-sigma modulation process on the same signal block using the two or more delta-sigma modulation circuits to output the output signal, and outputting an output selection signal for combining the plurality of output signals; and performing the combining process using the output selection signal of the delta-sigma modulation circuit that processes a preceding signal block of the plurality of signal blocks and the initial value. Effect of the Invention

[0012] According to the above configuration, it is possible to suppress calculation errors with a simpler configuration than the related art. Problems, configurations, and effects other than those described above will become apparent from the description of the following embodiments. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 illustrates an example of the configuration of a delta-sigma modulation device 10. [Diagram 2] FIG. 2 is a diagram illustrating an example of the configuration of a delta-sigma modulation circuit 200. [Diagram 3] FIG. 2 is a diagram illustrating an example of the configuration of a delta-sigma modulation circuit 300. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of an error feedback type delta-sigma modulation circuit 400. [Diagram 5] 1 is a diagram showing an example of the relationship between an input signal to a parallel circuit section 120 and an output signal from a combining section 130. FIG. [Figure 6]It is a table showing the circuit state of the delta-sigma modulation circuit 121-1 in the process of processing the signal block #J. [Figure 7] It is a table showing the circuit state of the delta-sigma modulation circuit 122-1 in the process of processing the signal block #J+1. [Figure 8] It is a table showing the circuit state of the delta-sigma modulation circuit 122-1 in the process of processing the signal block #J+1. [Figure 9] It is a graph showing an example of the calculation error due to discontinuity calculated by simulation. [Figure 10] It is a diagram showing an example of the configuration of the delta-sigma modulation device 1000. [Figure 11] It is a diagram showing an example of the configuration of the error feedback type delta-sigma modulation circuit 1100. [Figure 12] It is a table showing the circuit state of the delta-sigma modulation circuit 121-n in the process of processing the signal block #J. [Figure 13] It is a table showing the circuit state of the delta-sigma modulation circuit 122-n in the process of processing the signal block #J+1. [Figure 14] It is a diagram showing an example of the configuration of the delta-sigma modulation device 1400. [Figure 15] It is a table showing the circuit state of the delta-sigma modulation circuit 121-n in the process of processing the signal block #J. [Figure 16] It is a table showing the circuit state of the delta-sigma modulation circuit 122-n in the process of processing the signal block #J+1. [Figure 17] It is a table showing the circuit state of the delta-sigma modulation circuit 121-n in the process of processing the signal block #J. [Figure 18] It is a table showing the circuit state of the delta-sigma modulation circuit 122-n in the process of processing the signal block #J+1. [Figure 19] It is a diagram showing an example of the configuration of the error feedback type delta-sigma modulation circuit 1900. [Figure 20] It is a diagram showing an example of the configuration of the delta-sigma modulation device 2000. [Figure 21] 13 is a flowchart showing the flow of processing performed by the delta-sigma modulation device 2000. [Figure 22] FIG. 22 illustrates an example of an information processing device 2200 for implementing a delta-sigma modulator. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, one or more embodiments will be described with reference to the accompanying drawings. In this disclosure, the drawings are related to one or more embodiments. In this specification and drawings, elements that can be similarly described are given the same reference numerals to avoid redundant description.

[0015] The explanation will be given in the following order: 1. Embodiment 1-1. Overview of the embodiment 1-2. Details of the embodiment 1-3.Hardware configuration 2. Other embodiments

[0016] <<1. Embodiment>> A brief summary of one or more embodiments is provided below.

[0017] <1-1. Overview of the embodiment> For example, assume that a high-speed digital signal having a sampling frequency exceeding 1 Gbps is to be processed, and since the operating frequency of a hardware circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) is lower than the sampling frequency of the input signal, it is difficult to process the input signal using only one delta-sigma modulation circuit.

[0018] In order to solve the above problems, a delta-sigma modulation device including a plurality of delta-sigma modulation circuits may be used. In this configuration, the plurality of delta-sigma modulation circuits are arranged in parallel. The delta-sigma modulation device divides an input signal into a plurality of signal blocks of a predetermined data length, and inputs the plurality of signal blocks to the plurality of delta-sigma modulation circuits, respectively. With this configuration, high-speed digital signals can be processed.

[0019] 1 is a diagram showing an example of the configuration of a delta-sigma modulation device 10. The delta-sigma modulation device 10 includes a distribution section 110, a parallel circuit section 120, and a combination section .

[0020] The distributor 110 includes a first storage unit 111 and a first selection unit 112. The first storage unit 111 stores multi-bit digital data, which is an input signal. The first selection unit 112 receives the digital data from the first storage unit 111. The first selection unit 112 divides the digital data into a plurality of signal blocks. The first selection unit 112 inputs the plurality of signal blocks to the parallel circuit unit 120.

[0021] The parallel circuit section 120 includes a plurality of filter circuits 121 and 122. The plurality of filter circuits 121 and 122 are arranged in parallel. In this example, for the sake of simplicity, the number of filter circuits is two, but is not limited to this configuration. Three or more filter circuits may be arranged in parallel.

[0022] The first selection unit 112 inputs a plurality of signal blocks to a plurality of filter circuits 121 and 122. The signal block input to the filter circuit 121 and the signal block input to the filter circuit 122 are different (that is, they do not overlap with each other).

[0023] The filter circuit 121 includes a delta-sigma modulation circuit 121-1. The delta-sigma modulation circuit 121-1 performs delta-sigma modulation processing on a plurality of data included in a signal block. As described later, the signal block has a predetermined data length. The delta-sigma modulation circuit 121-1 performs processing in order from the first data to the last data included in the signal block. The delta-sigma modulation circuit 121-1 outputs an output signal (a bit string of 1 bit) to the combining unit 130.

[0024] Similarly, the filter circuit 122 includes a delta-sigma modulation circuit 122-1. The delta-sigma modulation circuit 122-1 performs delta-sigma modulation processing on a plurality of data included in a signal block. The delta-sigma modulation circuit 122-1 performs processing in order from the first data to the last data included in the signal block. The delta-sigma modulation circuit 122-1 outputs an output signal (a bit string of 1 bit) to the combining unit 130.

[0025] The combining unit 130 includes a second storage unit 131 and a second selection unit 132. The second storage unit 131 stores an output signal from the delta-sigma modulation circuit 121-1 and an output signal from the delta-sigma modulation circuit 122-1. The second selection unit 132 outputs a plurality of output signals stored in the second storage unit 131. The second selection unit 132 outputs the processing results (1-bit bit strings) of the signal blocks input to the second storage unit 131 in order starting from the earliest.

[0026] Hereinafter, for the sake of explanation, the signal block data input to the delta-sigma modulation circuit is referred to as “input data.” The processing result (i.e., the output signal) output from the delta-sigma modulation circuit is referred to as “output data.”

[0027] 2 is a diagram showing an example of the configuration of a delta-sigma modulation circuit 200. The delta-sigma modulation circuit 200 is an Nth-order delta-sigma modulation circuit. N represents the order of the delta-sigma modulation circuit. The larger the value of N, the better the noise shaping performance, which is a feature of the delta-sigma modulation circuit. In this example, for simplicity of explanation, N=3, but the present invention is not limited to this configuration. A fourth-order or higher delta-sigma modulation circuit may also be used.

[0028] The delta-sigma modulation circuit 200 includes integrators 210-1, 210-2, and 210-3, adder-subtractors 220-1, 220-2, and 220-3, a quantization section 230, and a delay unit 240.

[0029] The integrators 210-1, 210-2, and 210-3 are connected in series. The adder-subtractors 220-1, 220-2, and 220-3 are disposed on the input sides of the integrators 210-1, 210-2, and 210-3, respectively.

[0030] The output signal of integrator 210-1 is input to quantization section 230. Quantization section 230 quantizes the output signal of integrator 210-1 and outputs a 1-bit bit string as output data. The output data is stored in delay device 240. Thereafter, the output data is fed back to adder-subtractors 220-1, 220-2, and 220-3.

[0031] Therefore, the adder-subtractor 220-3 outputs a signal calculated from the input data and the output data to the integrator 210-3 as an output signal. The integrator 210-3 processes the output signal of the adder-subtractor 220-3 and outputs the output signal to the adder-subtractor 220-2. The adder-subtractor 220-2 outputs a signal calculated from the output signal of the integrator 210-3 and the output data to the integrator 210-2 as an output signal. The integrator 210-2 processes the output signal of the adder-subtractor 220-2 and outputs the output signal to the adder-subtractor 220-1. The adder-subtractor 220-1 outputs a signal calculated from the output signal of the integrator 210-2 and the output data to the integrator 210-1 as an output signal. The integrator 210-1 processes the output signal of the adder-subtractor 220-1 and outputs the output signal to the quantization unit 230.

[0032] The integrators 210-1, 210-2, and 210-3 have the same configuration. Here, only the integrator 210-1 will be described, and descriptions of the other integrators 210-2 and 210-3 will be omitted. The integrator 210-1 includes an adder-subtractor 211-1 and a delay unit 212-1. The output signal of the adder-subtractor 211-1 is fed back to the adder-subtractor 211-1 via the delay unit 212-1.

[0033] 2, the delta-sigma modulation circuit 200 is a type of infinite impulse response (IIR) filter. The delta-sigma modulation circuit 200 includes a quantization unit 230 arranged on a feedback path, and outputs a 1-bit bit string as output data.

[0034] Fig. 3 is a diagram showing an example of the configuration of a delta-sigma modulation circuit 300. The delta-sigma modulation circuit 300 is a modified example of the configuration of the delta-sigma modulation circuit 200 in Fig. 2. The delta-sigma modulation circuit 300 is also called an "error feedback type Nth order delta-sigma modulation circuit." Note that in this example, N=3 for ease of explanation, but the present invention is not limited to this configuration. A fourth or higher order delta-sigma modulation circuit may also be used.

[0035] The delta-sigma modulation circuit 300 includes adders / subtractors 310-1, 310-2, and 310-3, feedback amount calculation sections 320-1, 320-2, and 320-3, a quantization section 330, and an adder / subtractor 340.

[0036] The adder-subtractor 310-3 outputs a signal calculated from the input data and the output signal of the feedback amount calculation unit 320-3 to the adder-subtractor 310-2 as an output signal. The adder-subtractor 310-2 outputs a signal calculated from the output signal of the adder-subtractor 310-3 and the output signal of the feedback amount calculation unit 320-2 to the adder-subtractor 310-1 as an output signal. The adder-subtractor 310-1 outputs a signal calculated from the output signal of the adder-subtractor 310-2 and the output signal of the feedback amount calculation unit 320-1 to the quantization unit 330 as an output signal.

[0037] The quantization unit 230 quantizes the output signal of the adder-subtractor 310-1 and outputs a 1-bit bit string as output data. The adder-subtractor 340 outputs the output signal of the adder-subtractor 310-1 and a signal calculated from the output data as an output signal to the feedback amount calculation unit 320-1. The output signal of the adder-subtractor 340 is also fed back to the feedback amount calculation units 320-2 and 320-3.

[0038] The feedback amount calculation units 320-1, 320-2, and 320-3 have the same configuration. Here, the feedback amount calculation unit 320-1 will be described. The feedback amount calculation unit 320-1 includes a multiplier 321-1, a delay unit 322-1, and a coefficient memory unit 323-1. The coefficient memory unit 323-1 stores a feedback gain A1. The output signal of the adder-subtractor 340 is input to the multiplier 321-1 via the delay unit 322-1. The multiplier 321-1 multiplies the output signal of the adder-subtractor 340 by the feedback gain A1, and outputs the multiplication result to the adder-subtractor 310-1.

[0039] The other feedback amount calculation units 320-2 and 320-3 differ from the feedback amount calculation unit 320-1 in the following points: A coefficient memory 323-2 of the feedback amount calculation unit 320-2 stores a feedback gain A2. A coefficient memory 323-3 of the feedback amount calculation unit 320-3 stores a feedback gain A3.

[0040] As described above, the delta-sigma modulation circuit 300 has a configuration in which the output signal of the adder-subtractor 340 (i.e., the error signal between the input signal and output signal of the quantization section 330) is fed back to the adders-subtractors 310-1, 310-2, and 310-3 via the feedback amount calculation sections 320-1, 320-2, and 320-3.

[0041] When all of the feedback gains A1, A2, and A3 are 1, the configuration of the delta-sigma modulation circuit 200 in Fig. 2 is equivalent to the configuration of the delta-sigma modulation circuit 300 in Fig. 3. On the other hand, the delta-sigma modulation circuit 300 can be implemented with fewer components (e.g., adders / subtractors and delayers) than the delta-sigma modulation circuit 200. The delta-sigma modulation circuit 300 has an advantage over the delta-sigma modulation circuit 200 in that the circuit scale of the delta-sigma modulation circuit 300 can be made smaller than that of the delta-sigma modulation circuit 200.

[0042] Furthermore, in the delta-sigma modulation circuit 300, the feedback amount calculation section 320-1 multiplies the error signal (i.e., the output signal of the adder-subtractor 340) by a feedback gain A1. The feedback amount calculation sections 320-2 and 320-3 can also perform similar processing. There is also an advantage that the noise shaping characteristics can be controlled by adjusting the feedback gains A1, A2, and A3.

[0043] In the following, one or more embodiments using an error feedback type Nth order delta-sigma modulation circuit will be described, where N=2 for simplicity of explanation.

[0044] Fig. 4 is a diagram showing an example of the configuration of an error feedback type delta-sigma modulation circuit 400. Regarding the delta-sigma modulation circuit 400, the same components as those in the delta-sigma modulation circuit 300 in Fig. 3 are given the same reference numerals, and duplicated explanations will be omitted.

[0045] 3, the delta-sigma modulation circuit 400 further includes an adjustment unit 350. When the leading data of a signal block is input as input data, the adjustment unit 350 initializes the values ​​of the delay devices 322-1 and 322-2.

[0046] FIG. 5 is a diagram showing an example of the relationship between the input signal to the parallel circuit section 120 and the output signal from the combining section 130. As shown in FIG.

[0047] The first selection unit 112 of the distribution unit 110 divides the digital data into a plurality of signal blocks. Here, the signal block has a predetermined data length "I". That is, the signal block includes I data segments (or data elements). Furthermore, identification numbers (signal block numbers) are assigned in order from the signal block with the earliest input time. The Jth (J is a natural number) signal block is expressed as "signal block #J".

[0048] The xth data of signal block #J is expressed as "a(J,x)". The smaller the value of J or x, the earlier the data to which that value is assigned is input. As described above, if signal block #3 includes I data segments, the first (first) data of signal block #3 is expressed as a(3,1), and the Ith (last) data is expressed as a(3,I).

[0049] The first selection unit 112 alternately inputs a plurality of signal blocks to the filter circuits 121 and 122, starting from signal block #1 which was input earliest. For example, the first selection unit 112 inputs a certain signal block #J to the filter circuit 121, and inputs the next signal block #J+1 to the filter circuit 122. The first selection unit 112 repeatedly executes such an operation.

[0050] Through the above operations, the first selection unit 112 distributes the odd-numbered signal blocks to the filter circuits 121 in the order in which they were input to the distribution unit 110. The first selection unit 112 distributes the even-numbered signal blocks to the filter circuits 122 in the order in which they were input to the distribution unit 110.

[0051] The delta sigma modulation circuit 121-1 of the filter circuit 121 processes I data segments (input data) included in a signal block in the input order, and outputs output data corresponding to the signal block to the second storage unit 131 of the combining unit 130. The delta sigma modulation circuit 122-1 of the filter circuit 122 processes I data segments (input data) included in a signal block in the input order, and outputs output data corresponding to the signal block to the second storage unit 131 of the combining unit 130. The delta sigma modulation circuits 121-1 and 122-1 each have the configuration shown in FIG. 4. Just before the delta sigma modulation circuit 121-1 processes the first data of each signal block, the adjustment unit 350 sets the values ​​of the delay units 322-1 and 322-2 to initial values. For example, zero is used as the initial value. Similarly, immediately before the delta-sigma modulation circuit 122-1 processes the leading data of each signal block, the adjustment section 350 sets the values ​​of the delay devices 322-1 and 322-2 to their initial values.

[0052] Here, the value obtained by multiplying the time length of a signal block (= the number of data included in a signal block × the sampling time) by the number of filter circuits (in this example, 2) is referred to as the "first time." If the filter circuits 121 and 122 complete the processing within the first time, the filter circuits 121 and 122 can execute the processing in real time. In other words, if the drive frequency of the hardware circuit is equal to or greater than 1 / (the sampling frequency) the number of filter circuits, the filter circuits 121 and 122 can execute the processing in real time.

[0053] The second selection section 132 of the combining section 130 outputs data in order from the data stored in the second storage section 131 earliest in time (that is, the data processed by the parallel circuit section 120 earliest in time).

[0054] For example, in the example of FIG. 5, at time t0, the first selection unit 112 starts inputting the signal block #1 to the filter circuit 121. At time t1, the delta-sigma modulation circuit 121-1 of the filter circuit 121 starts processing the signal block #1. At time t2, the second selection unit 132 of the combining unit 130 starts outputting the processing result of the signal block #1. In parallel with this processing, the delta-sigma modulation circuit 122-1 of the filter circuit 122 executes processing on the signal block #2. At time t3, the delta-sigma modulation circuit 122-1 ends the processing on the signal block #1. At time t4, the second selection unit 132 ends the output of the processing result of the signal block #1. Thereafter, the second selection unit 132 starts outputting the processing result of the signal block #2.

[0055] According to the above configuration, high-speed digital data can be processed by a hardware circuit having a drive frequency lower than the sampling frequency of the input signal.

[0056] However, the above configuration has a problem that a calculation error occurs near the boundary between successive signal blocks. The delta-sigma modulation circuits 121-1 and 122-1 process temporally successive signal blocks in parallel. For example, assume that the delta-sigma modulation circuit 121-1 processes a preceding signal block, and the delta-sigma modulation circuit 122-1 processes a succeeding signal block. In this case, the delta-sigma modulation circuit 121-1 cannot notify the delta-sigma modulation circuit 122-1 of the state (final state) at the time when it processes the last data of the signal block. This problem will be described with reference to Figs. 6 and 7.

[0057] Each row of the tables in Figures 6 and 7 may be referred to as a "circuit state" when processing the data of the signal block. In particular, the circuit state for the data at the beginning of the signal block may be referred to as an "initial state." Furthermore, the circuit state for the data at the end of the signal block may be referred to as a "final state."

[0058] Hereinafter, J is an odd number. It is assumed that the delta-sigma modulation circuit 121-1 processes a preceding signal block #J, and the delta-sigma modulation circuit 122-1 processes a succeeding signal block #J+1.

[0059] Fig. 6 is a table showing the circuit state of the delta-sigma modulation circuit 121-1 in the process of processing signal block #J. Specifically, Fig. 6 shows combinations of the values ​​of the delay devices 322-1 and 322-2 and the output value (error signal) of the adder-subtractor 340 in the process of processing data from data a(J,I-2) to data a(J,I).

[0060] For example, in the row of data a(J,I-2), the value of the delay unit 322-1 is d(J,I-3), and the value of the delay unit 322-2 is d(J,I-4). d(J,I-3) corresponds to the output value of the adder-subtractor 340 when the data a(J,I-3) is processed. d(J,I-4) corresponds to the output value of the adder-subtractor 340 when the data a(J,I-4) is processed. Therefore, when the data a(J,I-2) is processed, the output value of the adder-subtractor 340 one time before d(J,I-3), the output value of the adder-subtractor 340 two times before d(J,I-4), and the data a(J,I-2) are used to obtain d(J,I-2) as the output value of the adder-subtractor 340. The same applies to the other rows.

[0061] Fig. 7 is a table showing the circuit state of the delta-sigma modulation circuit 122-1 in the process of processing the signal block #J+1. Specifically, Fig. 7 shows combinations of the values ​​of the delay devices 322-1 and 322-2 and the output value (error signal) of the adder-subtracter 340 in the process of processing data a(J+1,1) to a(J+1,3).

[0062] Here, there is a problem that the circuit state in the first row of the table in Fig. 7 cannot be realized. This is due to the following reason. When the delta-sigma modulation circuit 122-1 processes the data a(J+1,1), the delta-sigma modulation circuit 121-1 has not yet completed the processing (for example, see Fig. 5). Specifically, the delta-sigma modulation circuit 121-1 has not yet completed the processing for the data a(J,I-1) and the processing for the data a(J,I). The delta-sigma modulation circuit 122-1 cannot receive the value to be stored in the delay unit 322-1 (i.e., d(J,I)) and the value to be stored in the delay unit 322-2 (i.e., d(J,I-1)) from the delta-sigma modulation circuit 121-1.

[0063] Therefore, the delta-sigma modulation circuit 122-1 has no choice but to process the data a(J+1,1) using initial values ​​(for example, the most probable values) as the values ​​of the delay devices 322-1 and 322-2.

[0064] 8 is a table showing the circuit state of the delta-sigma modulation circuit 122-1 in the process of processing signal block #J+1, and shows an example in which initial values ​​are set as the values ​​of delay devices 322-1 and 322-2. The initial value is preferably the value with the highest occurrence probability among the output values ​​of the adder-subtractor 340, but for simplicity, it is assumed to be zero below. For example, immediately before the delta-sigma modulation circuit 122-1 processes the first data a(J+1,1) of signal block #J+1, the adjustment unit 350 sets the values ​​of delay devices 322-1 and 322-2 to their initial values ​​(=zero).

[0065] As described above, when processing the first data a(J+1,1) of signal block #J+1, the delta-sigma modulation circuit 122-1 cannot use the circuit state (i.e., the final state) when processing the last data a(J,I) of the preceding signal block #J. Therefore, for example, the output value d(J+1,1) of the adder-subtractor 340 in the table of Fig. 7 and the output value d(J+1,1) of the adder-subtractor 340 in the table of Fig. 8 may each be a different bit string.

[0066] The output signal of the combiner 130 is passed through an analog low-pass filter to remove quantization noise that spreads on both sides of the signal spectrum. When such processing is performed for each of the patterns in Figures 7 and 8 and the signals are compared, errors may occur near the boundaries of the signal blocks. Hereinafter, such errors are referred to as "computation errors due to discontinuities."

[0067] Fig. 9 is a graph showing an example of a calculation error due to discontinuity calculated by simulation. The horizontal axis is time. The vertical axis is the square error between a signal obtained by passing an output signal in a configuration including the delta-sigma modulation circuits arranged in parallel through an analog low-pass filter, and a signal obtained by passing an output signal in a configuration not including the delta-sigma modulation circuits arranged in parallel through an analog low-pass filter. In the calculation of Fig. 9, an OFDM signal with a signal bandwidth of 1 GHz and a sampling frequency of 12.5 GSps is used as an input signal, and the data length of the signal block is 10,000.

[0068] In Figure 9, the impulse-like squared error occurring at a period of 0.8 μs (= 1 / 12.5 GSps × 10,000 pieces) is a calculation error caused by discontinuity. The magnitude of the calculation error caused by discontinuity varies. This is for the following reason. If the value of the delay device 322-1 and the output value of the adder / subtractor 340 in the final state of the delta-sigma modulation circuit responsible for processing the preceding signal block are significantly different from the initial value (= zero), a large squared error will occur, but if the values ​​happen to be close, the squared error will be small.

[0069] In response to this, Patent Document 2 discloses a configuration for suppressing calculation errors caused by discontinuity. However, the configuration disclosed in Patent Document 2 has multiple conditional branches, and therefore the processing is complicated. The configuration disclosed in Patent Document 2 is not suitable for the above-mentioned multiple delta-sigma modulation circuits arranged in parallel, which are required to process high-speed digital signals.

[0070] One or more embodiments described below provide a technique that can suppress calculation errors due to discontinuity with a simpler configuration than the related techniques described above (for example, Patent Document 2).

[0071] In order to solve the above problems, a delta-sigma modulation device according to one or more embodiments includes a division unit that divides an input signal into a plurality of blocks, two or more filter circuits arranged in parallel, and a combination unit that combines a plurality of output signals corresponding to the plurality of blocks. Each of the two or more filter circuits includes two or more delta-sigma modulation circuits. The initial states of the two or more delta-sigma modulation circuits are different from each other. In other words, the two or more delta-sigma modulation circuits have different initial values. The two or more delta-sigma modulation circuits process the same signal block and output an output selection signal. The combination unit selects an output signal of the delta-sigma modulation circuit having an initial state that is closest to the initial state of the digital modulation circuit processing the subsequent signal block estimated from the final state of the digital sigma modulation circuit processing the preceding signal block.

[0072] <1-2. Details of the embodiment> 10 is a diagram showing an example of the configuration of a delta-sigma modulation device 1000. Regarding the delta-sigma modulation device 1000, the same components as those in the delta-sigma modulation device 10 described above are given the same reference numerals, and duplicated explanations will be omitted.

[0073] The parallel circuit section 120 includes a plurality of filter circuits 121 and 122. The plurality of filter circuits 121 and 122 are arranged in parallel. In this example, for the sake of simplicity, the number of filter circuits is two, but is not limited to this configuration. Three or more filter circuits may be arranged in parallel.

[0074] The filter circuit 121 includes a plurality of delta-sigma modulation circuits 121-1, ..., 121-4. Similarly, the filter circuit 122 includes a plurality of delta-sigma modulation circuits 122-1, ..., 122-4. In this example, for the sake of explanation, the filter circuit includes four delta-sigma modulation circuits, but the filter circuit may include two or more delta-sigma modulation circuits.

[0075] The first selection unit 112 inputs a plurality of signal blocks to a plurality of filter circuits 121 and 122. The plurality of filter circuits 121 and 122 output a plurality of output signals corresponding to the plurality of signal blocks. Here, the first selection unit 112 inputs the same signal block to the plurality of delta-sigma modulation circuits 121-1, ..., 121-4. Therefore, the plurality of delta-sigma modulation circuits 121-1, ..., 121-4 perform delta-sigma modulation processing on the same signal block. Similarly, the first selection unit 112 inputs the same signal block to the plurality of delta-sigma modulation circuits 122-1, ..., 122-4. Therefore, the plurality of delta-sigma modulation circuits 122-1, ..., 122-4 perform delta-sigma modulation processing on the same signal block.

[0076] Fig. 11 is a diagram showing an example of the configuration of an error feedback type delta sigma modulation circuit 1100. A plurality of delta sigma modulation circuits 121-1, ..., 121-4 and a plurality of delta sigma modulation circuits 122-1, ..., 122-4 have the configuration shown in Fig. 11. Note that, with regard to the delta sigma modulation circuit 1100, the same components as those in the delta sigma modulation circuit 400 in Fig. 4 are denoted by the same reference numerals, and redundant explanations will be omitted.

[0077] The adjustment unit 350 refers to the output value of the adder-subtractor 340, the value of the delay unit 322-1, and the value of the delay unit 322-2. The adjustment unit 350 outputs an output selection signal to the combining unit 130. The output selection signal is used to combine multiple output signals corresponding to multiple signal blocks. The output selection signal may include, for example, at least one of the output value of the adder-subtractor 340, the value of the delay unit 322-1, and the value of the delay unit 322-2.

[0078] In the following description, the delta-sigma modulation circuits 121-1 to 121-4 are collectively referred to as "delta-sigma modulation circuits 121-n" using the delta-sigma modulation circuit identification number n (n=1, 2, 3, 4). The delta-sigma modulation circuits 122-1 to 122-4 are collectively referred to as "delta-sigma modulation circuits 122-n."

[0079] As described above, the first selection unit 112 divides the digital data into a plurality of signal blocks. The first selection unit 112 alternately inputs the plurality of signal blocks to the filter circuits 121 and 122. For example, the first selection unit 112 distributes odd-numbered signal blocks to the filter circuit 121. That is, the first selection unit 112 inputs the odd-numbered signal blocks to the delta-sigma modulation circuit 121-n. The first selection unit 112 distributes even-numbered signal blocks to the filter circuit 122. That is, the first selection unit 112 inputs the even-numbered signal blocks to the delta-sigma modulation circuit 122-n.

[0080] As described above, it is assumed that the delta-sigma modulation circuit 121-n processes the preceding signal block #J, and the delta-sigma modulation circuit 122-n processes the following signal block #J+1.

[0081] The delta-sigma modulation circuit 121-n performs delta-sigma modulation processing on the same signal block #J. The delta-sigma modulation circuit 122-n performs delta-sigma modulation processing on the same signal block #J+1.

[0082] Here, the initial value of the delay unit 322-1 and the initial value of the delay unit 322-2 included in the delta sigma modulation circuit 121-n are set individually. Also, the initial value of the delay unit 322-1 and the initial value of the delay unit 322-2 included in the delta sigma modulation circuit 122-n are set individually. Specifically, the initial value of the delay unit 322-1 included in the delta sigma modulation circuits 121-n and 122-n is represented as "αn". The initial value of the delay unit 322-2 included in the delta sigma modulation circuits 121-n and 122-n is represented as "βn". As described above, n=1, 2, 3, 4.

[0083] The value of αn is preferably the output value of the adder-subtractor 340 when processing the last data a(J,I) of the preceding signal block #J. In consideration of this, for example, an information processing device such as a computer may calculate the distribution of the output values ​​of the adder-subtractor 340 by simulation or the like, and may preselect the value with the highest occurrence probability based on the distribution as the value of αn.

[0084] Similarly, the value of βn is preferably the value of the delay device 322-1 when processing the last data a(J,I) of the preceding signal block #J. In consideration of this, the information processing device may calculate the distribution of the values ​​of the delay device 322-1 by simulation or the like, and may preselect the value with the highest occurrence probability based on the distribution as the value of βn.

[0085] For example, assume that when processing the last data a(J,I) of signal block #J, the output value of adder / subtractor 340 is most likely to be +0.5 and -0.5, and the value of delayer 322-1 is most likely to be +0.7 and -0.7. In this case, αn and βn may be set as follows. Hereinafter, the following setting of αn and βn is referred to as "setting 1". α1=+0.5 β1=+0.7 α2=+0.5 β2=-0.7 α3=-0.5 β3=+0.7 α4=-0.5 β4=-0.7

[0086] If there are multiple delta-sigma modulation circuits having the same combination of α and β, the output signals of those delta-sigma modulation circuits will be the same, and calculations will be wasted. Therefore, α and β may be set so that the combinations of α and β are different from each other.

[0087] In this example, when the adjustment unit 350 has processed the last data of the signal block to be processed, it outputs an output selection signal to the combining unit 130. The output selection signal includes the output value of the adder / subtractor 340 when the last data of the signal block has been processed, and the value of the delay unit 322-1 when the last data of the signal block has been processed.

[0088] Fig. 12 is a table showing the circuit state of the delta-sigma modulation circuit 121-n in the process of processing signal block #J. Fig. 13 is a table showing the circuit state of the delta-sigma modulation circuit 122-n in the process of processing signal block #J+1.

[0089] The adjustment unit 350 included in each of the delta-sigma modulation circuits 121-n outputs the value dn(J,I-1) of the delay unit 322-1 and the output value dn(J,I) of the adder / subtractor 340 as an output selection signal to the combining unit 130 when processing the last data a(J,I) of the signal block #J.

[0090] When processing the leading data a(J+1,1) of signal block #J+1, the adjustment section 350 included in each of the delta-sigma modulation circuits 122-n sets the value of the delay device 322-1 to αn and the value of the delay device 322-2 to βn. With the values ​​of the delay devices 322-1 and 322-2 set in this way, the delta-sigma modulation circuit 122-n executes delta-sigma modulation processing on the data a(J+1,1).

[0091] The following describes the combining process in which the combining unit 130 combines a plurality of output signals using the output selection signal.

[0092] Here, the operation of the combining unit 130 will be described based on the following assumptions. The combining unit 130 selects one of the delta-sigma modulation circuits 121-n that processes the preceding signal block #J. The delta-sigma modulation circuit selected in this manner is referred to as the "first delta-sigma modulation circuit 121-s." In this example, the combining unit 130 selects the delta-sigma modulation circuit 121-1 as the first delta-sigma modulation circuit 121-s.

[0093] Furthermore, the combining unit 130 uses the output selection signal to select one of the delta-sigma modulation circuits 122-n that processes the subsequent signal block #J+1. The delta-sigma modulation circuit selected in this manner is referred to as the "second delta-sigma modulation circuit 122-s." The combining unit 130 combines the output signal of the first delta-sigma modulation circuit 121-s and the output signal of the second delta-sigma modulation circuit 122-s.

[0094] Specifically, the second selection unit 132 selects, as the second delta-sigma modulation circuit 122-s, the delta-sigma modulation circuit that has performed delta-sigma modulation processing with a combination of αn and βn that is closest to the combination of the output value d1(J,I) of the adder-subtractor 340 and the value d1(J,I-1) of the delay device 322-1 included in the output selection signal received from the first delta-sigma modulation circuit 121-s (in this example, the delta-sigma modulation circuit 121-1).

[0095] For example, assume that αn and βn are set as in Setting 1 above. Further assume that the values ​​contained in the output select signal received from delta-sigma modulation circuit 121-1 are as follows: Output value d1(J,I) of the adder / subtractor 340=-0.9 The value of delay unit 322-1 is d1(J,I-1)=+0.5

[0096] In this case, the combination of αn and βn closest to the combination of the output value d1(J,I) of the adder / subtractor 340 and the value d1(J,I-1) of the delay unit 322-1 is the combination of α3 and β3. The second selection unit 132 selects the delta-sigma modulation circuit 122-3 as the second delta-sigma modulation circuit 122-s. The second selection unit 132 combines the output signal of the delta-sigma modulation circuit 121-1 and the output signal of the delta-sigma modulation circuit 122-3. For example, the second selection unit 132 outputs the output signals in the order of the signal block numbers. The second selection unit 132 outputs the output signal of the delta-sigma modulation circuit 121-1, and then outputs the output signal of the delta-sigma modulation circuit 122-3.

[0097] The second selection section 132 may select the second delta-sigma modulation circuit 122-s using the feedback gains A1 and A2. The second selection section 132 calculates the feedback amount using the following formula (1). A1·d1(J,I)+A2·d1(J,I-1) ···(1)

[0098] The second selection unit 132 calculates the following equation (2) for αn and βn. A1 αn + A2 βn (2)

[0099] The second selection section 132 may select the delta-sigma modulation circuit that corresponds to the value of equation (2) that is closest to the value of equation (1) as the second delta-sigma modulation circuit 122-s.

[0100] For example, assume that αn and βn are set as in Setting 1 above. Further assume that A1=+2.0 and A2=-1.0. Therefore, A1·d1(J,I)+A2·d1(J,I-1)=-2.3 A1·α1+A2·β1=+0.3 A1·α2+A2·β2=+1.7 A1·α3+A2·β3=-1.7 A1·α4+A2·β4=-0.3

[0101] The delta-sigma modulation circuit that corresponds to the value of equation (2) that is closest to the value of equation (1) is the delta-sigma modulation circuit 122-3. Therefore, the second selection section 132 selects the delta-sigma modulation circuit 122-3 as the second delta-sigma modulation circuit 122-s.

[0102] When the second selection unit 132 selects the output signal of the signal block #1, the preceding signal block #0 does not exist. In this case, the second selection unit 132 may perform the above-mentioned process assuming that d0(0,I)=0 and d0(0,I-1)=0.

[0103] According to the above configuration, the delta-sigma modulation device 1000 selects, from among the delta-sigma modulation circuits that have processed the subsequent signal block, a delta-sigma modulation circuit that has executed processing using an initial state (value of each delay device) that is closest to an initial state estimated from the final state of the delta-sigma modulation circuit that has processed the preceding signal block. Then, the delta-sigma modulation device 1000 selects the output signal of the selected delta-sigma modulation circuit and executes a combining process that combines a plurality of output signals. This makes it possible to suppress calculation errors due to discontinuity.

[0104] 14 is a diagram showing an example of the configuration of a delta-sigma modulation device 1400. Regarding delta-sigma modulation device 1400, the same components as those in delta-sigma modulation device 1000 described above are given the same reference numerals, and duplicated explanations will be omitted.

[0105] In the above-described delta-sigma modulation device 1000, the number of combinations of αn and βn is increased by increasing the number of delta-sigma modulation circuits included in each of the filter circuits 121 and 122. This increases the possibility of reducing the difference between the initial state of the delta-sigma modulation circuit 122-n that processes the subsequent signal block estimated from the final state of the delta-sigma modulation circuit 121-n that processes the preceding signal block and the actual initial state of the delta-sigma modulation circuit 122-n that processes the subsequent signal block. This makes it possible to improve the effect of suppressing calculation errors due to discontinuity. On the other hand, the circuit size increases.

[0106] In contrast, the delta-sigma modulation device 1400 has a configuration that enables a reduction in the circuit scale. Specifically, in the delta-sigma modulation device 1400, the number of delta-sigma modulation circuits included in each of the filter circuits 121 and 122 is two.

[0107] In the following description, the delta-sigma modulation circuits 121-1 to 121-2 will be collectively referred to as "delta-sigma modulation circuits 121-n" using the delta-sigma modulation circuit identification number n (n=1, 2). The delta-sigma modulation circuits 122-1 to 122-2 will be collectively referred to as "delta-sigma modulation circuits 122-n."

[0108] As described above, the first selection unit 112 divides the digital data into a plurality of signal blocks. The first selection unit 112 alternately inputs the plurality of signal blocks to the filter circuits 121 and 122. For example, the first selection unit 112 distributes odd-numbered signal blocks to the filter circuit 121. That is, the first selection unit 112 inputs the odd-numbered signal blocks to the delta-sigma modulation circuit 121-n. The first selection unit 112 distributes even-numbered signal blocks to the filter circuit 122. That is, the first selection unit 112 inputs the even-numbered signal blocks to the delta-sigma modulation circuit 122-n.

[0109] As described above, it is assumed that the delta-sigma modulation circuit 121-n processes the preceding signal block #J, and the delta-sigma modulation circuit 122-n processes the following signal block #J+1.

[0110] Fig. 15 is a table showing the circuit state of the delta-sigma modulation circuit 121-n in the process of processing signal block #J. Fig. 16 is a table showing the circuit state of the delta-sigma modulation circuit 122-n in the process of processing signal block #J+1.

[0111] 15, when processing the last data a(J,I) of signal block #J, the delta-sigma modulation circuit 121-n replaces the value dn(J,I-1) of the delay device 322-1 with zero. In this state, the delta-sigma modulation circuit 121-n performs delta-sigma modulation processing on the data a(J,I).

[0112] The adjustment section 350 included in each of the delta-sigma modulation circuits 121-n outputs the value dn(J,I-1) of the delay device 322-1 (i.e., the value before being replaced with zero) and the following equation (3) to the combining section 130 as an output selection signal. dn(J,I-1)+dn(J,I) (3)

[0113] As described above, the adjustment unit 350 adjusts the amount of feedback when processing the last data of the signal block. Specifically, when processing the last data of the signal block, the adjustment unit 350 sets the amount of feedback of N-1th order or less to zero. Furthermore, the adjustment unit 350 outputs the sum of a plurality of error signals calculated during processing from the data N-1 before the last data of the signal block to the last data as the output selection signal. In the above example, N=2. Therefore, the adjustment unit 350 sets the first order feedback amount (i.e., the value of the delay unit 322-1) to zero. The adjustment unit 350 outputs the sum of a plurality of error signals calculated during processing from the data one before the last data of the signal block to the last data (i.e., equation (3)) as the output selection signal.

[0114] For example, when N=3, the adjustment unit 350 may operate as follows: The adjustment unit 350 sets the second-order or lower feedback amounts (i.e., the values ​​of the delay units 322-1 and 322-2) to zero. The adjustment unit 350 outputs, as an output selection signal, the sum of a plurality of error signals calculated during processing from the data two data before the end data of the signal block to the end data.

[0115] 16, when processing the first data a(J+1,1) of signal block #J+1, the delta-sigma modulation circuit 122-n sets αn to a delay (in this example, delay 322-1) in which a value for calculating the primary feedback amount is stored, and sets zero to a delay (in this example, delay 322-2) for calculating the secondary feedback amount. In this state, the delta-sigma modulation circuit 122-n executes delta-sigma modulation processing on the data a(J+1,1).

[0116] As described above, the adjustment unit 350 sets the amount of feedback of second order or higher to zero when processing the data at the beginning of the signal block. In the above example, N=2. Therefore, the adjustment unit 350 sets only the amount of feedback of second order (i.e., the value of the delay unit 322-2) to zero.

[0117] The value of α may be selected from the distribution of formula (3). The information processing device may calculate the distribution of the values ​​of formula (3) by simulation or the like, and may pre-select two values ​​with the highest occurrence probability based on the distribution as the values ​​of α.

[0118] Here, it is assumed that the second selection unit 132 of the combining unit 130 selects the delta-sigma modulation circuit 121-1 as the first delta-sigma modulation circuit 121-s. Furthermore, the second selection unit 132 selects the delta-sigma modulation circuit having the initial value αn of the delay unit 322-1 that is closest to the value of equation (3) as the second delta-sigma modulation circuit 122-s. The second selection unit 132 combines the output signal of the first delta-sigma modulation circuit 121-s (i.e., the delta-sigma modulation circuit 121-1) and the output signal of the second delta-sigma modulation circuit 122-s.

[0119] 15, the value of dn(J,I-1) is not involved in the delta-sigma modulation process, and it appears that the output signal that should be obtained is not output. However, the value of dn(J,I-1) is involved in the initial value αn and the value of equation (3) included in the output selection signal, so it is possible to obtain an output signal whose difference from the original output signal is suppressed.

[0120] According to the above configuration, when processing the first data of a signal block, the initial value of delayer 322-2 is fixed to zero, and only the initial value of delayer 322-1 is set to be different. The number of delta-sigma modulation circuits for implementing delta-sigma modulation device 1400 is reduced, and as a result, the total circuit size can be reduced. In this way, the above configuration can reduce the circuit size and suppress calculation errors due to discontinuity.

[0121] As described above, when processing the first data of a signal block, the delta-sigma modulation device 1400 replaces the initial value of the delay device 322-2 with zero. Therefore, the output value of the adder-subtractor 340 and the output signal of the delta-sigma modulation circuit are different from those in the case where the initial value of the delay device 322-2 is not replaced with zero. As a result, a calculation error may occur. Hereinafter, such a calculation error is referred to as a "calculation error due to zero replacement."

[0122] In the following, a description will be given of an embodiment for suppressing calculation errors due to zero substitution. Since the configuration of the delta-sigma modulation device is the same as that of one or more of the above embodiments, a duplicated description will be omitted.

[0123] As described above, the first selection unit 112 divides the digital data into a plurality of signal blocks. The first selection unit 112 alternately inputs the plurality of signal blocks to the filter circuits 121 and 122. For example, the first selection unit 112 distributes odd-numbered signal blocks to the filter circuit 121. That is, the first selection unit 112 inputs the odd-numbered signal blocks to the delta-sigma modulation circuit 121-n. The first selection unit 112 distributes even-numbered signal blocks to the filter circuit 122. That is, the first selection unit 112 inputs the even-numbered signal blocks to the delta-sigma modulation circuit 122-n.

[0124] As described above, it is assumed that the delta-sigma modulation circuit 121-n processes the preceding signal block #J, and the delta-sigma modulation circuit 122-n processes the following signal block #J+1.

[0125] Fig. 17 is a table showing the circuit state of the delta-sigma modulation circuit 121-n in the process of processing signal block #J. Fig. 18 is a table showing the circuit state of the delta-sigma modulation circuit 122-n in the process of processing signal block #J+1.

[0126] 17, when processing the last data a(J,I) of signal block #J, the delta-sigma modulation circuit 121-n replaces the value dn(J,I-2) of the delay device 322-2 with the value of the following equation (4). The second term (term on the right side) of equation (4) may be referred to as an "adjustment value for the value dn(J,I-2) of the delay device 322-2."

number

[0127] With the value dn(J,I-2) of the delay device 322-2 substituted with the value of equation (4), the delta-sigma modulation circuit 121-n performs delta-sigma modulation processing on the data a(J,I).

[0128] The adjustment section 350 included in each of the delta-sigma modulation circuits 121-n outputs the value dn(J,I-1) of the delay device 322-1 and the following equation (5) calculated from the output value dn(I,J) of the adder / subtractor 340 as an output selection signal to the combining section 130.

number

[0129] As described above, the adjustment unit 350 uses the adjustment value to adjust the amount of feedback when processing the last data of the signal block. The adjustment unit 350 outputs the error signal and the adjustment value when processing the last data of the signal block as an output selection signal. Specifically, the adjustment value is calculated based on one or more error signals calculated during processing from the data N-1 before the last data of the signal block to the data immediately before the last data. In the above example, N=2. Therefore, the adjustment value is calculated based on the error signal (i.e., dn(J,I-1)) calculated for the data immediately before the last data. The adjustment value is a value obtained by multiplying dn(J,I-1) by a predetermined coefficient. As described above, the predetermined coefficient may be a value based on the feedback gains A1 and A2 (for example, equation (5)). The adjustment unit 350 outputs the value dn(J,I-1) of the delay unit 322-1 and the value of equation (5) as an output selection signal.

[0130] For example, when N=3, the adjustment value is calculated based on two error signals (i.e., dn(J,I-1) and dn(J,I-2)) calculated during processing from the data two data before the last data of the signal block to the data before the last data. The adjustment value may be a value obtained by multiplying each of dn(J,I-1) and dn(J,I-2) by a predetermined coefficient. As described above, the predetermined coefficient may be a value based on at least one feedback gain.

[0131] 18, when processing the first data a(J+1,1) of signal block #J+1, the delta-sigma modulation circuit 122-n sets αn to the delay device 322-1 and sets zero to the delay device 322-2. In this state, the delta-sigma modulation circuit 122-n executes delta-sigma modulation processing on the data a(J+1,1).

[0132] The value of α may be selected from the distribution of formula (5). The information processing device may calculate the distribution of the values ​​of formula (5) by simulation or the like, and may pre-select two values ​​with the highest occurrence probability based on the distribution as the values ​​of α.

[0133] Here, it is assumed that the second selection unit 132 of the combining unit 130 selects the delta-sigma modulation circuit 121-1 as the first delta-sigma modulation circuit 121-s. Furthermore, the second selection unit 132 selects the delta-sigma modulation circuit having the initial value αn of the delay unit 322-1 that is closest to the value of equation (5) as the second delta-sigma modulation circuit 122-s. The second selection unit 132 combines the output signal of the first delta-sigma modulation circuit 121-s (i.e., the delta-sigma modulation circuit 121-1) and the output signal of the second delta-sigma modulation circuit 122-s.

[0134] According to the above configuration, when processing the first data of a signal block, the initial value of the delayer 322-2 is fixed to zero, and only the initial value of the delayer 322-1 is set to be different. The number of delta-sigma modulation circuits for implementing the delta-sigma modulation device is reduced, and as a result, the total circuit size can be reduced. Furthermore, when processing the last data of a signal block, the value of the delayer 322-2 is not replaced with zero, so that calculation errors due to zero replacement can be suppressed.

[0135] The following describes the calculation error that occurs when the value of delay device 322-2 is replaced with the value of equation (4) when processing the last data a(J,I) of signal block #J. The amount of feedback due to the second term (the term on the right side) of equation (4) is expressed by the following equation (6).

number

[0136] The amount of feedback due to the value dn(J,I-1) of the delay device 322-1 is expressed by the following equation (7).

number

[0137] The sum of equations (6) and (7) is expressed by the following equation (8).

number

[0138] In addition, since (A2 / A1)<1, it is generally understood that the effect can be suppressed compared to the case where the original feedback amount (i.e., equation (7)) becomes zero due to the zero replacement process of the delay unit 322-1. For example, when A1=+2 and A2=-1, 1-(A2 / A1) 2 = 0.75. Therefore, the error in the amount of primary feedback when processing the data at the end of the signal block can be reduced from 100% to 25%. With the above configuration, it is possible to suppress the calculation error due to zero substitution and also the calculation error due to discontinuity.

[0139] The amount of feedback when processing the last data a(J,I) of signal block #J is expressed by the following equation (9).

number

[0140] Therefore, when processing the last data a(J,I) of signal block #J, the adjustment section 350 may set the value of the delay unit 322-1 to dn(J,I-1), the value of the delay unit 322-2 to dn(J,I-2), and the feedback gain A1 of the coefficient memory 323-1 to the value of the following equation (10). Even with this configuration, it is possible to suppress calculation errors due to zero substitution.

number

[0141] Fig. 19 is a diagram showing an example of the configuration of an error feedback type delta sigma modulation circuit 1900. In the delta sigma modulation circuit 1900, the same components as those in the delta sigma modulation circuit 1100 in Fig. 11 are given the same reference numerals, and redundant explanations will be omitted.

[0142] 19, a path from the adjustment unit 350 to the coefficient storage unit 323-1 is added. For example, when processing the data a(J,I) at the end of the signal block #J, the adjustment unit 350 can replace the feedback gain A1 of the coefficient storage unit 323-1 with the value of Equation (10).

[0143] According to the above configuration, when the value of equation (10) is known, the adjustment unit 350 can set the feedback gain A1 of the coefficient storage unit 323-1 to the value of equation (10) in advance. In this configuration, it is not necessary to calculate the value to be set in the delay unit 322-2 (i.e., the value of equation (4)) for each signal block. Therefore, the circuit scale can be further reduced.

[0144] 20 is a diagram showing an example of a configuration of a delta-sigma modulation device 2000. The delta-sigma modulation device 2000 includes a distribution section 2010, a parallel circuit section 2020, and a combination section 2030.

[0145] The distributor 2010 divides the input signal into a plurality of signal blocks, and inputs the plurality of signal blocks to the parallel circuit section 2020 .

[0146] The parallel circuit unit 2020 includes two or more filter circuits 2021, 2022 arranged in parallel. The two or more filter circuits 2021, 2022 perform delta-sigma modulation processing on a plurality of signal blocks and output a plurality of output signals corresponding to the plurality of signal blocks. Each of the two or more filter circuits 2021, 2022 includes two or more delta-sigma modulation circuits including different initial values. For example, the filter circuit 2021 includes two or more delta-sigma modulation circuits 2021-1, 2021-2.

[0147] The combining unit 2030 executes a combining process for combining a plurality of output signals.

[0148] FIG. 21 is a flowchart illustrating an example of the process flow of the delta-sigma modulation device 2000.

[0149] The distributor 2010 divides an input signal into a plurality of signal blocks (2101). The distributor 2010 inputs the plurality of signal blocks to two or more filter circuits 2021 and 2022.

[0150] The parallel circuit unit 2020 executes delta-sigma modulation processing (2102). Specifically, two or more delta-sigma modulation circuits execute delta-sigma modulation processing on the same signal block, output an output signal to the combining unit 2030, and output an output selection signal to the combining unit 2030 for combining the multiple output signals.

[0151] The combining unit 2030 performs a combining process to combine a plurality of output signals output from the parallel circuit unit 2020. Specifically, the combining unit 2030 performs the combining process using an output selection signal of a delta-sigma modulation circuit that processes a preceding signal block among a plurality of signal blocks, and an initial value.

[0152] According to the above configuration, it is possible to suppress calculation errors due to discontinuity. The distribution unit 2010 may have a configuration similar to that of the distribution unit 110 described above. The parallel circuit unit 2020 may have a configuration similar to that of the parallel circuit unit 120 described above. The coupling unit 2030 may have a configuration similar to that of the coupling unit 130 described above.

[0153] <1-3. Hardware configuration> FIG. 22 is a diagram illustrating an example of an information processing device 2200 for implementing a delta-sigma modulation device.

[0154] The information processing device 2200 includes a processor 2210, a memory 2220, an input interface 2230, and an output interface 2240. The processor 2210, the memory 2220, the input interface 2230, and the output interface 2240 are connected to each other via a bus 2250.

[0155] The processor 2210 may include, for example, one or more of a central processing unit (CPU), a micro processing unit (MPU), and a microcontroller. The processor 2210 executes a program 2222 stored in the memory 2220 to realize a delta-sigma modulation device according to one or more of the above embodiments.

[0156] The memory 2220 is an element that temporarily or permanently stores programs (instructions) 2222 and data used to execute various processes in the delta-sigma modulation device. The memory 2220 includes volatile memory and non-volatile memory. The volatile memory may include, for example, a random access memory (RAM). The non-volatile memory may include, for example, one or more of a read only memory (ROM), a hard disk drive (HDD), and a solid state drive (SSD). The memory 2220 includes an input signal storage unit 2221 for temporarily storing an input signal, and an output signal storage unit 2223 for temporarily storing an output signal.

[0157] The input interface 2230 is an interface for receiving input from a user or another information processing device, and the output interface 2240 is an interface for outputting to a display unit (not shown) or another information processing device.

[0158] <<2. Other embodiments>> Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments. It will be understood by those skilled in the art that these embodiments are merely examples and that various modifications are possible without departing from the scope and spirit of the present disclosure.

[0159] For example, the steps in the processes described herein do not necessarily have to be performed chronologically according to the order depicted in the sequence diagrams. For example, the steps in the processes may be performed in an order different from that depicted in the sequence diagrams, or may be performed in parallel. Also, some of the steps in the processes may be deleted, and additional steps may be added to the processes.

[0160] Also, a method including the processing of the above-mentioned components may be provided, or a program for causing a processor to execute the processing of the above-mentioned components may be provided. Also, a non-transitory computer readable medium having the program recorded thereon may be provided. Naturally, such an apparatus, module, method, program, and non-transitory computer readable medium are also included in the scope of the present disclosure.

[0161] A part or all of the above-described embodiments may be described as, but is not limited to, the following supplementary notes.

[0162] (Appendix 1) A distributor that divides an input signal into a plurality of signal blocks; a parallel circuit unit including two or more filter circuits arranged in parallel and performing delta-sigma modulation processing on the signal blocks to output a plurality of output signals corresponding to the signal blocks, each of the two or more filter circuits including two or more delta-sigma modulation circuits including different initial values; a combining unit that performs a combining process for combining the plurality of output signals; Equipped with the two or more delta-sigma modulation circuits perform the delta-sigma modulation process on a same signal block to output the output signal, and output an output selection signal for combining the multiple output signals; the combining unit performs the combining process using the output selection signal of the delta-sigma modulation circuit that processes a preceding signal block among the plurality of signal blocks and the initial value. Delta Sigma Modulation Device.

[0163] (Appendix 2) In the joining process, the joining unit selecting one of the two or more delta-sigma modulation circuits that processes the preceding signal block as a first delta-sigma modulation circuit; selecting one of the two or more delta-sigma modulation circuits that processes a subsequent signal block relative to the preceding signal block as a second delta-sigma modulation circuit; combining the output signal of the first delta-sigma modulation circuit with the output signal of the second delta-sigma modulation circuit; 2. The delta-sigma modulation device of claim 1.

[0164] (Appendix 3) the output selection signal includes an error signal when the first delta-sigma modulation circuit processes the end data of the preceding signal block, and a value of a delay unit when the first delta-sigma modulation circuit processes the end data of the preceding signal block, the coupling unit selects, as the second delta-sigma modulation circuit, the delta-sigma modulation circuit having the initial value closest to the output selection signal, from among the two or more delta-sigma modulation circuits processing the subsequent signal block; 3. The delta-sigma modulation device of claim 2.

[0165] (Appendix 4) the delta-sigma modulation circuit is an Nth-order (N≧2) digital sigma modulation circuit, The delta-sigma modulation device comprises: an adjustment unit that sets a second or higher order feedback amount to zero when the delta-sigma modulation circuit processes the first data of the signal block, and adjusts a feedback amount when the delta-sigma modulation circuit processes the last data of the signal block, 3. The delta-sigma modulation device of claim 2.

[0166] (Appendix 5) The adjustment unit is When processing the data at the end of the signal block, set the feedback amounts of N-1 orders or less to zero; outputting, as the output selection signal, a sum of a plurality of error signals calculated during processing from the data N-1 before the last data of the signal block to the last data; 5. The delta-sigma modulation device of claim 4.

[0167] (Appendix 6) The adjustment unit adjusts an amount of feedback when processing the tail data of the signal block using an adjustment value; the adjustment value is calculated based on one or more error signals calculated while processing data from the last data of the signal block to data one data before the last data, the adjustment unit outputs an error signal and the adjustment value when processing the last data of the signal block as the output selection signal. 5. The delta-sigma modulation device of claim 4.

[0168] (Appendix 7) The adjustment unit is changing a feedback gain when processing the tail data of the signal block to a predetermined value; outputting an error signal when processing the last data of the signal block and an adjustment value for the error signal as the output selection signal; The adjustment value is calculated based on one or more error signals calculated while processing data from the last data of the signal block to the data just before the last data. 5. The delta-sigma modulation device of claim 4.

[0169] (Appendix 8) 1. A delta-sigma modulation method, comprising: Dividing an input signal into a plurality of signal blocks; inputting the plurality of signal blocks to two or more filter circuits to output a plurality of output signals corresponding to the plurality of signal blocks, wherein the two or more filter circuits are arranged in parallel, and each of the two or more filter circuits includes two or more delta-sigma modulation circuits having different initial values; performing a combining process for combining the plurality of output signals; Including, The delta-sigma modulation method comprises: using the two or more delta-sigma modulation circuits, performing delta-sigma modulation processing on a same signal block to output the output signal, and outputting an output selection signal for combining the multiple output signals; performing the combining process using the output selection signal of the delta-sigma modulation circuit that processes a preceding signal block of the plurality of signal blocks and the initial value; Further comprising: Delta Sigma Modulation Method. [Explanation of symbols]

[0170] 10, 1000, 1400, 2000: Delta Sigma Modulator 110, 2010: Distribution section 120, 2020: Parallel circuit section 130, 2030: Joint part

Claims

1. A distributor that divides an input signal into a plurality of signal blocks; a parallel circuit unit including two or more filter circuits arranged in parallel and performing delta-sigma modulation processing on the signal blocks to output a plurality of output signals corresponding to the signal blocks, each of the two or more filter circuits including two or more delta-sigma modulation circuits having different initial values; a combining unit that performs a combining process for combining the plurality of output signals; Equipped with the two or more delta-sigma modulation circuits perform the delta-sigma modulation process on a same signal block to output the output signal, and output an output selection signal for combining the multiple output signals; the combining unit performs the combining process using the output selection signal of the delta-sigma modulation circuit that processes a preceding signal block among the plurality of signal blocks and the initial value. Delta Sigma Modulation Device.

2. In the joining process, the joining unit selecting one of the two or more delta-sigma modulation circuits that processes the preceding signal block as a first delta-sigma modulation circuit; selecting one of the two or more delta-sigma modulation circuits that processes a subsequent signal block relative to the preceding signal block as a second delta-sigma modulation circuit; combining the output signal of the first delta-sigma modulation circuit with the output signal of the second delta-sigma modulation circuit; 2. The delta-sigma modulation device according to claim 1.

3. the output selection signal includes an error signal when the first delta-sigma modulation circuit processes the end data of the preceding signal block, and a value of a delay unit when the first delta-sigma modulation circuit processes the end data of the preceding signal block, the coupling unit selects, as the second delta-sigma modulation circuit, the delta-sigma modulation circuit having the initial value closest to the output selection signal, from among the two or more delta-sigma modulation circuits processing the subsequent signal block; 3. The delta-sigma modulation device according to claim 2.

4. the delta-sigma modulation circuit is an Nth-order (N≧2) digital sigma modulation circuit, The delta-sigma modulation device comprises: an adjustment unit that sets a second or higher order feedback amount to zero when the delta-sigma modulation circuit processes the first data of the signal block, and adjusts a feedback amount when the delta-sigma modulation circuit processes the last data of the signal block, 3. The delta-sigma modulation device according to claim 2.

5. The adjustment unit is When processing the tail data of the signal block, set the feedback amounts of N-1 orders or less to zero; outputting, as the output selection signal, a sum of a plurality of error signals calculated during processing from the data N-1 before the last data of the signal block to the last data; 5. The delta-sigma modulation device according to claim 4.

6. The adjustment unit adjusts an amount of feedback when processing the tail data of the signal block using an adjustment value; the adjustment value is calculated based on one or more error signals calculated while processing data from N-1 data before the last data of the signal block to data one data before the last data, the adjustment unit outputs an error signal and the adjustment value when processing the last data of the signal block as the output selection signal.

5. The delta-sigma modulation device according to claim 4.

7. The adjustment unit is changing a feedback gain when processing the tail data of the signal block to a predetermined value; outputting an error signal when processing the last data of the signal block and an adjustment value for the error signal as the output selection signal; The adjustment value is calculated based on one or more error signals calculated while processing data from N-1 data before the last data of the signal block to data one data before the last data.

5. The delta-sigma modulation device according to claim 4.

8. 1. A delta-sigma modulation method, comprising: Dividing an input signal into a plurality of signal blocks; inputting the plurality of signal blocks to two or more filter circuits to output a plurality of output signals corresponding to the plurality of signal blocks, wherein the two or more filter circuits are arranged in parallel, and each of the two or more filter circuits includes two or more delta-sigma modulation circuits having different initial values; performing a combining process for combining the plurality of output signals; Including, The delta-sigma modulation method comprises: Using the two or more delta-sigma modulation circuits, perform delta-sigma modulation processing on a same signal block to output the output signal, and output an output selection signal for combining the multiple output signals; performing the combining process using the output selection signal of the delta-sigma modulation circuit that processes a preceding signal block of the plurality of signal blocks and the initial value; Further comprising: Delta Sigma Modulation Method.

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