Semiconductor measuring device and semiconductor measuring method

Abstract

To provide a semiconductor measuring device and a semiconductor measuring method that can improve the capacitance measurement accuracy.SOLUTION: According to one embodiment, a semiconductor measuring device 1 includes a CBCM circuit 10 having a first terminal T01 and a connection terminal T03, and a potential difference applying circuit 13 connected to the connection terminal T03 and having a second terminal T02 to which a predetermined potential difference to the output of the first terminal T01 is applied. Parasitic capacitance of a measurement system is obtained from the capacitance in a connected state in which the first terminal T01 and the second terminal T02 are connected to a transistor MTR, and the capacitance in a disconnected state in which the first terminal T01 and the second terminal T02 are disconnected from the transistor MTR, and then capacitance of the transistor MTR is calculated.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor measuring device and a semiconductor measuring method, and more particularly to a semiconductor measuring device and a semiconductor measuring method for semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). [Background technology]

[0002] Patent Document 1 describes a capacitance measuring circuit and a capacitance measuring method for a semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-356169 A Summary of the Invention [Problem to be solved by the invention]

[0004] When measuring the capacitance of a semiconductor device, it is necessary to eliminate parasitic capacitance. However, there are some materials for which it is difficult to eliminate parasitic capacitance, making it difficult to improve the measurement accuracy of the capacitance of the semiconductor device.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor measuring device includes a CBCM circuit having a first terminal and an auxiliary terminal, and a potential difference applying circuit connected to the auxiliary terminal, the potential difference applying circuit having a second terminal and applying a predetermined potential difference to an output of the first terminal, and determines a parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor, and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculates the capacitance of the transistor.

[0007] According to one embodiment, a semiconductor measurement method uses a semiconductor measurement device including a CBCM circuit having a first terminal and an auxiliary terminal, and a potential difference applying circuit connected to the auxiliary terminal, the potential difference applying circuit having a second terminal and applying a predetermined potential difference to an output of the first terminal, and the method determines a parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor, and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculates a capacitance of the transistor. Effect of the Invention

[0008] According to the embodiment, it is possible to provide a semiconductor measuring device and a semiconductor measuring method capable of improving the capacitance measurement accuracy. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram illustrating a capacitance measuring circuit according to a first comparative example. [Diagram 2] 10 is a diagram illustrating capacitance between the gate, drain, and source of a transistor to be measured in the capacitance measuring circuit according to Comparative Example 1. FIG. [Diagram 3] FIG. 11 is a circuit diagram illustrating a capacitance measuring circuit according to a second comparative example. [Figure 4]11 is a sequence diagram illustrating the operation of a capacitance measuring circuit according to Comparative Example 2, in which the horizontal axis indicates time and the vertical axis indicates the voltage Vnode of node N1, the current I(Vnode) of node N1, the voltage of gate circuit Ppgu, and the voltage of gate circuit Npgu. [Diagram 5] 11 is a circuit diagram illustrating the operation during charging of the capacitance measurement circuit according to Comparative Example 2. FIG. [Figure 6] 11 is a circuit diagram illustrating the operation of the capacitance measurement circuit according to Comparative Example 2 during discharging. FIG. [Figure 7] 1 is a circuit diagram illustrating a main part of a semiconductor measuring device according to a first embodiment. [Figure 8] 1 is a circuit diagram illustrating a semiconductor measuring device according to a first embodiment. [Figure 9] 1 is a circuit diagram illustrating a semiconductor measuring device according to a first embodiment. [Figure 10] 4A to 4C are diagrams illustrating a semiconductor measuring method in the semiconductor measuring apparatus according to the first embodiment. [Figure 11] 11 is a circuit diagram illustrating a semiconductor measuring device according to a second embodiment. [Figure 12] 11 is a circuit diagram illustrating a semiconductor measuring device according to a second embodiment. [Figure 13] 10 is a diagram illustrating a semiconductor measuring method in the semiconductor measuring device according to the second embodiment. [Figure 14] FIG. 11 is a circuit diagram illustrating a semiconductor measuring device according to a third embodiment. [Figure 15] FIG. 11 is a circuit diagram illustrating a semiconductor measuring device according to a third embodiment. [Figure 16] 11 is a diagram illustrating a semiconductor measuring method in the semiconductor measuring device according to the third embodiment. [Figure 17] FIG. 11 is a circuit diagram illustrating a semiconductor measuring device according to a fourth embodiment. [Figure 18] FIG. 11 is a circuit diagram illustrating a semiconductor measuring device according to a fourth embodiment. [Figure 19] 13 is a diagram illustrating a semiconductor measuring method in the semiconductor measuring device according to the fourth embodiment. FIG. [Figure 20]4 is a flow chart illustrating a semiconductor measuring method in the semiconductor measuring apparatus according to the first to fourth embodiments. [Figure 21] 4 is a flow chart illustrating a semiconductor measuring method in the semiconductor measuring apparatus according to the first to fourth embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Note that in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary. Also, reference numerals are omitted as appropriate to avoid cluttering the drawings. Connection includes electrical connection.

[0011] First, in <Comparative Example>, a capacitance measurement circuit and a capacitance measurement method according to the comparative example are described. Then, in <Problems newly discovered by the inventor>, problems newly discovered by the inventor regarding the capacitance measurement circuit and capacitance measurement method of the comparative example are described. Then, in <Embodiment 1> to <Embodiment 4>, a semiconductor measurement device and a semiconductor measurement method according to each embodiment are described. This makes the semiconductor measurement device and the semiconductor measurement method of each embodiment clearer. Note that the capacitance measurement circuit and capacitance measurement method according to the comparative example, as well as the problems newly discovered by the inventor, are also within the technical concept of the embodiments.

[0012] <Comparative Example 1> A capacitance measuring circuit and a capacitance measuring method according to a first comparative example will be described. FIG. 1 is a circuit diagram illustrating a capacitance measuring circuit 100 according to a first comparative example. As shown in FIG. 1, the capacitance measuring circuit 100 according to the first comparative example includes a PMOS transistor MP1, a PMOS transistor MP2, an NMOS transistor MN1, and an NMOS transistor MN2. The PMOS transistor MP2 and the NMOS transistor MN2 are directly connected to each other. A reference potential REF is applied to the source of the PMOS transistor MP2. Thus, a current Iref flows through the source of the PMOS transistor MP2. The source of the NMOS transistor MN2 is grounded. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 are connected to a node N0.

[0013] A PMOS transistor MP1 and an NMOS transistor MN1 are connected in series. A test potential TST is applied to the source of the PMOS transistor MP1. Therefore, a current Itst flows through the source of the PMOS transistor MP1. The source of the NMOS transistor MN1 is grounded. The drains of the PMOS transistor MP1 and NMOS transistor MN1 are connected at a node N1.

[0014] A PMOS gate potential Gp is ​​applied to the gates of the PMOS transistors MP1 and MP2, and an NMOS gate potential Gn is applied to the gates of the NMOS transistors MN1 and MN2. A node N1 between the drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 is connected to the gate electrode of the NMOS transistor MTST(n) to be measured, which is formed in the P well region 108 of the bottom N well region 107. The PMOS transistors MP1 and MP2 are formed to have the same transistor size, and the NMOS transistors MN1 and MN2 are formed to have the same transistor size.

[0015] The NMOS transistor MTST(n) to be measured, which is formed in the P-well region 108, has a pad 121 formed on the source region, a pad 122 formed on the backgate region, and a pad 123 formed on the drain region, and a pad 120 provided in the bottom N-well region 107. Due to the presence of the bottom N-well region 107, the NMOS transistors MN1 and MN2 for CBCM (Charge-Based Capacitance Measurement) and the NMOS transistor MTST(n) to be measured are formed separately.

[0016] By providing the pads 121 and 123, it is possible to set potentials independently for the source region and drain region of the NMOS transistor MTST(n) to be measured. Furthermore, by isolating the NMOS transistors MN1 and MN2 from the NMOS transistor MTST(n) to be measured, the potential (substrate potential (backgate potential)) of the P-well region 108 can be set by the pad 122, so that the substrate potential as well as the source region and drain region of the NMOS transistor MTST(n) to be measured can be set independently from the NMOS transistors MN1 and MN2. Furthermore, by fixing the bottom N-well region 107 at a potential at which a reverse bias is applied to the PN junction by the pad 120, it is possible to improve the isolation characteristics between the NMOS transistors MN1 and MN2 for CBCM and the NMOS transistor MTST(n) to be measured.

[0017] By commonly connecting the pads 121 to 123 with an external cable and applying a fixed potential V1 to the external cable, the source-substrate junction capacitance Cjs and the drain-substrate junction capacitance Cjd can be set to "0".

[0018] Therefore, by measuring the charging current (test current Itst) to the NMOS transistor MTST(n) to be measured by the CBCM method, the gate capacitance can be measured as the target capacitance.

[0019] In this way, the general CBCM method has a circuit configuration in which a pair of PMOS transistor MP1 and NMOS transistor MN1 for charging and discharging the NMOS transistor MTST(n) to be measured is connected to a pair of PMOS transistor MP2 and NMOS transistor MN2 for canceling parasitic capacitance. The pair of PMOS transistor MP2 and NMOS transistor MN2 is not directly connected to the NMOS transistor MTST(n) to be measured.

[0020] 2 is a diagram illustrating the capacitance between the gate, drain, and source of a transistor to be measured MTST in the capacitance measuring circuit according to Comparative Example 1. As shown in FIG. 2, the capacitances Ciss, Coss, and Crss measured while changing the voltage Vds between the drain and source are defined as in the following formulas (1) to (3).

[0021] Ciss = Cgs + Cgd (1) Coss = Cgd + Cds (2) Crss=Cgd (3)

[0022] Here, the capacitance Cgs indicates the capacitance between the gate and the source, the capacitance Cgd indicates the capacitance between the gate and the drain, and the capacitance Cds indicates the capacitance between the drain and the source.

[0023] <Comparative Example 2> Next, a capacitance measuring circuit and a capacitance measuring method according to Comparative Example 2 will be described. FIG. 3 is a circuit diagram illustrating a capacitance measuring circuit 200 according to Comparative Example 2. As shown in FIG. 3, the capacitance measuring circuit 200 includes a PMOS transistor MP1, a PMOS transistor MP2, an NMOS transistor MN1, and an NMOS transistor MN2. The PMOS transistor MP1 and the NMOS transistor MN1 are directly connected. The measuring circuit SMUa is connected to the source of the PMOS transistor MP1. The ground circuit GNDU is connected to the source of the NMOS transistor MN1. The drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 are connected at a node N1.

[0024] A PMOS transistor MP2 and an NMOS transistor MN2 are connected in series. A measurement circuit SMUb is connected to the source of the PMOS transistor MP2. A ground circuit GNDU is connected to the source of the NMOS transistor MN2. The drains of the PMOS transistor MP2 and NMOS transistor MN2 are connected at a node N0.

[0025] A gate circuit Ppgu is connected to the gates of the PMOS transistors MP1 and MP2. A gate circuit Npgu is connected to the gates of the NMOS transistors MN1 and MN2. As in Comparative Example 1, the PMOS transistors MP1 and MP2 are formed to have the same transistor size, and the NMOS transistors MN1 and MN2 are formed to have the same transistor size.

[0026] A node N1 between the drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 is connected to a measurement target MTST. One end of the measurement target MTST is connected to the node N1. The other end of the measurement target MTST is grounded or set to a constant voltage. A capacitance C1 between one end and the other end of the measurement target MTST is measured.

[0027] The gate circuit Ppgu applies a pulse voltage Vp that turns the gates of the PMOS transistors MP1 and MP2 ON or OFF. The gate circuit Npgu applies a pulse voltage Vn that turns the gates of the NMOS transistors MN1 and MN2 ON or OFF. The measurement circuit SMUa applies a voltage Vdd1 (Vcc) to cause a current I (Vdd1) to flow. The measurement circuit SMUb applies a voltage Vdd2 (Vcc) to cause a current I (Vdd2) to flow.

[0028] In the capacitance measurement circuit 200 of Comparative Example 2, the gate circuit Ppgu, the gate circuit Npgu, the PMOS transistor MP1, the NMOS transistor MN1, and the ground circuit GNDU constitute a CBCM circuit. That is, the CBCM circuit may include the gate circuit Ppgu, the gate circuit Npgu, the PMOS transistor MP1, the NMOS transistor MN1, and the ground circuit GNDU. With such a configuration, the capacitance measurement circuit 200 of Comparative Example 2 measures the measurement capacitance C1 of the measurement target MTST. Note that the capacitance between the node N0 and the ground GND is the parasitic capacitance C0. The capacitance between the node N1 and the ground GND is the parasitic capacitance C0. A voltage Vnode is applied to the measurement target MTST via the node N1.

[0029] FIG. 4 is a sequence diagram illustrating the operation of the capacitance measurement circuit 200 according to Comparative Example 2. The horizontal axis represents time, and the vertical axis represents the voltage Vnode of the node N1, the current I(Vnode) of the node N1, the voltage of the gate circuit Ppgu, and the voltage of the gate circuit Npgu. FIG. 5 is a circuit diagram illustrating the charging operation of the capacitance measurement circuit 200 according to Comparative Example 2. FIG. 6 is a circuit diagram illustrating the discharging operation of the capacitance measurement circuit 200 according to Comparative Example 2.

[0030] As shown in FIGS. 4 and 5, when charging the measurement target MTST, the gate circuit Npgu applies a pulse voltage that turns off the gates of the NMOS transistors MN1 and MN2. Next, the gate circuit Ppgu applies a pulse voltage that turns on the gates of the PMOS transistors MP1 and MP2. Then, a current I(Vnode) flows through the node N1. As the current I(Vnode) flows through the node N1, the voltage Vnode of the node N1 gradually increases. Accordingly, the current I(Vnode) decreases. When the voltage Vnode of the node N1 saturates, the current I(Vnode) becomes 0. In this way, the measurement target MTST is charged with electric charge. The capacitance of the measurement target MTST is the capacitance C1. In this case, the parasitic capacitance C0 also occurs.

[0031] As shown in FIG. 4 and FIG. 6, when the measurement object MTST is discharged, the gate circuit Ppgu applies a pulse voltage to turn off the gates of the PMOS transistors MP1 and MP2. Next, the gate circuit Npgu applies a pulse voltage to turn on the gates of the NMOS transistors MN1 and MN2. Then, a current I(Vnode) flows through the node N1. As shown by the dotted lines in the figures, the measurement circuit SMUa and the measurement circuit SMUb cannot measure the discharge current. The current I(Vnode) flows through the node N1 during discharge, so that the voltage Vnode of the node N1 decreases. Accordingly, the current I(Vnode) during discharge decreases. When the voltage Vnode of the node N1 becomes 0, the current I(Vnode) during discharge becomes 0. In this way, the charge is discharged from the measurement object MTST. One cycle of charging and discharging is a period T[1 / f].

[0032] The capacitance C1 of the measurement target MTST is calculated by the following equations (4) and (5), where CO is the parasitic capacitance.

[0033] C1 = (C1 + C0) - C0 (4) =(I(Vdd1)-I(Vdd2)) / (Vcc×f) (5)

[0034] Here, the relationship of units in the above formula is shown in the following formula (6).

[0035] [F] = [A] / ([V] × [Hz]) (6)

[0036] <New problem discovered by the inventor> Next, the problems newly discovered by the inventors will be described. In the capacitance measurement circuit of Comparative Example 1, the measurement target MTST and the transistor pair for charging and discharging the measurement target MTST are arranged on the same wafer. The capacitance measurement circuit of Comparative Example 1 measures the capacitance C1 of the measurement target MTST with such a circuit configuration on the same wafer. However, for example, in the case of measuring the capacitance of a power MOS transistor, when there is only the measurement target MTST on the wafer and the transistor pair for charging and discharging the measurement target MTST is outside the wafer, it is difficult to duplicate all the configurations including the probe needles.

[0037] Also, for example, it is conceivable to switch between capacitance measurement and parasitic capacitance measurement by moving the probe needles up and down. However, in that case, it is difficult to measure the parasitic capacitance on the wafer stage side. Therefore, the parasitic capacitance on the wafer stage side cannot be canceled. Furthermore, a configuration in which a CBCM circuit is installed on the wafer stage side and a measurement circuit is arranged on the opposite side sandwiching the measurement target can be considered to ignore the parasitic capacitance of the wafer stage. However, in that case, it is difficult to measure the parasitic capacitance from the measurement circuit to the probe needles, and the parasitic capacitance from the measurement circuit to the probe needles cannot be canceled.

[0038] <Embodiment 1> Next, the semiconductor measurement device and the semiconductor measurement method according to Embodiment 1 will be described. FIG. 7 is a circuit diagram illustrating a main part of the semiconductor measurement device 1 according to Embodiment 1. As shown in FIG. 7, the semiconductor measurement device 1 includes a CBCM circuit 10 and a potential difference application circuit 13. The CBCM circuit 10 has a first terminal T01 and a connection terminal T03. The potential difference application circuit 13 is connected to the connection terminal T03. The potential difference application circuit 13 also has a second terminal T02. The potential difference application circuit 13 outputs a predetermined potential difference to the second terminal T02 with respect to the output of the first terminal T01.

[0039] The semiconductor measuring apparatus 1 measures the capacitance Coss of the measurement object MTST, etc. For example, the semiconductor measuring apparatus 1 measures the capacitance in a connected state where the first terminal T01 and the second terminal T02 are connected to the measurement object MTST, and the capacitance in a disconnected state where the first terminal T01 and the second terminal T02 are disconnected from the measurement object MTST. In this way, the semiconductor measuring apparatus 1 finds the parasitic capacitance of the measurement system from the capacitance in the connected state and the capacitance in the disconnected state, and calculates the capacitance Coss of the measurement object MTST, etc. The measurement system includes, for example, a stage.

[0040] As described above, the CBCM circuit 10 has a charge transistor and a discharge transistor. The charge transistor outputs a predetermined charge voltage to the measurement object MTST via the first terminal T01 and the second terminal T02. The discharge transistor outputs a predetermined discharge voltage to the measurement object MTST via the first terminal T01 and the second terminal T02.

[0041] 8 and 9 are circuit diagrams illustrating the semiconductor measuring apparatus 1 according to the embodiment 1. As shown in Fig. 8, the semiconductor measuring apparatus 1 of the embodiment may measure the capacitances of a plurality of measurement objects MTST, or may measure the capacitance of one measurement object MTST as shown in Fig. 9.

[0042] The semiconductor measuring device 1 may include components arranged on the stage STG (ground circuit GNDU, etc.) and components separated from the stage STG (probe card, CBCM circuit 10, measuring circuit SMUa, etc.). The measuring object MTST is formed on a wafer WF placed on the stage STG. The components separated from the stage STG and the measuring object MTST in the semiconductor measuring device 1 are collectively called a measuring object DUT. In FIG. 9, the semiconductor measuring device 1 includes one measuring object DUT. In FIG. 8, the semiconductor measuring device 1 includes a plurality of measuring objects DUT1 to DUT3 arranged in parallel. Note that the plurality of measuring objects DUT are not limited to three measuring objects DUT1 to DUT3, and may include two measuring objects DUT1 to DUT2, or may include four or more measuring objects DUT. In the following, for convenience of explanation, a description will be given using FIG. 9.

[0043] The measurement target MTST includes a transistor MTR. The transistor MTR is formed on a wafer WF. The transistor MTR may include a gate G, a source S, and a drain D, or may include a base, an emitter, and a collector. In the following, a transistor MTR including a gate G, a source S, and a drain D will be described. When a plurality of transistors MTR are measured, each transistor MTR includes gates G1 to G3, sources S1 to S3, and drains D1 to D3, respectively.

[0044] The gate G is connected to a gate terminal TG. Thus, the terminal of the gate G is the gate terminal TG. The source S is connected to a source terminal TS. Thus, the terminal of the source S is the source terminal TS. The drain D is connected to a drain terminal TD. Thus, the terminal of the drain D is the drain terminal TG.

[0045] The source S or emitter may be called the first region, and the source terminal TS or emitter terminal may be called the first region terminal. In this case, the first region includes the source S or the emitter. The drain D or collector may be called the second region, and the drain terminal TD or collector terminal may be called the second region terminal. In this case, the second region includes the drain D or the collector. Note that the source S or the emitter may be replaced with the second region, and the source terminal TS or the emitter terminal may be replaced with the second region terminal. The drain D or the collector may be replaced with the first region, and the drain terminal TD or the collector terminal may be replaced with the first region terminal.

[0046] As shown in FIG. 9, the semiconductor measuring device 1 may include a measuring circuit SMUa, a switch terminal TSW1, a gate switch SWG1, a ground circuit GNDU, a drain switch SWD, probe needles H1 and H2, and a control unit 20 in addition to the CBCM circuit 10 and the potential difference applying circuit 13. The semiconductor measuring device 1 may further include components other than those described above, or may omit some of the components described above. The drain switch SWD may be referred to as a second region switch. The drain switch SWD may be replaced with a first region switch. The CBCM circuit 10 further includes a measuring terminal T04.

[0047] The measurement circuit SMUa is connected to the measurement terminal T04 in the CBCM circuit 10. The measurement circuit SMUa applies a voltage Vforce to the CBCM circuit 10 via the measurement terminal T04 and measures the current Imeas.

[0048] The probe needles H1 and H2 switch between a connected state in which the first terminal T01 and the second terminal T02 are connected to the transistor MTR, and a disconnected state in which the first terminal T01 and the second terminal T02 are disconnected from the transistor MTR. The probe needles H1 and H2 operate in conjunction with each other. In the connected state, the probe needle H1 connects the source terminal TS to the first terminal T01. In the connected state, the probe needle H2 connects the gate terminal TG to the switch terminal TSW1. On the other hand, in the disconnected state, the probe needle H1 disconnects the source terminal TS from the first terminal T01. In the disconnected state, the probe needle H2 disconnects the gate terminal TG from the switch terminal TSW1.

[0049] The switch terminal TSW1 is connected to the gate terminal TG in the connected state. The switch terminal TSW1 is disconnected from the gate terminal TG in the disconnected state. The first terminal T01 is connected to the source terminal TS in the connected state. The first terminal T01 is disconnected from the source terminal TS in the disconnected state.

[0050] The gate switch SWG1 has one end and the other end. One end of the gate switch SWG1 is fixed to a switch terminal TSW1. The other end of the gate switch SWG1 is connected to the first terminal T01 or the second terminal T02. In this manner, the gate switch SWG1 connects the switch terminal TSW1 to the first terminal T01 or the second terminal T02.

[0051] The drain terminal TD is connected to the drain switch SWD. The drain switch SWD is connected to the ground circuit GNDU. The ground circuit GNDU outputs a ground potential. The drain switch SWD connects and disconnects the drain terminal TD and the ground circuit GNDU.

[0052] The control unit 20 controls the operations of the gate switch SWG1, the drain switch SWD, the probe needles H1 and H2, and the measurement circuit SMUa. The control unit 20 may control the operation of the semiconductor measurement method described below.

[0053] Next, a semiconductor measurement method for the measurement target MTST using the semiconductor measuring apparatus 1 will be described. FIG. 10 is a diagram illustrating a semiconductor measurement method in the semiconductor measuring apparatus 1 according to the first embodiment. As shown in FIG. 10, the semiconductor measurement method of this embodiment includes Measurement II, Measurement I-II, Measurement I-III, and Measurement I-IV. Each measurement may be performed under the control of the control unit 20. Note that a part or all of each measurement may be performed manually by a user of the semiconductor measuring apparatus 1.

[0054] First, as shown in measurement II in FIG. 10, the control unit 20 connects the switch terminal TSW1 and the second terminal T02 in the gate switch SWG1. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW1. This results in a configuration in which the output of the second terminal T02 of the CBCM circuit 10 is applied to the gate G. The output of the second terminal T02 is applied with a potential difference (e.g., 10 V) to the first terminal T01 by the potential difference applying circuit 13. This results in a potential Vgs (e.g., 10 V) being generated between the gate G and the source S when the probe needles H1 and H2 are down.

[0055] In addition, the control unit 20 turns off the drain switch SWD. Furthermore, when the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This causes the output of the first terminal T01 of the CBCM circuit 10 to be applied to the source S.

[0056] In this configuration, the control unit 20 raises the probe needle H1 to disconnect the source terminal TS from the first terminal T01. The control unit 20 also raises the probe needle H2 to disconnect the gate terminal TG from the switch terminal TSW1. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitances C01 of the multiple measurement objects DUTs from the sum of the currents flowing through the measurement terminals T04 of the measurement objects DUTs.

[0057] Next, as shown in measurement I-II in Fig. 10, the control unit 20 connects the switch terminal TSW1 and the second terminal T02 of the gate switch SWG1. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW1. This results in a configuration in which the output of the second terminal T02 of the CBCM circuit 10 is applied to the gate G.

[0058] In addition, the control unit 20 turns off the drain switch SWD. Furthermore, when the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This causes the output of the first terminal T01 of the CBCM circuit 10 to be applied to the source S.

[0059] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the first terminal T01. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW1. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitances C01 of the multiple measurement objects DUTs and the parasitic capacitance Cstg of the entire stage STG from the sum of the currents flowing through the measurement terminals T04 of the measurement objects DUTs.

[0060] Next, as shown in measurements I-III in Fig. 10, the control unit 20 connects the switch terminal TSW1 and the first terminal T01 of the gate switch SWG1. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the gate G. Therefore, when the probe needles H1 and H2 are down, the potential Vgs between the gate G and the source S becomes 0V.

[0061] The control unit 20 also connects the drain switch SWD. This applies the ground potential to the drain D via the drain terminal TD. When the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This configures the source S to receive the output of the first terminal T01 of the CBCM circuit 10.

[0062] In this configuration, the control unit 20 raises the probe needle H1 to disconnect the source terminal TS and the first terminal T01. The control unit 20 also raises the probe needle H2 to disconnect the gate terminal TG and the switch terminal TSW1. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitance C0 of each measurement object DUT from the current flowing through each measurement terminal T04 of each measurement object DUT.

[0063] Next, as shown in measurements I-IV in Fig. 10, the control unit 20 connects the switch terminal TSW1 and the first terminal T01 of the gate switch SWG1. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the gate G.

[0064] The control unit 20 also connects the drain switch SWD. This applies the ground potential to the drain D via the drain terminal TD. When the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This configures the source S to receive the output of the first terminal T01 of the CBCM circuit 10.

[0065] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the first terminal T01. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW1. In this case, the control unit 20 causes the measurement circuit SMUa to measure the capacitance Coss of the transistor MTR, the parasitic capacitance C0 of each measurement object DUT, and the parasitic capacitance Cstg of the stage STG of each measurement object DUT from the current flowing through each measurement terminal T04 of each measurement object DUT.

[0066] From the measurements II and I-II, the semiconductor measuring apparatus 1 can calculate the parasitic capacitance Cstg of the entire stage STG. Here, the value obtained by dividing the parasitic capacitance Cstg of the entire stage STG by the number of parallel DUTs to be measured can be approximately regarded as the parasitic capacitance Cstg of the stage STG of each DUT to be measured. Also, the parasitic capacitance C0 of each DUT to be measured can be calculated from the measurements I-III. Then, from the parasitic capacitance Cstg and the parasitic capacitance C0 obtained from the measurements II, I-II, and I-III, and the measurements I-IV, the semiconductor measuring apparatus 1 can calculate the capacitance Coss of the transistor MTR of each DUT to be measured. Specifically, the semiconductor measuring device 1 can calculate the capacitance Coss of the transistor MTR from (the capacitance Coss of the transistor MTR of each measured object DUT, the parasitic capacitance C0 of each measured object DUT, and the parasitic capacitance Cstg of the stage STG) - (the parasitic capacitance C0 of each measured object DUT) - (the parasitic capacitance Cstg of the entire stage STG / the number of parallel measured object DUTs).

[0067] Next, the effects of this embodiment will be described. The semiconductor measuring device 1 of this embodiment includes a potential difference applying circuit 13 that applies a relative potential difference to the output of the CBCM circuit 10. As a result, the semiconductor measuring device 1 can suppress the occurrence of charging and discharging of the parasitic capacitances Cgd and Cgs of the transistors of the measurement target MTST by driving the gate G of the transistor of the measurement target MTST. This improves the measurement accuracy of the capacitance of the measurement target MTST. In this way, the semiconductor measuring device 1 of this embodiment provides an offset voltage that is linked to the output of the CBCM circuit 10, and enables cancellation of the parasitic capacitance by turning on the gate G of the device of the measurement target MTST as necessary.

[0068] Furthermore, in order to measure the parasitic capacitance C0 and the like, the semiconductor measuring device 1 sets the transistor to be measured MTST in the ON state (the drain-source can be regarded as a simple resistive element). Therefore, the target range of charging and discharging (parasitic capacitance measurement range) of the CBCM method using the CBCM circuit 10 can be expanded.

[0069] A related semiconductor measurement method is the automatic balancing bridge method using an LCR meter. The automatic balancing bridge method can only measure one device at a time during wafer testing, for example, and cannot perform parallel measurement. This places a high burden on the cost of the automatic balancing bridge method. In addition, when parallelizing capacitance measurements during wafer testing using a general CBCM circuit, there is an issue with how to cancel parasitic capacitance of the stage, etc., making it difficult to parallelize capacitance measurements.

[0070] In contrast, the semiconductor measuring device 1 of this embodiment can form a path for charging and discharging to the stage by applying a potential difference to the gate G of a transistor (measurement target) on the wafer in conjunction with the output of the CBCM circuit 10. Therefore, during wafer testing, the parasitic capacitance Cstg of the stage can be canceled, and capacitance measurements using the CBCM circuit 10 can be parallelized. In addition, the potential of the gate G is synchronized with the first terminal of the CBCM circuit 10 to maintain a constant potential difference Vgs, so that no charging or discharging occurs to the parasitic capacitance Cgs and parasitic capacitance Cgd of the transistor when measuring the parasitic capacitance Cstg of the stage, and therefore the accuracy of measuring the parasitic capacitance Cstg of the stage can be improved.

[0071] <Embodiment 2> Next, a semiconductor measuring device and a semiconductor measuring method according to the second embodiment will be described. Fig. 11 and Fig. 12 are circuit diagrams illustrating a semiconductor measuring device 2 according to the second embodiment. As shown in Fig. 11, the semiconductor measuring device 2 of this embodiment may measure the capacitances of a plurality of measurement targets MTST, or as shown in Fig. 12, may measure the capacitance of one measurement target MTST. For convenience of explanation, the following description will be given with reference to Fig. 12. When measuring a plurality of measurement targets MTST, a plurality of measurement targets DUT are arranged in parallel.

[0072] 12, in addition to the CBCM circuit 10 and the potential difference applying circuit 13, the semiconductor measuring apparatus 2 may include a measuring circuit SMUa, a measuring circuit SMUb, a switch terminal TSW2, a gate switch SWG2, an auxiliary terminal TH2 and an auxiliary switch SWH2, probe needles H1 and H2, and a control unit 20. Note that the semiconductor measuring apparatus 2 may further include components other than those described above, or may omit some of the components described above. The measuring circuit SMUb may be referred to as an auxiliary measuring circuit.

[0073] The measurement circuit SMUa is connected to the measurement terminal T04 in the CBCM circuit 10. The measurement circuit SMUa applies a voltage Vforce to the CBCM circuit 10 via the measurement terminal T04 and measures the current Imeas.

[0074] Probe needle H1 and probe needle H2 operate in conjunction with each other. In a connected state, probe needle H1 connects the source terminal TS and the auxiliary terminal TH2. In a connected state, probe needle H2 connects the gate terminal TG and the switch terminal TSW2. On the other hand, in a disconnected state, probe needle H1 disconnects the source terminal TS and the auxiliary terminal TH2. In a disconnected state, probe needle H2 disconnects the gate terminal TG and the switch terminal TSW2.

[0075] The switch terminal TSW2 is connected to the gate terminal TG in the connected state. The switch terminal TSW2 is disconnected from the gate terminal TG in the disconnected state. The auxiliary terminal TH2 is connected to the source terminal TS in the connected state. The auxiliary terminal TH2 is disconnected from the source terminal TS in the disconnected state. The first terminal T01 is connected to the drain terminal TD.

[0076] The gate switch SWG2 has one end and the other end. One end of the gate switch SWG2 is fixed to the switch terminal TSW2. The other end of the gate switch SWG2 is connected to the second terminal T02 or the auxiliary terminal TH02. In this manner, the gate switch SWG2 connects the switch terminal TSW2 to the second terminal T02 or the auxiliary terminal TH2.

[0077] The measuring circuit SMUb is connected to the auxiliary switch SWH2. The auxiliary switch SWH2 is connected to the auxiliary terminal TH2. Thus, the auxiliary switch SWH2 connects and disconnects the auxiliary terminal TH2 and the measuring circuit SMUb. When the auxiliary switch SWH2 is connected, the measuring circuit SMUb performs feedback control so that the current Iforce flowing through the auxiliary terminal TH2 becomes zero. In this manner, the measuring circuit SMUb may further include a measuring circuit SMUb that outputs a predetermined voltage to the auxiliary terminal TH2. The measuring circuit SMUb may have either the function of being able to perform feedback control so that the current flowing through the auxiliary terminal TH2 becomes zero, or the function of having the auxiliary switch SWH2 that connects and disconnects the auxiliary terminal TH2 and the measuring circuit SMUb.

[0078] The control unit 20 controls the operations of the gate switch SWG2, the auxiliary switch SWH2, the probe needles H1 and H2, the measuring circuit SMUa, and the measuring circuit SMUb. The control unit 20 may control the operation of the semiconductor measuring method described below.

[0079] Next, a description will be given of a semiconductor measurement method for the measurement target MTST using the semiconductor measurement apparatus 2. Fig. 13 is a diagram illustrating a semiconductor measurement method in the semiconductor measurement apparatus 2 according to embodiment 2. As shown in Fig. 13, the semiconductor measurement method of this embodiment includes Measurement II-I, Measurement II-II, and Measurement II-IV.

[0080] First, as shown in measurement II-I of FIG. 13, the control unit 20 connects the switch terminal TSW2 and the second terminal T02 of the gate switch SWG2. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW2. As a result, the output of the second terminal T02 of the CBCM circuit 10 is applied to the gate G. The output of the second terminal T02 is applied with a potential difference (for example, 10 V) to the first terminal T01 by the potential difference applying circuit 13. As a result, when the probe needles H1 and H2 are down, a potential Vgd (for example, 10 V) is generated between the gate G and the drain D.

[0081] Also, the drain terminal TD is connected to the first terminal T01 in the CBCM circuit 10. Therefore, the drain D is configured to receive the output of the first terminal 11 of the CBCM circuit 10. Furthermore, the control unit 20 disconnects the auxiliary terminal TH2 or connects the auxiliary switch SWH2 to feedback control the measuring device SMUb. When the probe needle H1 is down, the source terminal TS is connected to the auxiliary terminal TH2. When the auxiliary switch SWH2 is disconnected, the source S is open. When the auxiliary switch SWH2 is connected, the measuring device SMUb performs feedback control so that the current Iforce flowing through the auxiliary terminal TH2 becomes 0. As a result, the source S is configured to have a current of 0. In this way, the measuring circuit SMUb may further include a measuring circuit SMUb that outputs a predetermined voltage to the auxiliary terminal TH2. The measuring circuit SMUb may have either a function of performing feedback control so that the current flowing through the auxiliary terminal TH2 becomes 0, or a function of having an auxiliary switch SWH2 that connects and disconnects the auxiliary terminal TH2 and the measuring circuit SMUb.

[0082] In this configuration, the control unit 20 raises the probe needle H1 to disconnect the source terminal TS from the auxiliary terminal TH2. The control unit 20 also raises the probe needle H2 to disconnect the gate terminal TG from the switch terminal TSW2. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitance Cstg of the stage STG from the current flowing through the measurement terminal T04.

[0083] Next, as shown in measurement II-II of Fig. 13, the control unit 20 connects the switch terminal TSW2 and the second terminal T02 of the gate switch SWG2. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW2. This results in a configuration in which the output of the second terminal T02 of the CBCM circuit 10 is applied to the gate G.

[0084] Also, the drain terminal TD is connected to the first terminal T01 in the CBCM circuit 10. Therefore, the drain D is configured to receive the output of the first terminal 11 of the CBCM circuit 10. Furthermore, the control unit 20 disconnects the auxiliary terminal TH2 or connects the auxiliary switch SWH2 to perform feedback control on the measurement device SMUb.

[0085] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the auxiliary terminal TH2. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW2. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitances C01 of the multiple measurement objects DUT and the parasitic capacitance Cstg of the stage STG from the current flowing through the measurement terminal T04.

[0086] 13, the control unit 20 connects the switch terminal TSW2 and the auxiliary terminal TH2 to the gate switch SWG2. Therefore, when the probe needle H2 is down, the output of the measurement circuit SMUb is applied to the gate G via the auxiliary switch SWH2.

[0087] Furthermore, the drain D is connected to the first terminal T01 in the CBCM circuit 10. Therefore, the drain D is configured to receive the output of the first terminal T01 of the CBCM circuit 10. Furthermore, the control unit 20 connects the auxiliary switch SWH2. Then, the control unit 20 outputs Vforce=0 to the measurement circuit SMUb. As a result, when the probe needle H1 is down, the source terminal TS is connected to the measurement circuit SMUb. Therefore, the source S is configured to receive Vforce=0.

[0088] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the auxiliary terminal TH2. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW2. In this case, the control unit 20 causes the measurement circuit SMUb to measure the capacitance Coss of the transistor MTR and the parasitic capacitance C0 of each measurement object DUT from the current flowing through each auxiliary terminal TH2 of each measurement object DUT.

[0089] From measurements II-I and II-II, the semiconductor measuring device 2 can calculate the parasitic capacitance C01 of the multiple DUTs to be measured. Here, the value obtained by dividing C01 by the number of parallel DUTs to be measured can be approximately regarded as the parasitic capacitance C0 of each DUT to be measured. In addition, from the calculated parasitic capacitance C01 and measurements I-IV, the semiconductor measuring device 2 can calculate the capacitance Coss of the transistor MTR by (the capacitance Coss of the transistor MTR of each DUT to be measured and the parasitic capacitance C0 of each DUT to be measured)-(the parasitic capacitance C01 of each DUT to be measured / the number of parallel DUTs to be measured).

[0090] According to this embodiment, even if the CBCM circuit 10 is arranged on the stage side, the semiconductor measuring device 2 can suppress the occurrence of charging and discharging to the parasitic capacitances Cgd and Cgs of the transistor MTR by driving the gate G of the transistor MTR that is the measurement target MTST. This can improve the measurement accuracy of the capacitance Coss of the transistor MTR. Other configurations and effects are included in the description of the first embodiment.

[0091] <Embodiment 3> Next, a semiconductor measuring device and a semiconductor measuring method according to the third embodiment will be described. Fig. 14 and Fig. 15 are circuit diagrams illustrating a semiconductor measuring device 3 according to the third embodiment. As shown in Fig. 14, the semiconductor measuring device 3 may measure the capacitances of a plurality of measurement targets MTST, or as shown in Fig. 15, may measure the capacitance of one measurement target MTST. For convenience of explanation, Fig. 15 will be used below for explanation. When measuring a plurality of measurement targets MTST, a plurality of measurement targets DUT are arranged in parallel.

[0092] As shown in FIG. 15, in addition to the CBCM circuit 10 and the potential difference applying circuit 13, the semiconductor measuring device 3 may include a switch terminal TSW31, a switch terminal TSW32, a gate switch SWG3, a source switch SWS3, a ground circuit GNDU, a drain switch SWD, probe needles H1 and H2, a measurement circuit SMUa, and a control unit 20. Note that the semiconductor measuring device 3 may further include members other than those described above, or some of the above members may be omitted. The source switch SWS3 may be referred to as a first region switch. Note that the source switch SWS3 may be replaced with a second region switch. The measurement circuit SMUa is connected to the measurement terminal T04 in the CBCM circuit 10. The measurement circuit SMUa applies a voltage Vforce to the CBCM circuit 10 via the measurement terminal T04 and measures a current Imeas.

[0093] The probe needles H1 and H2 operate in conjunction. In the connected state, the probe needle H1 connects the source terminal TS and the switch terminal TSW32. In the connected state, the probe needle H2 connects the gate terminal TG and the switch terminal TSW31. On the other hand, in the disconnected state, the probe needle H1 disconnects the source terminal TS and the switch terminal TSW32. In the disconnected state, the probe needle H2 disconnects the gate terminal TG and the switch terminal TSW31.

[0094] In the connected state, the switch terminal TSW31 connects to the gate terminal TG. In the disconnected state, the switch terminal TSW31 disconnects from the gate terminal TG. In the connected state, the switch terminal TSW32 connects to the source terminal TS. In the disconnected state, the switch terminal TSW32 disconnects from the source terminal TS.

[0095] The gate switch SWG3 has one end and the other end. One end of the gate switch SWG3 is fixed to a switch terminal TSW31. The other end of the gate switch SWG3 is connected to the first terminal T01 or the second terminal T02. In this manner, the gate switch SWG3 connects the switch terminal TSW31 to the first terminal T01 or the second terminal T02.

[0096] The source switch SWS3 has one end and the other end. One end of the source switch SWS3 is fixed to the switch terminal TSW32. The other end of the source switch SWG3 is connected to the first terminal T01 or the drain terminal TD. In this manner, the source switch SWS3 connects the switch terminal TSW32 to the first terminal T01 or the drain terminal TD.

[0097] The drain terminal TD is connected to the drain switch SWD. The drain switch SWD is connected to the ground circuit GNDU. The ground circuit GNDU outputs a ground potential. The drain switch SWD connects and disconnects the drain terminal TD and the ground circuit GNDU.

[0098] The control unit 20 controls the operations of the gate switch SWG3, the drain switch SWD, the source switch SWS3, the probe needles H1 and H2, and the measurement circuit SMUa. The control unit 20 may control the operation of the semiconductor measurement method described below.

[0099] Next, a description will be given of a semiconductor measurement method for the measurement target MTST using the semiconductor measurement apparatus 3. Fig. 16 is a diagram illustrating a semiconductor measurement method in the semiconductor measurement apparatus 3 according to embodiment 3. As shown in Fig. 16, the semiconductor measurement method of this embodiment includes Measurement III-I, Measurement III-II, Measurement III-III, and Measurement III-IV.

[0100] First, as shown in Measurement III-I of FIG. 16, the control unit 20 connects the switch terminal TSW31 and the second terminal T02 to the gate switch SWG3. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW31. As a result, the gate G is configured such that the output of the second terminal T02 of the CBCM circuit 10 is applied.

[0101] Also, the control unit 20 connects the switch terminal TSW32 and the first terminal T01 to the source switch SWS3. Therefore, when the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. As a result, the source S is configured such that the output of the first terminal T01 of the CBCM circuit 10 is applied. Further, the control unit 20 disconnects the drain switch SWD.

[0102] With such a configuration, the control unit 20 raises the probe needle H1 and disconnects the source terminal TS and the switch terminal TSW32. Also, the control unit 20 raises the probe needle H2 and disconnects the gate terminal TG and the switch terminal TSW31. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitance C01 of the plurality of measurement devices DUT from the sum of the currents flowing through the measurement terminals T04 of each measurement device DUT.

[0103] Next, as shown in Measurement III-II of FIG. 16, the control unit 20 connects the switch terminal TSW31 and the second terminal T02 to the gate switch SWG3. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW31. As a result, the gate G is configured such that the output of the second terminal T02 of the CBCM circuit 10 is applied.

[0104] Furthermore, the control unit 20 causes the source switch SWS3 to connect the switch terminal TSW32 to the first terminal T01. Therefore, when the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the source S. Furthermore, the control unit 20 causes the drain switch SWD to be disconnected.

[0105] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the switch terminal TSW32. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW31. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitances C01 of the multiple measurement objects DUTs and the parasitic capacitance Cstg of the entire stage STG from the sum of the currents flowing through the measurement terminals T04 of the respective measurement objects DUTs.

[0106] Next, as shown in measurement III-III in Fig. 16, the control unit 20 connects the switch terminal TSW31 and the first terminal T01 in the gate switch SWG3. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the gate G.

[0107] The control unit 20 also connects the switch terminal TSW32 and the drain terminal TD to the source switch SWS3. As a result, when the probe needle H1 is down, the source terminal TS is connected to the drain terminal TD. Furthermore, the control unit 20 connects the drain switch SWD. As a result, the ground potential is applied to the drain D via the drain terminal TD.

[0108] In this configuration, the control unit 20 raises the probe needle H1 to disconnect the source terminal TS from the switch terminal TSW32. The control unit 20 also raises the probe needle H2 to disconnect the gate terminal TG from the switch terminal TSW31. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitance C0 of each measurement object DUT from the current flowing through the measurement terminal T04 of each measurement object DUT.

[0109] Next, as shown in measurements III-IV in Fig. 16, the control unit 20 connects the switch terminal TSW31 and the first terminal T01 in the gate switch SWG3. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the gate G.

[0110] In addition, the control unit 20 connects the switch terminal TSW32 and the drain terminal TD to the source switch SWS3. As a result, when the probe needle H1 is down, the source terminal TS is connected to the drain terminal TD. Furthermore, the control unit 20 connects the drain switch SWD.

[0111] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the switch terminal TSW32. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW31. In this case, the control unit 20 causes the measurement circuit SMUa to measure the capacitance Ciss of the transistor MTR, the parasitic capacitance C0 of each measurement object DUT, and the parasitic capacitance Cstg of the stage from the current flowing through each measurement terminal T04 of each measurement object DUT.

[0112] From the measurements III-I and III-II, the semiconductor measuring device 3 can calculate the parasitic capacitance Cstg of the entire stage STG. Here, the value obtained by dividing the parasitic capacitance Cstg of the entire stage STG by the number of parallel DUTs to be measured can be approximately regarded as the parasitic capacitance Cstg of the stage STG of each DUT to be measured. Also, the parasitic capacitance C0 of each DUT to be measured can be calculated from the measurements III-III. Furthermore, from the parasitic capacitance Cstg and the parasitic capacitance C0 obtained from the measurements III-I, III-II, and III-III, and the measurements III-IV, the semiconductor measuring device 3 can calculate the capacitance Ciss of the transistor MTR of each DUT to be measured. Specifically, the semiconductor measuring device 3 can calculate the capacitance Ciss of the transistor MTR from (the capacitance Ciss of the transistor MTR of each measured object DUT, the parasitic capacitance C0 of each measured object DUT, and the parasitic capacitance Cstg of the stage STG) - (the parasitic capacitance C0 of each measured object DUT) - (the parasitic capacitance Cstg of the entire stage STG / the number of parallel measured object DUTs).

[0113] According to this embodiment, the capacitance Ciss of the transistor MTR of the measurement target MTST can be measured with high accuracy. Other configurations and effects are included in the description of the first and second embodiments.

[0114] <Embodiment 4> Next, a semiconductor measuring device and a semiconductor measuring method according to the fourth embodiment will be described. Fig. 17 and Fig. 18 are circuit diagrams illustrating a semiconductor measuring device 4 according to the fourth embodiment. As shown in Fig. 17, the semiconductor measuring device 4 may measure the capacitances of a plurality of measurement targets MTST, or as shown in Fig. 18, may measure the capacitance of one measurement target MTST. For convenience of explanation, Fig. 18 will be used below for explanation. When measuring a plurality of measurement targets MTST, a plurality of measurement targets DUT are arranged in parallel.

[0115] 18, the semiconductor measuring apparatus 4 may include, in addition to the CBCM circuit 10 and the potential difference applying circuit 13, switch terminals TSW41 and TSW42, a gate switch SWG4, a source switch SWS4, a ground circuit GNDU, a drain switch SWD, probe needles H1 and H2, a measuring circuit SMUa, and a control unit 20. The semiconductor measuring apparatus 4 may further include components other than those described above, or may omit some of the components described above. The measuring circuit SMUa is connected to a measuring terminal T04 in the CBCM circuit 10. The measuring circuit SMUa applies a voltage Vforce to the CBCM circuit 10 via the measuring terminal T04 and measures a current Imeas.

[0116] Probe needle H1 and probe needle H2 operate in conjunction with each other. In a connected state, probe needle H1 connects the source terminal TS and the switch terminal TSW42. In a connected state, probe needle H2 connects the gate terminal TG and the switch terminal TSW41. On the other hand, in a disconnected state, probe needle H1 disconnects the source terminal TS and the switch terminal TSW42. In a disconnected state, probe needle H2 disconnects the gate terminal TG and the switch terminal TSW41.

[0117] The switch terminal TSW41 is connected to the gate terminal TG in the connected state. The switch terminal TSW41 is disconnected from the gate terminal TG in the disconnected state. The switch terminal TSW42 is connected to the source terminal TS in the connected state. The switch terminal TSW42 is disconnected from the source terminal TS in the disconnected state.

[0118] The gate switch SWG4 has one end and the other end. One end of the gate switch SWG4 is fixed to a switch terminal TSW41. The other end of the gate switch SWG4 is connected to the first terminal T01 or the second terminal T02. In this manner, the gate switch SWG4 connects the switch terminal TSW41 to the first terminal T01 or the second terminal T02.

[0119] The source switch SWS4 connects and disconnects the switch terminal TSW42 and the first terminal T01. The drain terminal TD is connected to the drain switch SWD. The drain switch SWD is connected to the ground circuit GNDU. The ground circuit GNDU outputs a ground potential. The drain switch SWD connects and disconnects the drain terminal TD and the ground circuit GNDU.

[0120] The control unit 20 controls the operations of the gate switch SWG4, the drain switch SWD, the source switch SWS4, the probe needles H1 and H2, and the measurement circuit SMUa. The control unit 20 may control the operation of the semiconductor measurement method described below.

[0121] Next, a description will be given of a semiconductor measurement method for the measurement target MTST using the semiconductor measurement apparatus 4. Fig. 19 is a diagram illustrating a semiconductor measurement method in the semiconductor measurement apparatus 4 according to embodiment 4. As shown in Fig. 19, the semiconductor measurement method of this embodiment includes measurements IV-I, IV-II, IV-III, and IV-IV.

[0122] First, as shown in measurement IV-I of Fig. 19, the control unit 20 connects the switch terminal TSW41 and the second terminal T02 of the gate switch SWG4. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW41. This results in a configuration in which the output of the second terminal T02 of the CBCM circuit 10 is applied to the gate G.

[0123] Furthermore, the control unit 20 causes the source switch SWS4 to connect the switch terminal TSW42 to the first terminal T01. Therefore, when the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the source S. Furthermore, the control unit 20 causes the drain switch SWD to be disconnected.

[0124] In this configuration, the control unit 20 raises the probe needle H1 to disconnect the source terminal TS from the switch terminal TSW42. The control unit 20 also raises the probe needle H2 to disconnect the gate terminal TG from the switch terminal TSW41. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitances C01 of the multiple measurement objects DUTs from the sum of the currents flowing through the measurement terminals T04 of the measurement objects DUTs.

[0125] Next, as shown in measurement IV-II of Fig. 19, the control unit 20 connects the switch terminal TSW41 and the second terminal T02 of the gate switch SWG4. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the switch terminal TSW41. This results in a configuration in which the output of the second terminal T02 of the CBCM circuit 10 is applied to the gate G.

[0126] Furthermore, the control unit 20 causes the source switch SWS4 to connect the switch terminal TSW42 to the first terminal T01. Therefore, when the probe needle H1 is down, the source terminal TS is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the source S. Furthermore, the control unit 20 causes the drain switch SWD to be disconnected.

[0127] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the switch terminal TSW42. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW41. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitances C01 of the multiple measurement objects DUTs and the parasitic capacitance Cstg of the entire stage STG from the sum of the currents flowing through the measurement terminals T04 of the measurement objects DUTs.

[0128] Next, as shown in measurements IV-III in Fig. 19, the control unit 20 connects the switch terminal TSW41 and the first terminal T01 of the gate switch SWG4. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the gate G.

[0129] The control unit 20 also controls the source switch SWS4 to disconnect the switch terminal TSW42 from the first terminal T01. Furthermore, the control unit 20 controls the drain switch SWD to connect. As a result, the ground potential is applied to the drain D via the drain terminal TD.

[0130] In this configuration, the control unit 20 raises the probe needle H1 to disconnect the source terminal TS from the switch terminal TSW42. The control unit 20 also raises the probe needle H2 to disconnect the gate terminal TG from the switch terminal TSW41. In this case, the control unit 20 causes the measurement circuit SMUa to measure the parasitic capacitance C0 of each measurement object DUT from the current flowing through the measurement terminal T04 of each measurement object DUT.

[0131] Next, as shown in measurement IV-IV in Fig. 19, the control unit 20 causes the gate switch SWG4 to connect the switch terminal TSW41 and the first terminal T01. Therefore, when the probe needle H2 is down, the gate terminal TG is connected to the first terminal T01. This results in a configuration in which the output of the first terminal T01 of the CBCM circuit 10 is applied to the gate G.

[0132] In addition, the control unit 20 causes the source switch SWS4 to disconnect the switch terminal TSW42 from the first terminal T01. Furthermore, the control unit 20 causes the drain switch SWD to connect.

[0133] In this configuration, the control unit 20 lowers the probe needle H1 to connect the source terminal TS and the switch terminal TSW42. The control unit 20 also lowers the probe needle H2 to connect the gate terminal TG and the switch terminal TSW41. In this case, the control unit 20 causes the measurement circuit SMUa to measure the capacitance Crss of the transistor MTR, the parasitic capacitance C0 of each measurement object DUT, and the parasitic capacitance Cstg of the stage from the current flowing through each measurement terminal T04 of each measurement object DUT.

[0134] From the measurements IV-I and IV-II, the semiconductor measuring device 4 can calculate the parasitic capacitance Cstg of the entire stage STG. Here, the value obtained by dividing the parasitic capacitance Cstg of the entire stage STG by the number of parallel DUTs to be measured can be approximately regarded as the parasitic capacitance Cstg of the stage STG of each DUT to be measured. Also, the parasitic capacitance C0 of each DUT to be measured can be calculated from the measurements IV-III. Furthermore, from the parasitic capacitance Cstg and the parasitic capacitance C0 obtained from the measurements IV-I, IV-II, and IV-III, and the measurements IV-IV, the semiconductor measuring device 4 can calculate the capacitance Crss of the transistor MTR of each DUT to be measured. Specifically, the semiconductor measuring device 4 can calculate the capacitance Crss of the transistor MTR from (the capacitance Crss of the transistor MTR of each measured object DUT, the parasitic capacitance C0 of each measured object DUT, and the parasitic capacitance Cstg of the stage STG) - (the parasitic capacitance C0 of each measured object DUT) - (the parasitic capacitance Cstg of the entire stage STG / the number of parallel measured object DUTs).

[0135] According to this embodiment, the capacitance Crss of the transistor MTR of the measurement target MTST can be measured with high accuracy. Other configurations and effects are included in the description of the first to third embodiments.

[0136] Next, the semiconductor measurement method of the first to fourth embodiments will be described from another perspective. FIGS. 20 and 21 are flow charts illustrating the semiconductor measurement method in the semiconductor measurement device according to the first to fourth embodiments. As shown in FIG. 20, the semiconductor measurement method of this embodiment includes a step SP11 for measuring parasitic capacitances (C01 (C0), Cstg), a step SP12 for measuring the capacitance of the measurement target (Cmeas), and a step SP13 for calculating the capacitance excluding the parasitic capacitance (Ccorr). For example, in the measurement steps SP11 and SP12, the capacitance in a connected state in which the first terminal T01 and the second terminal T02 are connected to the transistor MTR, and the capacitance in a disconnected state in which the first terminal T01 and the second terminal T02 are disconnected from the transistor MTR are measured. Then, in the calculation step SP13, the capacitance of the transistor MTR is calculated from these measured capacitances. In this way, the semiconductor measurement method of this embodiment may measure the capacitance of the measurement target MTST every time a wafer test (WT) measurement is performed.

[0137] In the case where the parasitic capacitance of the measurement object MTST does not change until the configuration of the semiconductor measuring device is changed, the parasitic capacitance (C01 (C0), Cstg) of the measurement object MTST may be measured and recorded in advance, as shown in step SP21 of FIG. 21. Then, when measuring the measurement object MTST during a wafer test, step SP22 of measuring the capacitance of the measurement object (Cmeas) and step SP23 of calculating the capacitance excluding the parasitic capacitance (Ccorr) may be performed. In this way, a flow in which the parasitic capacitance of the measurement object MTST is not measured during a wafer test may also be used.

[0138] The disclosure made by the present inventor has been specifically described above based on the embodiments, but the present disclosure is not limited to the above-mentioned embodiments and the above-mentioned modified examples, and it goes without saying that various modifications can be made without departing from the gist of the disclosure. For example, appropriate combinations of the configurations of Comparative Examples 1-2 and Embodiments 1-4 are also within the scope of the technical idea of ​​the embodiments. In addition, the following configurations are also within the scope of the technical idea of ​​the embodiments.

[0139] (Appendix 1) a CBCM circuit having a first terminal and a connection terminal; a potential difference applying circuit connected to the connection terminal, the potential difference applying circuit having a second terminal and applying a predetermined potential difference to an output of the first terminal; A semiconductor measurement method using a semiconductor measurement apparatus comprising: determining a parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor, and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculating a capacitance of the transistor; Semiconductor measurement methods.

[0140] (Appendix 2) The semiconductor measuring device includes: a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch connecting the switch terminal to the first terminal or the second terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects a second region terminal, which is a terminal of a second region of the transistor, to and from the ground circuit; A control unit that controls the gate switch and the second region switch; Further equipped with When measuring the capacitance of the transistor, measuring a first capacitance by connecting the switch terminal and the second terminal with the gate switch, disconnecting the second region switch, disconnecting the first terminal and a first region terminal which is a terminal of a first region of the transistor, and disconnecting the gate terminal and the switch terminal; measuring a second capacitance by connecting the gate switch to the switch terminal and the second terminal, disconnecting the second region switch, bringing the first terminal and the first region terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; measuring a third capacitance by connecting the gate switch to the switch terminal and the first terminal, connecting the second region switch, disconnecting the first terminal and the first region terminal, and disconnecting the gate terminal and the switch terminal; measuring a fourth capacitance by connecting the gate switch to the switch terminal and the first terminal, connecting the second region switch, placing the first terminal and the first region terminal in the connected state, and placing the gate terminal and the switch terminal in the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; 2. A semiconductor measurement method as described in appendix 1.

[0141] (Appendix 3) The semiconductor measuring device includes: an auxiliary terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; an auxiliary measuring circuit that performs feedback control so that the current flowing through the auxiliary terminal becomes zero; an auxiliary switch that connects and disconnects the auxiliary terminal and the auxiliary measuring circuit; a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the switch terminal to the second terminal or the auxiliary terminal; a control unit that controls the gate switch, the auxiliary switch, and the auxiliary measuring circuit; Further equipped with the first terminal is connected to a second region terminal which is a terminal of a second region of the transistor; When measuring the capacitance of the transistor, a first capacitance is measured by connecting the gate switch to the switch terminal and the second terminal, disconnecting the auxiliary switch or connecting the auxiliary switch and feedback-controlling the auxiliary measurement circuit, bringing the first region terminal and the auxiliary terminal into the disconnected state, and bringing the gate terminal and the switch terminal into the disconnected state; a second capacitance is measured by connecting the gate switch to the switch terminal and the second terminal, disconnecting the auxiliary switch or connecting the auxiliary switch to cause the auxiliary measurement circuit to perform feedback control, bringing the first region terminal and the auxiliary terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; a third capacitance is measured by connecting the gate switch to the switch terminal and the auxiliary terminal, closing the auxiliary switch, outputting a predetermined voltage from the auxiliary measuring circuit, bringing the first region terminal and the auxiliary terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, and the third capacitance; 2. A semiconductor measurement method as described in appendix 1.

[0142] (Appendix 4) The semiconductor measuring device includes: a first switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the first switch terminal to the first terminal or the second terminal; a second switch terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a first region switch that connects the second switch terminal to a second region terminal that is a terminal of a second region of the transistor or to the first terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects the second region terminal and the ground circuit; a control unit that controls the gate switch, the first region switch, and the second region switch; Further equipped with When measuring the capacitance of the transistor, measuring a first capacitance by connecting the gate switch to the first switch terminal and the second terminal, connecting the first region switch to the second switch terminal and the first terminal, disconnecting the second region switch, bringing the second switch terminal and the first region terminal into the disconnected state, and bringing the gate terminal and the first switch terminal into the disconnected state; measuring a second capacitance by connecting the gate switch to the first switch terminal and the second terminal, connecting the first region switch to the second switch terminal and the first terminal, disconnecting the second region switch, bringing the second switch terminal and the first region terminal into the connected state, and bringing the gate terminal and the first switch terminal into the connected state; measuring a third capacitance by connecting the gate switch to the first switch terminal and the first terminal, connecting the first region switch to the second switch terminal and the second region terminal, connecting the second region switch, bringing the second switch terminal and the first region terminal into the disconnected state, and bringing the gate terminal and the first switch terminal into the disconnected state; measuring a fourth capacitance by connecting the gate switch to the first switch terminal and the first terminal, connecting the first region switch to the second switch terminal and the second region terminal, connecting the second region switch, placing the second switch terminal and the first region terminal in the connected state, and placing the gate terminal and the first switch terminal in the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; 2. A semiconductor measurement method as described in appendix 1.

[0143] (Appendix 5) The semiconductor measuring device includes: a first switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the first switch terminal to the first terminal or the second terminal; a second switch terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a first region switch that connects or disconnects the second switch terminal and the first terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects a second region terminal, which is a terminal of a second region of the transistor, to and from the ground circuit; Further equipped with When measuring the capacitance of the transistor, measuring a first capacitance by causing the gate switch to connect the first switch terminal and the second terminal, to connect the first region switch, to disconnect the second region switch, to bring the second switch terminal and the first region terminal into the disconnected state, and to bring the gate terminal and the first switch terminal into the disconnected state; measuring a second capacitance by causing the gate switch to connect the first switch terminal and the second terminal, to connect the first region switch, to disconnect the second region switch, to bring the second switch terminal and the first region terminal into the connected state, and to bring the gate terminal and the first switch terminal into the connected state; measuring a third capacitance by causing the gate switch to connect the first switch terminal and the first terminal, to disconnect the first region switch, to connect the second region switch, to bring the second switch terminal and the first region terminal into the disconnected state, and to bring the gate terminal and the first switch terminal into the disconnected state; measuring a fourth capacitance by causing the gate switch to connect the first switch terminal and the first terminal, to disconnect the first region switch, to connect the second region switch, to bring the second switch terminal and the first region terminal into the connected state, and to bring the gate terminal and the first switch terminal into the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; 2. A semiconductor measurement method as described in appendix 1. [Explanation of symbols]

[0144] 1, 2, 3, 4 Semiconductor measuring equipment 10 CBCM Circuit T01 1st terminal T02 2nd terminal T03 Connection terminal T04 Measurement terminal 13 Potential difference applying circuit 20 Control section 100, 200 capacitance measurement circuit 107 N-well region 108 P-well area 120, 121, 122, 123 Pads Cdg, Cds, Cgs, Ciss, Coss, Crss Capacity Gn, Gp gate potential GNDU Ground circuit DUT, DUT1, DUT2, DUT3 Measurement object H1, H2 probe needles Imeas Measurement current Iref, Itst, I(Vdd1), I(Vdd2), I(Vnode) Current MN1, MN2 NMOS transistors MP1, MP2 PMOS transistors MTR Transistor MTST Inspection Target MTST(n) NMOS transistor N0, N1 nodes Npgu Gate Circuit Ppgu Gate Circuit REF Reference potential SMUa, SMUb measurement circuit STG Stage SWD Drain Switch SWG1, SWG2 Gate switch SWH2 Auxiliary Switch TD Drain terminal TG Gate terminal TH2 auxiliary terminal TS source terminal TST Test potential TSW1, TSW2, TSW31, TSW32 switch terminals Vcc, Vdd1, Vdd2, Vn, Vnode, Vp voltages Vforce measurement voltage WF wafer

Claims

1. a CBCM circuit having a first terminal and a connection terminal; a potential difference applying circuit connected to the connection terminal, the potential difference applying circuit having a second terminal and applying a predetermined potential difference to an output of the first terminal; Equipped with determining a parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculating a capacitance of the transistor; Semiconductor measuring equipment.

2. The probe needle further includes a probe needle that switches between the connected state and the disconnected state. The semiconductor measuring device according to claim 1 .

3. a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the switch terminal to the first terminal or the second terminal; Further equipped with The semiconductor measuring device according to claim 1 .

4. In the connected state, the first terminal is connected to a first region terminal which is a terminal of a first region of the transistor. The semiconductor measuring device according to claim 1 .

5. The first region includes a source or an emitter. The semiconductor measuring device according to claim 4 .

6. a ground circuit that outputs a ground potential; a second region switch that connects and disconnects a second region terminal, which is a terminal of a second region of the transistor, to and from the ground circuit; Further equipped with The semiconductor measuring device according to claim 1 .

7. The second region includes a drain or a collector. The semiconductor measuring device according to claim 6.

8. The CBCM circuit further includes a measurement terminal; A measurement circuit connected to the measurement terminal applies a voltage to the CBCM circuit via the measurement terminal and measures a current. The semiconductor measuring device according to claim 1 .

9. The CBCM circuit includes: a charging transistor that outputs a predetermined charging voltage to the transistor via the first terminal and the second terminal; a discharge transistor that outputs a predetermined discharge voltage to the transistor via the first terminal and the second terminal; having The semiconductor measuring device according to claim 1 .

10. a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch connecting the switch terminal to the first terminal or the second terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects a second region terminal, which is a terminal of a second region of the transistor, to and from the ground circuit; A control unit that controls the gate switch and the second region switch; Further equipped with The control unit is a first capacitance is measured by connecting the switch terminal and the second terminal with the gate switch, disconnecting the second region switch, disconnecting the first terminal and a first region terminal which is a terminal of a first region of the transistor, and disconnecting the gate terminal and the switch terminal; measuring a second capacitance by connecting the gate switch to the switch terminal and the second terminal, disconnecting the second region switch, bringing the first terminal and the first region terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; measuring a third capacitance by connecting the gate switch to the switch terminal and the first terminal, connecting the second region switch, bringing the first terminal and the first region terminal into the disconnected state, and bringing the gate terminal and the switch terminal into the disconnected state; measuring a fourth capacitance by connecting the gate switch to the switch terminal and the first terminal, connecting the second region switch, placing the first terminal and the first region terminal in the connected state, and placing the gate terminal and the switch terminal in the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; The semiconductor measuring device according to claim 1 .

11. The first terminal is connected to a second region terminal which is a terminal of a second region of the transistor. The semiconductor measuring device according to claim 1 .

12. an auxiliary terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the switch terminal to the second terminal or the auxiliary terminal; Further equipped with The semiconductor measuring device according to claim 1 .

13. further comprising an auxiliary measuring circuit that outputs a predetermined voltage to the auxiliary terminal; the auxiliary measuring circuit has either one of the following functions: a feedback control is performed so that the current flowing through the auxiliary terminal becomes zero; or an auxiliary switch is provided for connecting and disconnecting the auxiliary terminal and the auxiliary measuring circuit. The semiconductor measuring device according to claim 12.

14. an auxiliary terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; an auxiliary measuring circuit that outputs a predetermined voltage to the auxiliary terminal, the auxiliary measuring circuit having either one of the following functions: the auxiliary measuring circuit can perform feedback control so that the current flowing through the auxiliary terminal becomes zero; or the auxiliary measuring circuit has an auxiliary switch that connects and disconnects the auxiliary terminal and the auxiliary measuring circuit; a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the switch terminal to the second terminal or the auxiliary terminal; a control unit that controls the gate switch, the auxiliary switch, and the auxiliary measuring circuit; Further equipped with the first terminal is connected to a second region terminal which is a terminal of a second region of the transistor; The control unit is a first capacitance is measured by connecting the gate switch to the switch terminal and the second terminal, disconnecting the auxiliary switch or feedback controlling the auxiliary measurement circuit, disconnecting the first region terminal and the auxiliary terminal, and disconnecting the gate terminal and the switch terminal; a second capacitance is measured by connecting the gate switch to the switch terminal and the second terminal, disconnecting the auxiliary switch or feedback controlling the auxiliary measurement circuit, bringing the first region terminal and the auxiliary terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; a third capacitance is measured by connecting the switch terminal and the auxiliary terminal to the gate switch, bringing the auxiliary terminal and the auxiliary measurement circuit into a connected state, causing the auxiliary measurement circuit to output a predetermined voltage, bringing the first region terminal and the auxiliary terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, and the third capacitance; The semiconductor measuring device according to claim 1 .

15. a first switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the first switch terminal to the first terminal or the second terminal; a second switch terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a first region switch for connecting the second switch terminal to a second region terminal that is a terminal of a second region of the transistor or to the first terminal; Further equipped with The semiconductor measuring device according to claim 1 .

16. a first switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the first switch terminal to the first terminal or the second terminal; a second switch terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a first region switch for connecting the second switch terminal to a second region terminal that is a terminal of a second region of the transistor or to the first terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects the second region terminal and the ground circuit; a control unit that controls the gate switch, the first area switch, and the second area switch; Further equipped with The control unit is measuring a first capacitance by connecting the gate switch to the first switch terminal and the second terminal, connecting the first region switch to the second switch terminal and the first terminal, disconnecting the second region switch, bringing the second switch terminal and the first region terminal into the disconnected state, and bringing the gate terminal and the first switch terminal into the disconnected state; measuring a second capacitance by connecting the gate switch to the first switch terminal and the second terminal, connecting the first region switch to the second switch terminal and the first terminal, disconnecting the second region switch, bringing the second switch terminal and the first region terminal into the connected state, and bringing the gate terminal and the first switch terminal into the connected state; measuring a third capacitance by connecting the gate switch to the first switch terminal and the first terminal, connecting the first region switch to the second switch terminal and the second region terminal, connecting the second region switch, bringing the second switch terminal and the first region terminal into the disconnected state, and bringing the gate terminal and the first switch terminal into the disconnected state; measuring a fourth capacitance by connecting the gate switch to the first switch terminal and the first terminal, connecting the first region switch to the second switch terminal and the second region terminal, connecting the second region switch, placing the second switch terminal and the first region terminal in the connected state, and placing the gate terminal and the first switch terminal in the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; The semiconductor measuring device according to claim 1 .

17. a first switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the first switch terminal to the first terminal or the second terminal; a second switch terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a first region switch that connects or disconnects the second switch terminal and the first terminal; Further equipped with The semiconductor measuring device according to claim 1 .

18. a first switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch that connects the first switch terminal to the first terminal or the second terminal; a second switch terminal connected to a first region terminal, which is a terminal of the first region of the transistor, in the connected state; a first region switch that connects or disconnects the second switch terminal and the first terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects a second region terminal, which is a terminal of a second region of the transistor, to and from the ground circuit; a control unit that controls the gate switch, the first area switch, and the second area switch; Further equipped with The control unit is measuring a first capacitance by causing the gate switch to connect the first switch terminal and the second terminal, to connect the first region switch, to disconnect the second region switch, to bring the second switch terminal and the first region terminal into the disconnected state, and to bring the gate terminal and the first switch terminal into the disconnected state; measuring a second capacitance by causing the gate switch to connect the first switch terminal and the second terminal, to connect the first region switch, to disconnect the second region switch, to bring the second switch terminal and the first region terminal into the connected state, and to bring the gate terminal and the first switch terminal into the connected state; measuring a third capacitance by causing the gate switch to connect the first switch terminal and the first terminal, to disconnect the first region switch, to connect the second region switch, to bring the second switch terminal and the first region terminal into the disconnected state, and to bring the gate terminal and the first switch terminal into the disconnected state; measuring a fourth capacitance by causing the gate switch to connect the first switch terminal and the first terminal, to disconnect the first region switch, to connect the second region switch, to bring the second switch terminal and the first region terminal into the connected state, and to bring the gate terminal and the first switch terminal into the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; The semiconductor measuring device according to claim 1 .

19. a CBCM circuit having a first terminal and a connection terminal; a potential difference applying circuit connected to the connection terminal, the potential difference applying circuit having a second terminal and applying a predetermined potential difference to an output of the first terminal; A semiconductor measurement method using a semiconductor measurement apparatus comprising: determining a parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculating a capacitance of the transistor; Semiconductor measurement methods.

20. The semiconductor measuring device includes: a switch terminal connected to a gate terminal, which is a gate or base terminal of the transistor, in the connected state; a gate switch connecting the switch terminal to the first terminal or the second terminal; a ground circuit that outputs a ground potential; a second region switch that connects and disconnects a second region terminal, which is a terminal of a second region of the transistor, to and from the ground circuit; A control unit that controls the gate switch and the second region switch; Further equipped with When measuring the capacitance of the transistor, a first capacitance is measured by connecting the switch terminal and the second terminal with the gate switch, disconnecting the second region switch, disconnecting the first terminal and a first region terminal which is a terminal of a first region of the transistor, and disconnecting the gate terminal and the switch terminal; measuring a second capacitance by connecting the gate switch to the switch terminal and the second terminal, disconnecting the second region switch, bringing the first terminal and the first region terminal into the connected state, and bringing the gate terminal and the switch terminal into the connected state; measuring a third capacitance by connecting the gate switch to the switch terminal and the first terminal, connecting the second region switch, bringing the first terminal and the first region terminal into the disconnected state, and bringing the gate terminal and the switch terminal into the disconnected state; measuring a fourth capacitance by connecting the gate switch to the switch terminal and the first terminal, connecting the second region switch, placing the first terminal and the first region terminal in the connected state, and placing the gate terminal and the switch terminal in the connected state; calculating the capacitance of the transistor from the first capacitance, the second capacitance, the third capacitance, and the fourth capacitance; 20. The semiconductor measurement method according to claim 19.

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