Semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device that can detect a failure of read processing of data written in a nonvolatile element to start normally when an external power source is turned on.SOLUTION: A semiconductor integrated circuit device 100 includes: a nonvolatile storage element 115; an internal boost power supply circuit 111 that boosts a voltage of an external power supply to a set value when an external power supply is turned on and supplies the voltage to the nonvolatile storage element 115; a monitor circuit 112 that detects that the voltage value of the internal boost power supply circuit 111 exceeds a prescribed value and outputs the same; a timer circuit 113 that detects that a predetermined time has elapsed after the external power supply is turned on and outputs the same; and an initial control circuit 114 that instructs the start of reading the data stored in the nonvolatile storage element 115 according to output of at least one of the monitor circuit 112 and the timer circuit 113. The initial control circuit 114 outputs the operational conditions of the monitor circuit 112 and the timer circuit 113 to an external terminal 122.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a circuit for reading data written in a nonvolatile memory element when power is turned on. [Background technology]

[0002] The semiconductor integrated circuit device has a non-volatile memory element therein, and when an external power source is turned on, data written to the non-volatile memory element is read out and used as a trimming value for an internal power supply voltage circuit, etc., to adjust the voltage value of the internal power supply voltage circuit.

[0003] The process of reading data written to the non-volatile element is initiated by a monitor circuit detecting whether the voltage of the internal boost power supply has reached a set value, and when the set value is reached, a trigger signal generated by the monitor circuit is input to the non-volatile element.

[0004] However, if the monitor circuit does not generate a trigger signal for some reason, for example if the voltage of the internal boost power supply does not reach a set value, the data written in the non-volatile element cannot be read normally, and the semiconductor integrated circuit device may remain in a standby state and not operate when the external power supply is turned on.

[0005] The invention described in Patent Document 1 below discloses a semiconductor memory device that is provided with a voltage detection circuit that detects whether the boosted voltage of an internal boost circuit has reached a predetermined potential, and a timer, and applies a voltage to a memory cell when the boosted voltage has reached the predetermined potential or when a predetermined time has elapsed on the timer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2002-025287 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, the invention described in Patent Document 1 has a problem that if the timer does not operate normally, the supply of voltage to the memory cells does not start, and the semiconductor integrated circuit does not operate normally.

[0008] In consideration of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device that is capable of detecting whether the read process of data written to a non-volatile element has not started normally when an external power source is turned on. [Means for solving the problem]

[0009] In order to solve the above problems, a semiconductor integrated circuit device of the present invention comprises a non-volatile memory element, an internal boost power supply circuit that boosts the voltage of the external power supply to a set value when an external power supply is turned on and supplies the voltage to the non-volatile memory element, a monitor circuit that detects when the voltage value of the internal boost power supply circuit exceeds a predetermined value and outputs the detection result, a timer circuit that detects that a predetermined time has elapsed after the external power supply is turned on and outputs the detection result, and an initial control circuit that instructs the start of reading of stored data in the non-volatile memory element in response to outputs of at least one of the monitor circuit and the timer circuit, and the initial control circuit outputs a signal indicating the operating states of the monitor circuit and the timer circuit to an external terminal. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of a semiconductor integrated circuit device according to an embodiment; [Diagram 2]FIG. 2(A) is a diagram showing the operation when the monitor circuit detects that the boosted voltage output by the internal boost power supply circuit has exceeded a predetermined value; FIG. 2(B) is a diagram showing the operation when the boosted voltage output by the internal boost power supply circuit has not exceeded a predetermined value and the timer circuit has detected that a predetermined time has elapsed; and FIG. 2(C) is a diagram showing the operation when the boosted voltage output by the internal boost power supply circuit has not exceeded a predetermined value and the timer circuit has not output a timeout signal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0012] Fig. 1 is a schematic diagram of a semiconductor integrated circuit device 100 according to an embodiment. As shown in Fig. 1, the semiconductor integrated circuit device 100 includes a power-on reset circuit 110 (hereinafter referred to as "POR circuit 110"), an internal boost power supply circuit 111, a monitor circuit 112, a timer circuit 113, an initial control circuit 114, and a non-volatile memory element 115. The semiconductor integrated circuit device 100 also includes an external power supply terminal 121 and an external monitor terminal 122.

[0013] The POR circuit 110 is connected to an external power supply terminal 121, and is supplied with an external power supply VCC from the external power supply terminal 121. An output node of the POR circuit 110 is connected to input nodes of an internal boost power supply circuit 111, a monitor circuit 112, and a timer circuit 113, which will be described later. The POR circuit 110 outputs a power-on reset signal PRS when the external power supply VCC is applied from the external power supply terminal 121. That is, when the supply of the external power supply VCC starts, the POR circuit 110 outputs an H level as the voltage value of the external power supply VCC rises, and then outputs a power-on reset signal that becomes an L level when the voltage value of the external power supply VCC exceeds a predetermined voltage value.

[0014] The internal boost power circuit 111 receives the external power supply VCC from the external power supply terminal 121, and is connected to an output node of the POR circuit 110 and an input node of the nonvolatile memory element 115. The output node of the internal boost power circuit 111 is connected to a monitor signal input node of the monitor circuit 112. When the external power supply VCC is turned on and the POR circuit 110 outputs a power-on reset signal PRS, the internal boost power circuit 111 generates a boosted voltage VPRD by boosting the voltage of the external power supply VCC, and supplies the boosted voltage to the nonvolatile memory element 115, which will be described later. The internal boost power circuit 111 also boosts the output voltage to a voltage value set by a trimming value provided by the nonvolatile memory element 115.

[0015] For example, the voltage value of the external power supply VCC is set to 1.8 V, and the boost voltage VPRD is set to 5 V, but the respective voltage values ​​are not limited to these values. Note that immediately after turning on the external power supply VCC, no trimming value is provided from the nonvolatile memory element 115, so the voltage value of the boost voltage VPRD is a value that corresponds to the voltage value of the external power supply VCC, which is determined by the voltage division ratio of resistor elements, etc.

[0016] The monitor circuit 112 is connected to an output node of the POR circuit 110, an output node of the internal boost power supply circuit 111, and an input node of the initial control circuit 114. The monitor circuit 112 detects the voltage value output by the internal boost power supply circuit 111, and when it detects that the voltage value exceeds a predetermined value, it outputs the detection result to the initial control circuit 114 as a voltage normal signal VMEND.

[0017] The timer circuit 113 is connected to an output node of the POR circuit 110 and an input node of the initial control circuit 114. The timer circuit 113 starts measuring the passage of a predetermined time from when the external power supply VCC is turned on and the POR circuit 110 outputs a power-on reset signal PRS. When the timer circuit 113 detects that the predetermined time has elapsed, it outputs the detection result to the initial control circuit 114 as a timeout signal TMEND.

[0018] The initial control circuit 114 is connected to an output node of the monitor circuit 112, an output node of the timer circuit 113, and an input node of the nonvolatile memory element 115. In addition, the output node of the initial control circuit 114 is connected to an external monitor terminal 122. The initial control circuit 114 outputs an instruction signal to start reading stored data to the nonvolatile memory element 115 in response to at least one output of the monitor circuit 112 and the timer circuit 113. In addition, the initial control circuit 114 outputs a monitor signal STST indicating the operating states of the monitor circuit 112 and the timer circuit 113 to the external monitor terminal 122.

[0019] Specifically, the initial control circuit 114 directly outputs the result of a NOR operation between the output of the monitor circuit 112 and the output of the timer circuit 113 to the external monitor terminal 122 as a monitor signal STST indicating the operating states of the monitor circuit 112 and the timer circuit 113.

[0020] An input node of the nonvolatile memory element 115 is connected to an output node of the internal boost power supply circuit 111 and an output node of the initial control circuit 114. Upon receiving a read start instruction signal from the initial control circuit 114, the nonvolatile memory element 115 reads out data written therein and uses the data as a trimming value for adjusting the voltage value of the internal boost power supply circuit 111 and the setting values ​​of other circuits (not shown).

[0021] The operation of the semiconductor integrated circuit device 100 described above will be described with reference to Figures 2(A) to 2(C). First, with reference to Figure 2(A), the operation will be described when the monitor circuit 112 detects that the boosted voltage of the internal boost power supply circuit 111 has exceeded a predetermined value, and as a result, a data read operation of the non-volatile memory element 115 is started.

[0022] Time t in Figure 2(A) A0 At time t A1When the voltage value of the external power supply VCC exceeds a predetermined voltage value, the output goes to an L level (at time t A2 The GND terminal GND is connected to the ground terminal GND, and outputs a power-on reset signal PRS (which goes to L level when

[0023] When the POR circuit 110 outputs the power-on reset signal PRS, that is, at time t A2 When the power-on reset signal goes from H level to L level at time t, the internal boost power supply circuit 111 starts boosting the voltage of the external power supply VCC. In FIG. 2A, this output voltage is shown as a boosted voltage VPRD. The internal boost power supply circuit 111 boosts the voltage of the external power supply VCC to a set value, and at time t A4 After the boost voltage VPRD reaches the set value, the set value is maintained.

[0024] time t A2 When the POR circuit 110 outputs the power-on reset signal PRS, that is, when the power-on reset signal PRS changes from H level to L level at time t A3 When the monitor circuit 112 detects that the voltage value of the boosted voltage VPRD has exceeded a predetermined value, it outputs a voltage normal signal VMEND, that is, switches the voltage normal signal VMEND from an L level to an H level and outputs it. Note that the predetermined voltage value at which the monitor circuit 112 determines to output the voltage normal signal VMEND is set slightly lower than the above-mentioned set value when the internal boost power supply circuit 111 boosts the boosted voltage VPRD.

[0025] Also, at time t A2 When the POR circuit 110 outputs the power-on reset signal PRS, that is, when the power-on reset signal PRS goes from H level to L level, the timer circuit 113 starts counting the passage of a predetermined time. Then, when the timer circuit 113 detects that the predetermined time has passed, for example, at time t A6That is, the timer circuit 113 switches the timeout signal TMEND from an L level to an H level and outputs the signal.

[0026] The initial control circuit 114 starts at time t A3 In response to the voltage normal signal VMEND switching from L level to H level in the nonvolatile memory element 115, a read start instruction signal is output to the nonvolatile memory element 115, and the read operation of the data written therein is started.

[0027] In addition, the initial control circuit 114 outputs, as the monitor signal STST, a NOR of the output of the monitor circuit 112 and the output of the timer circuit 113. In FIG. 2A, the monitor signal STST is generated when the voltage normal signal VMEND of the monitor circuit 112 is at time t A3 At time t A3 When the signal is switched to the H level at time t A5 By detecting this L-level signal at the external monitor terminal 122, it can be determined that the data read operation of the nonvolatile memory element 115 is proceeding normally.

[0028] Next, referring to FIG. 2(B), an operation will be described in which the boosted voltage of the internal boost power supply circuit 111 does not exceed a predetermined value and the timer circuit 113 detects that a predetermined time has elapsed, thereby starting a data read operation of the non-volatile memory element 115.

[0029] Time t in Figure 2(B) B0 At time t , the power supply is turned on and the external power supply VCC starts to be supplied from the external power supply terminal 121. Then, similar to FIG. 2A, the voltage value of the external power supply VCC increases over time. As the voltage value of the external power supply VCC increases, the POR circuit 110 B1becomes an H level corresponding to the voltage value of the external power supply VCC, and becomes an L level when the voltage value of the external power supply VCC exceeds a predetermined voltage value (in FIG. 2(B), at time t B2 becomes an L level), and outputs a power-on reset signal PRS.

[0030] When the POR circuit 110 outputs the power-on reset signal PRS, that is, when the power-on reset signal changes from the H level to the L level at time t B2 <000017>, the internal boost power supply circuit 111 starts the boosting operation of the voltage of the external power supply VCC. In FIG. 2(B), it is assumed that the internal boost power supply circuit 111 cannot boost the voltage of the external power supply VCC to the set value for some reason.

[0031] At time t B2 When the POR circuit 110 outputs the power-on reset signal PRS, the monitor circuit 112 starts monitoring the boosted voltage VPRD of the internal boost power supply circuit 111. However, the boosted voltage VPRD does not rise beyond a predetermined voltage value close to the set value. Therefore, the voltage normal signal VMEND output by the monitor circuit 112 remains at the L level.

[0032] Here, the timer circuit 113 measures the elapse of a predetermined time from the output of the power-on reset signal PRS. When the timer circuit 113 detects that the predetermined time has elapsed, for example, at time t B4 it outputs a timeout signal TMEND. That is, the timer circuit 113 switches the timeout signal TMEND from the L level to the H level and outputs it.

[0033] The initial control circuit 114 outputs an instruction signal for starting reading to the non-volatile memory element 115 in response to the timeout signal TMEND switching from the L level to the H level at time t B4 <000020>, and starts the reading operation of the data written therein.

[0034] In addition, the initial control circuit 114 outputs, as the monitor signal STST, a NOR of the output of the monitor circuit 112 and the output of the timer circuit 113. In FIG. 2B, the time-out signal TMEND of the timer circuit 113 is output as the monitor signal STST at time t B4 Until the signal changes from L level to H level at time t B4 When the timeout signal TMEND is switched to the H level at time t B5 At this time, the monitor signal STST switches from H level to L level. By detecting this L level signal at the external monitor terminal 122, it can be determined that the data read operation of the nonvolatile memory element 115 is being performed normally.

[0035] Next, with reference to FIG. 2C, an operation will be described in a case where the boosted voltage of the internal boost power supply circuit 111 does not exceed a predetermined value and the timer circuit 113 does not output a timeout signal.

[0036] Time t in Figure 2(C) C0 At time t , the power supply is turned on and the external power supply VCC starts to be supplied from the external power supply terminal 121. Then, as in the case of FIG. 2A and FIG. 2B, the voltage value of the external power supply VCC increases over time. As the voltage value of the external power supply VCC increases, the POR circuit 110 C1 When the voltage value of the external power supply VCC exceeds a predetermined voltage value, the output goes to an L level (at time t C2 The GND terminal GND is connected to the ground terminal GND, and outputs a power-on reset signal PRS (which goes to L level when

[0037] When the POR circuit 110 outputs the power-on reset signal PRS, that is, at time t C2When the power-on reset signal PRS changes from H level to L level in the figure, the internal boost power supply circuit 111 starts boosting the voltage of the external power supply VCC. In Fig. 2(C), it is assumed that the internal boost power supply circuit 111 cannot boost the voltage of the external power supply VCC up to a set value.

[0038] time t C2 When the POR circuit 110 outputs the power-on reset signal PRS in the EEPROM 110, the monitor circuit 112 starts monitoring the boosted voltage VPRD of the internal boost power supply circuit 111. However, the boosted voltage VPRD does not rise above a predetermined voltage value close to the set value. Therefore, the voltage normal signal VMEND output by the monitor circuit 112 remains at the L level.

[0039] Here, the timer circuit 113 is timing the passage of a predetermined time from the output of the power-on reset signal PRS. If the timer circuit 113 is operating normally, it outputs a timeout signal TMEND when the predetermined time has elapsed. However, in FIG. 2(C), for some reason, the timeout signal TMEND remains at L level even after the predetermined time has elapsed.

[0040] Since both the voltage normal signal VMEND and the timeout signal TMEND remain at the L level, the initial control circuit 114 cannot output a read start signal to the nonvolatile memory element 115 and cannot start the operation of reading data from the nonvolatile memory element 115.

[0041] The initial control circuit 114 outputs, as the monitor signal STST, the NOR of the output of the monitor circuit 112 and the output of the timer circuit 113. In Fig. 2C, since both the voltage normal signal VMEND and the timeout signal TMEND remain at L level, even after the predetermined period has elapsed, the monitor signal STST remains in a state in which an H level signal with a voltage value corresponding to the voltage value of the external power supply VCC is output. By detecting this output at the external monitor terminal 122, it becomes possible to detect a malfunction of the circuit.

[0042] According to the present disclosure described above, it is possible to provide a semiconductor integrated circuit device that is capable of detecting whether the read process of data written to a non-volatile element has not started normally when an external power source is turned on.

[0043] In the above description, the initial control circuit 114 is configured to output, as the monitor signal STST, a NOR of the output of the monitor circuit 112 and the output of the timer circuit 113 to the external monitor terminal 122. However, the initial control circuit 114 may output, as the monitor signal STST, a logical OR to the external monitor terminal 122. In that case, if the monitor signal STST is at an H level, it indicates that the device is operating normally, and if it is at an L level, it can be detected that some abnormality has occurred. [Explanation of symbols]

[0044] 100 Semiconductor integrated circuit device 110 Power-on reset circuit (POR circuit) 111 Internal boost power supply circuit 112 Monitor circuit 113 Timer Circuit 114 Initial Control Circuit 115 Non-volatile memory element 121 External power supply terminal 122 External monitor terminal

Claims

1. A non-volatile memory element; an internal boost power supply circuit that boosts a voltage of the external power supply to a set value when an external power supply is turned on and supplies the voltage to the nonvolatile memory element; a monitor circuit that detects when a voltage value of the internal boost power supply circuit exceeds a predetermined value and outputs the detection result; a timer circuit for detecting that a predetermined time has elapsed since the external power source was turned on and outputting the detection result; an initial control circuit that instructs a start of reading of stored data in the non-volatile memory element in response to an output of at least one of the monitor circuit and the timer circuit; The initial control circuit outputs a signal indicating the operating states of the monitor circuit and the timer circuit to an external terminal.

2. 2. The semiconductor integrated circuit device according to claim 1, wherein said initial control circuit outputs a negative OR operation result of an output of said monitor circuit and an output of said timer circuit to said external terminal as a signal indicating an operating state of said monitor circuit and said timer circuit.

3. a power-on reset circuit that outputs a power-on reset signal which goes to H level as the voltage value of the external power supply rises when an external power supply is turned on and goes to L level when the voltage value of the external power supply exceeds a predetermined voltage value, When the power-on reset circuit outputs the power-on reset signal, the internal boost power supply circuit starts boosting the voltage of the external power supply; the monitor circuit starts detecting the voltage value of the internal boost power supply circuit, 3. The semiconductor integrated circuit device according to claim 1, wherein said timer circuit starts measuring the lapse of said predetermined time.

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