Semiconductor device and inverter system

Abstract

To provide a semiconductor device capable of reducing a chip area.SOLUTION: A semiconductor device comprises a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip includes a first switch. The other of the first semiconductor chip and the second semiconductor chip includes a second switch. The third semiconductor chip includes a first transformer. When the first switch is in an OFF state and the second switch is in an ON state, a signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer. When the second switch is in an OFF state and the first switch is in an ON state, a signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an inverter system.

Background Art

[0002] For example, International Publication No. 2014 / 097425 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first transmission circuit, a first reception circuit, and a first transformer. The second semiconductor chip has a second transmission circuit, a second reception circuit, and a second transformer. In the semiconductor device described in Patent Document 1, a signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer, and a signal is transmitted from the second semiconductor chip to the first semiconductor chip by the second transformer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device described in Patent Document 1, two transformers are required to transmit and receive signals, resulting in an increase in chip area. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0005] The semiconductor device of the present disclosure includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip has a first switch. The other of the second semiconductor chip and the second semiconductor chip has a second switch. The third semiconductor chip has a first transformer. When the first switch is in the off state and the second switch is in the on state, a signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer. When the second switch is in the off state and the first switch is in the on state, a signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer.

Advantages of the Invention

[0006] According to the semiconductor device of the present disclosure, it is possible to reduce the chip area.

Brief Description of the Drawings

[0007]

Figure 1

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Embodiments for Carrying Out the Invention

[0008] Details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and duplicate explanations will not be repeated. The semiconductor device according to the embodiment is referred to as semiconductor device DEV, and the inverter system according to the embodiment is referred to as inverter system INV.

[0009] (Configuration of Semiconductor Device DEV) The configuration of the semiconductor device DEV will be described below.

[0010] FIG. 1 is a block diagram of the semiconductor device DEV. As shown in FIG. 1, the semiconductor device DEV includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3.

[0011] The semiconductor chip CHP1 has a transceiver circuit TRX1, a transmission circuit TX1, a reception circuit RX1, a switch SW1, and a control circuit CC1. The semiconductor chip CHP2 has a transceiver circuit TRX2, a transmission circuit TX2, a reception circuit RX2, a switch SW2, a control circuit CC2, and a drive circuit DR. The semiconductor chip CHP3 has a transformer TR1, a transformer TR2, and a transformer TR3, and lead-out wirings PL1, PL2, PL3, and PL4. The transceiver circuit TRX1 has a transmission circuit TRX1a and a reception circuit TRX1b. The transceiver circuit TRX2 has a transmission circuit TRX2a and a reception circuit TRX2b.

[0012] The transformer TR1 has a transceiver coil CL1 and a transceiver coil CL2. The transceiver coils CL1 and CL2 are electrically connected to the transceiver circuit TRX1 and the transceiver circuit TRX2, respectively. The transceiver coil CL1 has a coil CL11 and a coil CL12. The coils CL11 and CL12 are electrically connected in series with the lead-out wiring PL1 interposed therebetween. The transceiver coil CL2 has a coil CL21 and a coil CL22. The coils CL21 and CL22 are electrically connected in series with the lead-out wiring PL2 interposed therebetween.

[0013] The lead wiring PL1 is electrically connected to the switch SW1. Since the switch SW1 is connected to the ground potential, when the switch SW1 is turned on, the lead wiring PL1 is electrically connected to the ground potential. The lead wiring PL2 is electrically connected to the switch SW2. Since the switch SW2 is connected to the ground potential, when the switch SW2 is turned on, the lead wiring PL2 is electrically connected to the ground potential. The switches SW1 and SW2 are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate width of the MOSFET constituting the switch SW1 and the gate width of the MOSFET constituting the switch SW2 may be, for example, 5 μm or more in order to reduce the loss due to the on-resistance. In addition, when the gate is divided for stabilizing the gate potential in one MOSFET, the gate width is the sum of the widths of the divided gates. The gate width and the gate length of the MOSFET constituting the switch SW1 and the MOSFET constituting the switch SW2 may be, for example, 0.5 μm or more in order to reduce the loss associated with leakage.

[0014] The transformer TR2 has a transmission coil CL3 and a reception coil CL4. The transmission coil CL3 and the reception coil CL4 are electrically connected to the transmission circuit TX1 and the reception circuit RX2, respectively. The transmission coil CL3 has a coil CL31 and a coil CL32. The coil CL31 and the coil CL32 are electrically connected in series. The reception coil CL4 has a coil CL41 and a coil CL42. The coil CL41 and the coil CL42 are electrically connected in series with the lead wiring PL3 interposed therebetween.

[0015] Transformer TR3 has a transmission coil CL5 and a reception coil CL6. The transmission coil CL5 and the reception coil CL6 are electrically connected to a transmission circuit TX2 and a reception circuit RX1, respectively. The transmission coil CL5 has a coil CL51 and a coil CL52. The coil CL51 and the coil CL52 are electrically connected in series. The reception coil CL6 has a coil CL61 and a coil CL62. The coil CL61 and the coil CL62 are electrically connected in series with a lead wire PL4 interposed therebetween.

[0016] Although not shown in the figure, the control circuit CC1 is electrically connected to the transceiver circuit TRX1, the transmission circuit TX1, the reception circuit RX1, and the switch SW1, and the control circuit CC2 is electrically connected to the transceiver circuit TRX2, the transmission circuit TX2, the reception circuit RX2, and the switch SW2. Similarly, although not shown in the figure, the drive circuit DR is electrically connected to the control circuit CC2.

[0017] FIG. 2 is an explanatory diagram showing an example of signal transmission from the semiconductor chip CHP1 to the semiconductor chip CHP2. As shown in FIG. 2, first, the control circuit CC1 turns off the switch SW1, and the control circuit CC2 turns on the switch SW2. As a result, the transceiver coil CL1 functions as a transmission coil, and the transceiver coil CL2 functions as a reception coil. At this time, the control circuit CC1 electrically connects the transmission circuit TRX1a to the transceiver coil CL1, and the control circuit CC2 electrically connects the reception circuit TRX2b to the transceiver coil CL2.

[0018] Second, the control circuit CC1 outputs a signal SG1 to the transceiver circuit TRX1 (transmission circuit TRX1a). The signal SG1 is a square wave. The transmission circuit TRX1a modulates the signal SG1 into a signal SG2 and sends the signal SG2 to the transceiver coil CL1. When the signal SG2 flows through the transceiver coil CL1, a signal SG3 corresponding to the signal SG2 flows through the transceiver coil CL2 due to the induced electromotive force. The transceiver circuit TRX2 (reception circuit TRX2b) amplifies the signal SG3 and demodulates it into a square wave.

[0019] When attempting to transmit a signal from semiconductor chip CHP2 to semiconductor chip CHP1, control circuit CC1 turns switch SW1 on and control circuit CC2 turns switch SW2 off. As a result, transceiver coil CL1 functions as a receiving coil and transceiver coil CL2 functions as a transmitting coil. Also, at this time, control circuit CC1 electrically connects receiving circuit TRX1b to transceiver coil CL1, and control circuit CC2 electrically connects transmitting circuit TRX2a to transceiver coil CL2. Regarding other aspects, the transmission of a signal from semiconductor chip CHP2 to semiconductor chip CHP1 will be performed in the same manner using transformer TR1.

[0020] In this way, the transmission of a signal from semiconductor chip CHP1 to semiconductor chip CHP2 and the transmission of a signal from semiconductor chip CHP2 to semiconductor chip CHP1 by transformer TR1 are performed by a pulse communication method. More specifically, this signal transmission is performed by an SPI (Serial Peripheral Interface) communication method.

[0021] When transmitting a signal from semiconductor chip CHP1 to semiconductor chip CHP2 by transformer TR2, a signal is output from control circuit CC1 to transmitting circuit TX1 and the signal is sent to transmitting coil CL3, and a signal flows through receiving coil CL4 due to the induced electromotive force. The signal flowing through receiving coil CL4 is received after being amplified and demodulated by receiving circuit RX2.

[0022] Based on the signal received by receiving circuit RX2, control circuit CC2 drives drive circuit DR. That is, when transmitting a signal from semiconductor chip CHP1 to semiconductor chip CHP2 by transformer TR2, it is also performed by a pulse communication method. More specifically, this signal transmission is performed by a PWM (Pulse Width Modulation) communication method. The signal transmission from semiconductor chip CHP2 to semiconductor chip CHP1 by transformer TR3 is also performed in the same manner as the signal transmission from semiconductor chip CHP1 to semiconductor chip CHP2 by transformer TR2.

[0023] FIG. 3 is a first plan view of semiconductor chip CHP3. FIG. 4 is a second plan view of semiconductor chip CHP3. FIG. 5 is a third plan view of semiconductor chip CHP3. FIG. 6 is a cross-sectional view taken along VI-VI in FIG. 3. As shown in FIGS. 3 to 6, semiconductor chip CHP3 further includes a semiconductor substrate SUB.

[0024] Semiconductor substrate SUB has a first surface FS and a second surface SS. The second surface SS is the opposite surface of the first surface FS. The first surface FS and the second surface SS are end faces in the thickness direction of the semiconductor substrate SUB. The constituent material of the semiconductor substrate SUB is, for example, single-crystalline silicon. The semiconductor substrate SUB has an impurity implantation region IR. The impurity implantation region IR is formed on the first surface FS. The conductivity type of the semiconductor substrate SUB is, for example, p-type. The dopant concentration in the impurity implantation region IR is higher than the dopant concentration outside the impurity implantation region IR.

[0025] Semiconductor chip CHP3 further includes an insulating film IF1. The insulating film IF1 is disposed on the semiconductor substrate SUB. More specifically, the insulating film IF1 is disposed on the first surface FS. The constituent material of the insulating film IF1 is, for example, silicon oxide.

[0026] Semiconductor chip CHP3 further includes a wiring layer WL1. The wiring layer WL1 is disposed on the insulating film IF1. The wiring layer WL1 has wirings WL1a, WL1b, WL1c, WL1d, WL1e, and WL1f. The wirings WL1a, WL1b, WL1c, WL1d, WL1e, and WL1f extend along a first direction DR1 in a plan view. The constituent material of the wiring layer WL1 is, for example, a conductive material mainly composed of aluminum.

[0027] The semiconductor chip CHP3 further has an insulating film IF2. The insulating film IF2 is disposed on the insulating film IF1 so as to cover the wiring layer WL1. The constituent material of the insulating film IF2 is, for example, silicon oxide.

[0028] The semiconductor chip CHP3 further has a wiring layer WL2. The wiring layer WL2 is disposed on the insulating film IF2. The wiring layer WL2 has a transmission / reception coil CL1 (coils CL11 and CL12), a transmission coil CL3 (coils CL31 and CL32), a reception coil CL6 (coils CL61 and CL62), a wiring WL2a, a wiring WL2b, a wiring WL2c, a wiring WL2d, a wiring WL2e, a wiring WL2f, a lead wiring PL1, and a lead wiring PL4. The constituent material of the wiring layer WL2 is, for example, a conductive material mainly composed of aluminum.

[0029] The coils CL11 and CL12 are adjacent to each other in the first direction DR1. The coils CL11 and CL12 are wound in a spiral shape in a plan view. More specifically, in the example shown in FIG. 4, the coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and the coil CL12 is wound in a clockwise spiral shape from the outermost circumference to the innermost circumference in a plan view. The coils CL11 and CL12 are electrically connected in series to each other with the lead wiring PL1 interposed therebetween. More specifically, the end portion at the outermost circumference of the coil CL11 is connected to the end portion at the outermost circumference of the coil CL12 with one end portion of the lead wiring PL1 interposed therebetween.

[0030] Coils CL31 and CL32 are adjacent to each other in the first direction DR1. Coils CL31 and CL32 are wound in a spiral shape in a plan view. More specifically, in the example shown in FIG. 4, coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and coil CL32 is wound in a clockwise spiral shape from the outermost circumference to the innermost circumference in a plan view. Coils CL31 and CL32 are electrically connected in series with each other. More specifically, the end portion at the outermost circumference of coil CL31 is connected to the end portion at the outermost circumference of coil CL32.

[0031] Coils CL61 and CL62 are adjacent to each other in the first direction DR1. Coils CL61 and CL62 are wound in a spiral shape in a plan view. More specifically, in the example shown in FIG. 4, coil CL61 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and coil CL62 is wound in a clockwise spiral shape from the outermost circumference to the innermost circumference in a plan view. Coils CL61 and CL62 are electrically connected in series with each other via the lead wire PL4. More specifically, the end portion at the outermost circumference of coil CL61 is connected to the end portion at the outermost circumference of coil CL62 via one end portion of the lead wire PL4.

[0032] The transceiver coil CL1, the transmitter coil CL3, and the receiver coil CL6 are arranged along the first direction DR1. In the first direction DR1, the transceiver coil CL1 is located between the transmitter coil CL3 and the receiver coil CL6.

[0033] The wiring WL2a, wiring WL2b, wiring WL2c, wiring WL2d, wiring WL2e, and wiring WL2f extend along the second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. One end of the wiring WL2a and one end of the wiring WL2b are adjacent to the coil CL11 and the coil CL12, respectively. One end of the wiring WL2c and one end of the wiring WL2d are adjacent to the coil CL31 and the coil CL32, respectively. One end of the wiring WL2e and one end of the wiring WL2f are adjacent to the coil CL61 and the coil CL62, respectively.

[0034] One end of the wiring WL2a and the innermost peripheral end of the coil CL11 are electrically connected by the wiring WL1a and the via plug VP2. One end of the wiring WL2b and the innermost peripheral end of the coil CL12 are electrically connected by the wiring WL1b and the via plug VP2. One end of the wiring WL2c and the innermost peripheral end of the coil CL31 are electrically connected by the wiring WL1c and the via plug VP2. One end of the wiring WL2d and the innermost peripheral end of the coil CL32 are electrically connected by the wiring WL1c and the via plug VP2.

[0035] One end of the wiring WL2e and the innermost peripheral end of the coil CL61 are electrically connected by the wiring WL1e and the via plug VP2. One end of the wiring WL2f and the innermost peripheral end of the coil CL62 are electrically connected by the wiring WL1f and the via plug VP2. The via plug VP2 is embedded in the insulating film IF2. The constituent material of the via plug VP2 is, for example, a conductive material mainly composed of tungsten.

[0036] Semiconductor chip CHP3 further has a plurality of insulating films IF3. The plurality of insulating films IF3 are laminated. The lowermost insulating film IF3 is disposed on the insulating film IF2 so as to cover the wiring layer WL2. The constituent material of the insulating film IF3 is, for example, silicon oxide. The semiconductor chip CHP3 has a plurality of wiring layers WL3. The wiring layer WL3 is disposed on one insulating film IF3 and is covered with another insulating film IF3 on the one insulating film IF3.

[0037] Semiconductor chip CHP3 further has a wiring layer WL4. The wiring layer WL4 has a transceiver coil CL2 (coils CL21 and CL22), a receiving coil CL4 (coils CL41 and CL42), a transmitting coil CL5 (coils CL51 and CL52), a lead wiring PL2, and a lead wiring PL3. The constituent material of the wiring layer WL4 is, for example, a conductive material mainly composed of aluminum.

[0038] Coils CL21 and CL22 are adjacent to each other in the first direction DR1. Coils CL21 and CL22 are wound in a spiral shape in a plan view. More specifically, in the example shown in FIG. 5, coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and coil CL22 is wound in a clockwise spiral shape from the outermost circumference to the innermost circumference in a plan view. Coils CL21 and CL22 are electrically connected in series with each other with the lead wiring PL2 interposed therebetween. More specifically, the end portion at the outermost circumference of coil CL21 is connected to the end portion at the outermost circumference of coil CL22 with one end portion of the lead wiring PL2 interposed therebetween.

[0039] Coils CL41 and CL42 are adjacent to each other in the first direction DR1. Coils CL41 and CL42 are wound in a spiral shape in a plan view. More specifically, in the example shown in FIG. 5, coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and coil CL42 is wound in a clockwise spiral shape from the outermost circumference to the innermost circumference in a plan view. Coils CL41 and CL42 are electrically connected in series with each other with the lead wire PL3 interposed therebetween. More specifically, the end portion at the outermost circumference of coil CL41 is connected to the end portion at the outermost circumference of coil CL42 with one end portion of the lead wire PL3 interposed therebetween.

[0040] Coils CL51 and CL52 are adjacent to each other in the first direction DR1. Coils CL51 and CL52 are wound in a spiral shape in a plan view. More specifically, in the example shown in FIG. 5, coil CL51 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and coil CL52 is wound in a clockwise spiral shape from the outermost circumference to the innermost circumference in a plan view. Coils CL51 and CL52 are electrically connected in series with each other. More specifically, the end portion at the outermost circumference of coil CL51 is connected to the end portion at the outermost circumference of coil CL52.

[0041] The wiring layer WL4 further has pads PD1, PD2, PD3, PD4, PD5, and PD6. Pads PD1 and PD2 are connected to the end portions at the innermost circumferences of coils CL21 and CL22, respectively. Pads PD3 and PD4 are connected to the end portions at the innermost circumferences of coils CL41 and CL42, respectively. Pads PD5 and PD6 are connected to the end portions at the innermost circumferences of coils CL51 and CL62, respectively.

[0042] The wiring layer WL4 further has pad PD7, pad PD8, pad PD9, pad PD10, pad PD11, and pad PD12. Pad PD7 and pad PD8 are electrically connected to the other ends of wiring WL2a and wiring WL2b respectively by the wiring layer WL4 and via plug VP3. Pad PD9 and pad PD10 are electrically connected to the other ends of wiring WL2c and wiring WL2d respectively by the wiring layer WL4 and via plug VP3. Pad PD11 and pad PD12 are electrically connected to the other ends of wiring WL2e and wiring WL2f respectively by the wiring layer WL4 and via plug VP3. The via plug VP3 is embedded in the insulating film IF3. The constituent material of the via plug VP3 is a conductive material mainly composed of, for example, tungsten.

[0043] The wiring layer WL4 further has pad PD13, pad PD14, pad PD15, and pad PD16. Pad PD13 and pad PD14 are connected to the other ends of the lead-out wiring PL2 and the lead-out wiring PL3 respectively. Pad PD15 is electrically connected to the other end of the lead-out wiring PL1 by the wiring layer WL3 and via plug VP3. Pad PD16 is electrically connected to the other end of the lead-out wiring PL4 by the wiring layer WL3 and via plug VP3.

[0044] Note that the semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP2 at pads PD1, PD2, PD3, PD4, PD5, PD6, PD13, and PD14. The semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP1 at pads PD7, PD8, PD9, PD10, PD11, PD12, PD15, and PD16.

[0045] The wiring layer WL4 is disposed on the uppermost insulating film IF3. The transmission / reception coil CL2 overlaps the transmission / reception coil CL1 in a plan view. The reception coil CL4 overlaps the transmission coil CL3 in a plan view. The transmission coil CL5 overlaps the reception coil CL6 in a plan view. Therefore, the transmission / reception coil CL2, the reception coil CL4, and the transmission coil CL5 are disposed to face the transmission / reception coil CL1, the transmission coil CL3, and the reception coil CL6, respectively, with an insulating layer (a plurality of insulating films IF3) interposed therebetween.

[0046] As described above, the transmission / reception coil CL1, the transmission coil CL3, and the reception coil CL6 are arranged along the first direction DR1 such that the transmission / reception coil CL1 is located between the transmission coil CL3 and the reception coil CL4. Therefore, the transformers TR1, TR2, and TR3 are arranged along the first direction DR1 such that the transformer TR1 is located between the transformer TR2 and the transformer TR3.

[0047] The number of coil turns of the transformer TR1 is, for example, larger than the number of coil turns of the transformer TR2 and the number of coil turns of the transformer TR3. The number of coil turns of a transformer is defined as the number of turns of the coil included in the transformer. For example, the number of coil turns of the transformer TR1 is the number of turns of the coil CL11 (coil CL12, coil CL21, coil CL22). When the number of turns of the coil included in the transformer is n turns or more and less than (n + 1) turns, the number of coil turns is regarded as (n + 1). The number of coil turns of the transformer TR1 is, for example, one or two turns more than the number of coil turns of the transformer TR2 and the number of coil turns of the transformer TR3.

[0048] FIG. 7 is a cross-sectional view taken along VII-VII in FIG. 3. As shown in FIG. 7, the semiconductor chip CHP3 further has a guard ring GR. The guard ring GR surrounds the transformers TR1, TR2, and TR3 in a plan view.

[0049] The guard ring GR is composed of a wiring layer WL4, a wiring layer WL3, a wiring layer WL2, a wiring layer WL1, via plugs V1, via plugs VP2, and via plugs VP3. In the guard ring GR, between the wiring layer WL4 and the uppermost wiring layer WL3, between the stacked wiring layers WL3, and between the lowermost wiring layer WL3 and the wiring layer WL2 are connected by via plugs VP3. In the guard ring GR, between the wiring layer WL2 and the wiring layer WL1 is connected by a via plug VP2, and between the wiring layer WL1 and the semiconductor substrate SUB is connected by a via plug V1. The via plug V1 is embedded in the insulating film IF1. The constituent material of the via plug V1 is, for example, a conductive material mainly composed of tungsten.

[0050] The distance between the transformer TR1 and the transformer TR2 in a plan view and the distance between the transformer TR1 and the transformer TR2 in a plan view are, for example, 15 μm or more. The distance between the transformer TR1 and the guard ring GR in a plan view, the distance between the transformer TR2 and the guard ring GR in a plan view, and the distance between the transformer TR3 and the guard ring GR in a plan view are, for example, 50 μm or more.

[0051] Although not shown in the figure, the semiconductor chip CHP3 further has a passivation film. The passivation film is disposed on the uppermost insulating film IF3 so as to cover the wiring layer WL4. Note that openings for exposing the pads PD1 to PD16 are formed in the passivation film.

[0052] FIG. 8 is a block diagram of the inverter system INV. As shown in FIG. 8, the inverter system INV has a semiconductor device DEV and an inverter circuit INVC. The inverter circuit INVC has a switching circuit composed of a plurality of power semiconductor elements PWS. The power semiconductor element PWS is, for example, an IGBT (Insulated Gate Bipolar Transistor). The power semiconductor element PWS is to be driven by a drive circuit DR.

[0053] FIG. 9 is a manufacturing process diagram of the semiconductor chip CHP3. As shown in FIG. 9, the manufacturing method of the semiconductor chip CHP3 has a preparation step S1, an ion implantation step S2, a first insulating film formation step S3, a first via plug formation step S4, a first wiring layer formation step S5, and a second insulating film formation step S6. The manufacturing method of the semiconductor chip CHP3 further has a second via plug formation step S7, a second wiring layer formation step S8, a third insulating film formation step S9, a third via plug formation step S10, a third wiring layer formation step S11, a fourth wiring layer formation step S12, and a passivation film formation step S13.

[0054] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, the ion implantation step S2 is performed. FIG. 10 is a cross-sectional view for explaining the ion implantation step S2. As shown in FIG. 10, in the ion implantation step S2, an impurity implantation region IR is formed by performing ion implantation. After the ion implantation step S2, the first insulating film formation step S3 is performed.

[0055] FIG. 11 is a cross-sectional view for explaining the first insulating film formation step S3. As shown in FIG. 11, in the first insulating film formation step S3, an insulating film IF1 is formed on the semiconductor substrate SUB by, for example, the CVD (Chemical Vapor Deposition) method. After the first insulating film formation step S3, the first via plug formation step S4 is performed.

[0056] FIG. 12 is a cross-sectional view for explaining the first via plug forming step S4. As shown in FIG. 12, in the first via plug forming step S4, a via plug VP1 is embedded in the insulating film IF1. In the first via plug forming step S4, first, a via hole is formed in the insulating film IF1 by dry etching using a resist pattern formed by photolithography as a mask. Second, the constituent material of the via plug VP1 is embedded in the via hole, for example, by CVD method. Third, the constituent material of the via plug VP1 protruding from the via hole is removed, for example, by CMP (Chemical Mechanical Polishing) method. After the first via plug forming step S4, a first wiring layer forming step S5 is performed.

[0057] FIG. 13 is a cross-sectional view for explaining the first wiring layer forming step S5. As shown in FIG. 13, in the first wiring layer forming step S5, a wiring layer WL1 is formed on the insulating film IF1. In the first wiring layer forming step S5, first, the constituent material of the wiring layer WL1 is formed into a film, for example, by sputtering method. Second, the formed constituent material of the wiring layer WL1 is patterned by dry etching using a resist pattern formed by photolithography as a mask. After the first wiring layer forming step S5, a second insulating film forming step S6 is performed.

[0058] FIG. 14 is a cross-sectional view for explaining the second insulating film forming step S6. As shown in FIG. 14, in the second insulating film forming step S6, an insulating film IF2 is formed on the insulating film IF1 so as to cover the wiring layer WL1. In the second insulating film forming step S6, first, the constituent material of the insulating film IF2 is formed into a film, for example, by CVD method. Second, the formed constituent material of the insulating film IF2 is planarized, for example, by CMP method. After the second insulating film forming step S6, a second via plug forming step S7 is performed.

[0059] FIG. 15 is a cross-sectional view for explaining the second via plug forming step S7. As shown in FIG. 15, in the second via plug forming step S7, a via plug VP2 is embedded in the insulating film IF2 in the same manner as in the first via plug forming step S4. After the second via plug forming step S7, a second wiring layer forming step S8 is performed.

[0060] FIG. 16 is a cross-sectional view for explaining the second wiring layer forming step S8. As shown in FIG. 16, in the second wiring layer forming step S8, a wiring layer WL2 is formed on the insulating film IF2. In the second wiring layer forming step S8, first, the constituent material of the wiring layer WL2 is formed into a film, for example, by sputtering. Second, the constituent material of the formed wiring layer WL2 is patterned by dry etching using, for example, a resist pattern formed by photolithography as a mask. After the second wiring layer forming step S8, a third insulating film forming step S9 is performed.

[0061] FIG. 17 is a cross-sectional view for explaining the third insulating film forming step S9. As shown in FIG. 17, in the third insulating film forming step S9, an insulating film IF3 is formed on the insulating film IF2 so as to cover the wiring layer WL2. After the third insulating film forming step S9, a third via plug forming step S10 is performed.

[0062] FIG. 18 is a cross-sectional view for explaining the third via plug forming step S10. As shown in FIG. 18, in the third via plug forming step S10, a via plug VP3 is embedded in the insulating film IF3 in the same manner as in the second via plug forming step S7. After the third via plug forming step S10, a third wiring layer forming step S11 is performed.

[0063] FIG. 19 is a cross-sectional view for explaining the third wiring layer forming step S11. As shown in FIG. 19, in the third wiring layer forming step S11, a wiring layer WL3 is formed in the same manner as in the second wiring layer forming step S8. The third insulating film forming step S9, the third via plug forming step S10, and the third wiring layer forming step S11 are repeated until the insulating film IF3 on the uppermost layer is formed. After the insulating film IF3 on the uppermost layer is formed, a fourth wiring layer forming step S12 is performed.

[0064] FIG. is a cross-sectional view for explaining the fourth wiring layer forming step S12. In the fourth wiring layer forming step S12, a wiring layer WL4 is formed on the insulating film IF3 on the uppermost layer in the same manner as in the second wiring layer forming step S8. After the fourth wiring layer forming step S12, a passivation film forming step S13 is performed.

[0065] In the passivation film forming step S13, a passivation film is formed on the insulating film IF3 on the uppermost layer so as to cover the wiring layer WL4. In the passivation film forming step S13, first, the constituent material of the passivation film is formed by, for example, CVD method. Second, the constituent material of the passivation film is patterned by dry etching using a resist pattern formed by, for example, photolithography as a mask. After performing the above steps, by dicing or the like to individualize, the structure of the semiconductor chip CHP3 shown in FIGS. 3 to 7 is formed.

[0066] (Effect of Semiconductor Device DEV) Hereinafter, the effect of the semiconductor device DEV will be described.

[0067] In the semiconductor device DEV, by switching the switch SW1 and the switch SW2, one of the transmission / reception coils CL1 and the transmission / reception coil CL2 can be made to function as a transmission coil, and the other of the transmission / reception coils CL1 and the transmission / reception coil CL2 can be made to function as a reception coil. Therefore, it becomes possible to make the transformer TR1 assume the functions of two transformers, and thus it is possible to reduce the chip area.

[0068] Note that in semiconductor device DEV, switches SW1 and SW2 are formed not in semiconductor chip CHP3 but in semiconductor chips CHP1 and CHP2, respectively. Therefore, in semiconductor device DEV, it is not necessary to apply a CMOS (Complementary Metal Oxide Semiconductor) process to semiconductor chip CHP3, and the manufacturing process of semiconductor chip CHP3 can be simplified.

[0069] By increasing the number of turns of coil of transformer TR1, the coupling coefficient between transmission / reception coil CL1 and transmission / reception coil CL2 is improved, and the loss associated with signal transmission is reduced. In semiconductor device DEV, loss occurs due to the resistance of switches SW1 and SW2. However, by making the number of turns of coil of transformer TR1 larger than the number of turns of coil of transformer TR2 and the number of turns of coil of transformer TR3, it is possible to compensate for the loss due to the resistance of switches SW1 and SW2.

[0070] On the other hand, if the number of turns of coil of transformer TR1 is made excessively larger than the number of turns of coil of transformer TR2 and the number of turns of coil of transformer TR3, the chip area will increase. Therefore, by setting the number of turns of coil of transformer TR1 to be 1.2 times or less the number of turns of coil of transformer TR2 and the number of turns of coil of transformer TR3, it is possible to reduce the chip area while compensating for the loss due to the resistance of switches SW1 and SW2.

[0071] In semiconductor device DEV, since transformer TR1 is arranged between transformer TR2 and transformer TR3 in a plan view, the distance between transmission coil CL3 and transmission coil CL5 and the distance between reception coil CL4 and reception coil CL6 become large. As a result, according to semiconductor device DEV, it is possible to suppress crosstalk between transformer TR2 and transformer TR3.

[0072] The invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Signs

[0073] CC1 and CC2 control circuits, CHP1, CHP2, and CHP3 semiconductor chips, CL1 transceiver coil, CL11 and CL12 coils, CL2 transceiver coil, CL21 and CL22 coils, CL3 transmission coil, CL31 and CL32 coils, CL4 reception coil, CL41 and CL42 coils, CL5 transmission coil, CL51 and CL52 coils, CL6 reception coil, CL61 and CL62 coils, DEV semiconductor device, DR drive circuit, DR1 first direction, DR2 second direction, FS first surface, GR guard ring, IF1, IF2, and IF3 insulating films, INV inverter system, INVC inverter circuit, IR impurity implantation region, PWS power semiconductor element, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, and PD16 pads, PL1, PL2, PL3, and PL4 lead-out wirings, RX1 and RX2 reception circuits, S1 preparation process, S2 ion implantation process, S3 first insulating film formation process, S4 first via plug formation process, S5 first wiring layer formation process, S6 second insulating film formation process, S7 second via plug formation process, S8 second wiring layer formation process, S9 third insulating film formation process, S10 third via plug formation process, S11 third wiring layer formation process, S12 fourth wiring layer formation process, S13 passivation film formation process, SG1, SG2, and SG3 signals, SS second surface, SUB semiconductor substrate, SW1 switch, SW2 switch, TR1, TR2, and TR3 transformers, TRX1 transceiver circuit, TRX1a transmission circuit, TRX1b reception circuit, TRX2 transceiver circuit, TRX2a transmission circuit, TRX2b reception circuit, TX1 and TX2 transmission circuits, V1, VP1, VP2, and VP3 via plugs, WL1a, WL1b, WL1c, WL1d, WL1e, WL1f, WL2a, WL2b, WL2c, WL2d, WL2e, and WL2f wirings, WL1, WL2, WL3, and WL4 wiring layers.

Claims

1. A first semiconductor chip, a second semiconductor chip, and a third semiconductor chip, wherein one of the first semiconductor chip and the second semiconductor chip has a first switch, the other of the second semiconductor chip and the second semiconductor chip has a second switch, the third semiconductor chip has a first transformer, when the first switch is in an off state and the second switch is in an on state, a signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer, when the second switch is in an off state and the first switch is in an on state, a signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer, a semiconductor device.

2. The third semiconductor chip has a semiconductor substrate, a first transmission / reception coil and a second transmission / reception coil constituting the first transformer, a first lead wiring and a second lead wiring, and an insulating layer, the first transmission / reception coil has a first coil and a second coil, the first coil and the second coil are arranged side by side in a plan view and are connected in series with each other with the first lead wiring interposed therebetween, the second transmission / reception coil has a third coil and a fourth coil, the third coil and the fourth coil are disposed opposite to the first coil and the second coil with the insulating layer interposed therebetween, respectively, and are connected in series with each other with the second lead wiring interposed therebetween, the first lead wiring and the second lead wiring are electrically connected to the first switch and the second switch, respectively, the semiconductor device according to claim 1.

3. The first semiconductor chip further has a first transmission / reception circuit electrically connected to the first transmission / reception coil, the first transmission / reception circuit has a first transmission circuit and a first reception circuit, the second semiconductor chip further has a second transmission / reception circuit electrically connected to the second transmission / reception coil, the second transmission / reception circuit has a second transmission circuit and a second reception circuit, when the first switch is in an off state and the second switch is in an on state, the first transmission circuit is electrically connected to the first transmission / reception coil and the second reception circuit is electrically connected to the second transmission / reception coil, The semiconductor device according to claim 2, wherein when the second switch is in an off state and the first switch is in an off state, the first receiving circuit is electrically connected to the first transmitting and receiving coil and the second transmitting circuit is electrically connected to the second transmitting and receiving coil.

4. The first semiconductor chip further includes a first control circuit that switches between an on state and an off state of the first switch. The semiconductor device according to claim 2, wherein the second semiconductor chip further includes a second control circuit that switches between an on state and an off state of the second switch.

5. The first switch is a first MOSFET. The second switch is a second MOSFET. The semiconductor device according to claim 1, wherein a gate width of the first MOSFET and a gate width of the second MOSFET are 5 μm or more.

6. The third semiconductor chip includes a second transformer and a third transformer. The second transformer includes a first transmitting coil and a first receiving coil. The third transformer includes a second transmitting coil and a second receiving coil. The first transmitting coil and the second transmitting coil are disposed opposite to the first receiving coil and the second receiving coil, respectively, with the insulating layer interposed therebetween. A signal is transmitted from the first semiconductor chip to the second semiconductor chip by the second transformer. The semiconductor device according to claim 2, wherein a signal is transmitted from the second semiconductor chip to the first semiconductor chip by the third transformer.

7. The semiconductor device according to claim 6, wherein in a plan view, the first transformer, the second transformer, and the third transformer are arranged such that the first transformer is positioned between the second transformer and the third transformer.

8. The third semiconductor chip further includes a guard ring. The guard ring surrounds the first transformer, the second transformer, and the third transformer in a plan view. A distance between the first transformer and the second transformer and a distance between the first transformer and the third transformer are 15 μm or more. The distances between the first transformer and the guard ring, between the second transformer and the guard ring, and between the third transformer and the guard ring are 50 μm or more. The semiconductor device according to claim 7.

9. The number of turns of the coil in the first transformer is larger than the number of turns of the coil in the second transformer and the number of turns of the coil in the third transformer. The semiconductor device according to claim 6.

10. The number of turns of the coil in the first transformer is 1.2 times or less the number of turns of the coil in the second transformer and the number of turns of the coil in the third transformer. The semiconductor device according to claim 7.

11. The signal transmission method between the first semiconductor chip and the second semiconductor chip by the first transformer is the SPI communication method. The signal transmission method between the first semiconductor chip and the second semiconductor chip by the second transformer and the signal transmission method between the first semiconductor chip and the second semiconductor chip by the third transformer are the PWM communication methods. The semiconductor device according to claim 6.

12. An inverter circuit including a power semiconductor element, A first semiconductor chip, A second semiconductor chip, And a third semiconductor chip, One of the first semiconductor chip and the second semiconductor chip has a first switch. The other of the second semiconductor chip and the second semiconductor chip has a second switch. The second semiconductor chip is electrically connected to the inverter circuit. The third semiconductor chip has a first transformer. When the first switch is in the off state and the second switch is in the on state, a signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer. An inverter system in which when the second switch is in the off state and the first switch is in the on state, a signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer.

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