Nonvolatile memory device

Abstract

To provide a nonvolatile memory device that accurately detects failures in memory elements.SOLUTION: A nonvolatile memory device (1) includes: memory elements (M1, M2) whose gates are driven by a voltage; and gate control circuits (11, 12) that can control the gate voltages of the memory elements (M1, M2) so that the memory elements (M1, M2) copy a reference current (IREF), in which the gate control circuits (11, 12) are configured to detect connection failures according to changes in current values (Id1, Id2) flowing through the memory elements (M1, M2).SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a non-volatile memory device.

Background Art

[0002] The semiconductor non-volatile memory circuit proposed in Patent Document 1 is formed by integrating a pair of transistors including a first transistor and a second transistor having a higher on-current than the first transistor as a memory cell for storing 1-bit data.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In the shipping test of the semiconductor non-volatile memory circuit proposed in Patent Document 1, there are cases where a memory cell with a high-resistance connection part on the source side cannot be removed as a defective product.

[0005] A non-volatile memory device according to an aspect of the present disclosure includes a memory element whose gate is driven by a voltage, and a gate control circuit that controls the gate voltage of the memory element so that the memory element copies a reference current. When confirming a connection failure of the memory element, a connection failure is detected according to a change in the current value flowing through the memory element.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0007] [Detailed Description] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor in which the gate structure is composed of at least three layers of "a layer made of a conductor or a semiconductor such as polysilicon with a small resistance value", "an insulating layer", and "a P-type, N-type, or intrinsic semiconductor layer". That is, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, an N-channel MOS field effect transistor is referred to as an NMOS transistor, and a P-channel MOS field effect transistor is referred to as a PMOS transistor.

[0008] [Nonvolatile Memory Device] FIG. 1 is a block diagram showing an overall configuration example of the nonvolatile memory device 1. The nonvolatile memory device 1 shown in FIG. 1 includes a memory array 10, an X decoder 20, a Y decoder 30, and a controller 40.

[0009] The memory array 10 includes m gate lines G1 to Gm (= word lines) laid in the X-axis direction, 2n bit lines BL1 to BL2n laid in the Y-axis direction, and a plurality (= m × n) of memory cells CELL arranged in a matrix along the gate lines G1 to Gm and the bit lines BL1 to BL2n. The configuration and operation of the memory array 10 will be described in detail later.

[0010] The X decoder (row decoder) 20 drives the gate lines G1 to Gm according to an instruction from the controller 40.

[0011] The Y decoder (column decoder) 30 drives the bit lines BL1 to BL2n according to an instruction from the controller 40.

[0012] The controller 40 controls each part of the device according to a command input from outside the device.

[0013] <Memory array> Figure 2 is a circuit diagram showing a configuration example of the memory array 10. The memory array 10 shown in Figure 2 includes a first memory element M1, a second memory element M2, a sense amplifier SA, NMOS transistors Q1 and Q2, and PMOS transistors Q3 and Q4. A pair of the first memory element M1 and the second memory element M2 forms one memory cell CELL (see Figure 1).

[0014] In the memory cell CELL, data of "0" or data of "1" is stored by the combination of the first memory element M1 and the second memory element M2.

[0015] The first memory element M1 and the second memory element M2 are each composed of an NMOS transistor. The first memory element M1 and the second memory element M2 are each an element capable of executing a program operation by changing the characteristics of the transistor by hot carrier injection, and are also referred to as OTP (One Time Programmable) elements. Note that the first memory element M1 and the second memory element M2 may be any element capable of executing a program operation, and may be an element other than an NMOS transistor.

[0016] The gates of the first memory element M1 and the second memory element M2 arranged in the i-th row are connected to the gate line Gi. Here, i is an arbitrary natural number from 1 to m. The drain of the first memory element M1 is connected to the first input terminal of the sense amplifier SA via the NMOS transistor Q1. The drain of the second memory element M2 is connected to the second input terminal of the sense amplifier SA via the NMOS transistor Q2.

[0017] The source of the first memory element M1 is connected to the source of the PMOS transistor Q3. The source of the second memory element M2 is connected to the source of the PMOS transistor Q4. The drain of the PMOS transistor Q4 arranged in the j-th column is connected to the bit line BL2j - 1. The drain of the PMOS transistor Q3 arranged in the j-th column is connected to the bit line BL2j. Here, j is an arbitrary natural number from 1 to n.

[0018] Before the execution of the program operation in the first memory element M1 and the second memory element M2, the drain current Id1 flowing through the first memory element M1 is equal to the drain current Id2 flowing through the second memory element M2. In this case, since there is no difference between the drain current Id1 flowing through the first memory element M1 and the drain current Id2 flowing through the second memory element M2, the data is indeterminate. That is, in the non-volatile memory device 1, the initial value of the data in the state where the program operation is not executed in the first memory element M1 and the second memory element M2 is not set.

[0019] Here, for a transistor, the structure is a concept that includes the size of the transistor. Therefore, for any plurality of transistors, if their structures are the same as each other, it means that the sizes of the plurality of transistors are also the same as each other. When the structures of a certain plurality of transistors are the same as each other, if hot carrier injection by a program operation is not performed on the plurality of transistors, the electrical characteristics (including the gate threshold voltage, etc.) of the plurality of transistors will also be the same as each other. However, for any plurality of transistors, if their structures and electrical characteristics are the same, it means that they are the same in design, but actually may include errors (that is, being the same is a concept including errors).

[0020] In the non-volatile memory device 1, a read operation for reading data stored in the first memory element M1 and the second memory element M2, and a program operation (write operation) for storing data (logical value) in the first memory element M1 and the second memory element M2 can be executed.

[0021] In the program operation, by injecting hot carriers into one of the first memory element M1 and the second memory element M2, the electrical characteristics of one of the first memory element M1 and the second memory element M2 are changed. Due to this change, the gate threshold voltage of one of the first memory element M1 and the second memory element M2 increases. Here, in FIG. 3, the solid line waveform INI represents the gate-source voltage dependence of the drain current of one of the first memory element M1 and the second memory element M2 before the execution of the program operation. Also, in FIG. 3, the dotted line waveform PRG represents the gate-source voltage dependence of the drain current of one of the first memory element M1 and the second memory element M2 after the execution of the program operation. Thus, due to the program operation, the gate threshold voltage Vth of one of the first memory element M1 and the second memory element M2 increases.

[0022] When the controller 40 executes a program operation, it applies a high voltage (power supply voltage VDD) to the gates of the first memory element M1 and the second memory element M2 that execute the program operation, and turns on the switch S12 described later. Then, when the transistor that injects hot carriers is the first memory element M1, the controller 40 turns on the switch S7 described later to ground the drain of the transistor that injects hot carriers, and turns off the switch S8 described later. On the other hand, when the transistor that injects hot carriers is the second memory element M2, the controller 40 turns on the switch S8 described later to ground the drain of the transistor that injects hot carriers, and turns off the switch S7 described later.

[0023] In a state where the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2 are supplied, the sense amplifier SA outputs an output signal DOUT corresponding to the value (logical value) of the data stored in the memory cell CELL based on the magnitude relationship between the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2 in the read operation.

[0024] Among the first memory element M1 and the second memory element M2 before the execution of the program operation, by injecting hot carriers into the first memory element M1 by the execution of the program operation, the gate threshold voltage of the first memory element M1 increases. As a result, after the execution of the program operation, the gate threshold voltage of the first memory element M1 becomes higher than the gate threshold voltage of the second memory element M2. For this reason, the drain current Id1 of the first memory element M1 becomes smaller than the drain current Id2 of the second memory element M2. The state where the drain current Id1 of the first memory element M1 is smaller than the drain current Id2 of the second memory element M2 corresponds to a state where "0" data is stored. Therefore, in the read operation, when the drain current Id1 of the first memory element M1 is smaller than the drain current Id2 of the second memory element M2, the sense amplifier SA outputs an output signal DOUT (low-level DOUT) corresponding to "0" data.

[0025] On one hand, among the first memory element M1 and the second memory element M2 before the execution of the program operation, hot carriers are injected into the second memory element M2 by the execution of the program operation, so that the gate threshold voltage of the second memory element M2 increases. As a result, after the execution of the program operation, the gate threshold voltage of the second memory element M2 becomes higher than the gate threshold voltage of the first memory element M1. For this reason, the drain current Id1 of the first memory element M1 becomes larger than the drain current Id2 of the second memory element M2. The state where the drain current Id1 of the first memory element M1 is larger than the drain current Id2 of the second memory element M2 corresponds to the state where the data of "1" is stored. Therefore, in the read operation, when the drain current Id1 of the first memory element M1 is larger than the drain current Id2 of the second memory element M2, the sense amplifier SA outputs an output signal DOUT (high-level DOUT) corresponding to the data of "1".

[0026] As shown in FIG. 2, the sense amplifier SA includes PMOS transistors Q5 and Q6, switches S1 to S4, and inverters IV1 to IV4. The memory array 10 includes switches S5 to S12.

[0027] The source of the PMOS transistor Q6 is connected to the applied end of the power supply voltage VDD. The drain of the PMOS transistor Q6 is connected to the line Ln1. The gate of the PMOS transistor Q6 is connected to the line Ln2. The line Ln1 is connected to the drain of the first memory element M1 via the NMOS transistor Q1. The line Ln2 is connected to the drain of the second memory element M2 via the NMOS transistor Q2.

[0028] The source of the PMOS transistor Q5 is connected to the applied end of the power supply voltage VDD. The drain of the PMOS transistor Q5 is connected to the line Ln2. The gate of the PMOS transistor Q5 is connected to the line Ln1.

[0029] A switch S1 is connected between the applied end of the power supply voltage VDD and the line Ln1. A switch S2 is connected between the applied end of the power supply voltage VDD and the line Ln2.

[0030] The input end of the inverter IV1 is connected to the line Ln1. The output end of the inverter IV1 is connected to the input end of the inverter IV2. The output end of the inverter IV2 is connected to the input end of the inverter IV3. An output signal DOUT is output from the inverter IV3.

[0031] Switches S3 and S5 are connected between the line Ln1 and the ground end. The on / off of the switch S3 is controlled according to the output of the inverter IV1. Switches S4 and S6 are connected between the line Ln2 and the ground end. The input end of the inverter IV4 is connected to the line Ln2. The on / off of the switch S4 is controlled according to the output of the inverter IV4. A switch S7 is connected between the source of the NMOS transistor Q1 and the ground end. A switch S8 is connected between the source of the NMOS transistor Q2 and the ground end. A switch S9 is connected between the drain of the PMOS transistor Q3 and the applied end of the power supply voltage VDD. A switch S10 is connected between the drain of the PMOS transistor Q4 and the applied end of the power supply voltage VDD. A switch S11 is connected between the sources of the first memory element M1 and the second memory element M2 and the ground end. A switch S12 is connected between the sources of the first memory element M1 and the second memory element M2 and the applied end of the power supply voltage VDD.

[0032] The gate control circuit 11 to be described later can output a signal XRST and control the on / off of the switches S1 and S2 based on an instruction from the controller 40.

[0033] Here, FIG. 4 is a timing chart showing waveform examples of the signal XRST, the voltage V1 of line Ln1, and the voltage V2 of line Ln2. With reference to FIG. 4, the operation of the sense amplifier SA will be described. In the read operation, the period during which the signal XRST is at the low level is referred to as the precharge period, and the period during which it is at the high level is referred to as the read period. Note that in the read operation, the controller 40 turns on the switches S5 and S6.

[0034] During the precharge period, which is the period when the signal XRST is at the low level, the controller 40 sets the gate voltages of the first memory element M1 and the second memory element M2 to the low level and turns on the switches S1 and S2. As a result, the gates and sources of the PMOS transistors Q5 and Q6 are short-circuited, and the PMOS transistors Q5 and Q6 turn off. Also, positive charge is supplied to line Ln1 through the on-state switch S1, and the voltage V1 reaches the level of the power supply voltage VDD. Positive charge is supplied to line Ln2 through the on-state switch S2, and the voltage V2 also reaches the level of the power supply voltage VDD. At this time, since the outputs of the inverters IV1 and IV4 are at the low level, the switches S3 and S4 turn off.

[0035] Then, when the signal XRST is switched from the low level to the high level and the precharge period transitions to the read period, the controller 40 sets the gate voltages of the first memory element M1 and the second memory element M2 to the high level and turns off the switches S1 and S2. When the drain current Id2 of the second memory element M2 flows, the voltage V2 decreases, and when the drain current Id1 of the first memory element M1 flows, the voltage V1 decreases.

[0036] In the read operation after executing the program operation and injecting hot carriers into the first memory element M1, the drain current Id1 of the first memory element M1 is approximately "0", and since the drain current Id2 of the second memory element M2 is larger than the drain current Id1 of the first memory element M1, the voltage V2 decreases (V2(Id2>Id1) in FIG. 4). When the voltage V2 reaches the threshold Th, the output of the inverter IV4 switches from the low level to the high level, and the switch S4 is switched on. As a result, the voltage V2 = 0V, the PMOS transistor Q6 is turned on, and the voltage V1 = VDD. At this time, the PMOS transistor Q5 is turned off. Therefore, the output signal DOUT output from the inverter IV3 becomes the low level. That is, the output signal DOUT is output as a signal indicating the state in which "0" is stored.

[0037] On the other hand, in the read operation after executing the program operation and injecting hot carriers into the second memory element M2, the drain current Id2 of the second memory element M2 is approximately "0", and since the drain current Id2 of the second memory element M2 is smaller than the drain current Id1 of the first memory element M1, the voltage V1 decreases. When the voltage V1 reaches the threshold Th, the output of the inverter IV1 switches from the low level to the high level, and the switch S3 is switched on. As a result, the voltage V1 = 0V, the PMOS transistor Q5 is turned on, and the voltage V2 = VDD. At this time, the PMOS transistor Q6 is turned off. Therefore, the output signal DOUT output from the inverter IV3 becomes the high level. That is, the output signal DOUT is output as a signal indicating the state in which "1" is stored.

[0038] <Shipping Test> Before the non-volatile memory device 1 is shipped, a shipping test is executed on the non-volatile memory device 1.

[0039] For example, if the connection of the source connection part of the first memory element M1 is disconnected, the first memory element M1 may not operate, and the non-volatile memory device 1 may not operate. The same applies when the connection of the drain connection part of the first memory element M1 is disconnected. The same also applies to the second memory element M2.

[0040] In addition, for the source connection failure and drain connection failure of the first memory element M1, in addition to the case where the connection is disconnected, there may be a case where the connection is not completely disconnected but partially connected and the resistance is high. When the resistance of the connection part is high, the gate-source voltage becomes small and should be identified as a defect. However, when performing the shipment test, when a high voltage is applied to the gate, a sufficient gate-source voltage may be generated, and it may not be identified as a defective product. Also, when the temperature of the connection part rises, the resistance may decrease, and a sufficient gate-source voltage may be generated. Thus, although the connection part has a high resistance (hereinafter referred to as being in a high-resistance state), there may be a case where what should originally be identified as a defective product is distributed as a non-defective product.

[0041] The non-volatile memory device 1 solves the above problems by providing the gate control circuit 11 in the memory array 10. That is, the non-volatile memory device 1 can accurately identify defective products due to the high resistance of the connection parts of the first memory element M1 and the second memory element M2.

[0042] FIG. 5 is a circuit diagram showing an example of the gate control circuit 11. m gate control circuits 11_1 to 11_m are connected to the respective gate lines G1 to Gm. Note that all of the m gate control circuits 11_1 to 11_m have the same configuration, and in the following description, the gate control circuit 11_1 connected to the gate line G1 is taken as a representative and described as the gate control circuit 11. As shown in FIG. 5, the gate control circuit 11 includes an NMOS transistor Q7, a PMOS transistor Q8, an NMOS transistor Q9, and a switching switch SW1.

[0043] The gate control circuit 11 is configured to receive a reference current IREF supplied from the outside.

[0044] The switching switch SW1 is connected to the gate line G1. The switching switch SW1 has a first terminal T1, a second terminal T2, and a third terminal T3. The switching switch SW1 is configured to be controlled by the controller 40 so as to switch between a first connection state in which the first terminal T1 and the third terminal T3 are connected and a second connection state in which the second terminal T2 and the third terminal T3 are connected. Note that the switching switch SW1 may include a disconnected state in which the third terminal T3 is not connected to either the first terminal T1 or the second terminal T2.

[0045] The third terminal T3 of the switching switch SW1 is connected to the gate line G1. The first terminal T1 is connected to the gate of the NMOS transistor Q7. The second terminal T2 is connected to the connection point P1 between the source of the PMOS transistor Q8 and the drain of the NMOS transistor Q9.

[0046] The reference current IREF supplied from the outside is supplied to the drain of the NMOS transistor Q7. The source of the NMOS transistor Q7 is connected to the ground terminal. The gate of the NMOS transistor Q7 is connected to the drain and, as described above, is connected to the first terminal T1 of the switching switch SW1. The NMOS transistor Q7, the first memory element M1, and the second memory element M2 have the same structure. That is, when the first memory element M1 and the second memory element M2 are normal, when the switching switch SW1 is in the first connection state, the NMOS transistor Q7, the first memory element M1, and the second memory element M2 constitute a current mirror circuit. That is, the NMOS transistor Q7 is an element that constitutes a reference current supply circuit.

[0047] That is, when the first memory element M1 and the second memory element M2 are non-defective, when the switching switch SW1 is in the first connection state, the drain current Id1 of the first memory element M1 and the drain current Id2 of the second memory element M2 are configured to be currents obtained by mirroring the reference current IREF supplied to the NMOS transistor Q7.

[0048] The source of the PMOS transistor Q8 is connected to the connection terminal of the constant voltage VREG. Note that the constant voltage VREG may be the power supply voltage VDD. The drain of the PMOS transistor is connected to the drain of the NMOS transistor Q9. The connection point P1 between the drain of the PMOS transistor and the drain of the NMOS transistor Q9 is connected to the second terminal T2 of the switching switch SW1.

[0049] The gate of the PMOS transistor Q8 and the gate of the NMOS transistor Q9 are connected. The control signal XC1 from the X decoder 20 is input to the connection point P2 between the gate of the PMOS transistor Q8 and the gate of the NMOS transistor Q9. The source of the NMOS transistor Q9 is connected to the ground terminal. The PMOS transistor Q8 and the NMOS transistor Q9 constitute a CMOS (Complementary MOS) inverter circuit. The CMOS inverter circuit composed of the PMOS transistor Q8 and the NMOS transistor Q9 is an element that constitutes a gate voltage supply circuit.

[0050] In the CMOS inverter circuit, when the control signal XC1 is at a high level, the drive signal XD1, which is the signal output from the connection point P1, is at a Lo level, and when the control signal XC1 is at a low level, the drive signal XD1 is at a high level. Note that the drive signal XD1, when at a high level, is determined by the constant voltage VREG input to the source of the PMOS transistor Q8 and is a voltage that can control the first memory element M1 and the second memory element M2 to turn on. When the drive signal XD1 is at a low level, it is the voltage of the ground terminal, that is, approximately "0" V.

[0051] When the switching switch SW1 is in the second connection state, the drive signal XD1 is input to the gate of the first memory element M1 and the second memory element M2. The drive signal XD1 is a gate voltage for driving the first memory element M1 and the second memory element M2.

[0052] The non-volatile memory device 1 operates the gate control circuit 11 to perform a shipping test. In the first test, the first memory element M1 before executing the program operation is the test target.

[0053] The controller 40 switches the switching switch SW1 of the gate control circuit 11 to the first connection state so that the NMOS transistor Q7 is connected to the gate line G1. Then, the controller 40 turns on the NMOS transistor Q1 and the PMOS transistor Q3 in the same column as the first memory element M1 that is the test target, and turns off the switch S9. Further, the controller 40 turns off the NMOS transistor Q2 and the PMOS transistor Q4 in the same column as the first memory element M1 that is the test target, and turns on the switch S10.

[0054] Thereby, the first memory element M1 that is the test target constitutes a current mirror circuit with the NMOS transistor Q7. For example, when the first memory element M1 can operate normally, that is, when it is a good product, a drain current Id1 obtained by mirroring the reference current IREF supplied to the NMOS transistor Q7 flows through the first memory element M1. On the other hand, when the resistance increases due to a connection failure or the like at the connection portion on the source side of the first memory element M1, the gate-source voltage of the first memory element M1 decreases, so the current flowing through the drain-source, that is, the drain current Id1 decreases.

[0055] In the first test, the drain current Id1 flowing through the bit line BL2 to which the first memory element M1 is connected is detected. If it is greater than the threshold value corresponding to the reference current IREF, it is determined that there is no abnormality in the first memory element M1 that is the test target, that is, it is determined to be a good product. On the other hand, if the drain current Id1 is smaller than the threshold value, it is determined that there is an abnormality in the first memory element M1, that is, it is determined to be a defective product.

[0056] The non-volatile memory device 1 operates the gate control circuit 11 to perform a shipping test. In the second test, the second memory element M2 before executing the program operation is targeted for testing.

[0057] The controller 40 switches the switching switch SW1 of the gate control circuit 11 to the first connection state so that the NMOS transistor Q7 is connected to the gate line G1. Then, the controller 40 turns on the NMOS transistor Q2 and the PMOS transistor Q4 in the same column as the second memory element M2 that is the test target, and turns off the switch S10. Further, the controller 40 turns off the NMOS transistor Q1 and the PMOS transistor Q3 in the same column as the second memory element M2 that is the test target, and turns on the switch S9.

[0058] As a result, the second memory element M2 that is the test target constitutes a current mirror circuit with the NMOS transistor Q7. For example, when the second memory element M2 can operate normally, that is, when it is a good product, a drain current Id1 obtained by mirroring the reference current IREF supplied to the NMOS transistor Q7 flows through the second memory element M2. On the other hand, when the resistance increases due to a connection failure or the like at the connection portion on the source side of the second memory element M2, the gate-source voltage of the second memory element M2 decreases, so the current flowing between the drain and source, that is, the drain current Id2 decreases.

[0059] In the second test, the drain current Id2 flowing through the bit line BL1 to which the second memory element M2 is connected is detected. If it is greater than the threshold value corresponding to the reference current IREF, it is determined that there is no abnormality in the second memory element M2 that is the test target, that is, it is determined to be a good product. On the other hand, if the drain current Id2 is smaller than the threshold value, it is determined that there is an abnormality in the second memory element M2, that is, it is determined to be a defective product.

[0060] In this way, by configuring the NMOS transistor Q7 of the gate control circuit 11 to form a current mirror circuit with the first memory element M1 and the second memory element M2, it is possible to accurately determine the defect caused by the high resistance of the connection portion on the source side of the first memory element M1 and the second memory element M2.

[0061] The memory array 10 shown in FIG. 2 further includes an inverter IV5, NAND gates N1 to N3, and buffers B1 and B2.

[0062] The circuit composed of the inverter IV5, the NAND gates N1 and N2, and the buffers B1 and B2 controls the on / off of the NMOS transistors Q1 and Q2 based on the signals SG1 and SG2 output from the controller 40. The signal SG1 is supplied to each first input terminal of the NAND gates N1 and N2. The signal SG2 is supplied to the second input terminal of the NAND gate N1. The signal SG2 is supplied to the input terminal of the inverter IV5. The output terminal of the inverter IV5 is connected to the second input terminal of the NAND gate N2. The output terminal of the NAND gate N1 is connected to the gate of the NMOS transistor Q1 via the buffer B1. The output terminal of the NAND gate N2 is connected to the gate of the NMOS transistor Q2 via the buffer B2.

[0063] The signal SG1 becomes high level when the shipping test is being performed and low level when the shipping test is not being performed. The signal SG2 is the same signal as the signal that becomes low level when injecting hot carriers into the first memory element M1 and high level when injecting hot carriers into the second memory element M2.

[0064] The NAND gate N3 controls the on / off of the PMOS transistors Q3 and Q4 based on the signals SG2 and SG3 output from the controller 40. The signal SG2 is supplied to the first input terminal of the NAND gate N3. The signal SG3 is supplied to the second input terminal of the NAND gate N3. The output terminal of the NAND gate N3 is connected to each gate of the PMOS transistors Q3 and Q4.

[0065] <Modification Example> FIG. 6 is a timing chart showing an example of the waveform of the voltage V1 of line Ln1 during the shipping test. As described above, the first memory element M1 and the second memory element M2 are NMOS transistors having the same configuration, and both form an NMOS transistor Q7 and a current mirror circuit. Therefore, in FIG. 6, an example of the waveform during the shipping test of the first memory element M1 is shown, but the second memory element M2 shows the same behavior during the shipping test.

[0066] When performing the shipping test, in the first memory element M1, after the start of the shipping test, the drain current Id1 rises and stabilizes at a certain current value after a certain period of time. When the connection part on the source side of the first memory element M1 has a high resistance, the gate-source voltage becomes low, so the drain current Id1 becomes low and the rise of the drain current Id1 also becomes gentle. That is, when the first memory element M1 is a defective product, it takes a longer time than when it is a non-defective product until the drain current Id1 stabilizes. Therefore, when detecting the drain current Id1 and performing a pass / fail determination based on its value, the test may take a long time.

[0067] Therefore, in the shipping test of the modification example, the pass / fail determination of the first memory element M1 and the second memory element M2 is performed based on the change in the voltage V1 of the line Ln1 of the sense amplifier SA.

[0068] First, the change in the voltage V1 of the line Ln1 will be described when the first memory element M1 is a non-defective product and when it is a defective product. As described above, when the first memory element M1 is a non-defective product, the drain current Id1 stabilizes at the current mirroring the reference current IREF in a short time. Therefore, the voltage V1 of the line Ln1 drops suddenly and reaches the threshold Th in a short time (specifically, at the time t0 shown in FIG. 6). On the other hand, when the first memory element M1 is a defective product, the drop of the drain current Id1 is slower than when it is a non-defective product and does not reach the threshold Th at the time t0.

[0069] Therefore, in the shipping test of the modified example, when the voltage V1 of line Ln1 at a timing (time t1) slightly longer than time t0 is smaller than the threshold value Th, the first memory element M1 is determined to be a non-defective product. On the other hand, when the voltage V1 of line Ln1 at time t1 is larger than the threshold value Th, the first memory element M1 is determined to be a defective product.

[0070] Next, a specific method for the shipping test of the modified example will be described. In the shipping test, the controller 40 switches the switching switch SW1 of the gate control circuit 11 to the first connection state. Also, the PMOS transistor Q3 and the PMOS transistor Q4 are turned off, and the switch S9 and the switch S10 are turned off. Then, the operation is switched to the read operation. And when time t1 has elapsed, if the output signal DOUT is at a high level, that is, a signal indicating a state in which the output signal DOUT stores "1" is output, the first memory element M1 is determined to be a non-defective product. On the other hand, when time t1 has elapsed, if the output signal DOUT is at a low level, that is, a signal indicating a state in which the output signal DOUT stores "0" is output, the first memory element M1 is determined to be a defective product.

[0071] As described above, in a configuration for determining the quality of a memory element based on the output signal of the sense amplifier SA, compared with the case of determining the quality based on the measured drain current, the time required for determining the quality of the non-volatile memory device 1 can be shortened.

[0072] FIG. 7 is a circuit diagram showing the gate control circuit 12 of the modified example. The gate control circuit 12 shown in FIG. 7 is different from the gate control circuit 11 in that the NMOS transistor Q7 constituting the current mirror circuit is omitted and the switching switch SW2 is arranged at a position different from the switching switch SW1. Regarding other points of the gate control circuit 12, it has the same configuration as the gate control circuit 11, the same parts are denoted by the same reference numerals, and detailed descriptions of the same parts are omitted.

[0073] As shown in FIG. 7, the gate control circuit 12 has a CMOS inverter using a PMOS transistor Q8 and an NMOS transistor Q9. The source of the PMOS transistor Q8 is connected to the connection terminal of the constant voltage VREG. When the PMOS transistor Q8 is on, it is configured to supply the reference current IREF to the PMOS transistor Q8. The NMOS transistor Q9, the first memory element M1, and the second memory element M2 constitute a current mirror circuit.

[0074] The connection point P1 between the source of the PMOS transistor Q8 and the drain of the NMOS transistor Q9 is connected to the gate line G1. The gates of the PMOS transistor Q8 and the NMOS transistor Q9 are connected to the switching switch SW2.

[0075] The first terminal T1 of the switching switch SW2 is connected to the gate of the PMOS transistor Q8. The second terminal T2 of the switching switch SW2 is connected to the connection point P1 between the source of the PMOS transistor Q8 and the drain of the NMOS transistor Q9. The third terminal T3 of the switching switch SW2 is connected to the gate of the NMOS transistor Q9. The switching switch SW2 is switched between a first connection state in which the first terminal T1 and the third terminal T3 are connected and a second connection state in which the second terminal T2 and the third terminal T3 are connected according to an instruction from the controller 40. The control signal XE1 from the X decoder 20 is supplied to the first terminal T1 of the switching switch SW2 and the PMOS transistor Q8.

[0076] The CMOS inverter circuit composed of the PMOS transistor Q8 and the NMOS transistor Q9 constitutes the gate voltage supply circuit of the gate control circuit 12. The PMOS transistor Q8 constitutes the reference current supply circuit of the gate control circuit 12. Further, in the gate control circuit 12, the reference current supply circuit and the gate voltage supply circuit share the PMOS transistor Q8.

[0077] When the gate control circuit 12 is in the second connection state, the control signal XE1 is input only to the gate of the PMOS transistor Q8. Therefore, the PMOS transistor Q8 supplies the reference current IREF to the first memory element M1 and the second memory element M2. When in the second connection state, currents obtained by mirroring the reference current IREF flow as the drain current Id1 and the drain current Id2.

[0078] Also, when the switching switch SW2 is in the first connection state, the PMOS transistor Q8 and the NMOS transistor Q9 form a CMOS inverter. Note that the CMOS inverter is the same as the gate control circuit 12 and supplies a drive signal XD1, which is a voltage signal for driving the gates of the first memory element M1 and the second memory element M2.

[0079] The gate control circuit 12 enters a state where it performs a shipping test when the switching switch SW2 is in the second connection state, and enters a state where it drives the first memory element M1 and the second memory element M2 when in the first connection state. Then, since the quality determination of the first memory element M1 and the second memory element M2 is performed using the drain currents Id1 and Id2, it is possible to accurately detect a defect in the connection state of the first memory element M1 and the second memory element M2.

[0080] <Others> The above embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is shown not by the description of the above embodiments but by the claims, and it should be understood that all modifications within the meaning and scope equivalent to the claims are included.

[0081] <Supplementary Note> Hereinafter, the various embodiments described above will be summarized.

[0082] The non-volatile memory device (1) described above has memory elements (M1, M2) whose gates are driven by voltage, and gate control circuits (11, 12) that control the gate voltages of the memory elements (M1, M2) so that the memory elements (M1, M2) copy a reference current (IREF). When checking for a connection failure in the memory elements (M1, M2), it is configured (first configuration) to detect the connection failure according to changes in the current values (Id1, Id2) flowing through the memory elements (M1, M2).

[0083] In the non-volatile memory device (1) having the first configuration, the gate control circuit (11) includes a reference current supply circuit configured to supply a reference current (IREF), a gate voltage supply circuit configured to supply a voltage for driving the gates of the memory elements (M1, M2), and a switching switch (SW1, SW2) configured to be able to switch between the reference current supply circuit and the gate voltage supply circuit. This is the configuration (second configuration).

[0084] In the non-volatile memory device (1) having the first configuration, the gate control circuit (12) includes a reference current supply circuit configured to supply a reference current (IREF) and a gate voltage supply circuit configured to supply a voltage for driving the gates of the memory elements (M1, M2). The reference current supply circuit and the gate voltage supply circuit are configured to share at least some MOS transistors (Q8). This is the configuration (third configuration).

[0085] In the non-volatile memory device (1) having any one of the first to third configurations, the gate control circuit is configured to form a current mirror circuit with the memory element. This is the configuration (fourth configuration).

[0086] In the non-volatile memory device (1) having the first or second configuration, the gate control circuit (11) is configured such that a reference current (IREF) is supplied from the outside. This is the configuration (fifth configuration).

[0087] In the non-volatile memory device (1) having any one of the first to fifth configurations, a sense amplifier (SA) for determining data stored based on currents (Id1, Id2) flowing through the memory elements (M1, M2) is further provided. When the determination by the sense amplifier (SA) is within a predetermined time (t1), it is determined that the connection state of the memory elements (M1, M2) is good, and when it does not fall within the time (t1), it is determined that the connection state of the memory elements (M1, M2) is bad. This is the configuration (the sixth configuration).

Explanation of Signs

[0088] 1 Non-volatile memory device 10 Memory array 11 Gate control circuit 12 Gate control circuit 20 X decoder 30 Y decoder 40 Controller 50 Controller B1, B2 Buffer BL1~BL2n Bit line CELL Memory cell G1~Gm Gate line IV1~IV5 Inverter M1 First memory element M2 Second memory element N1~N3 NAND gate Q1, Q2 NMOS transistor Q3~Q6 PMOS transistor Q7 NMOS transistor Q8 PMOS transistor Q9 NMOS transistor S1~S12 Switch SA Sense amplifier SW1, SW2 Switching switch T1 First terminal T2 Second terminal T3 Third terminal

Claims

1. A memory element configured to be driven by a voltage, and a gate control circuit having a configuration capable of controlling the gate voltage of the memory element so that the memory element copies a reference current, wherein the gate control circuit is configured to detect a connection failure according to a change in the current value flowing through the memory element. A non-volatile memory device.

2. The gate control circuit includes a reference current supply circuit configured to supply the reference current, a gate voltage supply circuit configured to supply a voltage for driving the gate of the memory element, and a switching switch configured to be able to switch between the reference current supply circuit and the gate voltage supply circuit. The non-volatile memory device according to Claim 1.

3. The gate control circuit includes a reference current supply circuit configured to supply the reference current, a gate voltage supply circuit configured to supply a voltage for driving the gate of the memory element, and the reference current supply circuit and the gate voltage supply circuit are configured to share at least some MOS transistors. The non-volatile memory device according to Claim 1.

4. The gate control circuit is configured to form a current mirror circuit with the memory element. The non-volatile memory device according to Claim 1.

5. In the gate control circuit, the reference current is configured to be supplied from the outside. The non-volatile memory device according to Claim 2.

6. further comprising a sense amplifier configured to determine data stored based on the current flowing through the memory element, wherein when the determination by the sense amplifier is within a predetermined time, it is determined that the connection state of the memory element is good, and when it does not fall within the time, it is determined that the connection state of the memory element is bad. The non-volatile memory device according to any one of Claims 1 to 5.

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