Semiconductor device
By strategically placing gate pads and drain wirings between FET groups in a semiconductor device, the semiconductor device effectively reduces gate-drain capacitance, enhancing high-frequency performance and thermal management.
Patent Information
- Application Number
- JP2023194732
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-11-15
- Publication Date
- 2025-05-27
AI Technical Summary
The proximity of gate pads and drain pads in existing semiconductor devices leads to the generation of gate-drain parasitic capacitance, resulting in deteriorated FET characteristics.
The semiconductor device design includes a substrate with alternating first and second FET groups, where first gate pads are placed between the FET groups, and drain wirings are alternately positioned with the gate pads to reduce capacitance.
This design effectively suppresses gate-drain capacitance, thereby improving high-frequency characteristics and reducing thermal resistance.
Smart Images
Figure 2025081154000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device.
Background Art
[0002] A field effect transistor (FET) having a source electrode, a gate electrode, and a drain electrode is known. It is known to arrange a plurality of FETs in parallel in the direction of the electrodes and arrange two FET groups in the extending direction of the electrodes. It is known to provide a gate pad connected to the gate electrode and a drain pad connected to the drain electrode between the FET groups (for example, Patent Documents 1 and 2).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Patent Document 2
Summary of the Invention
Problems to be Solved by the Invention
[0004] However, since the gate pad and the drain pad are adjacent to each other, a gate-drain parasitic capacitance is generated. As a result, the characteristics of the FET deteriorate.
[0005] The present disclosure has been made in view of the above problems, and an object thereof is to suppress deterioration of characteristics.
Means for Solving the Problems
[0006] One embodiment of the present disclosure includes a substrate having a front surface and a back surface facing the front surface, a plurality of first source electrodes arranged in a first direction, a plurality of first drain electrodes, and a plurality of first gate electrodes. A first FET group provided on the front surface, overlapping the first FET group when viewed from a second direction intersecting the first direction, a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes. A second FET group provided on the front surface, electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes, and a plurality of first gate pads provided on the front surface between the first FET group and the second FET group. A plurality of drain wirings provided on the front surface alternately with the plurality of first gate pads, electrically connected to the plurality of first drain electrodes, and sandwiching the first FET group with the plurality of first gate pads. A drain pad, and a semiconductor device including the drain pad.
Advantages of the Invention
[0007] According to the present disclosure, deterioration of characteristics can be suppressed.
Brief Description of the Drawings
[0008]
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[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a substrate having a front surface and a back surface facing the front surface, a plurality of first source electrodes arranged in a first direction, a plurality of first drain electrodes, and a plurality of first gate electrodes. A first FET group provided on the front surface, overlapping the first FET group when viewed from a second direction intersecting the first direction, a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes. A second FET group provided on the front surface, electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes, a plurality of first gate pads provided on the front surface between the first FET group and the second FET group, and the plurality of first drain electrodes and the plurality of second drain electrodes are electrically connected to each other. Between the first FET group and the second FET group, a plurality of drain wirings provided on the front surface alternately with the plurality of first gate pads, and a drain pad electrically connected to the plurality of first drain electrodes and sandwiching the first FET group with the plurality of first gate pads. This can suppress the gate-drain capacitance. Therefore, the high-frequency characteristics can be improved. (2) In the above (1), a back surface metal layer provided on the back surface and electrically connected to the plurality of first source electrodes through a plurality of first via holes respectively overlapping the plurality of first source electrodes when viewed in the thickness direction of the substrate, and electrically connected to the plurality of second source electrodes through a plurality of second via holes respectively overlapping the plurality of second source electrodes when viewed in the thickness direction of the substrate may be provided. This can suppress the source inductance and improve the high-frequency characteristics. (3) In the above (1) or (2), the first FET group and the second FET group are respectively provided in a first active region and a second active region where the front surface is activated, and the plurality of first gate pads may be provided in an inactive region provided between the first active region and the second active region where the front surface is inactivated. This can suppress the gate-source capacitance and improve the high-frequency characteristics. (4) In any of (1) to (3) above, the width in the first direction of the plurality of drain wirings between the first FET group and the second FET group may be smaller than the width in the first direction of the plurality of first drain electrodes and the width in the first direction of the plurality of second drain electrodes. Thereby, the gate-drain capacitance can be suppressed and the high-frequency characteristics can be improved. (5) In any of (1) to (4) above, a second gate pad may be provided on the main surface with the second FET group sandwiched between the plurality of first gate pads and being electrically connected to the plurality of second gate electrodes. Thereby, bonding wires can be joined at two locations. (6) In any of (1) to (5) above, each of the plurality of first source electrodes includes a first portion, and a second portion and a third portion that are provided between the first portion and the first gate pad corresponding to the first portion and overlapping the first portion when viewed from the second direction and are arranged in the first direction. The first FET group may be provided between the second portion and the third portion and include a plurality of first gate wirings that electrically connect the corresponding first gate electrode and the corresponding first gate pad. Thereby, the gate resistance can be suppressed and the high-frequency characteristics can be improved. (7) In (6) above, each of the plurality of second source electrodes includes a fourth portion, and a fifth portion and a sixth portion that are provided between the fourth portion and the second gate pad corresponding to the fourth portion and overlapping the fourth portion when viewed from the second direction and are arranged in the first direction. The second FET group may be provided between the fifth portion and the sixth portion and include a plurality of second gate wirings that electrically connect the corresponding second gate electrode and the corresponding second gate pad. Thereby, the gate resistance can be suppressed and the high-frequency characteristics can be improved. (8) In any of (1) to (7) above, a guard ring may be provided on the main surface and electrically connected to the plurality of first source electrodes and the plurality of second source electrodes, surrounding the first FET group and the second FET group. Thereby, the first FET group and the second FET group can be shielded. (9) In any one of (1) to (8) above, it may include a base, a semiconductor chip mounted on the base and having the substrate, a first bonding wire connected to the first gate pad and extending in the second direction, and a second bonding wire connected to the drain pad and extending in the direction opposite to the second direction. Thereby, high-frequency signals are evenly input to the first FET group and the second FET group. (10) In (5) above, it may include a base, a semiconductor chip mounted on the base and having the substrate, a first bonding wire connected to the first gate pad and extending in the second direction, a second bonding wire connected to the drain pad and extending in the direction opposite to the second direction, and a third bonding wire connected to the second gate pad and extending in the second direction. Thereby, interference between different signals can be suppressed. (11) In (10) above, it may include a first capacitor mounted on the base, with its first end electrically connected to the base and its second end connected to the first bonding wire, and a second capacitor mounted on the base, with its first end electrically connected to the base and its second end connected to the third bonding wire. Thereby, interference between different signals can be suppressed.
[0010] [Details of Embodiments of the Present Disclosure] A specific example of the semiconductor device according to the embodiment of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.
[0011] [Example 1] In a base station for mobile communication, a semiconductor device used in an amplifier that amplifies a high-frequency signal in the range of, for example, 0.5 GHz to 10 GHz will be described as an example. FIGS. 1 and 2 are plan views of the semiconductor device in Example 1. In FIG. 1, the source electrodes 12a and 12b and the drain electrodes 16a and 16b are not shown. Also, the details of the active regions 11a and 11b are not shown. In the plan view of FIG. 2, when the drain electrodes 16a and 16b overlap the drain wiring 26, it becomes difficult to view. For this reason, in FIG. 2, the drain wiring 26 is seen through, and a thick line showing only the outer periphery of the drain wiring 26 is shown inside the drain electrodes 16a and 16b. Also, the source wirings 22a and 22b are not shown.
[0012] The thickness direction of the substrate 10 is the Z direction, the extending direction of the finger-shaped gate electrodes 14a and 14b is the Y direction (second direction), and the arrangement direction of the source electrode 12a, the gate electrode 14a, and the drain electrode 16a is the X direction (first direction).
[0013] As shown in FIGS. 1 and 2, in the semiconductor device 100 of Example 1, on the main surface 50 of the substrate 10, FET groups 30a (first FET group) and 30b (second FET group) are arranged in the Y direction. The FET groups 30a and 30b each include a plurality of FETs 31 arranged in the X direction. The FETs 31 in the FET group 30a are provided on the active region 11a (first active region) and include a finger-shaped source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode) extending in the Y direction. The plurality of source electrodes 12a and the plurality of drain electrodes 16a are alternately provided in the X direction. One of the plurality of gate electrodes 14a is sandwiched in the X direction between one of the plurality of source electrodes 12a and one of the plurality of drain electrodes 16a.
[0014] The FETs 31 in the FET group 30b are provided on the active region 11b (second active region), and include finger-shaped source electrodes 12b (second source electrodes), gate electrodes 14b (second gate electrodes), and drain electrodes 16b (second drain electrodes) that extend in the Y direction. The plurality of source electrodes 12b and the plurality of drain electrodes 16b are alternately provided in the X direction. One of the plurality of gate electrodes 14b is sandwiched between one of the plurality of source electrodes 12b and one of the plurality of drain electrodes 16b in the X direction. When viewed from the Y direction, the plurality of source electrodes 12b overlap the plurality of source electrodes 12a respectively, and the plurality of drain electrodes 16b overlap the plurality of drain electrodes 16a respectively.
[0015] The plurality of gate pads 34 (first gate pads) overlap the source electrodes 12a and 12b when viewed from the Y direction, are provided on the inactive region 13 of the main surface 50 between the source electrodes 12a and 12b, and are electrically connected to the gate electrodes 14a and 14b.
[0016] Gate wirings 18a (first gate wirings) and 19a that electrically connect the gate pad 34 and the gate electrode 14a, and gate wirings 18b (second gate wirings) and 19b that electrically connect the gate pad 34 and the gate electrode 14b are provided on the main surface 50.
[0017] The drain wiring 26 extends in the Y direction and is provided on the drain electrodes 16a and 16b. The drain wiring 26 electrically connects and shorts the drain electrodes 16a and 16b to the drain pad 36. The drain wiring 26 electrically connects the drain electrode 16a and the drain electrode 16b.
[0018] The plurality of drain wirings 26 are alternately provided with the gate pads 34 on the main surface 50 between the corresponding drain electrode 16a and the corresponding drain electrode 16b.
[0019] When viewed from the Z direction, via holes 20a (first via hole) and 20b (second via hole) overlap with source electrodes 12a and 12b, respectively.
[0020] FIG. 3 is an enlarged plan view of the semiconductor device according to Example 1. FIGS. 4 to 7 are cross-sectional views taken along lines A-A, B-B, C-C, and D-D of FIG. 3, respectively.
[0021] As shown in FIGS. 3 to 7, substrate 10 has a main surface 50 and a back surface 51 facing the main surface 50. Substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the region where the semiconductor layer 10b is inactivated by ion implantation or the like is the inactive region 13, and the regions that are not inactivated (i.e., the regions where a part of the substrate 10 is activated) are the active regions 11a and 11b. Active region 11a has active portions 21a to 21c. Source electrode 12a has source portions 13a to 13c. Gate electrode 14a has gate portions 15a to 15d. Drain electrode 16a has drain portions 17a to 17d. Source wiring 22a has wiring portions 23a and 23b.
[0022] Active portion 21a extends in the X direction. Active portions 21b and 21c are arranged in the X direction. FETs 31a and 31d are provided in active portion 21a. FETs 31b and 31c are provided in active portions 21b and 21c, respectively.
[0023] FET 31a includes a source portion 13a, a gate portion 15a, and a drain portion 17a. The source portion 13a and the drain portion 17a sandwich the gate portion 15a in the X direction. The source portion 13a, the gate portion 15a, and the drain portion 17a are arranged in this order in the + direction of the X direction.
[0024] FET31d includes a source portion 13a, a gate portion 15d, and a drain portion 17d. The source portion 13a and the drain portion 17d sandwich the gate portion 15d in the X direction. The source portion 13a, the gate portion 15d, and the drain portion 17d are arranged in this order in the - direction of the X direction. FET31a and 31d share the source portion 13a.
[0025] FET31b includes a source portion 13b, a gate portion 15b, and a drain portion 17b. The source portion 13b and the drain portion 17b sandwich the gate portion 15b in the X direction. The source portion 13b is provided inside the source portion 13a when viewed from the Y direction. That is, when viewed from the Y direction, the source portion 13b is not provided outside the source portion 13a. The drain portion 17b overlaps the drain portion 17a when viewed from the Y direction. The source portion 13b, the gate portion 15b, and the drain portion 17b are arranged in this order in the + direction of the X direction.
[0026] FET31c includes a source portion 13c, a gate portion 15c, and a drain portion 17c. The source portion 13c sandwiches the gate wiring 18a with the source portion 13b and is provided inside the source portion 13a when viewed from the Y direction. That is, when viewed from the Y direction, the source portion 13c is not provided outside the source portion 13a. The drain portion 17c overlaps the drain portion 17d when viewed from the Y direction. The source portion 13c and the drain portion 17c sandwich the gate portion 15c in the X direction. The source portion 13c, the gate portion 15c, and the drain portion 17c are arranged in this order in the - direction of the X direction.
[0027] On the source portions 13a to 13c, wiring portions 23a to 23c are respectively provided in contact. The wiring portion 23b electrically connects the source portion 13b and the wiring portion 23a. The wiring portion 23c electrically connects the source portion 13c and the wiring portion 23a. As a result, the source portions 13a to 13c are electrically short-circuited and have the same potential.
[0028] The drain wiring 26 on the right side of FIG. 3 electrically connects the drain portions 17a and 17b to the drain pad 36. The drain wiring 26 on the left side of FIG. 3 electrically connects the drain portions 17d and 17c to the drain pad 36.
[0029] On the inactive region 13 between the FETs 31b and 31c, a gate wiring 18a extending in the Y direction is provided. The gate wiring 18a is provided within the source portion 13a as viewed from the Y direction. That is, as viewed from the Y direction, the gate wiring 18a is not provided outside the source portion 13a. The gate wiring 18a is electrically connected to the gate pad 34.
[0030] On the inactive region 13 between the FETs 31a and 31b and between the FETs 31d and 31c, a gate wiring 19a extending in the X direction is provided. The gate wiring 19a intersects the wiring portions 23b and 23c without contact and electrically connects the gate wiring 18a and the gate portions 15a to 15d. As a result, the gate portions 15a to 15d are electrically connected to the gate pad 34 via the gate wirings 18a and 19a, short-circuited, and at the same potential.
[0031] The gate wiring 18a and the gate pad 34 include a gate metal layer 27a provided on the substrate 10 and a wiring layer 27b provided on the gate metal layer 27a. The gate wiring 19a includes the gate metal layer 27a and does not include the wiring layer 27b.
[0032] The via hole 20a penetrates the substrate 10. The via hole 20a overlaps the source portion 13a as viewed from the Z direction and is electrically connected to the source portion 13a. A metal layer 28 is provided on the back surface 51 of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20a. As a result, the metal layer 28 (back surface metal layer) is electrically connected to the source portion 13a via the via hole 20a, short-circuited, and at the same potential. The planar shape of the via holes 20a and 20b may be elliptical, oblong, rounded rectangular, or circular.
[0033] The source potential (e.g., a reference potential such as a ground potential) is supplied from the metal layer 28 to the source portion 13a via the metal layer 28a in the via hole 20a. Further, the source potential is supplied from the wiring portion 23a to the source portions 13b and 13c via the wiring portions 23b and 23c, respectively. The gate potential (e.g., a high-frequency signal and a gate bias voltage) is supplied from the gate pad 34 to the gate portions 15a to 15d via the gate wirings 18a and 19a. The drain bias voltage is supplied from the drain pad 36 to the drain portions 17a to 17d via the drain wiring 26. The high-frequency signals amplified in each of the FETs 31a to 31d are output from the drain wiring 26 to the drain pad 36.
[0034] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al 2 O 3 ) substrate. The semiconductor layer 10b includes, for example, nitride semiconductor layers such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the FET 31 is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, arsenide semiconductor layers such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as an LDMOS (Laterally Diffused Metal Oxide Semiconductor).
[0035] The source electrodes 12a and 12b, and the drain electrodes 16a and 16b are metal films, for example, a titanium film and an aluminum film from the side of the substrate 10. The gate electrodes 14a and 14b, and the gate metal layer 27a are metal films, for example, a nickel film and a gold film from the side of the substrate 10. The source wirings 22a and 22b, the drain wiring 26, and the wiring layer 27b are, for example, a gold layer, a copper layer, or an aluminum layer. The insulating layer 25 provided on the substrate 10 so as to cover the FET 31 is an organic insulator layer such as a polyimide layer or a BCB (Benzocyclobutene) layer, etc.
[0036] The width of the source portion 13a in the X direction is, for example, from 50 μm to 150 μm. The widths of the source portions 13b and 13c in the X direction are, for example, from 5 μm to 20 μm. The gate lengths of the gate portions 15a to 15d in the X direction are, for example, from 0.25 μm to 2 μm. The widths of the drain portions 17a to 17d in the X direction are, for example, from 5 μm to 150 μm. The width of the gate wiring 18a in the X direction is, for example, from 5 μm to 20 μm. The width of the gate wiring 19a in the Y direction is, for example, from 3 μm to 20 μm. In order to reduce the gate resistance, the width of the gate wiring 18a in the X direction and the width of the gate wiring 19a in the Y direction are larger than the gate length, for example, 2 times or more the gate length. The gate widths of the FETs 31a to 31d in the Y direction are, for example, from 100 μm to 400 μm. The widths of the via holes 20a and 20b in the X direction are, for example, from 10 μm to 60 μm.
[0037] The widths of the wiring portions 23a to 23c in the X direction are the same as, or slightly smaller than, the widths of the source portions 13a to 13c in the X direction, respectively. The width of the drain wiring 26 in the X direction is the same as, or slightly smaller than, the width of the drain portions 17a to 17d in the X direction.
[0038] [Comparative Example 1] FIG. 8 is a plan view of the semiconductor device according to Comparative Example 1. As shown in FIG. 8, in the semiconductor device 110 of Comparative Example 1, a FET group 30c having FETs 31a and 31d of FIG. 3 is provided. A plurality of FET groups 30d having FETs 31b and 31c are arranged in the Y direction. The gate pad 34 and the drain pad 36 are provided so as to sandwich the FET group 30c and the plurality of FET groups 30d. The gate wiring 18 is connected to the gate pad 34. Between the FET group 30c and the FET group 30d, and between the plurality of FET groups 30d, the gate wiring 19 electrically connects the gate electrode 14 and the gate wiring 18.
[0039] In Comparative Example 1, by using the gate wirings 18 and 19, the gate resistance between the gate electrode 14 and the gate pad 34 can be reduced. However, since the source wiring 22 becomes long, the source inductance becomes large. As a result, the high-frequency characteristics deteriorate. Also, since the gate electrodes 14 serving as heat generation sources become dense, the thermal resistance becomes high.
[0040] [Comparative Example 2] FIG. 9 is a plan view of the semiconductor device according to Comparative Example 2. As shown in FIG. 9, in the semiconductor device 112 of Comparative Example 2, a gate pad 34 is provided between the FET groups 30a and 30b. The gate pad 34 is provided above the source wirings 22a, 22b and the drain wiring 26 in the Z direction.
[0041] In Comparative Example 2, by providing the gate pad 34 between the FET groups 30a and 30b and providing via holes 20a and 20b in both the FET groups 30a and 30b, the source wirings 22a and 22b can be shortened. Thereby, the source inductance can be reduced. Also, the space between the gate electrodes 14a and 14b serving as heat generation sources becomes wider. Thereby, the thermal resistance can be reduced.
[0042] However, in Comparative Example 2, as viewed in the Z direction, the gate pad 34 overlaps the source wirings 22a and 22b and the drain wiring 26. For this reason, the gate-drain capacitance and the gate-source capacitance increase. As a result, the high-frequency characteristics deteriorate.
[0043] [Description of Example 1] According to Example 1, as shown in FIGS. 1 and 2, the gate pad 34 is provided between the source electrodes 12a and 12b. The drain wiring 26 is alternately provided with the gate pad 34 between the drain electrodes 16a and 16b.
[0044] As a result, the gate pad 34 does not overlap the source wirings 22a, 22b, and the drain wiring 26. Therefore, compared with Comparative Example 2, the gate-drain capacitance and the gate-source capacitance can be suppressed. Also, compared with Comparative Example 1, the source inductance can be suppressed. The FET group 30a is sandwiched between the drain pad 36 and the gate pad 34. As a result, the gate-drain capacitance between the gate pad and the drain pad can be suppressed as in Patent Documents 1 and 2. Due to these, the high-frequency characteristics can be improved compared with Comparative Examples 1 and 2 and Patent Documents 1 and 2.
[0045] Also, since the FET groups 30a and 30b are separated, the thermal resistance can be reduced compared with Comparative Example 1.
[0046] [Simulation] As an example, thermal simulation was performed for Example 1 and Comparative Example 1. In the simulation, it was assumed that 88 gate electrodes 14 were arranged in the X direction on the SiC substrate. In Example 1, the distance between the FET groups 30a and 30b was 130 μm. As a result of the simulation, the maximum temperatures on the upper surface of the SiC substrate in Example 1 and Comparative Example 1 were 120.1 °C and 125.4 °C, respectively. Thus, Example 1 has a lower thermal resistance than Comparative Example 1 and can reduce the maximum temperature.
[0047] As shown in FIGS. 1, 4, and 6, the metal layer 28 (back metal layer) is electrically connected to the plurality of source electrodes 12a and 12b via the plurality of via holes 20a and 20b, respectively. Thereby, since a source potential can be supplied to the source electrodes 12a and 12b, source inductance can be suppressed and high-frequency characteristics can be improved.
[0048] As shown in FIG. 1, the plurality of gate pads 34 are provided in the inactive region 13. Thereby, gate-source capacitance can be suppressed and high-frequency characteristics can be improved.
[0049] As shown in FIGS. 3 to 7, the source electrode 12a includes a source portion 13a (first portion), 13b (second portion), and a source portion 13c (third portion). When viewed in the Y direction, the source portions 13b and 13c overlap the source portion 13a and are provided between the source portion 13a and the gate pad 34. The gate wiring 18a is provided between the source portions 13b and 13c and electrically connects the gate electrode 14a and the gate pad 34. Thereby, the gate resistance in the FET group 30a can be reduced without increasing the size. Therefore, high-frequency characteristics can be improved.
[0050] Similarly, the source electrode 12b includes a source portion 13a (fourth portion), 13b (fifth portion), and a source portion 13c (sixth portion). The gate wiring 18b is provided between the source portions 13b and 13c and electrically connects the gate electrode 14b and the gate pad 34. Thereby, the gate resistance in the FET group 30b can be reduced without increasing the size. Therefore, high-frequency characteristics can be improved.
[0051] [Modification Example 1 of Example 1] FIG. 10 is an enlarged plan view of a semiconductor device according to Modification 1 of Example 1. As shown in FIG. 10, in the semiconductor device 101 of Modification 1 of Example 1, in the FET group 30a, the gate portions 15a and 15b are separated, and the gate portions 15d and 15c are separated. The gate portions 15a and 15d are electrically connected to the gate pad 34 via the gate wirings 19a and 18a. The gate portions 15b and 15c are electrically connected to the gate pad 34 without passing through the gate wirings 18a and 19a. Other configurations are the same as those of Example 1, and the description thereof is omitted. As in Modification 1 of Example 1, it is sufficient that some of the gate portions 15a to 15d are electrically connected to the gate pad 34 via the gate wirings 18a and 19a.
[0052] [Modification 2 of Example 1] FIG. 11 is a plan view of a semiconductor device according to Modification 2 of Example 1. As shown in FIG. 11, in the semiconductor device 102 of Modification 2 of Example 1, the drain wiring 26 includes portions 26a to 26c. The portions 26a and 26b are provided in the FET groups 30a and 30b, respectively. The portion 26c is a portion between the FET groups 30a and 30b. The width Wc of the portion 26c in the X direction is narrower than the widths Wa and Wb of the drain electrodes 16a, 16b, and the portions 26a and 26b in the X direction. Other configurations are the same as those of Example 1, and the description thereof is omitted.
[0053] According to Modification Example 2 of Embodiment 1, the width Wc in the X direction of the drain wiring 26 between the FET groups 30a and 30b is smaller than the widths Wa and Wb in the X direction of the drain electrodes 16a, 16b, the portions 26a and 26b. Thereby, the distance between the gate pad 34 and the drain wiring 26 becomes longer, and the gate-drain capacitance can be suppressed. Therefore, the high-frequency characteristics can be improved. The width Wc can be 0.9 times or less, 0.8 times or less, and 0.6 times or less of the widths Wa and Wb. When the lengths of the FET groups 30a and 30b in the Y direction are substantially the same, if the width Wc is about 0.5 times the widths Wa and Wb, the current density flowing through the portion 26c can be made the same as the current density at a location in the portion 26a close to the drain pad 36. Therefore, the width Wc can be 0.5 times or more of the widths Wa and Wb.
[0054] [Modification Example 3 of Embodiment 1] FIG. 12 is a plan view of a semiconductor device according to Modification Example 3 of Embodiment 1. As shown in FIG. 12, in the semiconductor device 103 of Modification Example 3 of Embodiment 1, in addition to the gate pad 34, a gate pad 35 (second gate pad) is provided. The gate pad 35 is provided so as to sandwich the FET group 30b on the main surface 50 together with the gate pad 34. The gate electrode 14b is electrically directly connected to the gate pad 35. Other configurations are the same as those in Embodiment 1 and the description thereof is omitted.
[0055] According to Modification Example 3 of Embodiment 1, by providing the gate pads 34 and 35, bonding wires can be joined to the gate pads at two locations in the Y direction.
[0056] [Modification Example 4 of Embodiment 1] FIG. 13 is a plan view of a semiconductor device according to Modification Example 4 of Example 1. As shown in FIG. 13, in the semiconductor device 104 of Modification Example 4 of Example 1, gate wirings 18a and 19a are not provided. The planar shapes of source electrodes 12a and 12b, and source wirings 22a and 22b are rectangular. Thus, the semiconductor device 104 is a multi-finger type FET. A gate pad 34 is provided between FET groups 30a and 30b. Other configurations are the same as those in Example 1 and the description thereof is omitted.
[0057] In Modification Example 4 of Example 1, compared with Example 1, since gate wirings 18a, 18b, 19a, and 19b are not provided, although the gate resistance becomes high, the gate resistance can be suppressed and the high-frequency characteristics can be improved as compared with a general multi-finger type FET.
[0058] [Modification Example 5 of Example 1] FIG. 14 is a plan view of a semiconductor device according to Modification Example 5 of Example 1. As shown in FIG. 14, in the semiconductor device 105 of Modification Example 5 of Example 1, guard rings 44a and 44b are provided on the main surface 50 so as to surround FET groups 30a and 30b. A plurality of drain pads 36 are provided corresponding to drain wiring 26. The guard ring 44a is electrically connected to the source wiring 22a via a connection wiring 43a provided between the plurality of drain pads 36. The guard ring 44b is electrically connected to the source wiring 22b via a connection wiring 43b. The guard rings 44a and 44b are electrically connected to source pads 42a and 42b. Other configurations are the same as those in Example 1 and the description thereof is omitted.
[0059] In Modification 5 of Example 1, guard rings 44a and 44b are electrically connected to source electrodes 12a and 12b on the main surface 50 and surround FET groups 30a and 30b. Thereby, the FET groups 30a and 30b can be shielded. The guard rings 44a and 44b may partially surround the FET groups 30a and 30b, or may completely surround them. By providing source pads 42a and 42b, the characteristics of the FET groups 30a and 30b can be confirmed before forming via holes 20a and 20b. The drain pad 36 may be provided integrally, but by being divided into a plurality, connection wiring 43a can be provided. A connection wiring for electrically connecting the gate electrode 14b may be provided between the source wiring 22b and the guard ring 44b. The connection wirings 43a and 43b may not be provided.
[0060] In Example 1 and its modifications, although an example has been described in which six FETs 31 are provided in the X direction, eight or more FETs 31 may be provided in the X direction. In each of the FET groups 30a and 30b, although an example has been described in which two FETs 31 are provided in the Y direction, three or more FETs 31 may be provided in the Y direction.
[0061] In Example 1 and its modifications, drain portions 17a and 17b (and 17d and 17c) to which the same drain wiring 26 is electrically connected are separated from each other in the inactive region 13. A plurality of drain portions 17a to 17d to which the drain wiring 26 is electrically connected may be connected to each other in the inactive region 13. In the FET 31, the source electrode 12a and the source wiring 22a can be collectively referred to as the source electrode, and the drain electrode 16a and the drain wiring 26 can be collectively referred to as the drain electrode.
[0062] [Example 2] Example 2 and its modified examples are examples of semiconductor devices in which the semiconductor chips of Example 1 and its modified examples are mounted in a package. FIG. 15 is a plan view of the semiconductor device in Example 2. FIG. 16 is an equivalent circuit diagram of FIG. 15. In FIG. 15, the lid of the package 52 is not shown.
[0063] As shown in FIG. 15, in the semiconductor device 106 of Example 2, the package 52 has a base 53, a frame 54, and a lid, at least the upper surface of which is conductive. The base 53 is a conductor substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the base 53. The frame 54 and the lid are dielectric layers made of a resin such as a glass epoxy resin or a ceramic. A semiconductor chip 60, and capacitive components 55a and 55b are mounted on the base 53. A frame 54 is provided on the base 53 so as to surround the semiconductor chip 60, the capacitive components 55a and 55b. The lid is joined to the upper surface of the frame 54 by an insulating adhesive such as a resin. The frame 54 and the lid seal the semiconductor chip 60 in a void.
[0064] The planar shape of the frame 54 is substantially rectangular. A lead 58 (input lead) is provided on one side in the Y direction of the frame 54. A lead 59 (output lead) is provided on the + side in the Y direction of the frame 54. The leads 58 and 59 are metal layers or metal plates such as copper. A high-frequency signal is input to the lead 58, and a high-frequency signal is output from the lead 59. The leads 58, the capacitive components 55a, 55b, the semiconductor chip 60, and the lead 59 are arranged in the Y direction.
[0065] The semiconductor chip 60 includes a substrate 10, a gate pad 34 and a drain pad 36 provided on the upper surface of the substrate 10, and a metal layer 28 (see FIGS. 4 to 7) provided on the back surface of the substrate 10. The semiconductor chip 60 is the semiconductor device 100 to 105 of Example 1 and its modified examples. The capacitive components 55a and 55b include a dielectric substrate 56, an electrode 57 provided on the upper surface of the dielectric substrate 56, and an electrode provided on the lower surface of the dielectric substrate 56. The electrode 57 and the lower electrode sandwiching the dielectric substrate 56 form a capacitor. The dielectric substrate 56 is, for example, an alumina substrate or a barium titanate substrate. The electrode 57 is a metal layer such as a gold layer, for example.
[0066] The bonding wire 71 electrically connects the lead 58 and the electrode 57 of the capacitive component 55a. The bonding wire 72 electrically connects the electrode 57 of the capacitive component 55a and the electrode 57 of the capacitive component 55b. The bonding wire 73 electrically connects the electrode 57 of the capacitive component 55b and the gate pad 34. The bonding wire 74 electrically connects the drain pad 36 and the lead 59.
[0067] As shown in FIG. 16, the source S of the FET Q1 is grounded, the gate G is electrically connected to the lead 58 via the matching circuit 62, and the drain D is electrically connected to the lead 59. Inductors L1 to L3 are connected in series between the lead 58 and the gate G. A capacitor C1 is shunt-connected to the node between the inductors L1 and L2, and a capacitor C2 is shunt-connected between the inductors L2 and L3. The inductors L1 to L3, the capacitors C1 and C2 function as the matching circuit 62. An inductor L4 is connected between the drain D and the lead 59.
[0068] The high-frequency signal input to the lead 58 is input to the gate G via the matching circuit 62. The matching circuit 62 matches the impedance between the lead 58 and the gate G. The FET Q1 amplifies the high-frequency signal input to the gate G and outputs the amplified high-frequency signal to the lead 59 via the inductor L4.
[0069] Inductors L1 to L4 respectively correspond to bonding wires 71 to 74, and capacitors C1 and C2 respectively correspond to capacitive components 55a and 55b.
[0070] In Embodiment 2, bonding wire 73 (the first bonding wire) is connected to gate pad 34 and extends in the - direction (the second direction) in the Y direction. Bonding wire 74 (the second bonding wire) is connected to drain pad 36 and extends in the + direction (the direction opposite to the second direction) in the Y direction. As a result, as shown in FIGS. 1 and 2, a high-frequency signal is input to gate pad 34 between FET groups 30a and 30b, so that the high-frequency signal is input equally to FET groups 30a and 30b. In particular, when matching circuit 62 also processes harmonic signals, the wavelength of the harmonic signal is shorter than that of the fundamental wave. For this reason, as shown in FIG. 8 of Comparative Example 1, if gate electrode 14 is long in the Y direction, it may not be possible to process harmonics uniformly. In Embodiment 2, since matching circuit 62 is connected to gate pad 34 between FET groups 30a and 30b, harmonic processing can be made more uniform.
[0071] [Modification Example 1 of Embodiment 2] FIG. 17 is a plan view of a semiconductor device according to Modification Example 1 of Embodiment 2. FIG. 18 is an equivalent circuit diagram of FIG. 17. As shown in FIG. 17, in semiconductor device 107 of Modification Example 1 of Embodiment 2, a capacitive component 55c is mounted on base 53 between capacitive component 55a and semiconductor chip 60a. Semiconductor chip 60a is the semiconductor device 103 of Modification Example 3 of Embodiment 1. Gate pads 34, 35 and drain pad 36 are provided on substrate 10. Bonding wire 72a electrically connects electrode 57 of capacitive component 55a and gate pad 35. Bonding wire 75 electrically connects electrode 57 of capacitive component 55c and gate pad 34. Other configurations are the same as those in FIG. 15 of Embodiment 2.
[0072] As shown in FIG. 18, inductors L1 and L2a are connected in series between lead 58 and gate G. An inductor L5 and a capacitor C3 are connected in series between a node between inductor L2a and gate G and ground. Inductors L1, L2a, and capacitor C1 function as matching circuit 62. Inductor L5 and capacitor C3 function as harmonic processing circuit 63. Harmonic processing circuit 63 has a function of suppressing the second harmonic or the third harmonic. For example, the resonance frequency of the series resonance circuit of inductor L5 and capacitor C3 is set to the frequency of the harmonic. Thereby, among the harmonic signals input to gate G, the harmonic signals flow to ground, and the harmonics can be suppressed. Other configurations are the same as those in FIG. 16 of the second embodiment.
[0073] [Comparative Example 3] FIG. 19 is a plan view of the semiconductor device according to Comparative Example 3. As shown in FIG. 19, in the semiconductor device 114 of Comparative Example 3, the semiconductor chip 60b is the semiconductor device 110 of Comparative Example 1. A gate pad 34 is not provided on the substrate 10, and a gate pad 35 is provided. The bonding wire 75 is connected to the gate pad 35. Other configurations are the same as those in FIG. 17.
[0074] The equivalent circuit of Comparative Example 3 is the same as that in FIG. 18. Since bonding wires 72a and 75 are connected to the same gate pad 35, different signals may interfere with each other, such as the signal of the fundamental wave matching circuit 62 and the signal of the harmonic processing circuit 63.
[0075] In Modification 1 of Example 2, the bonding wire 75 is connected to the gate pad 34, and the bonding wire 72a (third bonding wire) is connected to the gate pad 35. Thereby, interference between different signals, such as the signal of the fundamental wave matching circuit 62 and the signal of the harmonic processing circuit 63, can be suppressed. The capacitor C3 (first capacitor) has its first end electrically connected to the base 53, and the bonding wire 75 is connected to its second end. The capacitor C1 (second capacitor) has its first end electrically connected to the base 53, and the bonding wire 72a is connected to its second end. Thereby, the harmonic processing circuit 63 including the capacitor C3 and the bonding wire 75 can be formed, and the matching circuit 62 including the capacitor C1 and the bonding wire 72a can be formed. By connecting the harmonic processing circuit 63 to the gate pad 34, harmonics can be processed uniformly.
[0076] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.
Explanation of Reference Numerals
[0077] 10, 10a Substrate 10b Semiconductor layer 11a (first active region), 11b (second active region) Active region 12a (first source electrode), 12b (second source electrode) Source electrode 13a (first part, fourth part), 13b (second part, fifth part), 13c (third part, sixth part) Source part 13 Inactive region 14, 14a (first gate electrode), 14b (second gate electrode) Gate electrode 15a, 15b, 15c, 15d Gate part 16a (first drain electrode), 16b (second drain electrode) Drain electrode 17a, 17b, 17c, 17d Drain part 18, 18a (First gate wiring), 18b (Second gate wiring), 19, 19a, 19b gate wiring 20a, 20b via hole 21a, 21b, 21c active part 22, 22a, 22b source wiring 23a, 23b, 23c wiring part 25 insulating layer 26 drain wiring 26a, 26b, 26c part 27a gate metal layer 27b wiring layer 28, 28a metal layer 30a (First FET group), 30b (Second FET group), 30c, 30d FET group 31, 31a, 31b, 31c, 31d FET 34 (First gate pad), 35 (Second gate pad) gate pad 36 drain pad 42a, 42b source pad 43a, 43b connection wiring 44a, 44b guard ring 50 main surface 51 back surface 52 package 53 base 54 frame 55a, 55b, 55c capacitive component 56 dielectric substrate 57 electrode 58, 59 lead 60, 60a, 60b semiconductor chip 62 integrated circuit 63 harmonic processing circuit 71, 72, 72a (Third bonding wire), 73 (First bonding wire), 74 (Second bonding wire), 75 (First bonding wire) bonding wire 100, 101, 102, 103, 104, 105, 106, 107, 110, 112, 114 semiconductor device
Claims
1. A substrate having a front surface and a back surface opposite to the front surface, a first FET group provided on the front surface, comprising a plurality of first source electrodes, a plurality of first drain electrodes, and a plurality of first gate electrodes arranged in a first direction; a second FET group provided on the front surface, overlapping the first FET group when viewed from a second direction intersecting the first direction, and comprising a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes; a plurality of first gate pads provided on the front surface between the first FET group and the second FET group and electrically connected to the plurality of first gate electrodes and the plurality of second gate electrodes; a plurality of drain wirings provided on the front surface alternately with the plurality of first gate pads between the first FET group and the second FET group, and electrically connecting the plurality of first drain electrodes and the plurality of second drain electrodes respectively; a drain pad electrically connected to the plurality of first drain electrodes and sandwiching the first FET group with the plurality of first gate pads; A semiconductor device comprising the above.
2. The semiconductor device according to claim 1, further comprising a back surface metal layer provided on the back surface and electrically connected to the plurality of first source electrodes through a plurality of first via holes respectively overlapping the plurality of first source electrodes when viewed from the thickness direction of the substrate, and electrically connected to the plurality of second source electrodes through a plurality of second via holes respectively overlapping the plurality of second source electrodes when viewed from the thickness direction of the substrate.
3. The semiconductor device according to claim 1 or claim 2, wherein the first FET group and the second FET group are respectively provided in a first active region and a second active region where the front surface is activated, and the plurality of first gate pads are provided in an inactive region provided between the first active region and the second active region where the front surface is inactivated.
4. The semiconductor device according to claim 1 or claim 2, wherein the width of the plurality of drain wirings in the first direction between the first FET group and the second FET group is smaller than the width of the plurality of first drain electrodes in the first direction and the width of the plurality of second drain electrodes in the first direction.
5. The semiconductor device according to claim 1 or claim 2, comprising a second gate pad provided on the main surface with the second FET group sandwiched between the plurality of first gate pads and being electrically connected to the plurality of second gate electrodes.
6. Each of the plurality of first source electrodes includes a first portion, and a second portion and a third portion that are provided between the first portion and a first gate pad that overlaps the first portion when viewed from the second direction and corresponds to the first portion, and are arranged in the first direction. The first FET group is provided between the second portion and the third portion, and includes a plurality of first gate wirings that electrically connect the corresponding first gate electrode and the corresponding first gate pad. The semiconductor device according to claim 1 or claim 2.
7. Each of the plurality of second source electrodes includes a fourth portion, and a fifth portion and a sixth portion that are provided between the fourth portion and a second gate pad that overlaps the fourth portion when viewed from the second direction and corresponds to the fourth portion, and are arranged in the first direction. The second FET group is provided between the fifth portion and the sixth portion, and includes a plurality of second gate wirings that electrically connect the corresponding second gate electrode and the corresponding second gate pad. The semiconductor device according to claim 6.
8. The semiconductor device according to claim 1 or claim 2, comprising a guard ring that is electrically connected to the plurality of first source electrodes and the plurality of second source electrodes on the main surface and surrounds the first FET group and the second FET group.
9. A base, A semiconductor chip having the substrate, mounted on the base, A first bonding wire connected to the first gate pad and extending in the second direction, A second bonding wire connected to the drain pad and extending in the direction opposite to the second direction, The semiconductor device according to claim 1 or claim 2, comprising.
10. A base, A semiconductor chip having the substrate, mounted on the base, A first bonding wire connected to the first gate pad and extending in the second direction, A second bonding wire connected to the drain pad and extending in the direction opposite to the second direction, A third bonding wire connected to the second gate pad and extending in the second direction, The semiconductor device according to claim 5, comprising.
11. A first capacitor mounted on the base, having a first end electrically connected to the base and a second end to which the first bonding wire is connected; A second capacitor mounted on the base, having a first end electrically connected to the base and a second end to which the third bonding wire is connected; The semiconductor device according to claim 10, comprising:
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