Image sensor

Abstract

To provide an image sensor corresponding to pixel downsizing and having improved noise 20.SOLUTION: An image sensor EX1 includes: a top layer 200 on which a transfer transistor for transferring an electric signal generated by a photo diode consisting a pixel is disposed; a first intermediate layer 300 on which a plurality of sampling transistors connected to a plurality of capacitors connected through a first node connected to the transfer transistor and for switching the capacitors, are disposed, and which is bonded to the top layer on a lower part of the top layer; a second intermediate layer 400 on which a source follower connected through a second output node connected to the sampling transistor is disposed, and which is bonded to the first intermediate layer at a lower part of the first intermediate layer; and a bottom layer 500 on which an ADC circuit to which a pixel signal output through the source follower is inputted and processed is disposed, and which is bonded to the second intermediate layer at a lower part of the second intermediate layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor capable of improving noise while dealing with miniaturization of pixels. [Background technology]

[0002] Image sensors, which capture images and convert them into electrical signals, are used not only in consumer electronic devices such as digital cameras, cameras for mobile phones, and portable camcorders, but also in cameras mounted on automobiles, security devices, and robots. As pixels in image sensors become smaller and smaller, it is necessary to improve noise caused by smaller pixels. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the above-mentioned problems in the conventional technology, and an object of the present invention is to provide an image sensor capable of dealing with pixel miniaturization and improving noise. [Means for solving the problem]

[0004] In order to achieve the above object, an image sensor according to one embodiment of the present invention includes a photodiode constituting a pixel, and includes a top layer in which a transmission transistor for transmitting an electrical signal generated by the photodiode is arranged, a plurality of capacitors connected via a first output node connected to the transmission transistor, and a plurality of sampling transistors connected to the capacitors for switching the capacitors are arranged, a first intermediate layer bonded to the top layer below the top layer, a source follower connected via a second output node connected to the sampling transistor is arranged, a second intermediate layer bonded to the first intermediate layer below the first intermediate layer, and an ADC circuit in which a pixel signal output via the source follower is input and processed is arranged, and a bottom layer bonded to the second intermediate layer below the second intermediate layer.

[0005] According to another aspect of the present invention, an image sensor that achieves the above object includes a top layer including a photodiode constituting a pixel, and in which a transfer transistor for transferring an electrical signal generated by the photodiode is disposed; a first intermediate layer bonded to the top layer below the top layer, in which a source follower connected via a floating diffusion node connected to the transfer transistor is disposed; a second intermediate layer bonded to the first intermediate layer below the first intermediate layer, in which a plurality of capacitors connected via a floating diffusion node connected to the transfer transistor and a plurality of conversion efficiency switching transistors connected to the capacitors for switching the capacitors are disposed; and a bottom layer bonded to the second intermediate layer below the second intermediate layer, in which an ADC circuit is disposed to receive and process the pixel signal output via the source follower.

[0006] According to another aspect of the present invention, an image sensor that achieves the above object includes a top layer including a photodiode constituting a pixel, and in which a transmission transistor for transmitting an electrical signal generated by the photodiode is arranged, a first intermediate layer bonded to the top layer below the top layer, in which an ADC circuit connected to the transmission transistor and processing the electrical signal is arranged, a second intermediate layer bonded to the first intermediate layer below the first intermediate layer, in which a plurality of capacitors connected via floating diffusion nodes connected to the transmission transistors and a plurality of conversion efficiency switching transistors connected to the capacitors and switching the capacitors are arranged, and a bottom layer bonded to the second intermediate layer below the second intermediate layer, in which an additional transistor for driving the pixel is arranged.

[0007] According to another aspect of the present invention, an image sensor includes a photodiode constituting a pixel, the image sensor including a top layer having a transfer transistor for transferring an electrical signal generated by the photodiode, a source follower connected via a first output node connected to the transfer transistor, a first intermediate layer bonded to the top layer below the top layer, a plurality of capacitors connected to the source followers, and a plurality of sampling transistors connected to the capacitors for switching the capacitors, a second intermediate layer bonded to the first intermediate layer below the first intermediate layer, and a bottom layer bonded to the second intermediate layer below the second intermediate layer, the bottom layer having an ADC circuit for receiving and processing the pixel signal outputted via the source follower.

[0008] According to yet another aspect of the present invention, an image sensor that achieves the above object includes a photodiode constituting a pixel, and includes a top layer in which a transmission transistor for transmitting an electrical signal generated by the photodiode is arranged, a plurality of capacitors connected via a floating diffusion node connected to the transmission transistor, and a plurality of conversion efficiency switching transistors connected to the capacitors for switching the capacitors are arranged, and the top layer is bonded to the first intermediate layer below the top layer, a second intermediate layer bonded to the first intermediate layer below the first intermediate layer, and an ADC circuit connected to the transmission transistor for processing the electrical signal is arranged, and a bottom layer bonded to the second intermediate layer below the second intermediate layer, in which an additional transistor for driving the pixel is arranged. Effect of the Invention

[0009] In the image sensor according to the present invention, the top layer, the first intermediate layer, the second intermediate layer, and the bottom layer can be bonded to bonding pads or bonding through vias, and the components of the pixel circuit can be arranged separately on the top layer, the first intermediate layer, the second intermediate layer, and the bottom layer. By configuring in this way, the image sensor according to the present invention can respond to miniaturization of pixels and improve noise. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an image sensor according to an embodiment of the present invention; [Figure 2A] 4A to 4C are diagrams illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 2B] 4A to 4C are diagrams illustrating the operation of an image sensor according to an embodiment of the present invention. [Diagram 3] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 4] 1 is a circuit diagram of an image sensor according to an embodiment of the present invention. [Diagram 5] 1 is a circuit diagram of an image sensor according to an embodiment of the present invention. [Figure 6] 1 is a circuit diagram of an image sensor according to an embodiment of the present invention. [Figure 7] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 8] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 9] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 10] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 11] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 12] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 13] 1 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 14] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 15] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 16] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 17] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 18] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 19] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 20]4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 21] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 22] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 23] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Figure 24] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. [Diagram 25] 4A to 4C are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments of the present invention may be embodied by any one of them, and may be embodied by combining one or more of the following embodiments. Therefore, the technical idea of ​​the present invention should not be interpreted as being limited to one embodiment.

[0012] In this specification, the singular expression of an element may include the plural form unless the context clearly indicates otherwise. In this specification, the drawings are illustrated in an exaggerated manner in order to more clearly explain the present invention. In this specification, the order of first, second, etc. is for convenience of explanation, and the present invention is not limited thereto.

[0013] FIG. 1 is a block diagram showing an image sensor according to an embodiment of the present invention.

[0014] Specifically, the image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130, a counting code generator 140, an analog-to-digital conversion circuit 150 (hereinafter referred to as an ADC circuit), a data output circuit 180, and a timing controller 190. The image sensor 100 further includes a signal processing unit 195. A configuration including the ADC circuit 150 and the data output circuit 180 is referred to as a readout circuit.

[0015] The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix. The plurality of pixels PX are active pixel sensors (APS).

[0016] Each of the pixels PX includes at least one photoelectric conversion element, and each pixel PX senses light using the photoelectric conversion element and outputs an image signal, which is an electrical signal based on the sensed light. For example, the photoelectric conversion element includes a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0017] Each of the pixels PX can sense light in a specific spectral region. For example, the pixels PX may include a red pixel for converting light in a red spectral region into an electrical signal, a green pixel for converting light in a green spectral region into an electrical signal, and a blue pixel for converting light in a blue spectral region into an electrical signal. However, the pixels may further include a white pixel.

[0018] As another example, the pixels may include pixels combined with other color configurations, for example, a yellow pixel, a cyan pixel, and a magenta pixel. A color filter array for transmitting light in a specific spectral region is disposed on the upper part of the pixels PX, and the hue sensed by each of the pixels is determined by the color filter disposed on the upper part of each of the pixels. However, the present invention is not limited thereto. In some embodiments, a specific photoelectric conversion element converts light in a specific wavelength band into an electrical signal according to the level of an electrical signal applied to the photoelectric conversion element.

[0019] In some embodiments, each of the pixels PX has a dual conversion gain. The dual conversion gain includes a low conversion gain and a high conversion gain. Here, the conversion gain refers to a ratio at which charges accumulated in a floating diffusion node (or a floating diffusion region) are converted into a voltage. Charges generated in a photoelectric conversion element are transferred to and accumulated in a floating diffusion node FD, and the charges accumulated in the floating diffusion node FD are converted into a voltage by the conversion gain. At this time, the conversion gain is varied according to the capacitance of the floating diffusion node FD, and if the capacitance increases, the conversion gain decreases, and if the capacitance decreases, the conversion gain increases.

[0020] The row driver 120 drives the pixel array 110 in units of rows. The row driver 120 decodes a row control signal (e.g., an address signal) received from the timing controller 190, and selects at least one of the row lines constituting the pixel array 110 in response to the decoded row control signal.

[0021] For example, the row driver 120 generates a selection signal to select one of a plurality of rows. Then, the pixel array 110 outputs a pixel signal, for example, a pixel voltage, from a row selected by the selection signal provided by the row driver 120. The pixel signal includes a reset signal and an image signal. The row driver 120 transmits a control signal for outputting the pixel signal to the pixel array 110, and the pixel PX operates in response to the control signal to output the pixel signal.

[0022] The ramp signal generator 130 generates a ramp signal (e.g., a ramp voltage) whose level rises or falls at a predetermined slope under the control of the timing controller 190. The ramp signal RAMP is provided to each of a plurality of CDS (Correlated Double Sampling) circuits 160 included in the ADC circuit 150.

[0023] The counting code generator 140 generates a counting code CCD under the control of the timing controller 190. The counting code CCD is provided to each of the plurality of counter circuits 170. In some embodiments, the counting code generator 140 is embodied as a Gray code generator. The counting code generator 140 generates a plurality of code values ​​having a resolution according to a set number of bits as the counting code CCD. For example, when a 10-bit code is set, the counting code generator 140 generates a counting code CCD including 1024 code values ​​that sequentially increase or decrease.

[0024] The ADC circuit 150 includes a plurality of CDS circuits 160 (Correlated Double Sampling circuits) and a plurality of counter circuits 170. The ADC circuit 150 converts pixel signals (e.g., pixel voltages) input from the pixel array 110 into pixel values, which are digital signals. Each pixel signal received through each of the plurality of column lines CL is converted by the CDS circuit 160 and the counter circuit 170 into a pixel value, which is a digital signal.

[0025] The CDS circuit 160 compares a pixel signal, e.g., a pixel voltage, received through a column line CL with a ramp signal RAMP and outputs a comparison result as a comparison result signal. When the level of the ramp signal RAMP is the same as the level of the pixel signal, the CDS circuit 160 outputs a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low). The point in time at which the level of the comparison signal transitions is determined by the level of the pixel signal.

[0026] The CDS circuit 160 samples a pixel signal provided from the pixel PX by a correlated double sampling (CDS) method. The CDS circuit 160 samples a reset signal received as a pixel signal, compares the reset signal with a ramp signal RAMP, and generates a comparison signal according to the reset signal. The CDS circuit then samples an image signal correlated with the reset signal, and compares the image signal with the ramp signal RAMP to generate a comparison signal according to the image signal.

[0027] The counter circuit 170 counts the time points of level transition of the comparison result signal output from the CDS circuit 160, and outputs a count value. In some embodiments, the counter circuit 170 includes a latch circuit and an arithmetic circuit. The latch circuit receives the counting code CCD from the counting code generator 140 and the comparison signal from the CDS circuit 160, and latches the code value of the counting code CCD at the time points of the level transition of the comparison signal.

[0028] The latch circuit latches a code value corresponding to the reset signal, e.g., a reset value, and a code value corresponding to the image signal, e.g., an image signal value. The calculation circuit calculates the reset value and the image signal value to generate an image signal value from which the reset level of the pixel PX has been removed. The counter circuit 170 outputs the image signal value from which the reset level has been removed as a pixel value.

[0029] In this embodiment, the image sensor 100 includes a counting code generator 140, and the counter circuit 170 includes a circuit for latching the code value of the counting code CCD received from the counting code generator 140, but the present invention is not limited to this.

[0030] In some embodiments, the image sensor 100 does not include a separate counting code generator 140, and the counter circuit 170 may be embodied as an up counter and an arithmetic circuit in which the count value is sequentially increased based on a counting clock signal provided from the timing controller 190, or an up / down counter, or a bit-wise inversion counter.

[0031] The data output circuit 180 temporarily stores and then outputs the pixel values ​​output from the ADC circuit 150. The data output circuit 180 includes a plurality of column memories 181 and a column decoder 182. The column memory 181 stores the pixel values ​​received from the counter circuit 170. In some embodiments, each of the plurality of column memories 181 is included in the counter circuit 170. The plurality of pixel values ​​stored in the plurality of column memories 181 are output as image data IDT under the control of the column memory 181.

[0032] The timing controller 190 outputs control signals to each of the row driver 120, the ramp signal generator 130, the counting code generator 140, the ADC circuit 150, and the data output circuit 180, and controls the operation or timing of the row driver 120, the ramp signal generator 130, the counting code generator 140, the ADC circuit 150, and the data output circuit 180.

[0033] The signal processor 195 performs processes such as noise reduction, gain adjustment, waveform shaping, interpolation, white balance, gamma correction, edge enhancement, binning, etc. on the image data. In some embodiments, the signal processor 195 is included in a processor external to the image sensor 100.

[0034] 2A and 2B are diagrams illustrating the operation of an image sensor according to an embodiment of the present invention.

[0035] Specifically, FIGS. 2A and 2B are timing diagrams illustrating the operation of a global shutter mode (or scheme) and a rolling shutter mode (or scheme).

[0036] 1 and 2A, the image sensor 100 operates in a global shutter mode. One frame period FP includes a first period P1 and a second period P2.

[0037] In the first period P1, a plurality of pixels PX of the pixel array 110, i.e., a plurality of rows (e.g., the first row R1 to the nth row Rn) of the pixel array 110 simultaneously perform a reset operation, an exposure (storage) operation, and a global signal dumping operation. In the second period P2, a plurality of rows of the pixel array 110 sequentially perform a read (read-out) operation. The second period P2 is also referred to as a frame read-out period.

[0038] The first period P1 includes a reset period, an integration period, and a global signal dumping period GSDP. The pixels PX perform a reset operation to remove charges accumulated in the photodiodes (and floating diffusion nodes) during the reset period, perform an integration operation to generate and accumulate photocharges corresponding to the optical signals received by the photodiodes during the integration period, and store a reset signal according to a reset level of the floating diffusion node and an image signal corresponding to the photocharges accumulated in the photodiodes in at least two capacitors provided therein during the global signal dumping period GSDP.

[0039] In the second period P2, a rolling readout operation is performed in which the readout operations performed during the readout period are performed sequentially by row. For example, after the readout operation is performed for the first row R1 of the pixel array 110, the readout operation is performed for the next row R2. Then, after the readout operation is performed for the second row R2, the readout operation is performed for the next row R3. During the readout operation, the reset signal and the image signal stored in at least two capacitors during the global signal dumping period GSDP are output from each pixel PX as a pixel signal.

[0040] 1 and 2B, the image sensor 100 operates in a rolling shutter mode, in which a plurality of rows (e.g., a first row R1 through an n-th row Rn) of the pixel array 100 sequentially perform a reset operation, an exposure (accumulation) operation, and a read-out operation during one frame period FP.

[0041] The pixels PX of one row perform a reset operation during the reset period, perform an accumulation operation during the accumulation period, and output a reset signal (e.g., reset voltage) corresponding to the reset level of the floating diffusion node and an image signal (e.g., image voltage) corresponding to the photocharge generated in the photodiode as a pixel signal during the readout period. The readout periods of the plurality of rows of the pixel array 110 do not overlap. After the readout period, the pixels PX of one row perform a reset operation again after the wait period. In the embodiment, the wait period is set so that the readout period in the next frame period of at least one row (e.g., the first row R1, the second row R2, etc.) that is read out early in the frame period FP does not overlap with the readout period in the current frame period of at least one other row (e.g., the n-1th row Rn-1, the nth row Rn, etc.) that is read out late in the frame period FP. As described above, the image sensor 100 according to the present invention selectively operates in a global shutter mode or a rolling shutter mode.

[0042] FIG. 3 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0043] Specifically, the image sensor EX1 is an embodiment that embodies the image sensor 100 of Fig. 1. The image sensor EX1 includes the pixel PX of Fig. 1. The image sensor EX1 includes a top layer 200, a first middle layer 300, a second middle layer 400, and a bottom layer 500.

[0044] The image sensor EX1 has a bottom layer 500 on which a second intermediate layer 400, a first intermediate layer 300, and a top layer 200 are stacked. The image sensor EX1 is made up of four layers, with the second intermediate layer 400, the first intermediate layer 300, and the top layer 200 stacked on the bottom layer 500. The image sensor EX1 is made up of four layers, with the bottom layer 500, the second intermediate layer 400, the first intermediate layer 300, and the top layer 200 bonded together.

[0045] The transistors described below include planar transistors, multi bridge channel (MBC) transistors, gate all around (GAA) transistors, or field effect transistors (FinFET).

[0046] The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel isolation layer 215, a color filter 217, and a lens 219.

[0047] The first substrate 201 is a silicon substrate. The first substrate 201 includes a first front surface 201f and a first rear surface 201b facing the first front surface 201f. A photodiode is disposed on the first substrate 201. In some embodiments, one photodiode is disposed corresponding to one color filter 217 and lens 219. In some embodiments, a plurality of photodiodes, for example, two or four photodiodes, may be disposed corresponding to one color filter 217 and lens 219.

[0048] A first transistor 203 is formed on the first front surface 201f. In Fig. 3, a first source and drain region constituting the first transistor 203 is formed in the first substrate 201, but is omitted for convenience.

[0049] A first contact plug 207 and a first wiring layer 205 are connected to the first transistor 203. The first contact plug 207 is made of a metal layer, for example, a tungsten layer. The first wiring layer 205 is connected to a first via plug 211. The first contact plug 207 and the first wiring layer 205 are connected to a first front bonding pad 209. The first wiring layer 205, the first front bonding pad 209, and the first via plug 211 are made of a metal layer, for example, a copper layer.

[0050] The first intermediate layer 300 includes a second substrate 301 , a plurality of second transistors 305 , a second back-side bonding through via 307 , a second wiring layer 311 , a second contact plug 309 , a second front-side bonding pad 315 , a second via plug 313 , and a second insulating layer 317 .

[0051] The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300. The top layer 200 and the first intermediate layer 300 have an interface FF where the front faces F and F are bonded to each other.

[0052] The second substrate 301 is a silicon substrate. The second substrate 301 includes a second front surface 301f and a second back surface 301b facing the second front surface 301f. A second transistor 305 is formed on the second front surface 301f. In FIG. 3, second source and drain regions constituting the second transistor 305 are formed in the second substrate 301, but are omitted for convenience.

[0053] A through via hole 303 penetrating the second front surface 301f and the second back surface 301b is formed in the second substrate 301. In the through via hole 303, a second back surface bonding through via 307 insulated by a second insulating layer 317 is formed.

[0054] A second contact plug 309 and a second wiring layer 311 are connected to the second transistor 305. The second contact plug 309 is made of a metal layer, for example, a tungsten layer. The second contact plug 309 and the second wiring layer 311 are connected to the second front bonding pad 315 and the second back bonding through via 307. The second back bonding through via 307, the second wiring layer 311, the second front bonding pad 315, and the second via plug 313 are made of a metal layer, for example, a copper layer.

[0055] The second intermediate layer 400 includes a third substrate 401, a plurality of third transistors 409, a third through via 405, a third back surface bonding pad 407, a third wiring layer 411, a third contact plug 413, a third front surface bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0056] The second back surface bonding through via 307 constituting the first intermediate layer 300 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400. The second insulating layer 317 and the second substrate 301 constituting the first intermediate layer 300 are bonded to the third insulating layer 417 constituting the second intermediate layer 400. The first intermediate layer 300 and the second intermediate layer 400 have an interface BF where the back surface B and the front surface F are bonded.

[0057] The third substrate 401 is a silicon substrate. In FIG. 3, the third substrate 401 is illustrated as a silicon substrate, but in some embodiments, the third substrate 401 is a silicon on insulator (SOI) substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. In FIG. 3, third source and drain regions constituting the third transistor 409 are formed in the third substrate 401, but are omitted here for convenience.

[0058] A through via hole 403 penetrating a part of the third front surface 401f and the third rear surface 401b is formed in the third substrate 401. A third through via 405 insulated by a third insulating layer 417 is formed in the through via hole 403. The third through via 405 is connected to a third rear surface bonding pad 407 via a third via plug 414.

[0059] The third transistor 409 is connected to a third contact plug 413 and a third wiring layer 411. The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to a third front bonding pad 415 and a third back bonding pad 407. The third back bonding pad 407, the third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0060] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0061] The third back bonding pad 407 constituting the second intermediate layer 400 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400 are bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0062] The fourth substrate 501 is a silicon substrate. The fourth substrate 501 includes a fourth front surface 501f and a fourth back surface 401b facing the fourth front surface 501f. A fourth transistor 502 is formed on the fourth front surface 501f. In FIG. 3, a fourth source and drain region constituting the fourth transistor 502 is formed in the fourth substrate 501, but is omitted here for convenience.

[0063] A fourth contact plug 505 and a fourth wiring layer 503 are connected to the fourth transistor 502. The fourth contact plug 505 is made of a metal layer, for example, a tungsten layer. The fourth wiring layer 503 is connected to a fourth front bonding pad 507 through a fourth via plug 506. The fourth contact plug 505 and the fourth wiring layer 503 are connected to the fourth front bonding pad 507. The fourth front bonding pad 507, the fourth wiring layer 503, and the fourth via plug 506 are made of a metal layer, for example, a copper layer.

[0064] In the image sensor EX1, a first front bonding pad 209 constituting the top layer 200 and a second front bonding pad 315 constituting the first intermediate layer 300 are bonded together, and the top layer 200 and the first intermediate layer 300 have an interface FF at which the front faces F and F are bonded together.

[0065] In the image sensor EX1, the second back surface bonding through via 307 constituting the first intermediate layer 300 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400. The first intermediate layer 300 and the second intermediate layer 400 have an interface BF where the back surface B and the front surface F are bonded.

[0066] In the image sensor EX1, the third back surface bonding pad 407 constituting the second intermediate layer 400 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0067] As described above, the image sensor EX1 may bond the top layer 200, the first intermediate layer 300, the second intermediate layer 400, and the bottom layer 500 with bonding pads or bonding through vias, and may separately arrange components of a pixel circuit on the top layer 200, the first intermediate layer 300, the second intermediate layer 400, and the bottom layer 500. When configured in this manner, the image sensor EX1 may accommodate miniaturization of pixels and improve noise.

[0068] FIG. 4 is a circuit diagram of an image sensor according to an embodiment of the present invention.

[0069] Specifically, Fig. 4 is a schematic circuit diagram of a pixel PX of the image sensor 100 of Fig. 1. Fig. 4 is a schematic circuit diagram of a pixel PX that implements the operation of the global shutter mode (or method) of the image sensor 100 described in Figs. 1 and 2A. Fig. 4 is a schematic circuit diagram of a pixel PX of the image sensor EX1 of Fig. 3.

[0070] The pixel PX includes a photodiode PD and a pixel circuit PSCa that generates a pixel signal PXS. In FIG. 4, for convenience, one photodiode PD and one transmission transistor TX are illustrated as being connected to a floating diffusion node FD in the pixel circuit PSCa, but a plurality of photodiodes, for example, two or four photodiodes, and transmission transistors connected to the two or four photodiodes, may be connected to the floating diffusion node in the pixel circuit PSCa.

[0071] Control signals TS, RS, CGS, PSEL1, PSEL2, PC, SPS1, SPS2, and SEL are applied to the pixel circuit PSCa, and at least some of the control signals are generated by the row driver 120. The photodiode PD generates photocharges that vary depending on the light intensity. For example, the photodiode PD generates charges, i.e., electrons which are negative charges and holes which are positive charges, in proportion to the amount of incident light.

[0072] The pixel circuit PSCa includes a plurality of transistors TX, RX, DCG, SF1, PSX1, PSX2, PCX, SPX1, SPX2, SF2, SX, a first capacitor C1, and a second capacitor C2. Charges are reset in the first capacitor C1 and the second capacitor C2 by a reset operation, or charges are stored in the first capacitor C1 and the second capacitor C2 by a photocharge storage operation.

[0073] The pixel circuit PSCa includes a transfer transistor TX coupled to a photodiode PD. In some embodiments, the photodiode PD and the transfer transistor TX are disposed on the top layer 200 described above.

[0074] The transmission transistor TX is connected between the photodiode PD and a floating diffusion node FD, with a first terminal of the transmission transistor TX connected to an output terminal of the photodiode PD and a second terminal of the transmission transistor TX connected to the floating diffusion node FD.

[0075] The transmission transistor TX is turned on or off in response to a transmission control signal TS received from the row driver 120, and transmits the photocharges generated in the photodiode PD to the floating diffusion node FD.

[0076] The pixel circuit PSCa includes a reset transistor RX. The reset transistor RX resets the charge stored in the floating diffusion node FD. A first pixel voltage VPX1 (or a power supply voltage) is applied to a first terminal of the reset transistor RX, and a second terminal of the reset transistor RX is connected to the floating diffusion node FD. The reset transistor RX is turned on or off in response to a reset control signal RS received from the row driver 120, and the charge stored in the floating diffusion node FD is discharged to reset the floating diffusion node FD.

[0077] The pixel circuit PSCa includes a conversion gain transistor DCG. The conversion gain transistor DCG changes the capacitance of the floating diffusion node FD in response to a conversion gain signal CGS. When the conversion gain transistor DCG is turned on, the capacitance increases, and the pixel circuit PSCa operates in a low conversion gain mode. Conversely, when the conversion gain transistor DCG is turned off, the capacitance decreases, and the pixel circuit PSCa operates in a high conversion gain mode.

[0078] When the reset transistor RX is turned on by the reset control signal RS and the conversion gain transistor DCG is turned on by the conversion gain signal CGS, the floating diffusion node FD is reset based on the first pixel voltage VPX1, and a reset signal corresponding to the voltage level of the floating diffusion node FD is output.

[0079] The pixel circuit PSCa includes a first source follower SF1. A first terminal of the first source follower SF1 is connected to a second pixel voltage VPX2 (or a power supply voltage), and in some embodiments, the second pixel voltage VPX2 applied to the first source follower SF1 is lower than or equal to the first pixel voltage VPX1. A second terminal of the first source follower SF1 is connected to a first output node N1.

[0080] The first source follower SF1 serves as a buffer amplifier to buffer a signal according to the amount of charge stored in the floating diffusion node FD. The potential of the floating diffusion node FD varies depending on the amount of charge stored in the floating diffusion node FD, and the first source follower SF1 amplifies the potential change at the floating diffusion node FD and outputs it to the first output node N1.

[0081] The pixel circuit PSCa includes a first pre-charge selection transistor PSX1 for resetting the first output node N1. For example, the pixel circuit PSCa includes a first pre-charge selection transistor PSX1. A first terminal of the first pre-charge selection transistor PSX1 is coupled to the first output node N1 via the pre-charge transistor PCX, and a second terminal of the first pre-charge selection transistor PSX1 is coupled to the ground voltage.

[0082] The first pre-charge selection transistor PSX1 is turned on or off in response to a first pre-charge selection control signal PSEL1 received from the row driver 120, and resets the first output node N1 through the pre-charge transistor PCX. In some embodiments, the pixel circuit PSCa may include a plurality of pre-charge selection transistors for resetting the first output node N1.

[0083] For example, the pixel circuit PSCa further includes a second pre-charge selection transistor PSX2 in addition to the first pre-charge selection transistor PSX1. A first terminal of the second pre-charge selection transistor PSX2 is connected to the output node N1, and a second terminal of the second pre-charge selection transistor PSX2 is connected to the output node N2. The second pre-charge selection transistor PSX2 is turned on or off in response to a second pre-charge selection control signal PSEL2 received from the row driver 120, thereby resetting the first output node N1 and the second output node N2.

[0084] In this embodiment, the pixel PX includes two precharge selection transistors PSX1 and PSX2, but the present invention is not limited thereto. The pixel PX may include various numbers of precharge selection transistors, which are transistors for resetting the first output node N1.

[0085] The pixel circuit PSCa includes a precharge transistor PCX. A first terminal of the precharge transistor PCX is connected to the first output node N1, and a second terminal of the precharge transistor PCX is connected to the first precharge selection transistor PSX1. The precharge transistor PCX operates as a current source in response to a precharge control signal PC received from the row driver 120 to precharge the first output node N1.

[0086] In some embodiments, the reset transistor RX, the conversion gain transistor DCG, the first source follower SF1, the pre-charge transistor PCX, and the first pre-charge select transistor PSX1 are disposed in the first intermediate layer 300 described above.

[0087] The pixel circuit PSCa includes a first sampling transistor SPX1. A first terminal of the first sampling transistor SPX1 is coupled to the second output node N2, and a second terminal of the first sampling transistor SPX1 is coupled to the first capacitor C1. In response to a first sampling control signal SPS1 received from the row driver 120, the first sampling transistor SPX1 may be turned on or off to couple the first capacitor C1 to the second output node N2.

[0088] A first pixel voltage VPX1 is applied to a first terminal of the first capacitor C1, and a second terminal of the first capacitor C1 is connected to the first sampling transistor SPX1. Charge is stored in the first capacitor C1 by a switching operation of the first sampling transistor SPX1. For example, charge is stored in the first capacitor C1 by a reset operation in which the floating diffusion node FD is reset.

[0089] The pixel circuit PSCa includes a second sampling transistor SPX2. A first terminal of the second sampling transistor SPX2 is coupled to a second output node N2, and a second terminal of the second sampling transistor SPX2 is coupled to a second capacitor C2. In response to a second sampling control signal SPS2 received from the row driver 120, the second sampling transistor SPX2 may be turned on or off to couple the second capacitor C2 to the second output node N2.

[0090] A first pixel voltage VPX1 is applied to a first terminal of the second capacitor C2, and a second terminal of the second capacitor C2 is connected to the second sampling transistor SPX2. Charges are stored in the second capacitor C2 by a switching operation of the second sampling transistor SPX2. For example, charges are stored in the second capacitor C2 by a photocharge storage operation in which photocharges generated in the photodiode PD are stored in the floating diffusion node FD.

[0091] The first sampling transistor SPX1 and the second sampling transistor SPX2 are transistors for switching the first capacitor C1 and the second capacitor C2. In some embodiments, the first capacitor C1 and the second capacitor C2 include a metal insulator metal (MIM) capacitor, a metal oxide semiconductor (MOS) capacitor, a trench capacitor, a poly insulator poly (PIP) capacitor, or a three dimensional (3D) capacitor.

[0092] In this embodiment, the first sampling transistor SPX1 and the first capacitor C1, and the second sampling transistor SPX2 and the second capacitor C2 are illustrated as being connected to the second output node N2, but a third sampling transistor and a third capacitor may additionally be connected thereto.

[0093] In some embodiments, the second pre-charge selection transistor PSX2, the first sampling transistor SPX1, the second sampling transistor SPX2, the first capacitor C1, and the second capacitor C2 are disposed in the first intermediate layer 300 or the second intermediate layer 400 described above.

[0094] The pixel circuit PSCa has a parasitic capacitor Cp connected to a second output node N2. The pixel circuit PSCa further includes a second source follower SF2 and a selection transistor SX. A second pixel voltage VPX2 is applied to a first terminal of the second source follower SF2, and a second terminal of the second source follower SF2 is connected to the selection transistor SX. The second source follower SF2 amplifies and outputs a potential change at the second output node N2.

[0095] In some embodiments, the second pixel voltage VPX2 applied to the second source follower SF2 is lower than or equal to the first pixel voltage VPX1. A first terminal of the selection transistor SX is coupled to the second source follower SF2, and a second terminal of the selection transistor SX is coupled to a column line CL. The selection transistor SX is turned on or off in response to a selection control signal SEL received from the row driver 120. When the selection transistor SX is turned on in a readout operation, a pixel signal PXS including a reset signal RST corresponding to a reset operation or an image signal SIG corresponding to a charge accumulation operation is output to the column line CL.

[0096] For example, when the selection transistor SX is operating in an on state, if the first sampling transistor SPX1 is turned on and the second sampling transistor SPX2 is turned off, a reset signal RST corresponding to the charge stored in the first capacitor C1 is output. Also, when the selection transistor SX is operating in an on state, if the second sampling transistor SPX2 is turned on and the first sampling transistor SPX1 is turned off, an image signal SIG corresponding to the charge stored in the second capacitor C2 is output.

[0097] In this embodiment, an additional image signal SIG may be output. Specifically, after the first image signal corresponding to the charge stored in the second capacitor C2 is output in the above-described manner, a second image signal corresponding to the charge stored in the first capacitor C1 and the second capacitor C2 may be further output.

[0098] For example, while the selection transistor SX is operating in an on state, the first sampling transistor SPX1 and the second sampling transistor SPX2 are both operating in an on state, and a second image signal corresponding to the charges stored in the first capacitor C1 and the second capacitor C2 is output. If the first sampling transistor SPX1 and the second sampling transistor SPX2 are both operating in an on state, the first capacitor C1 and the second capacitor C2 are connected in parallel, and the capacitance increases. As a result, the voltage of the second image signal decreases compared to the first image signal due to the reduction in the conversion gain.

[0099] The first and second image signals read out in the above manner are selectively used to generate image data IDT depending on the illumination state. Specifically, the first image signal is used in a low illumination state, and the second image signal is used in a high illumination state.

[0100] In some embodiments, a second selection transistor is further connected to the first output node N1 of the pixel circuit PSCa. In this case, the pixel PX operates in a rolling shutter mode. When the pixel PX operates in the rolling shutter mode, the selection transistor SX is turned off and the second selection transistor is turned on. As a result, the reset signal RST and the image signal SIG are output to the column line CL as the pixel signal PXS via the first output node N1 through the second selection transistor.

[0101] In some embodiments, the second source follower SF2 and the selection transistor SX are arranged in the first intermediate layer 300 or the second intermediate layer 400 described above. In addition, the ADC circuit (150 in FIG. 1) is arranged in the bottom layer 500 described above.

[0102] FIG. 5 is a circuit diagram of an image sensor according to an embodiment of the present invention.

[0103] Specifically, Fig. 5 is a schematic circuit diagram of a pixel PX of the image sensor 100 of Fig. 1. Fig. 5 is a schematic circuit diagram of a pixel PX embodying the rolling shutter mode (or method) operation of the image sensor 100 described in Figs. 1 and 2B. Fig. 5 is a schematic circuit diagram of a pixel PX of the image sensor EX1 of Fig. 3. The pixel PX includes a photodiode PD and a pixel circuit PSCb that generates a pixel signal PXS.

[0104] For convenience, FIG. 5 illustrates one photodiode PD and one transmission transistor TX connected to a floating diffusion node FD in the pixel circuit PSCb. However, a plurality of photodiodes, for example, two or four photodiodes, and transmission transistors connected to the two or four photodiodes, may be connected to the floating diffusion node in the pixel circuit PSCb.

[0105] The pixel circuit PSCb includes a photoelectric conversion unit 51, a transfer transistor TX, a floating diffusion node FD, a first conversion efficiency switching transistor 54, a Metal-Insulator-Metal (MIM) type first capacitor 55, a second conversion efficiency switching transistor 56, a MIM type second capacitor 57, a reset transistor RX, a source follower SF, and a selection transistor SX.

[0106] The photoelectric conversion unit 51 includes a photodiode PD having a PN junction. The photoelectric conversion unit 51 receives incident light, performs photoelectric conversion, and stores electric charges. A transmission transistor TX is provided between the photoelectric conversion unit 51 and a floating diffusion node FD, and a drive signal TS is supplied to a gate electrode of the transmission transistor TX.

[0107] When the driving signal TS becomes high level, the transmission transistor TX is turned on, and the charge stored in the photoelectric conversion unit 51 is transmitted to the floating diffusion node FD through the transmission transistor TX. The floating diffusion node FD is a floating diffusion region and serves as a storage unit that temporarily stores the transmitted charge and the charge overflowing from the photoelectric conversion unit 51. In some embodiments, the photoelectric conversion unit 51 including the photodiode PD and the transmission transistor TX are disposed on the top layer 200 described above.

[0108] The first conversion efficiency switching transistor 54 is provided between the floating diffusion node FD and the first MIM capacitor 55. A power supply voltage MIMVDD is connected to one end of the first MIM capacitor 55. A driving signal FDG1 is supplied to the first conversion efficiency switching transistor 54. The first conversion efficiency switching transistor 54 corresponds to the above-mentioned conversion gain transistor.

[0109] When the first drive signal FDG1 reaches a high level, the first conversion efficiency switching transistor 54 is turned on, and the charge from the floating diffusion node FD is transferred to the MIM type first capacitor 55 via the first conversion efficiency switching transistor 54. The MIM type first capacitor 55 temporarily stores the charge overflowing in the photoelectric conversion unit 51.

[0110] When the first conversion efficiency switching transistor 54 is turned on, the region where the charges are stored becomes the region where the floating diffusion node FD and the first MIM type capacitor 55 are coupled, and the charges generated in the photoelectric conversion unit 51 are converted into a voltage. The first conversion efficiency switching transistor 54 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0111] The second conversion efficiency switching transistor 56 is provided between the first MIM capacitor 55 and the second MIM capacitor 57. One end of the second MIM capacitor 57 is connected to a power supply voltage MIMVDD. A second drive signal FDG2 is supplied to the second conversion efficiency switching transistor 56. If the second drive signal FDG2 is at a high level, the second conversion efficiency switching transistor 56 is turned on, and the charge from the first MIM capacitor 55 is transferred to the second MIM capacitor 57 through the second conversion efficiency switching transistor 56. The second conversion efficiency switching transistor 56 corresponds to the above-mentioned conversion gain transistor.

[0112] When the second conversion efficiency switching transistor 56 is turned on, the region where the charge is stored is the region where the floating diffusion node FD, the first MIM capacitor 55, and the second MIM capacitor 57 are coupled together. The second conversion efficiency switching transistor 56 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0113] The first conversion efficiency switching transistor 54 and the second conversion efficiency switching transistor 56 are transistors for switching the MIM type first capacitor 55 and the MIM type second capacitor 57. In the pixel circuit of this embodiment, the MIM type first capacitor 55 and the MIM type second capacitor 57 are exemplified, but may include a MOS (metal oxide semiconductor) capacitor, a trench capacitor, a PIP (poly insulator poly) capacitor, or a 3D (three dimensional) capacitor.

[0114] In some embodiments, the first conversion efficiency switching transistor 54, the second conversion efficiency switching transistor 56, the MIM type first capacitor 55 and the MIM type second capacitor 57 are disposed on the second intermediate layer 400 described above.

[0115] The MIM type first capacitor 55 and the MIM type second capacitor 57 each realize a high capacitance without sacrificing the area of ​​the surface of a substrate (e.g., a silicon substrate) on which a pixel transistor is arranged, and have a capacitance larger than that of the floating diffusion node FD.

[0116] The reset transistor RX is connected between a power supply VDD and the second MIM capacitor 57, and a drive signal (or control signal) RS is supplied to the reset transistor RX. When the drive signal RS is set to a high level, the reset transistor RX is turned on, and the potential of the second MIM capacitor 57 is reset to the power supply voltage level. In some embodiments, the reset transistor RX is disposed in the first intermediate layer 300 or the second intermediate layer 400 described above.

[0117] The source follower SF is an amplifying transistor. The gate electrode of the source follower SF is connected to the floating diffusion node FD, and the drain is connected to the power supply VDD. The selection transistor SX is connected between the source of the source follower SF and the vertical signal line CL, and a drive signal SEL is supplied to the selection transistor SX.

[0118] When the driving signal SEL is set to a high level, the selection transistor SX is turned on and the pixel is selected. As a result, the pixel signal output from the source follower SF is output to the vertical signal line CL through the selection transistor SX. The pixel signal is output to the ADC circuit (150 in FIG. 1).

[0119] The pixel circuit includes a floating diffusion node FD, a first MIM type capacitor 55, and a second MIM type capacitor 57, and these capacitors are connected in series to enable the conversion efficiency when converting the charge generated in the photoelectric conversion unit 51 into a voltage to be switched between three levels. The high conversion efficiency HCG is formed by the floating diffusion node FD. The medium conversion efficiency MCG is formed by the sum of the floating diffusion node FD and the first MIM type capacitor 55.

[0120] The low conversion efficiency LCG is composed of the sum of the floating diffusion node FD, the first MIM type capacitor 55, and the second MIM type capacitor 57. When the transmission transistor TX is turned on, the charge stored in the photoelectric conversion unit 51 is transmitted to the floating diffusion node FD, which has a high conversion efficiency, the floating diffusion node FD and the first MIM type capacitor 55, which have an intermediate conversion efficiency, and the floating diffusion node FD, the first MIM type capacitor 55, and the second MIM type capacitor 57, which have a low conversion efficiency.

[0121] In some embodiments, the source follower SF and the select transistor SX are disposed in the first intermediate layer 300 described above, and the ADC circuit (150 in FIG. 1) is disposed in the bottom layer 500 described above.

[0122] FIG. 6 is a circuit diagram of an image sensor according to an embodiment of the present invention.

[0123] Specifically, the image sensor circuit of Fig. 6 includes a digital pixel sensor (DPS) including an ADC circuit (150 in Fig. 1). Fig. 6 is a schematic circuit diagram of a pixel PX that implements the rolling shutter mode (or method) operation of the image sensor 100 described in Figs. 1 and 2B. In the description of Fig. 6, the contents described in Fig. 1 will be briefly described or omitted.

[0124] The pixel PX includes a photodiode PD and a pixel circuit PSCc that generates a pixel signal PXS. The pixel PX shown in FIG. 6 includes a number of sub-pixels (sub pix i, i+1, i+2, i+3, i+4), each of which includes a photodiode PD and a transmission transistor TX.

[0125] The sub-pixel is connected to a floating diffusion node FD. The circuit portion connected to the photodiode PD and the transfer transistor TX shown in FIG 6 corresponds to a sub-pixel (sub pix(i)).

[0126] The pixel circuit PSCc includes a transfer transistor TX coupled to a photodiode PD. In some embodiments, the photodiode PD and the transfer transistor TX are disposed on the top layer 200 described above.

[0127] A driving signal TS is applied to the transmission transistor TX. When the driving signal TS becomes high level, the transmission transistor TX is turned on and the charge stored in the photodiode PD is transferred to the floating diffusion node FD via the transmission transistor TX. A plurality of pixels (sub pix) are connected to the floating diffusion node FD. In some embodiments, four pixels are connected to the floating diffusion node FD.

[0128] The floating diffusion node FD acts as a storage unit for temporarily storing the transferred charge and the charge overflowing from the photodiode PD. In some embodiments, the photodiode PD and the transfer transistor TX are disposed on the top layer 200 described above.

[0129] A first conversion efficiency switching transistor 62 is connected to the floating diffusion node FD. The first conversion efficiency switching transistor 62 is provided between the floating diffusion node FD and a first MIM capacitor 66. A power supply voltage MIMVDD is connected to one end of the first MIM capacitor 66. A first drive signal FDG1 is supplied to the first conversion efficiency switching transistor 62. The first conversion efficiency switching transistor 62 corresponds to the above-mentioned conversion gain transistor.

[0130] When the driving signal FDG1 reaches a high level, the first conversion efficiency switching transistor 62 is turned on, and the charge from the floating diffusion node FD is transferred to the MIM type first capacitor 66 via the first conversion efficiency switching transistor 62. The MIM type first capacitor 66 temporarily stores the charge overflowing from the photodiode PD.

[0131] When the first conversion efficiency switching transistor 62 is turned on, the region where the charges are stored becomes the region where the floating diffusion node FD and the first MIM type capacitor 66 are coupled, and the charges generated in the photodiode PD are converted into a voltage. The first conversion efficiency switching transistor 62 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0132] The first conversion efficiency switching transistor 62 is connected to a second conversion efficiency switching transistor 64. The second conversion efficiency switching transistor 64 is provided between a first MIM capacitor 66 and a second MIM capacitor 68. One end of the second MIM capacitor 68 is connected to a power supply voltage MIMVDD. A second drive signal FDG2 is supplied to the second conversion efficiency switching transistor 64. If the second drive signal FDG2 is at a high level, the second conversion efficiency switching transistor 64 is turned on, and the charge from the first MIM capacitor 66 is transferred to the second MIM capacitor 68 via the second conversion efficiency switching transistor 64. The second conversion efficiency switching transistor 64 corresponds to the conversion gain transistor described above.

[0133] When the second conversion efficiency switching transistor 64 is turned on, the region where the charge is stored is the region where the floating diffusion node FD, the first MIM capacitor 66, and the second MIM capacitor 68 are coupled together. The second conversion efficiency switching transistor 64 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0134] The first conversion efficiency switching transistor 62 and the second conversion efficiency switching transistor 64 are transistors for switching the first MIM capacitor 66 and the second MIM capacitor 68.

[0135] In the pixel circuit of this embodiment, the MIM type first capacitor 66 and the MIM type second capacitor 68 are described as examples, but may include a MOS (metal oxide semiconductor) capacitor, a trench capacitor, a PIP (poly insulator poly) capacitor, or a PIP (poly insulator poly) capacitor.

[0136] In some embodiments, the first conversion efficiency switching transistor 62, the second conversion efficiency switching transistor 64, the first MIM capacitor 66 and the second MIM capacitor 68 are disposed on the first intermediate layer 300 or the second intermediate layer 400 described above.

[0137] The MIM type first capacitor 66 and the MIM type second capacitor 68 each realize a high capacitance without sacrificing the area of ​​the surface of a substrate (e.g., a silicon substrate) on which a pixel transistor is arranged, and have a capacitance larger than that of the floating diffusion node FD.

[0138] The reset transistor RX is connected between a power supply VDD and the second MIM capacitor 68, and a drive signal (or control signal) RS is supplied to the reset transistor RX. When the drive signal RS is set to a high level, the reset transistor RX is turned on, and the potential of the floating diffusion node FD is reset to the power supply voltage level.

[0139] In some embodiments, the first conversion efficiency switching transistor 62, the second conversion efficiency switching transistor 64, the first MIM capacitor 66 and the second MIM capacitor 68 are disposed on the first intermediate layer 300 or the second intermediate layer 400 described above.

[0140] The floating diffusion node FD is connected to a source follower SF. The charge stored in the floating diffusion node FD is amplified by the source follower SF to output a pixel signal PXS, e.g., a pixel voltage. The pixel voltage is stored in a capacitor C1. A ramp voltage is generated from the ramp signal generator 130. The ramp voltage is stored in a second capacitor C2. In some embodiments, the source follower SF, the ramp signal generator 130, the first capacitor C1, and the second capacitor C2 are disposed in the first intermediate layer 300 described above.

[0141] The first capacitor C1 and the second capacitor C2 are coupled to the ADC circuit 150. The ADC circuit 150 converts the pixel signal PXS into a digital value. The ADC circuit 150 converts the reset signal and the image signal received as the pixel signal PXS into a reset value and an image value, which are digital signals, respectively.

[0142] The ADC circuit 150 includes a CDS circuit (160 in FIG. 1) that includes a comparator. The comparator is implemented as an OTA (Operational Transconductance Amplifier) ​​(or a differential amplifier). The ADC circuit 150 includes an input stage (first stage) IPA of the OTA, an amplification stage REA of the OTA, and an output stage (second stage) OPA of the OTA. The ADC circuit 150 includes a number of switches S3a, S3b. In some embodiments, a first capacitor C1 and a second capacitor C2 may be included in the ADC circuit 150.

[0143] The ADC circuit 150 compares the pixel signal PXS with the ramp signal RAMP received from the ramp signal generator 130. A number of switches S3a and S3b are connected to a feedback line connecting an input terminal of the OTA's first stage IPA and an output terminal of the OTA's amplification stage REA to remove the offset of the comparator. The ADC circuit 150 transmits the CDS signal through the OTA's second stage OPA.

[0144] In some embodiments, the OTA input stage (first stage) IPA, the OTA amplification stage REA, and the OTA output stage (second stage) OPA constituting the ADC circuit 150 are arranged in the above-mentioned first intermediate layer 300 or the second intermediate layer 400. In some embodiments, the reset transistor RX and circuit elements constituting the pixel circuit PSCc of the image sensor, such as additional transistors required to drive the pixel PX, such as the count circuit (170 in FIG. 1) and the data output circuit 180, are arranged in the bottom layer 500 described above.

[0145] FIG. 7 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0146] Specifically, the image sensor EX2 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX2 includes the pixel PX of FIG 1. The image sensor EX2 is almost the same as the image sensor EX1 of FIG 3, except that the second intermediate layer 400-1 is different. In FIG 7, the contents described in FIG 3 will be briefly described or omitted.

[0147] The image sensor EX2 includes a top layer 200, a first intermediate layer 300, a second intermediate layer 400-1, and a bottom layer 500. The image sensor EX2 is made up of four layers, the bottom layer 500, the second intermediate layer 400-1, the first intermediate layer 300, and the top layer 200 bonded together.

[0148] The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300. The top layer 200 and the first intermediate layer 300 have an interface FF where the front faces F and F are bonded to each other.

[0149] The second intermediate layer 400-1 includes a third substrate 401-2, a plurality of third transistors 409, a third backside bonding through via 407-2, a third wiring layer 411, a third contact plug 413, a third frontside bonding pad 415, a third via plug 414, and a third insulating layer 417. The third substrate 401-2 includes a lower substrate layer 401-2a and an upper substrate layer 401-2b. The lower substrate layer 401-2a and the upper substrate layer 401-2b are made of silicon substrates. In addition, the lower substrate layer 401-2a and the upper substrate layer 401-2b may be made of silicon on insulator (SOI) substrates.

[0150] The second back-side bonding through via 307 constituting the first intermediate layer 300 is bonded to the third back-side bonding through via 407-2 constituting the second intermediate layer 400-1. The second insulating layer 317 and the second substrate 301 constituting the first intermediate layer 300 are bonded to the lower substrate layer 401-2a and the third insulating layer 417 constituting the second intermediate layer 400-1. The first intermediate layer 300 and the second intermediate layer 400-1 have an interface BB where the back surfaces B and B are bonded to each other.

[0151] The lower substrate layer 401-2a and the upper substrate layer 401-2b constituting the third substrate 401-2 are silicon layers. The lower substrate layer 401-2a includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. In FIG. 7, a third source and drain region constituting the third transistor 409 is formed in the lower substrate layer 401-2a, but is omitted here for convenience.

[0152] A through via hole 403 penetrating the third front surface 401f and the third back surface 401b is formed in the lower substrate layer 401-2a. A third back surface bonding through via 407-2 insulated by a third insulating layer 417 is formed in the through via hole 403. The third back surface bonding through via 407-2 is connected to a third front surface bonding pad 415 via a third contact plug 413, a third via plug 414, and a third wiring layer 411.

[0153] The third transistor 409 is connected to a third contact plug 413 and a third wiring layer 411. The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to a third front bonding pad 415. The third front bonding pad 415, the third wiring layer 411, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0154] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0155] The third front bonding pad 415 constituting the second intermediate layer 400-1 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the upper substrate layer 401-2b constituting the second intermediate layer 400-1 are bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-1 and the bottom layer 500 have an interface FF where the front faces F and F are bonded to each other.

[0156] In the above-mentioned image sensor EX2, the first front bonding pad 209 constituting the top layer 200 and the second front bonding pad 315 constituting the first intermediate layer 300 are bonded together, and the top layer 200 and the first intermediate layer 300 have an interface FF at which the front faces F and F are bonded together.

[0157] In the above-described image sensor EX2, the second back-side bonding through via 307 constituting the first intermediate layer 300 is bonded to the third back-side bonding through via 407-2 constituting the second intermediate layer 400-1. The first intermediate layer 300 and the second intermediate layer 400-1 have an interface BB where the back surfaces B and B are bonded to each other.

[0158] In the above-described image sensor EX2, the third front bonding pad 415 constituting the second intermediate layer 400-1 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-1 and the bottom layer 500 have an interface FF at which the front faces F and F are bonded to each other.

[0159] FIG. 8 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0160] Specifically, the image sensor EX3 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX3 includes the pixel PX of FIG 1. The image sensor EX3 is the same as the image sensor EX1 of FIG 3 described above, except that the first intermediate layer 300-1 and the second intermediate layer 400-2 are different. In FIG 8, the contents described in FIG 3 will be briefly described or omitted.

[0161] The image sensor EX3 is composed of four layers, namely, a bottom layer 500, a second intermediate layer 400-2, a first intermediate layer 300-1, and a top layer 200, which are bonded together. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel separation layer 215, a color filter 217, and a lens 219.

[0162] The first intermediate layer 300-1 includes a second substrate 301, a plurality of second transistors 305, a second back surface bonding pad 307-3, a second wiring layer 311, a second contact plug 309, a second front surface bonding pad 315, a second via plug 313, a first connecting via plug 319, and a second insulating layer 317-3.

[0163] The first front bonding pad 209 constituting the top layer 200 is bonded to the second back bonding pad 307-3 constituting the first intermediate layer 300-1. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317-3 constituting the first intermediate layer 300-1. The top layer 200 and the first intermediate layer 300-1 have an interface FB where the front surface F and the back surface B are bonded.

[0164] The second substrate 301 is a silicon substrate. The second substrate 301 includes a second front surface 301f and a second back surface 301b facing the second front surface 301f. A second transistor 305 is formed on the second front surface 301f. In FIG. 8, second source and drain regions constituting the second transistor 305 are formed in the second substrate 301, but are omitted for convenience.

[0165] A second contact plug 309 and a second wiring layer 311 are connected to the second transistor 305. The second contact plug 309 is made of a metal layer, for example, a tungsten layer. The second contact plug 309 and the second wiring layer 311 are connected to the second front bonding pad 315 and the second back bonding pad 307-3. The second back bonding pad 307-3, the second wiring layer 311, the second front bonding pad 315, and the second via plug 313 are made of a metal layer, for example, a copper layer.

[0166] A second insulating layer 317-3 is further formed on the lower surface of the second substrate 301. The second back surface bonding pad 307-3 is connected to the second wiring layer 311 by a first connecting via plug 319. The first connecting via plug 319 is longer in the vertical direction than the second via plug 313. The first connecting via plug 319 is made of a metal layer, for example, a tungsten layer.

[0167] The second intermediate layer 400-2 includes a third substrate 401, a plurality of third transistors 409, a third back-side bonding through via 407-3, a third wiring layer 411, a third contact plug 413, a third front-side bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0168] The second front bonding pad 315 constituting the first intermediate layer 300-1 is bonded to the third front bonding pad 415 constituting the second intermediate layer 400-2. The second insulating layer 317-3 constituting the first intermediate layer 300-1 is bonded to the third insulating layer 417 constituting the second intermediate layer 400-2. The first intermediate layer 300-1 and the second intermediate layer 400-2 have an interface FF where the front surfaces F and F are bonded to each other.

[0169] The third substrate 401 is a silicon substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. In FIG. 8, a third source and drain region constituting the third transistor 409 is formed in the third substrate 401, but is omitted here for convenience.

[0170] A through via hole 403 penetrating a part of the third front surface 401f and the third back surface 401b is formed in the third substrate 401. In the through via hole 403, a third back surface bonding through via 407-3 insulated by a third insulating layer 417 is formed.

[0171] The third transistor 409 is connected to a third contact plug 413 and a third wiring layer 411. The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to a third front bonding pad 415 and a third back bonding through via 407-3. The third back bonding through via 407-3, the third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0172] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0173] The third back surface bonding through via 407-3 constituting the second intermediate layer 400-2 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400-2 are bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-2 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0174] In the image sensor EX3 described above, the first front bonding pad 209 constituting the top layer 200 and the second back bonding pad 307-3 constituting the first intermediate layer 300-1 are bonded, and the top layer 200 and the first intermediate layer 300-1 have an interface FB where the front surface F and the back surface B are bonded.

[0175] In the above-mentioned image sensor EX3, the second front bonding pad 315 constituting the first intermediate layer 300-1 is bonded to the third front bonding pad 415 constituting the second intermediate layer 400-2. The first intermediate layer 300-1 and the second intermediate layer 400-2 have an interface FF where the front surfaces F and F are bonded to each other.

[0176] In the above-described image sensor EX3, the third back surface bonding through via 407-3 constituting the second intermediate layer 400-2 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-2 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0177] FIG. 9 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0178] Specifically, the image sensor EX4 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX4 includes the pixel PX of FIG 1. The image sensor EX4 is the same as the image sensor EX1 of FIG 3 described above, except that the first intermediate layer 300-1 and the second intermediate layer 400-3 are different. In FIG 9, the contents described in FIG 3 will be briefly described or omitted.

[0179] The image sensor EX4 is composed of four layers, namely, a bottom layer 500, a second intermediate layer 400-3, a first intermediate layer 300-1, and a top layer 200, which are bonded together. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel separation layer 215, a color filter 217, and a lens 219.

[0180] The first intermediate layer 300-1 includes a second substrate 301, a plurality of second transistors 305, a second back surface bonding pad 307-3, a second wiring layer 311, a second contact plug 309, a second front surface bonding pad 315, a second via plug 313, a first connecting via plug 319, and a second insulating layer 317-3.

[0181] The first front bonding pad 209 constituting the top layer 200 is bonded to the second back bonding pad 307-3 constituting the first intermediate layer 300-1. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317-3 constituting the first intermediate layer 300-1. The top layer 200 and the first intermediate layer 300-1 have an interface FB where the front surface F and the back surface B are bonded. The first intermediate layer 300-1 has been described in FIG. 8, so a detailed description thereof will be omitted here.

[0182] The second intermediate layer 400-3 includes a third substrate 401, a plurality of third transistors 409, a third back-side bonding through via 407-4, a third wiring layer 411, a third contact plug 413, a third front-side bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0183] The second front bonding pad 315 constituting the first intermediate layer 300-1 is bonded to the third back bonding through via 407-4 constituting the second intermediate layer 400-3. The second insulating layer 317-3 constituting the first intermediate layer 300-1 is bonded to the third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400-3. The first intermediate layer 300-1 and the second intermediate layer 400-3 have an interface FB where the front surface F and the back surface B are bonded.

[0184] The third substrate 401 is a silicon substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. In FIG. 9, a third source and drain region constituting the third transistor 409 is formed in the third substrate 401, but is omitted here for convenience.

[0185] A through via hole 403 penetrating the third front surface 401f and the third back surface 401b is formed in the third substrate 401. In the through via hole 403, a third back surface bonding through via 407-4 insulated by a third insulating layer 417 is formed.

[0186] The third transistor 409 is connected to a third contact plug 413 and a third wiring layer 411. The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to a third front bonding pad 415 and a third back bonding through via 407-4. The third back bonding through via 407-4, the third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0187] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0188] The third front bonding pad 415 constituting the second intermediate layer 400-3 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 constituting the second intermediate layer 400-3 is bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-3 and the bottom layer 500 have an interface FF where the front faces F and F are bonded to each other.

[0189] In the above-mentioned image sensor EX4, the first front bonding pad 209 constituting the top layer 200 and the second back bonding pad 307-3 constituting the first intermediate layer 300-1 are bonded, and the top layer 200 and the first intermediate layer 300-1 have an interface FB where the front surface F and the back surface B are bonded.

[0190] In the above-mentioned image sensor EX4, the second front bonding pad 315 constituting the first intermediate layer 300-1 is bonded to the third back bonding through via 407-4 constituting the second intermediate layer 400-3. The first intermediate layer 300-1 and the second intermediate layer 400-3 have an interface FB where the front surface F and the back surface B are bonded.

[0191] In the above-mentioned image sensor EX4, the third front bonding pad 415 constituting the second intermediate layer 400-3 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-2 and the bottom layer 500 have an interface FF at which the front faces F and F are bonded to each other.

[0192] FIG. 10 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0193] Specifically, the image sensor EX5 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX5 includes the pixel PX of FIG 1. The image sensor EX5 is the same as the image sensor EX1 of FIG 3 described above, except that the first intermediate layer 300-2 and the second intermediate layer 400-4 are different. In FIG 10, the contents described in FIG 3 will be briefly described or omitted.

[0194] The image sensor EX5 is composed of four layers, namely, a bottom layer 500, a second intermediate layer 400-4, a first intermediate layer 300-2, and a top layer 200, which are bonded together. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel separation layer 215, a color filter 217, and a lens 219.

[0195] The first intermediate layer 300-2 includes a second substrate 301, a plurality of second transistors 305, a second back-side bonding through-via 307, a second wiring layer 311, a second contact plug 309, a second front-side bonding pad 315, a second via plug 313, a second connecting via plug 321, and a second insulating layer 317.

[0196] The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300-2. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300-2. The top layer 200 and the first intermediate layer 300-2 have an interface FF where the front surfaces F and F are bonded to each other.

[0197] The second substrate 301 is a silicon substrate. The second substrate 301 includes a second front surface 301f and a second back surface 301b facing the second front surface 301f. A second transistor 305 is formed on the second front surface 301f. A through via hole 303 penetrating the second front surface 301f and the second back surface 301b is formed in the second substrate 301. A second back surface bonding through via 307 insulated by a second insulating layer 317 is formed in the through via hole 303.

[0198] A second contact plug 309 and a second wiring layer 311 are connected to the second transistor 305. The second contact plug 309 is made of a metal layer, for example, a tungsten layer. The second contact plug 309 and the second wiring layer 311 are connected to the second front bonding pad 315 and the second back bonding through via 307. The second back bonding through via 307, the second wiring layer 311, the second front bonding pad 315, and the second via plug 313 are made of a metal layer, for example, a copper layer.

[0199] The second connection via plug 321 is connected to the second wiring layer 311, and extends to the second intermediate layer 400-4 to be connected to the third wiring layer 411. The second connection via plug 321 is longer in the vertical direction than the second via plug 313. The second connection via plug 321 is made of a metal layer, for example, a tungsten layer.

[0200] The second intermediate layer 400-4 includes a third substrate 401, a plurality of third transistors 409, a third through via 405, a third back surface bonding pad 407-5, a third wiring layer 411, a third contact plug 413, a third front surface bonding pad 415, a third via plug 414, a third insulating layer 417, and a capacitor 421.

[0201] The second back surface bonding through via 307 constituting the first intermediate layer 300-2 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400-4. The second insulating layer 317 and the second substrate 301 constituting the first intermediate layer 300-2 are bonded to the third insulating layer 417 constituting the second intermediate layer 400-4. The first intermediate layer 300-2 and the second intermediate layer 400-4 have an interface BF where the back surface B and the front surface F are bonded.

[0202] The third substrate 401 is a silicon substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. A third back surface bonding pad 407-5 is disposed on the fourth back surface 401b. A third contact plug 413 and a third wiring layer 411 are connected to the third transistor 409. A capacitor 421 is disposed on the third wiring layer 411. The third wiring layer 411 is connected to the capacitor 421.

[0203] The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to the third front bonding pad 415. The third back bonding pad 407-5 is not shown in FIG. 10 for convenience, but is electrically connected to the third wiring layer 411 of the third substrate 401. The third back bonding pad 407-5, the third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0204] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0205] The third back surface bonding pad 407-5 constituting the second intermediate layer 400-4 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The third substrate 401 constituting the second intermediate layer 400-4 is bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-4 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0206] In the above-mentioned image sensor EX5, the first front bonding pad 209 constituting the top layer 200 and the second front bonding pad 315 constituting the first intermediate layer 300-2 are bonded, and the top layer 200 and the first intermediate layer 300-2 have an interface FF at which the front faces F and F are bonded.

[0207] In the above-mentioned image sensor EX5, the second back surface bonding through via 307 constituting the first intermediate layer 300-2 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400-4. The first intermediate layer 300-2 and the second intermediate layer 400-4 have an interface BF where the back surface B and the front surface F are bonded. The first intermediate layer 300-2 and the second intermediate layer 400-4 are connected by a second connecting via plug 321.

[0208] In the above-mentioned image sensor EX5, the third back surface bonding pad 407-5 constituting the second intermediate layer 400-4 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-4 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0209] FIG. 11 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0210] Specifically, the image sensor EX6 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX6 includes the pixel PX of FIG 1. The image sensor EX6 is the same as the image sensor EX1 of FIG 3 described above, except that the first intermediate layer 300-3 and the second intermediate layer 400-5 are different. In FIG 11, the contents described in FIG 3 will be briefly described or omitted.

[0211] The image sensor EX6 is composed of four layers, namely, a bottom layer 500, a second intermediate layer 400-5, a first intermediate layer 300-3, and a top layer 200, which are bonded together. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel separation layer 215, a color filter 217, and a lens 219.

[0212] The first intermediate layer 300-3 includes a second substrate 301, a plurality of second transistors 305, a second back surface bonding pad 307-6, a second wiring layer 311, a second contact plug 309, a second front surface bonding pad 315, a second via plug 313, a third connecting via plug 322, and a second insulating layer 317.

[0213] The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300-3. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300-3. The top layer 200 and the first intermediate layer 300-3 have an interface FF where the front surfaces F and F are bonded to each other.

[0214] The second substrate 301 is a silicon substrate. The second substrate 301 includes a second front surface 301f and a second back surface 301b facing the second front surface 301f. A second transistor 305 is formed on the second front surface 301f. A second contact plug 309 and a second wiring layer 311 are connected to the second transistor 305. The second contact plug 309 is made of a metal layer, for example, a tungsten layer. The second contact plug 309 and the second wiring layer 311 are connected to a second front bonding pad 315. The second wiring layer 311, the second front bonding pad 315, and the second via plug 313 are made of a metal layer, for example, a copper layer.

[0215] The third connection via plug 322 is connected to the second wiring layer 311 and the second front bonding pad 315. The third connection via plug 322 is longer in the vertical direction than the second via plug 313. The third connection via plug 322 is made of a metal layer, for example, a tungsten layer. The second back bonding pad 307-6 is electrically connected to the second wiring layer 311 of the second substrate 301, although it is not shown in FIG. 11 for convenience.

[0216] The second intermediate layer 400-5 includes a third substrate 401, a plurality of third transistors 409, a third back-side bonding through via 407-6, a third wiring layer 411, a third contact plug 413, a third front-side bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0217] The second back surface bonding pad 307-6 constituting the first intermediate layer 300-3 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400-5. The second substrate 301 constituting the first intermediate layer 300-3 is bonded to the third insulating layer 417 constituting the second intermediate layer 400-5. The first intermediate layer 300-3 and the second intermediate layer 400-5 have an interface BF where the back surface B and the front surface F are bonded.

[0218] The third substrate 401 is a silicon substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f.

[0219] A through via hole 403 penetrating the third front surface 401f and the third back surface 401b is formed in the third substrate 401. A third back surface bonding through via 407-6 insulated by a third insulating layer 417 is formed in the through via hole 403. The third back surface bonding through via 407-6 is connected to the third via plug 414 and the third wiring layer 411.

[0220] The third transistor 409 is connected to a third contact plug 413 and a third wiring layer 411. The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to a third front bonding pad 415. The third backside bonding through via 407-6, the third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0221] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0222] The third back-side bonding through via 407-6 constituting the second intermediate layer 400-5 is bonded to the fourth front-side bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400-5 are bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-5 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0223] In the above-mentioned image sensor EX6, the first front bonding pad 209 constituting the top layer 200 and the second front bonding pad 315 constituting the first intermediate layer 300-3 are bonded, and the top layer 200 and the first intermediate layer 300-3 have an interface FF at which the front faces F and F are bonded.

[0224] In the above-mentioned image sensor EX6, the second back surface bonding pad 307-6 constituting the first intermediate layer 300-3 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400-5. The first intermediate layer 300-3 and the second intermediate layer 400-5 have an interface BF where the back surface B and the front surface F are bonded.

[0225] In the above-mentioned image sensor EX6, the third back surface bonding through via 407-6 constituting the second intermediate layer 400-5 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-5 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0226] FIG. 12 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0227] Specifically, the image sensor EX7 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX7 includes the pixel PX of FIG 1. The image sensor EX7 is the same as the image sensor EX1 of FIG 3 described above, except that the first intermediate layer 300-1 and the second intermediate layer 400-6 are different. In FIG 12, the contents described in FIG 3 will be briefly described or omitted.

[0228] The image sensor EX7 is composed of four layers, namely, a bottom layer 500, a second intermediate layer 400-6, a first intermediate layer 300-1, and a top layer 200, which are bonded together. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel separation layer 215, a color filter 217, and a lens 219.

[0229] The first intermediate layer 300-1 includes a second substrate 301, a plurality of second transistors 305, a second backside bonding pad 307-3, a second wiring layer 311, a second contact plug 309, a second frontside bonding pad 315, a second via plug 313, a first connecting via plug 319, and a second insulating layer 317-3. The first intermediate layer 300-1 has been described in FIG. 8 above, and therefore will not be described here.

[0230] The first front bonding pad 209 constituting the top layer 200 is bonded to the second back bonding pad 307-3 constituting the first intermediate layer 300-1. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317-3 constituting the first intermediate layer 300-1. The top layer 200 and the first intermediate layer 300-1 have an interface FB where the front surface F and the back surface B are bonded.

[0231] The second intermediate layer 400-6 includes a third substrate 401, a plurality of third transistors 409, a third back bonding pad 407-7, a third wiring layer 411, a third contact plug 413, a third front bonding pad 415, a third via plug 414, a third insulating layer 417, a capacitor 421, and a fourth connecting via plug 423.

[0232] The second front bonding pad 315 constituting the first intermediate layer 300-1 is bonded to the third front bonding pad 415 constituting the second intermediate layer 400-6. The second insulating layer 317-3 constituting the first intermediate layer 300-1 is bonded to the third insulating layer 417 constituting the second intermediate layer 400-6. The first intermediate layer 300-1 and the second intermediate layer 400-6 have an interface FF where the front surfaces F and F are bonded to each other.

[0233] The third substrate 401 is a silicon substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. A third contact plug 413 and a third wiring layer 411 are connected to the third transistor 409.

[0234] The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to a third front bonding pad 415. A capacitor 421 is disposed on the third wiring layer 411. The third wiring layer 411 is connected to the capacitor 421. The third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0235] The fourth connection via plug 423 is connected to the third wiring layer 411 and the second front bonding pad 315. The fourth connection via plug 423 is longer in the vertical direction than the third via plug 414. The fourth connection via plug 423 is made of a metal layer, for example, a tungsten layer.

[0236] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0237] The third back surface bonding pad 407-7 constituting the second intermediate layer 400-6 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The third substrate 401 constituting the second intermediate layer 400-6 is bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-6 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0238] In the above-mentioned image sensor EX7, the first front bonding pad 209 constituting the top layer 200 and the second back bonding pad 307-3 constituting the first intermediate layer 300-1 are bonded, and the top layer 200 and the first intermediate layer 300-1 have an interface FB where the front surface F and the back surface B are bonded.

[0239] In the above-mentioned image sensor EX7, the second front bonding pad 315 constituting the first intermediate layer 300-1 is bonded to the third front bonding pad 415 constituting the second intermediate layer 400-6. The first intermediate layer 300-1 and the second intermediate layer 400-6 have an interface FF where the front surfaces F and F are bonded to each other.

[0240] In the above-mentioned image sensor EX7, the third back surface bonding pad 407-7 constituting the second intermediate layer 400-6 is bonded to the fourth front surface bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-6 and the bottom layer 500 have an interface BF where the back surface B and the front surface F are bonded.

[0241] FIG. 13 is a schematic cross-sectional view illustrating a structure of an image sensor according to an embodiment of the present invention.

[0242] Specifically, the image sensor EX8 is an embodiment that embodies the image sensor 100 of FIG 1. The image sensor EX8 includes the pixel PX of FIG 1. The image sensor EX8 is the same as the image sensor EX1 of FIG 3 described above, except that the first intermediate layer 300-4 and the second intermediate layer 400-7 are different. In FIG 13, the contents described in FIG 3 will be briefly described or omitted.

[0243] The image sensor EX8 is composed of four layers, namely, a bottom layer 500, a second intermediate layer 400-7, a first intermediate layer 300-4, and a top layer 200, which are bonded together. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, a first insulating layer 213, a pixel separation layer 215, a color filter 217, and a lens 219.

[0244] The first intermediate layer 300-4 includes a second substrate 301, a plurality of second transistors 305, second back surface bonding pads 307-8, a second wiring layer 311, a second contact plug 309, a second front surface bonding pad 315, a second via plug 313, a functional element 323, a fifth connecting via plug 325, and a second insulating layer 317.

[0245] The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300-4. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300-4. The top layer 200 and the first intermediate layer 300-4 have an interface FF where the front surfaces F and F are bonded to each other.

[0246] The second substrate 301 is a silicon substrate. The second substrate 301 includes a second front surface 301f and a second back surface 301b facing the second front surface 301f. A second transistor 305 is formed on the second front surface 301f. A second contact plug 309 and a second wiring layer 311 are connected to the second transistor 305.

[0247] The second contact plug 309 is made of a metal layer, for example, a tungsten layer. The second contact plug 309 and the second wiring layer 311 are connected to the second front bonding pad 315. The second wiring layer 311, the second front bonding pad 315, and the second via plug 313 are made of a metal layer, for example, a copper layer. A functional element 323 is disposed on the second wiring layer 311. The second wiring layer 311 is connected to the functional element 323. In some embodiments, the functional element 323 includes an image processing circuit, an AD converter, or a capacitor. In some embodiments, the capacitor may include a metal insulator metal (MIM) capacitor, a metal oxide semiconductor (MOS) capacitor, a trench capacitor, a poly insulator poly (PIP) capacitor, or a three dimensional (3D) capacitor.

[0248] The fifth connection via plug 325 is connected to the second wiring layer 311 and the second front bonding pad 315. The fifth connection via plug 325 is longer in the vertical direction than the second via plug 313. The fifth connection via plug 325 is made of a metal layer, for example, a tungsten layer. The second back bonding pad 307-8 is electrically connected to the second wiring layer 311 of the second substrate 301, although it is not shown in FIG. 13 for convenience.

[0249] The second intermediate layer 400-7 includes a third substrate 401, a plurality of third transistors 409, a third back surface bonding pad 407-8, a third wiring layer 411, a third contact plug 413, a third front surface bonding pad 415, a third via plug 414, a third insulating layer 417, and a sixth connecting via plug 425.

[0250] The second backside bonding pad 307-8 constituting the first intermediate layer 300-4 is bonded to the third backside bonding pad 407-8 constituting the second intermediate layer 400-7. The second substrate 301 constituting the first intermediate layer 300-4 is bonded to the third insulating layer 417 constituting the second intermediate layer 400-7. The first intermediate layer 300-4 and the second intermediate layer 400-7 have an interface BF where the backside B and the backside F are bonded.

[0251] The third substrate 401 is a silicon substrate. The third substrate 401 includes a third front surface 401f and a fourth back surface 401b facing the third front surface 401f. A third transistor 409 is formed on the third front surface 401f. A third contact plug 413 and a third wiring layer 411 are connected to the third transistor 409. A capacitor 421 may be disposed on the third wiring layer 411. The third wiring layer 411 may be connected to the capacitor 421.

[0252] The third contact plug 413 is made of a metal layer, for example, a tungsten layer. The third contact plug 413 and the third wiring layer 411 are connected to the third front bonding pad 415. The third back bonding pad 407-8, the third wiring layer 411, the third front bonding pad 415, and the third via plug 414 are made of a metal layer, for example, a copper layer.

[0253] The bottom layer 500 includes a fourth substrate 501 , a plurality of fourth transistors 502 , a fourth wiring layer 503 , a fourth contact plug 505 , a fourth front side bonding pad 507 , a fourth via plug 506 , and a fourth insulating layer 509 .

[0254] The third front bonding pad 415 constituting the second intermediate layer 400-7 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 constituting the second intermediate layer 400-7 is bonded to the fourth insulating layer 509 constituting the bottom layer 500. The second intermediate layer 400-7 and the bottom layer 500 have an interface FF where the front faces F and F are bonded to each other.

[0255] In the above-mentioned image sensor EX8, the first front bonding pad 209 constituting the top layer 200 and the second front bonding pad 315 constituting the first intermediate layer 300-4 are bonded, and the top layer 200 and the first intermediate layer 300-4 have an interface FF at which the front faces F and F are bonded.

[0256] In the above-mentioned image sensor EX8, the second backside bonding pad 307-8 constituting the first intermediate layer 300-4 is bonded to the third backside bonding pad 407-8 constituting the second intermediate layer 400-7. The first intermediate layer 300-4 and the second intermediate layer 400-7 have an interface BB where the backsides B and B are bonded to each other.

[0257] In the above-described image sensor EX8, the third front bonding through pad 415 constituting the second intermediate layer 400-7 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The second intermediate layer 400-7 and the bottom layer 500 have an interface FF at which the front faces F and F are bonded to each other.

[0258] 14 to 16 are cross-sectional views illustrating a method for manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention.

[0259] Specifically, in Figs. 14 to 16, the contents described in Fig. 3 will be briefly described or omitted. Referring to Fig. 14, a top layer 200 is prepared. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, and a first insulating layer 213. The first substrate 201 includes a first front surface 201f and a first back surface 201b facing the first front surface 201f. For convenience, the pixel isolation layer 215, the color filter 217, and the lens 219 described in Fig. 3 are not shown in Fig. 14.

[0260] A first intermediate layer 300 is prepared. The first intermediate layer 300 includes a second substrate 301, a plurality of second transistors 305, a second back-side bonding through via 307, a second wiring layer 311, a second contact plug 309, a second front-side bonding pad 315, a second via plug 313, and a second insulating layer 317.

[0261] The second substrate 301 includes a second front surface 301f and a second rear surface 301b facing the second front surface 301f. A through via hole 303 penetrating the second front surface 301f and the second rear surface 301b is formed in the second substrate 301. A second rear surface bonding through via 307 insulated by a second insulating layer 317 is formed in the through via hole 303.

[0262] The first front bonding pad 209 constituting the top layer 200 is bonded in the direction of the arrow to the second front bonding pad 315 constituting the first intermediate layer 300. The first insulating layer 213 constituting the top layer 200 is bonded in the direction of the arrow to the second insulating layer 317 constituting the first intermediate layer 300. When the first front bonding pad 209 and the second front bonding pad 315 are formed of a copper layer, the copper pads are bonded to each other.

[0263] 15, a second intermediate layer 400 is prepared. The second intermediate layer 400 includes a third substrate 401, a plurality of third transistors 409, a third through via 405, a third backside bonding pad 407, a third wiring layer 411, a third contact plug 413, a third frontside bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0264] The third substrate 401 includes a third front surface 401f and a fourth rear surface 401b facing the third front surface 401f. A through via hole 403 is formed in the third substrate 401, penetrating the third front surface 401f and a part of the third rear surface 401b. A third through via 405 insulated by a third insulating layer 417 is formed in the through via hole 403. The third through via 405 is connected to a third rear surface bonding pad 407 via a third via plug 414.

[0265] A bottom layer 500 is prepared. The bottom layer 500 includes a fourth substrate 501, a plurality of fourth transistors 502, a fourth wiring layer 503, a fourth contact plug 505, a fourth front bonding pad 507, a fourth via plug 506, and a fourth insulating layer 509. The fourth substrate 501 includes a fourth front surface 501f and a fourth back surface 401b facing the fourth front surface 501f.

[0266] The third back bonding pad 407 constituting the second intermediate layer 400 is bonded in the direction of the arrow to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400 are bonded in the direction of the arrow to the fourth insulating layer 509 constituting the bottom layer 500. When the third back bonding pad 407 and the fourth front bonding pad 507 are formed of a copper layer, the copper pads are bonded to each other.

[0267] 16, a bonded top layer 200 and a first intermediate layer 300 are prepared as described above in FIG 14. A bonded second intermediate layer 400 and a bottom layer 500 are prepared as described above in FIG 15. The second back surface bonding through via 307 constituting the first intermediate layer 300 is bonded to the third front surface bonding pad 415 constituting the second intermediate layer 400 in the direction of the arrow.

[0268] The second insulating layer 317 and the second substrate 301 constituting the first intermediate layer 300 are bonded to the third insulating layer 417 constituting the second intermediate layer 400 in the direction of the arrow. When the second back bonding through via 307 and the third front bonding pad 415 are formed of a copper layer, the copper via and the copper pad are bonded. Through such a process, the image sensor EX1 of FIG. 3 can be manufactured.

[0269] 17 and 18 are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention.

[0270] Specifically, in Figures 17 and 18, the contents described in Figures 3 and Figures 14 to 16 will be briefly described or omitted. Referring to Figure 17, the top layer 200 and the first intermediate layer 300 bonded as described in Figure 14 above are prepared. The top layer 200 is bonded onto the first intermediate layer 300. The first intermediate layer 300 includes the second substrate 301, a plurality of second transistors 305, a second back bonding through via 307, a second wiring layer 311, a second contact plug 309, a second front bonding pad 315, a second via plug 313, and a second insulating layer 317 as described above.

[0271] 15 above, the second intermediate layer 400 is prepared. The second intermediate layer 400 includes a third substrate 401, a plurality of third transistors 409, a third through via 405, a third backside bonding pad 407, a third wiring layer 411, a third contact plug 413, a third frontside bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0272] The second back-side bonding through via 307 constituting the first intermediate layer 300 is bonded in the direction of the arrow to the third front-side bonding pad 415 constituting the second intermediate layer 400. The second substrate 301 and the second insulating layer 317 constituting the first intermediate layer 300 are bonded in the direction of the arrow to the third insulating layer 417 constituting the second intermediate layer 400. When the second back-side bonding through via 307 and the third front-side bonding pad 415 are formed of a copper layer, the copper via and the copper pad are bonded.

[0273] 18, the top layer 200, the first intermediate layer 300, and the second intermediate layer 400 are prepared, which are bonded as described in FIG 17. The first intermediate layer 300 and the top layer 200 are bonded onto the second intermediate layer 400. As described above, the second intermediate layer 400 includes the third substrate 401, a plurality of third transistors 409, the third through vias 405, the third back bonding pads 407, the third wiring layer 411, the third contact plugs 413, the third front bonding pads 415, the third via plugs 414, and the third insulating layer 417.

[0274] A bottom layer 500 is prepared. The bottom layer 500 includes a fourth substrate 501, a plurality of fourth transistors 502, a fourth wiring layer 503, a fourth contact plug 505, a fourth front bonding pad 507, a fourth via plug 506, and a fourth insulating layer 509. The fourth substrate 501 includes a fourth front surface 501f and a fourth back surface 401b facing the fourth front surface 501f.

[0275] The third rear bonding pad 407 constituting the second intermediate layer 400 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500 in the direction of the arrow. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400 are bonded to the fourth insulating layer 509 constituting the bottom layer 500 in the direction of the arrow. If the third rear bonding pad 407 and the fourth front bonding pad 507 are formed of a copper layer, the copper pads are bonded to each other. Through such a process, the image sensor EX1 of FIG. 3 can be manufactured.

[0276] 19 to 21 are cross-sectional views illustrating a method for manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention.

[0277] 19 to 21, the contents described in FIG. 3 and FIG. 14 to FIG. 18 will be briefly described or omitted. Referring to FIG. 19, a first intermediate layer 300 is prepared. The first intermediate layer 300 includes a second substrate 301, a plurality of second transistors 305, a second back-side bonding through via 307, a second wiring layer 311, a second contact plug 309, a second front-side bonding pad 315, a second via plug 313, and a second insulating layer 317.

[0278] The second substrate 301 includes a second front surface 301f and a second rear surface 301b facing the second front surface 301f. A through via hole 303 penetrating the second front surface 301f and the second rear surface 301b is formed in the second substrate 301. A second rear surface bonding through via 307 insulated by a second insulating layer 317 is formed in the through via hole 303.

[0279] A second intermediate layer 400 is prepared. The second intermediate layer 400 includes a third substrate 401, a plurality of third transistors 409, a third through via 405, a third backside bonding pad 407, a third wiring layer 411, a third contact plug 413, a third frontside bonding pad 415, a third via plug 414, and a third insulating layer 417.

[0280] The third substrate 401 includes a third front surface 401f and a fourth rear surface 401b facing the third front surface 401f. A through via hole 403 is formed in the third substrate 401, penetrating the third front surface 401f and a part of the third rear surface 401b. A third through via 405 insulated by a third insulating layer 417 is formed in the through via hole 403. The third through via 405 is connected to a third rear surface bonding pad 407 via a third via plug 414.

[0281] The second back-side bonding through via 307 constituting the first intermediate layer 300 is bonded in the direction of the arrow to the third front-side bonding pad 415 constituting the second intermediate layer 400. The second substrate 301 and the second insulating layer 317 constituting the first intermediate layer 300 are bonded in the direction of the arrow to the third insulating layer 417 constituting the second intermediate layer 400. When the second back-side bonding through via 307 and the third front-side bonding pad 415 are formed of a copper layer, the copper via and the copper pad are bonded.

[0282] 20, a top layer 200 is prepared. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, and a first insulating layer 213. The first substrate 201 includes a first front surface 201f and a first back surface 201b facing the first front surface 201f. For convenience, the pixel isolation layer 215, the color filter 217, and the lens 219 described in FIG. 3 are not illustrated in FIG. 20.

[0283] 19, the bonded first intermediate layer 300 and second intermediate layer 400 are prepared. The first intermediate layer 300 is bonded onto the second intermediate layer 400. The top layer 200 is bonded onto the bonded first intermediate layer 300 in the direction of the arrow.

[0284] The first front bonding pad 209 constituting the top layer 200 is bonded in the direction of the arrow to the second front bonding pad 315 constituting the first intermediate layer 300. The first insulating layer 213 constituting the top layer 200 is bonded in the direction of the arrow to the second insulating layer 317 constituting the first intermediate layer 300. When the first front bonding pad 209 and the second front bonding pad 315 are formed of a copper layer, the copper pads are bonded to each other.

[0285] 21, the top layer 200, the first intermediate layer 300, and the second intermediate layer 400 are prepared, which are bonded as described in FIG 20. The first intermediate layer 300 and the top layer 200 are bonded onto the second intermediate layer 400. As described above, the second intermediate layer 400 includes the third substrate 401, a plurality of third transistors 409, the third through vias 405, the third back bonding pads 407, the third wiring layer 411, the third contact plugs 413, the third front bonding pads 415, the third via plugs 414, and the third insulating layer 417.

[0286] A bottom layer 500 is prepared. The bottom layer 500 includes a fourth substrate 501, a plurality of fourth transistors 502, a fourth wiring layer 503, a fourth contact plug 505, a fourth front bonding pad 507, a fourth via plug 506, and a fourth insulating layer 509. The fourth substrate 501 includes a fourth front surface 501f and a fourth back surface 501b facing the fourth front surface 501f.

[0287] The third rear bonding pad 407 constituting the second intermediate layer 400 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500 in the direction of the arrow. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400 are bonded to the fourth insulating layer 509 constituting the bottom layer 500 in the direction of the arrow. If the third rear bonding pad 407 and the fourth front bonding pad 507 are formed of a copper layer, the copper pads are bonded to each other. Through such a process, the image sensor EX1 of FIG. 3 can be manufactured.

[0288] Figures 22 and 23 are cross-sectional views for explaining a method for manufacturing the image sensor of Figure 3 according to one embodiment of the present invention. In Figures 22 and 23, the contents explained in Figure 3 and Figures 14 to 21 will be briefly explained or omitted.

[0289] 22, a first intermediate layer 300 is prepared. The first intermediate layer 300 includes a second substrate 301, a plurality of second transistors 305, a second backside bonding through via 307, a second wiring layer 311, a second contact plug 309, a second frontside bonding pad 315, a second via plug 313, and a second insulating layer 317.

[0290] The second substrate 301 includes a second front surface 301f and a second rear surface 301b facing the second front surface 301f. A through via hole 303 penetrating the second front surface 301f and the second rear surface 301b is formed in the second substrate 301. A second rear surface bonding through via 307 insulated by a second insulating layer 317 is formed in the through via hole 303.

[0291] The second intermediate layer 400 and the bottom layer 500 are prepared, which are bonded as described above. The third back bonding pad 407 constituting the second intermediate layer 400 is bonded to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400 are bonded to the fourth insulating layer 509 constituting the bottom layer 500.

[0292] The second back-side bonding through via 307 constituting the first intermediate layer 300 is bonded in the direction of the arrow to the third front-side bonding pad 415 constituting the second intermediate layer 400. The second insulating layer 317 and the second substrate 301 constituting the first intermediate layer 300 are bonded in the direction of the arrow to the third insulating layer 417 constituting the second intermediate layer 400. When the second back-side bonding through via 307 and the third front-side bonding pad 415 are formed of a copper layer, the copper via and the copper pad are bonded.

[0293] 23, a top layer 200 is prepared. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, and a first insulating layer 213. The first substrate 201 includes a first front surface 201f and a first back surface 201b facing the first front surface 201f. For convenience, the pixel isolation layer 215, the color filter 217, and the lens 219 described in FIG. 3 are not illustrated in FIG. 23.

[0294] The first intermediate layer 300, the second intermediate layer 400, and the bottom layer 500 are prepared, which are bonded as described in FIG. 22 above. The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300 in the direction of the arrow. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300 in the direction of the arrow. When the first front bonding pad 209 and the second front bonding pad 315 are formed of a copper layer, the copper pads are bonded to each other. Through such a process, the image sensor EX1 of FIG. 3 can be manufactured.

[0295] 24 and 25 are cross-sectional views illustrating a method for manufacturing the image sensor of FIG. 3 according to one embodiment of the present invention. In FIG. 24 and FIG. 25, the contents described in FIG. 3 and FIG. 14 to FIG. 23 are either briefly explained or omitted.

[0296] 24, a first intermediate layer 300 and a second intermediate layer 400 are prepared, which are bonded as described in FIG 19. The second back surface bonding through via 307 constituting the first intermediate layer 300 is bonded to a third front surface bonding pad 415 constituting the second intermediate layer 400. The second insulating layer 317 and the second substrate 301 constituting the first intermediate layer 300 are bonded to a third insulating layer 417 constituting the second intermediate layer 400.

[0297] A bottom layer 500 is prepared. The bottom layer 500 includes a fourth substrate 501, a plurality of fourth transistors 502, a fourth wiring layer 503, a fourth contact plug 505, a fourth front bonding pad 507, a fourth via plug 506, and a fourth insulating layer 509. The fourth substrate 501 includes a fourth front surface 501f and a fourth back surface 501b facing the fourth front surface 501f.

[0298] The third back bonding pad 407 constituting the second intermediate layer 400 is bonded in the direction of the arrow to the fourth front bonding pad 507 constituting the bottom layer 500. The third insulating layer 417 and the third substrate 401 constituting the second intermediate layer 400 are bonded in the direction of the arrow to the fourth insulating layer 509 constituting the bottom layer 500.

[0299] 25, a top layer 200 is prepared. The top layer 200 includes a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first front bonding pad 209, a first via plug 211, and a first insulating layer 213. The first substrate 201 includes a first front surface 201f and a first back surface 201b facing the first front surface 201f. For convenience, the pixel isolation layer 215, the color filter 217, and the lens 219 described in FIG. 3 are not illustrated in FIG. 25.

[0300] The first intermediate layer 300, the second intermediate layer 400, and the bottom layer 500 are prepared, which are bonded as described in FIG. 23 above. The first front bonding pad 209 constituting the top layer 200 is bonded to the second front bonding pad 315 constituting the first intermediate layer 300 in the direction of the arrow. The first insulating layer 213 constituting the top layer 200 is bonded to the second insulating layer 317 constituting the first intermediate layer 300 in the direction of the arrow. When the first front bonding pad 209 and the second front bonding pad 315 are formed of a copper layer, the copper pads are bonded to each other. Through such a process, the image sensor EX1 of FIG. 3 can be manufactured.

[0301] Although the present invention has been described above based on the embodiments shown in the drawings, these are merely illustrative, and a person skilled in the art will understand that various modifications, substitutions and equivalent other embodiments are possible from the above. It should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0302] 100 Image Sensor 110 pixel array 150 ADC circuit 160 CDS circuit 170 Counter Circuit 180 Data output circuit 181 Column Memory 200 Top Floor 201 First board 203 First transistor 209 1st front bond pad 217 Color Filter 219 Lens 300 First Middle Class 301 Second board 305 Second transistor 307 2nd backside bonded through via 307-3, 307-6, 307-8 2nd Rear Bond Pad 315 2nd front bond pad 400 Second Middle Class 401 3rd board 409 3rd transistor 405 3rd Through Via 407, 407-5, 407-7, 407-8 3rd Rear Bond Pad 407-2, 407-3, 407-4, 407-6 3rd Backside Bonding Through Via 415 3rd front bond pad 500 lowest level 501 4th board 502 4th transistor 507 4th front bond pad

Claims

1. a top layer including a photodiode constituting a pixel and a transfer transistor for transferring an electrical signal generated by the photodiode; a first intermediate layer bonded to the top layer under the top layer, the first intermediate layer including a plurality of capacitors connected to the first output node connected to the transfer transistor and a plurality of sampling transistors connected to the capacitors for switching the capacitors; a second intermediate layer bonded to the first intermediate layer under the first intermediate layer, the second intermediate layer having a source follower connected to the sampling transistor via a second output node; An image sensor comprising: a bottom layer bonded to the second intermediate layer below the second intermediate layer, in which an ADC circuit is disposed to receive and process a pixel signal output through the source follower.

2. 2. The image sensor of claim 1, further comprising: a floating diffusion node connected to the transfer transistor; a conversion gain transistor connected to the floating diffusion node; and a reset transistor connected to the conversion gain transistor, the first intermediate layer further comprising:

3. 2. The image sensor of claim 1, wherein the top layer includes a first front bonding pad, the first intermediate layer includes a second front bonding pad and a second rear bonding pad, the first front bonding pad of the top layer is bonded to the second front bonding pad or the second rear bonding pad of the first intermediate layer, and the first intermediate layer further includes a first connecting via plug connected to the second front bonding pad and a second wiring layer included in the first intermediate layer.

4. 2. The image sensor of claim 1, wherein the first intermediate layer includes a second front bonding pad, the second intermediate layer includes a third front bonding pad or a third back bonding through via, the second front bonding pad of the first intermediate layer is bonded to the third front bonding pad or the third back bonding through via of the second intermediate layer, and the first intermediate layer and the second intermediate layer further include a second connecting via plug that connects a second wiring layer included in the first intermediate layer and a third wiring layer included in the second intermediate layer.

5. 2. The image sensor of claim 1, wherein the second intermediate layer includes a third back surface bonding pad, a third back surface bonding through via, or a third front surface bonding pad, and the bottom layer includes a fourth front surface bonding pad, and the third back surface bonding pad, the third back surface bonding through via, or the third front surface bonding pad of the second intermediate layer is bonded to the fourth front surface bonding pad of the bottom layer.

6. a top layer including a photodiode constituting a pixel and a transfer transistor for transferring an electrical signal generated by the photodiode; a first intermediate layer bonded to the top layer and disposed under the top layer, the first intermediate layer including a source follower connected to the transfer transistor via a floating diffusion node; a second intermediate layer bonded to the first intermediate layer under the first intermediate layer, the second intermediate layer including a plurality of capacitors connected to the transfer transistor via a floating diffusion node and a plurality of conversion efficiency switching transistors connected to the capacitors for switching the capacitors; An image sensor comprising: a bottom layer bonded to the second intermediate layer below the second intermediate layer, in which an ADC circuit is disposed to receive and process a pixel signal output through the source follower.

7. a top layer including a photodiode constituting a pixel and a transfer transistor for transferring an electrical signal generated by the photodiode; a first intermediate layer bonded to the top layer and disposed below the top layer, the first intermediate layer including an ADC circuit connected to the transfer transistor and processing the electrical signal; a second intermediate layer bonded to the first intermediate layer under the first intermediate layer, the second intermediate layer including a plurality of capacitors connected to the transfer transistor via a floating diffusion node and a plurality of conversion efficiency switching transistors connected to the capacitors for switching the capacitors; an additional transistor for driving the pixel is disposed below the second intermediate layer; and a bottom layer bonded to the second intermediate layer.

8. 8. The image sensor of claim 7, further comprising: a source follower coupled to the transfer transistor; and a ramp signal generator configured to generate a ramp signal to be compared with a pixel signal generated by the source follower, the ramp signal generator being disposed in the first intermediate layer.

9. a top layer including a photodiode constituting a pixel and a transfer transistor for transferring an electrical signal generated by the photodiode; a first intermediate layer bonded to the top layer at a lower portion of the top layer, the first intermediate layer having a source follower connected to the transfer transistor via a first output node; a second intermediate layer bonded to the first intermediate layer under the first intermediate layer, the second intermediate layer including a plurality of capacitors connected to the source followers and a plurality of sampling transistors connected to the capacitors for switching the capacitors; An image sensor comprising: a bottom layer bonded to the second intermediate layer below the second intermediate layer, in which an ADC circuit is disposed to receive and process a pixel signal output through the source follower.

10. a top layer including a photodiode constituting a pixel and a transfer transistor for transferring an electrical signal generated by the photodiode; a first intermediate layer bonded to the top layer under the top layer, the first intermediate layer including a plurality of capacitors connected to the transfer transistors via floating diffusion nodes and a plurality of conversion efficiency switching transistors connected to the capacitors for switching the capacitors; a second intermediate layer bonded to the first intermediate layer under the first intermediate layer, the second intermediate layer including an ADC circuit connected to the transmission transistor and processing the electrical signal; an additional transistor for driving the pixel is disposed below the second intermediate layer; and a bottom layer bonded to the second intermediate layer.

Images