Semiconductor device

Abstract

To provide a semiconductor device which can hold a storage content even in the case where power is not supplied, and has no limit in the number of write times, and provide a manufacturing method of them.SOLUTION: A semiconductor device includes: a writing transistor 162(OS) that uses an oxide semiconductor, and has less leak current (an off-current) between a source and a drain in an off-state; and a non-volatile memory cell that contains a reading transistor 160 and a capacitative element 164 using a semiconductor material that is different from the writing transistor. A writing and re-writing to information to the memory cell are performed by holding an electric charge of a predetermined amount to a node by turning on the writing transistor, supplying an electric potential to one of the source electrode and the drain electrode of the writing transistor, and a node FG to which one of electrodes of a capacitative element and the gate electrode of the writing transistor are electrically connected, and after that, tuning off the writing transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a method for manufacturing the same.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile ones in which stored contents are lost when power supply is cut off and non-volatile ones in which stored contents are retained even when power supply is cut off.

[0003] As a typical example of a volatile memory device, there is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting transistors constituting a memory element and accumulating charges in a capacitor.

[0004] From the above principle, in DRAM, since the charges in the capacitor are lost when information is read out, a rewrite operation is required again every time information is read. Also, due to leakage current (off-current) between the source and drain in the off state of the transistors constituting the memory element, etc., charges flow out or in even when the transistor is not selected, so the retention period of data (information) is short. For this reason, a rewrite operation (refresh operation) is required at a predetermined cycle, and it is difficult to sufficiently reduce power consumption. Also, since stored contents are lost when power supply is cut off, another memory device using a magnetic material or an optical material is required for long-term retention of memory.

[0005] Another example of a volatile memory device is SRAM (Static Random Access ​There is (Memory). SRAM uses circuits such as flip - flops to store the stored content and does not require a refresh operation, which is advantageous over DRAM in this regard However, since circuits such as flip - flops are used, there is a problem that the unit price per storage capacity becomes high Also, in terms of the stored content being lost when the power supply is cut off, there is no difference from DRAM

[0006] A typical example of a non - volatile memory device is flash memory. Flash memory has a floating gate between the gate electrode and the channel - forming region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi - permanent), and it has the advantage that the refresh operation required for volatile memory devices is not necessary (see, for example, Patent Document 1) However, the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated during writing, resulting in a problem that the memory element stops functioning after a predetermined number of writes

[0007] To mitigate the influence of this problem, for example, a method of equalizing the number of writes of each memory element is adopted. However, to achieve this, complex peripheral circuits are required Thus, even if such a method is adopted, the fundamental problem of lifespan is not solved That is, flash memory is not suitable for applications with a high frequency of information rewriting

[0008] Also, to hold charges in the floating gate or to remove the charges, a high voltage is required, and a circuit for that is also required. Furthermore, the injection of charges ​​​​​​​​or the operation of removal requires a relatively long time, and it is not easy to speed up writing and erasing There is also such a problem.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, a new structure semiconductor device is provided that can retain the stored content even when no power is supplied and has no limit on the number of write operations. This is one of the objectives.

Means for Solving the Problems

[0011] In the invention disclosed in this specification and the like, a semiconductor device having a non-volatile memory cell including a writing transistor using an oxide semiconductor, a reading transistor using a semiconductor material different from that of the writing transistor, and a capacitive element is provided. Writing and rewriting information to the memory cell is performed by supplying a potential to a node where one of the source electrode or drain electrode of the writing transistor, one of the electrodes of the capacitive element, and the gate electrode of the reading transistor are electrically connected by turning on the writing transistor, and then holding a predetermined amount of charge in the node by turning off the writing transistor.

[0012] One aspect of the disclosed invention includes a first transistor, a second transistor, a capacitive element, ​​​​​​​​having a non-volatile memory cell including a first transistor and a second transistor, the first transistor and the second transistor are formed of different semiconductor materials, and the second transistor is formed of an oxide semiconductor and a first potential is supplied to a node where one of a source electrode or a drain electrode of the second transistor and one of the electrodes of the capacitor element are electrically connected to a gate electrode of the first transistor, so as to hold a predetermined amount of first charge at the node, and a first writing mode, and a second potential is supplied to the node holding the first charge, so as to hold a predetermined amount of second charge at the node, and a second writing mode, and is a semiconductor device having the same. Also, another aspect of the disclosed invention is a non-volatile memory cell including a first transistor, a second transistor, and a capacitor element, the first transistor and the second transistor are formed of different semiconductor materials, and the second transistor is formed of an oxide semiconductor, and by turning on the second transistor, a first potential is supplied to a node where one of a source electrode or a drain electrode of the second transistor and one of the electrodes of the capacitor element are electrically connected to a gate electrode of the first transistor, and then the second transistor is turned off, so as to hold a predetermined amount of first charge at the node, and a first writing mode, and by turning on the second transistor, a second potential is supplied to the node holding the first charge, and then the second transistor

[0013] is turned off, so as to hold a predetermined amount of second charge at the node, and a second writing mode, and is a semiconductor device having the same. Also, in the above semiconductor device, the off-current of the second transistor is the first transistor is formed of different semiconductor materials, and the second transistor is formed of an oxide semiconductor, and by turning on the second transistor, a first potential is supplied to a node where one of a source electrode or a drain electrode of the second transistor and one of the electrodes of the capacitor element are electrically connected to a gate electrode of the first transistor, and then the second transistor is turned off, so as to hold a predetermined amount of first charge at the node, and a first writing mode, and by turning on the second transistor, a second potential is supplied to the node holding the first charge, and then the second transistor is turned off, so as to hold a predetermined amount of second charge at the node, and a second writing mode, and is a semiconductor device having the same. is turned off, so as to hold a predetermined amount of first charge at the node, and a first writing mode, and by turning on the second transistor, a second potential is supplied to the node holding the first charge, and then the second transistor is turned off, so as to hold a predetermined amount of first charge at the node, and a first writing mode, and by turning on the second transistor, a second potential is supplied to the node holding the first charge, and then the second transistor is turned off, so as to hold a predetermined amount of second charge at the node, and a second writing mode, and is a semiconductor device having the same. is turned off, so as to hold a predetermined amount of second charge at the node, and a second writing mode, and is a semiconductor device having the same. is turned off, so as to hold a predetermined amount of second charge at the node, and a second writing mode, and is a semiconductor device having the same. is a semiconductor device.

[0014] Further, in the above semiconductor device, the off-current of the second transistor is the first transistor It is preferably lower than the off-current of the [object].

[0015] In the above semiconductor device, the switching speed of the first transistor is preferably greater than the switching speed of the second transistor. It is preferably greater than the switching speed of the second transistor.

[0016] In the above semiconductor device, the second transistor preferably includes a material having an energy gap greater than 3 eV. It is preferably composed of a material having an energy gap greater than 3 eV.

[0017] Note that in the above, a writing transistor with a small off-current is realized using an oxide semiconductor, but the disclosed invention is not limited to this. Materials capable of realizing off-current characteristics equivalent to those of an oxide semiconductor, such as wide-gap materials (Eg > 3 eV) including silicon carbide, may be applied. Note that in the above, a writing transistor with a small off-current is realized using an oxide semiconductor, but the disclosed invention is not limited to this. Materials capable of realizing off-current characteristics equivalent to those of an oxide semiconductor, such as wide-gap materials (Eg > 3 eV) including silicon carbide, may be applied. Note that in the above, a writing transistor with a small off-current is realized using an oxide semiconductor, but the disclosed invention is not limited to this. Materials capable of realizing off-current characteristics equivalent to those of an oxide semiconductor, such as wide-gap materials (Eg > 3 eV) including silicon carbide, may be applied. > 3 eV), etc., may be applied.

[0018] Note that in this specification, etc., a non-volatile memory cell refers to a memory cell capable of retaining information for a certain period or longer (at least 1 × 10 seconds or more, preferably 1 × 10 4 seconds or more) even in a state where no power is supplied. 6 seconds or more) even in a state where no power is supplied. seconds or more) even in a state where no power is supplied.

[0019] Note that in this specification, etc., terms such as "above" and "below" do not limit the positional relationship of components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", it excludes those including other components between the gate insulating layer and the gate electrode. Note that in this specification, etc., terms such as "above" and "below" do not limit the positional relationship of components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", it excludes those including other components between the gate insulating layer and the gate electrode. Note that in this specification, etc., terms such as "above" and "below" do not limit the positional relationship of components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", it excludes those including other components between the gate insulating layer and the gate electrode. Note that in this specification, etc., terms such as "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specifically mentioned, those with their upper and lower positions swapped are also included. Note that in this specification, etc., terms such as "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specifically mentioned, those with their upper and lower positions swapped are also included.

[0020] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0021] In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0022] Note that in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Note that in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Note that in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets.

[0023] For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions. For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions. For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

Advantages of the Invention

[0024] Since the off-current of a transistor using an oxide semiconductor is extremely small, by applying this transistor to a memory cell, it is possible to hold the stored information for an extremely long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so the power consumption of a semiconductor device including the memory cell Since the off-current of a transistor using an oxide semiconductor is extremely small, by applying this transistor to a memory cell, it is possible to hold the stored information for an extremely long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so the power consumption of a semiconductor device including the memory cell Since the off-current of a transistor using an oxide semiconductor is extremely small, by applying this transistor to a memory cell, it is possible to hold the stored information for an extremely long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so the power consumption of a semiconductor device including the memory cell Since the off-current of a transistor using an oxide semiconductor is extremely small, by applying this transistor to a memory cell, it is possible to hold the stored information for an extremely long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so the power consumption of a semiconductor device including the memory cell Power can be sufficiently reduced. Also, even when there is no power supply, the stored content can be retained over a long period of time.

[0025] In addition, the memory cell used in the semiconductor device according to the disclosed invention does not require a high voltage for writing information and has no problem of device degradation. For example, unlike conventional non-volatile memories, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, problems such as degradation of the gate insulating layer do not occur at all. That is, the memory cell according to the disclosed invention has no limit on the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information is not required.

[0026] In addition, transistors using materials other than oxide semiconductors can operate at a sufficiently high speed. Therefore, by combining this with a transistor using an oxide semiconductor, the high speed of the operation of the semiconductor device (for example, the information read operation) can be sufficiently ensured. Also, various circuits (logic circuits, drive circuits, etc.) that require high-speed operation can be preferably realized by transistors using materials other than oxide semiconductors.

[0027] In this way, by integrally providing a transistor using a semiconductor material other than an oxide semiconductor and a transistor using an oxide semiconductor, a semiconductor device having unprecedented characteristics can be realized.

Brief Description of the Drawings

[0028]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Mode for Carrying Out the Invention

[0029] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art can easily understand that various details can be changed. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. It is not construed as being limited to the description of the embodiments shown below.

[0030] Note that the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. Note that the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. It is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like.

[0031] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are attached to avoid confusion of components, and it is noted that they are not numerically limiting. Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are attached to avoid confusion of components, and it is noted that they are not numerically limiting.

[0032] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIG. 1. In the circuit diagram, the symbol OS may be attached together to indicate that it is a transistor using an oxide semiconductor. In the circuit diagram, the symbol OS may be attached together to indicate that it is a transistor using an oxide semiconductor. In the circuit diagram, the symbol OS may be attached together to indicate that it is a transistor using an oxide semiconductor.

[0033] The semiconductor device shown in FIG. 1(A-1) has a non-volatile memory cell including a transistor 160, a transistor 162, and a capacitive element 164. In FIG. 1(A-1), one of the source electrode or drain electrode of the transistor 162, one of the electrodes of the capacitive element 164, and the gate electrode of the transistor 160 are electrically connected. Also, the first wiring (also called the source line: 1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (also called the bit line: 2nd Line) and the drain electrode of the transistor 160 are electrically connected. Also, the third wiring (3rd Line: The semiconductor device shown in FIG. 1(A-1) has a non-volatile memory cell including a transistor 160, a transistor 162, and a capacitive element 164. In FIG. 1(A-1), one of the source electrode or drain electrode of the transistor 162, one of the electrodes of the capacitive element 164, and the gate electrode of the transistor 160 are electrically connected. Also, the first wiring (also called the source line: 1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (also called the bit line: 2nd Line) and the drain electrode of the transistor 160 are electrically connected. Also, the third wiring (3rd Line: One of the source electrode or drain electrode of the transistor 162, one of the electrodes of the capacitive element 164, and the gate electrode of the transistor 160 are electrically connected. Also, the first wiring (also called the source line: 1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (also called the bit line: 2nd Line) and the drain electrode of the transistor 160 are electrically connected. Also, the third wiring (3rd Line: One of the source electrode or drain electrode of the transistor 162, one of the electrodes of the capacitive element 164, and the gate electrode of the transistor 160 are electrically connected. Also, the first wiring (also called the source line: 1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (also called the bit line: 2nd Line) and the drain electrode of the transistor 160 are electrically connected. Also, the third wiring (3rd Line: 1st Line: also called the source line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line: also called the bit line) and the drain electrode of the transistor 160 are electrically connected. Also, the third wiring (3rd Line: (also referred to as the first signal line) and the other of the source electrode or the drain electrode of transistor 162 is electrically connected to the fourth wiring (4th Line: also referred to as the second signal line), and the gate electrode of transistor 162 is electrically connected. And the fifth wiring (5 th Line: also referred to as the word line) and the other of the electrodes of the capacitor element 164 are electrically connected to each other.

[0034] Here, a transistor using an oxide semiconductor is applied to transistor 162. The transistor using an oxide semiconductor has the characteristic that the leakage current (off-state current) between the source and the drain in the off state is extremely small. Therefore, by setting transistor 162 to the off state, one of the source electrode or the drain electrode of transistor 162, one of the electrodes of the capacitor element 164, and the gate electrode of transistor 160 are electrically connected to form a node (hereinafter, node FG), and the potential of node FG can be held for an extremely long time. And by having the capacitor element 164, it becomes easy to hold the charge given to node FG, and it also becomes easy to read the held information.

[0035] Also, there is no off-current limitation for transistor 160. In order to increase the operating speed of the memory cell, a transistor with a faster switching speed than transistor 162 (for example, a larger value of field-effect mobility) is used. That is, a transistor using a semiconductor material other than an oxide semiconductor is applied to transistor 160. Note that depending on the semiconductor material selected, the off-current of transistor 160 may be higher than the off-current of transistor 162. Examples of the semiconductor material used for transistor 160 include silicon, germanium, ... It is possible to use magnesium, silicon germanium, silicon carbide, gallium arsenide, etc., and it is preferable to use a single crystal semiconductor. A transistor 160 using such a semiconductor material can read the stored information at high speed. In the semiconductor device shown in Fig. 1(A-1), by taking advantage of the feature that the potential of node FG can be held, it is possible to set a write mode and a read mode. In the write mode for storing information in the memory cell, first, the potential of the fourth wiring is set to a potential at which transistor 162 is turned on, and transistor 162 is turned on.

[0036] In this way, the potential of the third wiring is supplied to node FG, and a predetermined amount of charge is accumulated in node FG. Here, it is assumed that either of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is given. Thereafter, the potential of the fourth wiring is set to a potential at which transistor 162 is turned off, and transistor 162 is turned off. As a result, node FG becomes a floating state, and a predetermined charge remains held in node FG.

[0037] As described above, by accumulating and holding a predetermined amount of charge in node FG, information can be stored in the memory cell (write mode). Since the off-current of transistor 162 is extremely small, the charge supplied to node FG is held for a long time. Therefore, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, and the power consumption can be sufficiently reduced.

[0038] This is achievable. Also, even when there is no power supply, the memory content can be retained over a long period of time. This is possible.

[0039] In the read mode for reading the information stored in the memory cell, with a predetermined potential (constant potential) applied to the first wiring, when an appropriate potential (read potential) is applied to the fifth wiring, the transistor 160 assumes different states according to the amount of charge held at the node FG. Generally, when the transistor 160 is an n-channel type, the apparent threshold voltage V of the transistor 160 when a high-level charge is held at the node FG is lower than the apparent threshold voltage V th_H of the transistor 160 when a low-level charge is held at the node FG. Here, the apparent threshold voltage refers to the potential of the fifth wiring required to turn the transistor 160 t h_L into the "on state". Therefore, by setting the potential of the fifth wiring to an intermediate potential V between V and V th_H and V th_L to V 0 , the charge held at the node FG can be discriminated. For example, in the write mode, when a high-level charge is applied, if the potential of the fifth wiring becomes V 0 (>V th_H ), the transistor 160 will be in the "on state". When a low-level charge is applied, even if the potential of the fifth wiring becomes V 0 (<V th_L ), the transistor 160 remains in the "off state". Therefore, by controlling the potential of the fifth wiring to read the on state or off state of the transistor 160 (read the potential of the second wiring), the stored information can be read. Can be output (read mode).

[0040] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. When the information of the memory cell is not read, a potential such that the transistor 160 is in the "off state" regardless of the state of the node FG, that is, a potential smaller than V may be applied to the fifth wiring. Or, a potential such that the transistor 160 is in the "on state" regardless of the state of the node FG, that is, a potential larger than V th_H may be applied to the fifth wiring. may be applied to the fifth wiring. th_L Larger potential may be applied to the fifth wiring.

[0041] Also, when rewriting the information stored in the memory cell, by supplying a new potential to the node FG that has held a predetermined amount of charge by the above write mode a charge related to new information is held in the node FG. Specifically, the potential of the fourth wiring is set to a potential at which the transistor 162 is in the on state, and the transistor 162 is turned on. As a result the potential of the third wiring (the potential related to the new information) is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Then, the potential of the fourth wiring is set to a potential at which the transistor 162 is in the off state and the transistor 162 is turned off, so that a charge related to new information is held in the node FG. That is, in a state where a predetermined amount of charge is held in the node FG by the write mode (the first write mode), by performing the same operation as the write mode (the second write mode), the information stored in the memory cell can be overwritten. That is, in a state where a predetermined amount of charge is held in the node FG by the write mode (the first write mode), by performing the same operation as the write mode (the second write mode), the information stored in the memory cell can be overwritten. a charge related to new information is held in the node FG. That is, in a state where a predetermined amount of charge is held in the node FG by the write mode (the first write mode), by performing the same operation as the write mode (the second write mode), the information stored in the memory cell can be overwritten. and the information stored in the memory cell can be overwritten. is possible.

[0042] Thus, the semiconductor device according to the disclosed invention can directly rewrite information by writing the information again. Therefore, it is not necessary to extract charges from the floating gate using a high voltage required in a flash memory or the like, and it is possible to suppress a decrease in the operating speed caused by the erasing operation. That is, high-speed operation of the semiconductor device is realized.

[0043] Note that the source electrode or the drain electrode of the transistor 162 functions equivalently to the floating gate of a floating gate type transistor used as a non-volatile memory element by being electrically connected to the gate electrode of the transistor 160. When the transistor 162 is in the off state, the node FG can be seen as being embedded in the insulator (so-called floating state), and charges are held in the node FG. The off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charges accumulated in the node FG due to the leakage of the transistor 162. That is, the transistor 162 using an oxide semiconductor can realize a non-volatile storage device capable of holding information without power supply.

[0044] For example, when the off-current of the transistor 162 at room temperature is 10 zA (1 zA (zeptoampere) is 1 × 10 -21 A) or less and the capacitance value of the capacitor element 164 is about 10 fF, data can be held for at least 10 4 seconds or more. Note that it goes without saying that the holding time varies depending on the transistor characteristics and the capacitance value.

[0045] In a conventional floating gate transistor, during writing (rewriting), since charges move through the gate insulating film (tunnel insulating film), deterioration of the gate insulating film (tunnel insulating film) was inevitable. However, in the semiconductor device shown in this embodiment, due to the switching operation of transistor 162, only the movement of charges between the third wiring and node FG occurs, so that deterioration of the gate insulating film, which has been a conventional problem, can be eliminated. This means that there is no theoretical limit on the number of write operations, and the rewrite endurance is extremely high. In addition, the high voltage that was required for writing and erasing in conventional floating gate transistors is also unnecessary.

[0046] The semiconductor device shown in FIG. 1(A-1) can be considered as shown in FIG. 1(A-2) assuming that elements such as transistors constituting the semiconductor device include resistors and capacitors. That is, in FIG. 1(A-2), it is considered that transistor 160 and capacitor element 164 are each configured to include a resistor and a capacitor. R1 and C1 are the resistance value and capacitance value of capacitor element 164, respectively, and the resistance value R1 corresponds to the resistance value due to the insulating layer constituting capacitor element 164. Also, R2 and C2 are the resistance value and capacitance value of transistor 160, respectively, and the resistance value R2 corresponds to the resistance value due to the gate insulating layer when transistor 160 is in the on state, and the capacitance value C2 corresponds to the so-called gate capacitance (the capacitance formed between the gate electrode and the source electrode and / or drain electrode, and the capacitance formed between the gate electrode and the channel formation region).

[0047] ​When the transistor 162 is in the off state, the resistance value between the source electrode and the drain electrode (also called the effective resistance) is defined as ROS. When the gate leakage of the transistor 162 is sufficiently small and R1 and R2 satisfy the conditions that R1 is greater than or equal to ROS and R2 is greater than or equal to ROS, the charge holding period (which can also be called the information holding period) is mainly determined by the off-current of the transistor 162. Conversely, when the above conditions are not met, even if the off-current of the transistor 162 is sufficiently small, it becomes difficult to ensure a sufficient holding period. This is because leakage currents other than the off-current of the transistor 162 (for example, leakage currents generated between the source electrode and the gate electrode) are large. Therefore, it can be said that it is desirable that the semiconductor device disclosed in this embodiment satisfies the above relationship. On the other hand, it is desirable that C1 and C2 satisfy the relationship that C1 is greater than or equal to C2. By increasing C1, when controlling the potential of the node FG by the fifth wiring (for example, at the time of reading), the fluctuation of the potential of the fifth wiring can be suppressed to a low level. By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layers of the transistors 160 and 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship. In the semiconductor device shown in this embodiment, the node FG is a floating gate of a flash memory or the like.

[0048] Conversely, when the above conditions are not satisfied, even if the off-current of the transistor 162 is sufficiently small, it becomes difficult to ensure a sufficient holding period. This is because leakage currents other than the off-current of the transistor 162 (for example, leakage currents generated between the source electrode and the gate electrode) are large. Therefore, it can be said that it is desirable that the semiconductor device disclosed in this embodiment satisfies the above relationship. On the other hand, it is desirable that C1 and C2 satisfy the relationship that C1 is greater than or equal to C2. By increasing C1, when controlling the potential of the node FG by the fifth wiring (for example, at the time of reading), the fluctuation of the potential of the fifth wiring can be suppressed to a low level. By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layers of the transistors 160 and 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship. In the semiconductor device shown in this embodiment, the node FG is a floating gate of a flash memory or the like. By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layers of the transistors 160 and 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship.

[0049] On the other hand, it is desirable that C1 and C2 satisfy the relationship that C1 is greater than or equal to C2. By increasing C1, when controlling the potential of the node FG by the fifth wiring (for example, at the time of reading), the fluctuation of the potential of the fifth wiring can be suppressed to a low level. By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layers of the transistors 160 and 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship. In the semiconductor device shown in this embodiment, the node FG is a floating gate of a flash memory or the like.

[0050] By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layers of the transistors 160 and 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship. R1 and R2 are controlled by the gate insulating layers of the transistors 160 and 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship. In the semiconductor device shown in this embodiment, the node FG is a floating gate of a flash memory or the like.

[0051] In the semiconductor device shown in this embodiment, the node FG is a floating gate of a flash memory or the like. It has the same function as the floating gate of a finFET transistor, but the node FG in the present embodiment has characteristics that are essentially different from those of the floating gate of a flash memory or the like. In a flash memory, since the voltage applied to the control gate is high, in order to prevent the influence of that potential from reaching the floating gates of adjacent cells, it is necessary to maintain a certain distance between cells. This is one of the factors that hinders the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of applying a high electric field to generate a tunnel current.

[0052] Also, due to the above principle of flash memory, the deterioration of the insulating film progresses, and another problem of the write cycle limit (about 10,000 times) occurs.

[0053] The semiconductor device according to the disclosed invention operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by the tunnel current as described above. That is, it is not necessary to apply a high electric field for injecting charges like a flash memory. As a result, since it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, the distance between cells can be narrowed, and high integration becomes easy.

[0054] Also, since the principle of charge injection by the tunnel current is not used, there is no cause of deterioration of the memory cell. That is, it has high durability and reliability compared to flash memory.

[0055] Also, the fact that a high electric field is not required and a large peripheral circuit (such as a boost circuit) is not required is also a point of ​​​​​​​Advantages for the shared memory.

[0056] In addition, when the relative dielectric constant εr1 of the insulating layer forming the capacitance element 164 is made different from the relative dielectric constant εr2 of the insulating layer forming the transistor 160, while the area S1 of the insulating layer forming the capacitance element 164 and the area S2 of the insulating layer forming the gate capacitance in the transistor 160 satisfy 2·S2 ≥ S1 (preferably S2 ≥ S1), it is easy to realize C1 > C2. That is, while reducing the area of the insulating layer forming the capacitance element 164, it is possible to realize C1 > C2. Specifically, for example, in the insulating layer forming the capacitance element 164, a film made of a high dielectric constant (high-k) material such as hafnium oxide, or a laminated structure of a film made of a high dielectric constant (high-k) material such as hafnium oxide and a film made of an oxide semiconductor is adopted to make εr1 ≥ 10, preferably εr1 ≥ 15, and in the insulating layer forming the gate capacitance, silicon oxide is adopted to make εr2 = 3 - 4. By using such a configuration together, further high integration of the semiconductor device according to the disclosed invention is possible.

[0057]

[0058] Note that the above description is for the case of using an n-type transistor (n-channel transistor) in which electrons are majority carriers, but it goes without saying that a p-type transistor (p-channel transistor) in which holes are majority carriers can be used instead of the n-type transistor.

[0059] As described above, a semiconductor device according to one aspect of the disclosed invention has a source and a drain in an off state. A write transistor with low leakage current (off-current) between gates, a read transistor using a semiconductor material different from that of the write transistor, and a non-volatile memory cell including a capacitive element. has a non-volatile

[0060] The off-current of the write transistor is 100 zA ( 1×10 -19 A) or less, preferably 10 zA (1×10 -20 A) or less, more preferably 1 zA (1×10 -21 A) or less at the temperature during use (for example, 25°C). It is difficult to obtain such a low off-current with a normal silicon semiconductor, but it can be achieved in a transistor obtained by processing an oxide semiconductor under appropriate conditions. Therefore, it is preferable to use a transistor including an oxide semiconductor as the write transistor. Furthermore, a transistor using an oxide semiconductor has a small subthreshold swing value (S value), so it is possible to sufficiently increase the switching speed even if the mobility is relatively low. Therefore, by using the transistor as the write transistor, the rise of the write pulse applied to the node FG can be made extremely steep. Also, since the off-current is small, it is possible to reduce the amount of charge held in the node FG.

[0061] That is, by using a transistor using an oxide semiconductor as the write transistor, information can be rewritten at high speed. As for the read transistor, there is no limitation on the off-current, but in order to increase the read speed, it is preferable to use a transistor that operates at high speed. For example, for the read As for the read transistor, there is no limitation on the off-current, but in order to increase the read speed, it is preferable to use a transistor that operates at high speed. For example, for the read As for the read transistor, there is no limitation on the off-current, but in order to increase the read speed, it is preferable to use a transistor that operates at high speed. For example, for the read As for the read transistor, there is no limitation on the off-current, but in order to increase the read speed, it is preferable to use a transistor that operates at high speed. For example, for the read As for the read transistor, there is no limitation on the off-current, but in order to increase the read speed, it is preferable to use a transistor that operates at high speed. For example, for the read

[0062] As for the read transistor, there is no limitation on the off-current, but in order to increase the read speed, it is preferable to use a transistor that operates at high speed. For example, for the read read, in order to increase the speed, it is preferable to use a transistor that operates at high speed. For example, for the read It is preferable to use a transistor with a switching speed of 1 nanosecond or less as the writing transistor. Preferably.

[0063] Writing information to the memory cell is achieved by turning on the writing transistor, supplying a potential to a node where one of the source electrode or drain electrode of the writing transistor, one of the electrodes of the capacitive element, and the gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor to hold a predetermined amount of charge at the node. Here, since the off-current of the writing transistor is extremely small, the charge supplied to the node is held for a long time. If the off-current is substantially 0, for example, the refresh operation required in a conventional DRAM becomes unnecessary, or the frequency of the refresh operation can be made extremely low (for example, about once a month to once a year), and the power consumption of the semiconductor device can be sufficiently reduced. Also, information can be directly rewritten by rewriting the information to the memory cell again. For this reason, the erasing operation required in a flash memory or the like is unnecessary, and the decrease in the operating speed due to the erasing operation can be suppressed. That is, high-speed operation of the semiconductor device is realized. Also, since a high voltage required for writing and erasing in a conventional floating-gate type transistor is not required, the power consumption of the semiconductor device can be further reduced. The maximum value of the voltage applied to the memory cell according to this embodiment (the difference between the maximum and minimum values of the potentials simultaneously applied to each terminal of the memory cell) is two levels (1

[0064] Furthermore, information can be directly rewritten by rewriting the information to the memory cell again. This makes the erasing operation required in a flash memory or the like unnecessary, and the decrease in the operating speed due to the erasing operation can be suppressed. That is, high-speed operation of the semiconductor device is realized. Also, since a high voltage required for writing and erasing in a conventional floating-gate type transistor is not required, the power consumption of the semiconductor device can be further reduced. The maximum value of the voltage applied to the memory cell according to this embodiment (the difference between the maximum and minimum values of the potentials simultaneously applied to each terminal of the memory cell) is two levels (1 When writing and erasing, it does not require the high voltage required by a conventional floating-gate type transistor, so the power consumption of the semiconductor device can be further reduced. The maximum value of the voltage applied to the memory cell according to this embodiment (the difference between the maximum and minimum values of the potentials simultaneously applied to each terminal of the memory cell) is two levels (1 When writing and erasing, it does not require the high voltage required by a conventional floating-gate type transistor, so the power consumption of the semiconductor device can be further When writing information of (bits), in one memory cell, it is 5V or less, preferably 3V or less.

[0065] The memory cell arranged in the semiconductor device according to the disclosed invention only needs to include at least a writing transistor, a reading transistor, and a capacitive element. Also, even if the area of the capacitive element is small, it can operate. Therefore, the area per memory cell can be made sufficiently small compared to, for example, SRAM that requires six transistors per memory cell, and memory cells can be arranged at high density in the semiconductor device .

[0066] Also, in a conventional floating gate transistor, since charge moves through the gate insulating film (tunnel insulating film) during writing, deterioration of the gate insulating film (tunnel insulating film) was inevitable. However, in the memory cell according to one aspect of the present invention, information is written by holding a predetermined amount of charge at the node by the switching operation of the writing transistor, so that deterioration of the gate insulating film, which has been a conventional problem, can be eliminated . This means that there is no theoretical limit on the number of write operations, and the write endurance is extremely high . For example, the memory cell according to one aspect of the present invention shows no deterioration in current-voltage characteristics even after 1 × 10 times ( one billion times) or more of writing. 9 times ( one billion times) or more of writing.

[0067] Furthermore, when using a transistor using an oxide semiconductor as the writing transistor of the memory cell , the oxide semiconductor has a large energy gap of 3.0 to 3.5 eV and heat There may be extremely few exciting carriers. For example, even in a high-temperature environment of 150 ° C, there is no deterioration in the current-voltage characteristics of the memory cell. No deterioration is observed.

[0068] As a result of intensive research, the inventors have found that a transistor using an oxide semiconductor does not deteriorate in characteristics even at a high temperature of 150 ° C, and has an extremely small off-current of 100 zA or less at room temperature. For the first time, it has been found that it has excellent characteristics. One aspect of the disclosed invention is to apply a transistor having such excellent characteristics as a writing transistor of a memory cell, and to provide a semiconductor device having unprecedented characteristics. Note that the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0069]

[0070] (Embodiment 2) In this embodiment, an application example of the semiconductor device shown in the previous embodiment will be described with reference to FIGS. 2 and 3.

[0071] FIGS. 2(A) and 2(B) are circuit diagrams of a semiconductor device formed by using a plurality of semiconductor devices (hereinafter also referred to as memory cell 190) shown in FIG. 1(A-1). FIG. 2(A) is a circuit diagram of a so-called NAND-type semiconductor device in which memory cells 190 are connected in series, and FIG. 2(B) is a circuit diagram of a so-called NOR-type semiconductor device in which memory cells 190 are connected in parallel.

[0072] The semiconductor device shown in FIG. 2(A) includes a source line SL, a bit line BL, a first signal line S1, a plurality of second signal lines S2, a plurality of word lines WL, and a plurality of memory cells 190. FIG. 2(A ) has a configuration with one source line SL and one bit line BL each, but it is not limited to this, and a configuration with a plurality of source lines SL and bit lines BL may be used.

[0073] In each memory cell 190, one of the gate electrode of the transistor 160, the source electrode or the drain electrode of the transistor 162 and one of the electrodes of the capacitor element 164 are electrically connected. Also, the first signal line S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected, and the second signal line S2 and the gate electrode of the transistor 162 are electrically connected. And the word line WL and the other of the electrodes of the capacitor element 164 are electrically connected.

[0074] Also, the source electrode of the transistor 160 included in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 of the adjacent memory cell 190, and the drain electrode of the transistor 160 included in the memory cell 190 is electrically connected to the source electrode of the transistor 160 of the adjacent memory cell 190. However, among a plurality of memory cells connected in series, the drain electrode of the transistor 160 included in the memory cell 190 provided at one end is electrically connected to the bit line. Also, among a plurality of memory cells connected in series, the source electrode of the transistor 160 included in the memory cell 190 provided at the other end is electrically connected to the source line.

[0075] The semiconductor device shown in FIG. 2(A) performs a write operation and a read operation for each row. The write operation is performed as follows. Transistor 1 is connected to the second signal line S2 of the row where writing is to be performed. Apply a potential that turns on 62, and turn on the transistor 162 of the row where writing is to be performed. Thereby, the potential of the first signal line S1 is applied to the gate electrode of the transistor 160 of the specified row, and a predetermined charge is applied to the gate electrode. In this way, data can be written into the memory cells of the specified row.

[0076] Also, the read operation is performed as follows. First, to the word lines WL other than the row where reading is to be performed, regardless of the charge on the gate electrode of the transistor 160, apply a potential that turns on the transistor 160, and turn on the transistors 160 other than the row where reading is to be performed. Then, to the word line WL of the row where reading is to be performed, apply a potential (read potential) such that the on state or off state of the transistor 160 is selected by the charge on the gate electrode of the transistor 160. Then, apply a constant potential to the source line SL and put the read circuit (not shown) connected to the bit line BL into an operating state. Here, since the plurality of transistors 160 between the source line SL and the bit line BL are in the on state except for the row where reading is to be performed, the conductance between the source line SL and the bit line BL is determined by the state of the transistor 160 of the row where reading is to be performed. That is, depending on the charge on the gate electrode of the transistor 160 of the row where reading is to be performed, the potential of the bit line BL read by the read circuit takes different values. In this way, data can be read from the memory cells of the specified row.

[0077] The semiconductor device shown in FIG. 2(B) has a plurality of source lines SL, bit lines BL, first signal lines S1, second signal lines S2, and word lines WL, and has a plurality of memory cells 190. 。The gate electrode of each transistor 160 is electrically connected to one of the source electrode or the drain electrode of the transistor 162 and one of the electrodes of the capacitor element 164. Also, the source line SL is electrically connected to the source electrode of the transistor 160, and the bit line BL is electrically connected to the drain electrode of the transistor 160. Further, the first signal line S 1 is electrically connected to the other of the source electrode or the drain electrode of the transistor 162, and the second signal line S2 is electrically connected to the gate electrode of the transistor 162. And the word line WL and the other electrode of the capacitor element 164 are electrically connected.

[0078] The semiconductor device shown in FIG. 2(B) performs a write operation and a read operation for each row. The write operation is performed in the same manner as the semiconductor device shown in FIG. 2(A) described above. The read operation is performed as follows. First, a potential is applied to the word lines WL other than the row for which reading is to be performed so that the transistor 160 is turned off regardless of the charge on the gate electrode of the transistor 160, and the transistors 160 other than the row for which reading is to be performed are turned off. Then, a potential (read potential) is applied to the word line WL of the row for which reading is to be performed such that the on state or the off state of the transistor 160 is selected by the charge on the gate electrode of the transistor 160. Then, a fixed potential is applied to the source line SL, and a read circuit (not shown) connected to the bit line BL is brought into an operating state. Here, the conductance between the source line SL and the bit line BL is determined by the state of the transistor 160 in the row for which reading is to be performed. That is, The potential of the bit line BL read by the circuit takes different values. In this way, data can be read from the memory cells in the specified row.

[0079] Next, an example of a read circuit that can be used in a semiconductor device shown in FIG. 2 will be described with reference to FIG. 3.

[0080] FIG. 3(A) shows a schematic of the read circuit. The read circuit includes a transistor and a sense amplifier circuit.

[0081] At the time of reading, terminal A is connected to the bit line to which the memory cell performing the reading is connected. Also, a bias potential Vbias is applied to the gate electrode of the transistor, and the potential of terminal A is controlled.

[0082] Memory cell 190 exhibits different resistance values depending on the data stored therein. Specifically, when the transistor 160 of the selected memory cell 190 is in the on state, it is in a low-resistance state, and when the transistor 160 of the selected memory cell 190 is in the off state, it is in a high-resistance state.

[0083] When memory cell 190 is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier outputs a potential (data "1") corresponding to the potential of terminal A. On the other hand, when memory cell 190 is in the low-resistance state, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "0") corresponding to the potential of terminal A.

[0084] In this way, by using the read circuit, data can be read from memory cell 190. Note that the read circuit of this embodiment is an example. Other known circuits can also be used. ​​​​​​​​​​​​ Good. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected. It may be configured such that a reference bit line is connected.

[0085] FIG. 3(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has an input terminal Vin(+), an input terminal Vin(−), and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(−). If Vin(+) > Vin(−), Vout is generally a High output, and if Vin(+) < Vin(−), Vout is generally a Low output. When the differential sense amplifier is used in a read circuit, one of Vin(+) and Vin(−) is connected to terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(−). amp has an input terminal Vin(+), an input terminal Vin(−), and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(−). If Vin(+) > Vin(−), Vout is generally a High output, and if Vin(+) < Vin(−), Vout is generally a Low output. When the differential sense amplifier is used in a read circuit, one of Vin(+) and Vin(−) is connected to terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(−). in(+) and Vin(−), and the reference potential Vref is applied to the other of Vin(+) and Vin(−). t is generally a High output, and if Vin(+) < Vin(−), Vout is generally a Low output. When the differential sense amplifier is used in a read circuit, one of Vin(+) and Vin(−) is connected to terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(−). output. When the differential sense amplifier is used in a read circuit, one of Vin(+) and Vin(−) is connected to terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(−). n(−) is connected to terminal A, and the reference potential Vref is applied to the other of Vin(+) and Vin(−). ef is applied.

[0086] FIG. 3(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2, an input terminal for a control signal Sp, and an input terminal for a control signal Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, the latch-type sense amplifier has input / output terminals V1 and V2, an input terminal for a control signal Sp, and an input terminal for a control signal Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, and the input terminal for the control signal Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, the power supply potential (Vdd) is cut off. Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, the comparison potentials V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, , one of V1 and V2 is connected to terminal A and the output terminal via a switch, and the other is given a reference potential Vref.

[0087] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0088] (Embodiment 3) In this embodiment, the configuration of a semiconductor device according to an aspect of the disclosed invention and its manufacturing method will be described with reference to FIGS. 7 to 9.

[0089] 〈Cross-sectional configuration and planar configuration of semiconductor device〉 FIG. 7 shows an example of the configuration of a semiconductor device. FIG. 7(A) shows the cross-section of the semiconductor device, and FIG. 7( B) shows the plan view of the semiconductor device. Here, FIG. 7(A) corresponds to the cross-section at A 1 - A2 and B1 - B2 of FIG. 7(B). The semiconductor device shown in FIGS. 7(A) and 7(B) has a transistor 160 using a semiconductor material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than that of the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics.

[0090] Note that although the above transistors are all described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, the technical essence of the disclosed invention is to use an oxide semiconductor for the transistor 162 in order to hold information. ​​​​​​​​​Since the purpose is to use the semiconductor device, it is not necessary to limit the specific configuration of the semiconductor device to that shown here. .

[0091] The transistor 160 in FIG. 7 is formed on a substrate 100 including a semiconductor material (e.g., silicon). 00 and a channel forming region 116 provided so as to sandwich the channel forming region 116. The impurity region 114 and the high-concentration impurity region 120 (collectively referred to as the impurity region) A gate insulating layer 108a is provided on the channel forming region 116, and a gate A gate electrode 110a provided on the insulating layer 108a is electrically connected to the impurity region. A source or drain electrode 130a and a source or drain electrode 130b has.

[0092] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Also, when viewed from a direction perpendicular to the surface of the substrate 100, the sidewall insulating layer 118 is not overlapped. The region having a high concentration impurity region 120 is a metal compound region adjacent to the high concentration impurity region 120. A material region 124 is formed on the substrate 100. The material region 124 surrounds the transistor 160. An isolation insulating layer 106 is provided, and an interlayer insulating layer 12 is provided to cover the transistor 160. 6 and an interlayer insulating layer 128 are provided. A source or drain electrode 130a, The source electrode or drain electrode 130b is formed by insulating interlayer 126 and insulating interlayer 1 Through the opening formed in the insulating film 28, the insulating film 28 is electrically connected to the metal compound region 124. Thus, the source electrode or drain electrode 130a and the source electrode or drain electrode 13 0b is a region between the high concentration impurity region 120 and the impurity region 114 via the metal compound region 124. is electrically connected. Further, the electrode 130c is electrically connected to the gate electrode 110a through an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. Note that the sidewall insulating layer 118 may not be formed for the integration of the transistor 160 or the like in some cases.

[0093] The transistor 162 in FIG. 7 includes a source electrode or drain electrode 142a provided on the interlayer insulating layer 128, and the source electrode or drain electrode 142b, and the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b are electrically connected to the oxide semiconductor layer 144 that is continued, and the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, a gate insulating layer 146 that covers the oxide semiconductor layer 144, and a gate electrode 148a provided so as to overlap the oxide semiconductor layer 144 on the gate insulating layer 146. Here, it is desirable that the oxide semiconductor layer 144 is highly purified by sufficiently removing impurities such as hydrogen and by sufficiently supplying oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10

[0094] atoms / cm or less, desirably 5×10 atoms / cm 19 or less, more desirably 5×10 atoms / cm 3 or less, and even more desirably 5×10 18 atoms / cm 3 or less, and most desirably 5×10 1 7 atoms / cm 3 or less. Note that the hydrogen concentration in the oxide semiconductor layer 144 described above is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spect rometry). It is measured by spectroscopy. Thus, in the oxide semiconductor layer 144 where the hydrogen concentration is sufficiently reduced to achieve high purity and the defect levels in the energy gap due to oxygen deficiency are reduced by sufficient supply of oxygen, the carrier concentration is less than 1×10 / cm 12 ; preferably less than 1×10 3 / cm ; more preferably less than 1.45×10 11 / cm 3 . For example, the off-current at room temperature (here, the value per unit channel width (1 μm)) 10 is 100 zA / μm or less (1 zA (zeptoampere) is 1×10 3 A); preferably 10 zA / μm or less. Thus, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained . . -21 . . . .

[0095] Note that in the transistor 162 of FIG. 7, since the oxide semiconductor layer 144 is not processed into an island shape, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented .

[0096] The capacitor element 164 is composed of a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate insulating layer 146, and an electrode 148b. That is, the source electrode or the drain electrode 142a functions as one electrode of the capacitor element 164, and the electrode 148b functions as the other electrode of the capacitor element 164 . . .

[0097] Note that in the capacitor element 164 of FIG. 7, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, the insulation between the source electrode or the drain electrode 142a and the electrode 148b is achieved Sufficient properties can be ensured.

[0098] In the transistor 162 and the capacitive element 164, the source electrode or the drain electrode 142a and the ends of the source electrode or the drain electrode 142b are preferably in a tapered shape. Here, the taper angle is, for example, 30° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 1 42a) when observed from a direction perpendicular to the cross section (the plane perpendicular to the surface of the substrate). By forming the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b in a tapered shape, the coverage of the oxide

[0099] semiconductor layer 144 can be improved and step discontinuities can be prevented. Also, an interlayer insulating layer 150 is provided over the transistor 162 and the capacitive

[0100] <Method for manufacturing a semiconductor device> Next, an example of the method for manufacturing the above semiconductor device will be described. Hereinafter, first, the method for manufacturing the lower transistor 160 will be described with reference to FIG. 8, and then the method for manufacturing the upper transistor 162

[0101] <Method for manufacturing the lower transistor>

[0102] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 8(A)). As the substrate 100 containing a semiconductor material, a single-crystalline semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied . Here, as the substrate 100 including a semiconductor material, a case of using a single crystal silicon substrate will be shown as an example. In general, the "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification and the like, it is used as a concept including a substrate having a configuration in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the semiconductor layer included in the "SOI substrate" is not limited to a silicon semiconductor layer. Also, the SOI substrate includes those having a configuration in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate .

[0103] A protective layer 102 serving as a mask for forming an element isolation insulating layer is formed on the substrate 100 (see Fig. 8(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used as the material. Note that before and after this step , in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon , as the impurity imparting n-type conductivity, for example, phosphorus (P), arsenic (As ) etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron (B), aluminum (Al), gallium (Ga), etc. can be used.

[0104] Next, etching is performed using the above protective layer 102 as a mask, and a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region) is removed. As a result, other semiconductors A semiconductor region 104 separated from the region is formed (see FIG. 8(B)). For this etching it is preferable to use dry etching, but wet etching may also be used. The etching gas and etching liquid can be appropriately selected according to the material to be etched. This can be done.

[0105] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in the region superimposed on the semiconductor region 104 is selectively removed to form an element isolation insulating layer 106 (see FIG. 8(B) ). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. As a method for removing the insulating layer, there are polishing processes such as CMP and etching processes, etc., and any of them may be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the protective layer 102 is removed.

[0106] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. This is done.

[0107] The insulating layer will be the subsequent gate insulating layer, and is obtained using the CVD method, sputtering method, etc. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0 , y>0)), hafnium silicate with nitrogen added (HfSixOy (x>0, y> 0)), hafnium aluminate with nitrogen added (HfAlxOy (x>0, y>0) ), etc. It is preferable to have a single-layer structure or a laminated structure of a film containing such materials. In addition, by performing high-density plasma treatment or thermal oxidation treatment to oxidize and nitride the surface of the semiconductor region 104, the above insulating layer is formed. It may be achieved. The high-density plasma treatment can be performed using, for example, a mixed gas of a noble gas such as He, Ar, Kr, Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Also, the thickness of the insulating layer can be, for example, 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0108] The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Also, a layer containing a conductive material may be formed using a semiconductor material such as polycrystalline silicon. The forming method is not particularly limited, and various film-forming methods such as vapor deposition, CVD method, sputtering method, spin coating method, etc. can be used. In this embodiment, a case of forming a layer containing a conductive material using a metal material is shown as an example.

[0109] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a and the gate electrode 110a (see FIG. 8(C)).

[0110] Next, an insulating layer 112 covering the gate electrode 110a is formed (see FIG. 8(C)). Then, phosphorus (P), arsenic (As), etc. are added to the semiconductor region 104 to form an impurity region 114 with a shallow junction depth (see FIG. 8(C)). Here, phosphorus (P) and arsenic (As) are added to form an n-type transistor, but when forming a p-type transistor, impurity elements such as boron (B) and aluminum (Al) may be added. By forming the above impurity region 114, a channel formation region 116 is formed under the gate insulating layer 108a of the semiconductor region 104 (see FIG. 8(C)). Here, the concentration of the impurity to be added is appropriately set. ​ Although it can be determined, when the semiconductor element is highly miniaturized, it is desirable to increase its concentration. Here, a process of forming the impurity region 114 after forming the insulating layer 112 is adopted. However, a process of forming the insulating layer 112 after forming the impurity region 114 may also be used. Here, a process of forming the impurity region 114 after forming the insulating layer 112 is adopted. However, a process of forming the insulating layer 112 after forming the impurity region 114 may also be used. is also acceptable.

[0111] Next, a sidewall insulating layer 118 is formed (see Fig. 8(D)). The sidewall insulating layer 118 can be self-alignedly formed by performing an anisotropic etching process on the insulating layer and the insulating layer 112 after forming an insulating layer so as to cover the insulating layer 112. Next, a sidewall insulating layer 118 is formed (see Fig. 8(D)). The sidewall insulating layer 118 can be self-alignedly formed by performing an anisotropic etching process on the insulating layer and the insulating layer 112 after forming an insulating layer so as to cover the insulating layer 112. At this time, it is preferable to partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114. Note that the sidewall insulating layer 118 may not be formed for purposes such as high integration. At this time, it is preferable to partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114. Note that the sidewall insulating layer 118 may not be formed for purposes such as high integration. At this time, it is preferable to partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114. Note that the sidewall insulating layer 118 may not be formed for purposes such as high integration. At this time, it is preferable to partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114. Note that the sidewall insulating layer 118 may not be formed for purposes such as high integration.

[0112] Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 8(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 8(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low-resistance metal compound. Examples of such metal materials include titanium, tantalum, tungsten, nickel, and copper. Examples include baltic and platinum.

[0113] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 8(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of 0a that contacts the metal layer 122.

[0114] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region 124 is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed by the metal compound. The metal compound region is formed by the metal compound. By doing so, it is possible to sufficiently reduce the electrical resistance and improve the device characteristics. After compound region 124 is formed, metal layer 122 is removed.

[0115] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using silicon oxide. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tungsten oxide The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum. It is also possible to form the insulating film by using an organic insulating material such as acrylic. Although it has a stacked structure of layer 126 and the interlayer insulating layer 128, one aspect of the disclosed invention is not limited to this. It may be a single layer or a stacked structure of three or more layers. After the formation of the interlayer insulating layer 128, it is desirable to planarize its surface by CMP, etching, or the like. Then, an opening reaching the metal compound region 124 is formed in the interlayer insulating layer, and a source electrode or drain electrode 130a and a source electrode or drain electrode 130b are formed in the opening (see FIG. 8(H)). The source electrode or drain electrode 130a and the source electrode or drain electrode 130b can be formed, for example, by forming a conductive layer in the region including the opening using a PVD method, a CVD method, or the like, and then removing a part of the conductive layer using a method such as etching or CMP. More specifically, for example, a titanium film is thinly formed in the region including the opening by the PVD method, a titanium nitride film is thinly formed by the CVD method, and then a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method has a function of reducing the contact resistance with the oxide film (such as a natural oxide film) on the formation surface and the lower electrode (here, the metal compound region 124). Further, the titanium nitride film formed thereafter has a barrier function of suppressing the diffusion of the conductive material. Also, after forming a barrier film made of titanium, titanium nitride, or the like, a copper film may be formed by electroplating. Note that, by removing a part of the conductive layer, the source electrode or drain electrode 130a, the source electrode

[0116] or drain electrode 130b can be formed.

[0117]

[0118] ​​​​​​​​​​​​​When forming the drain electrode 130b, it is desirable to process it so that its surface becomes flat. For example, after thinly forming a titanium film or a titanium nitride film in the region including the opening, when forming a tungsten film so as to embed it in the opening, unnecessary tungsten films, titanium films, titanium nitride films, etc. are removed by subsequent CMP, and the flatness of its surface can be improved. In this way, by planarizing the surface including the source electrode or drain electrode 130a and the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Note that here, only the source electrode or drain electrode 130a and the source electrode or drain electrode 130b in contact with the metal compound region 124 are shown, but in this process, electrodes in contact with the gate electrode 110a, etc. can be formed together. There is no particular limitation on the materials that can be used as the source electrode or drain electrode 130a and the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum,

[0119] titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Also, considering the heat treatment to be performed later, it is desirable to form the source electrode or drain electrode 130a and the source electrode or drain electrode 130b using materials having heat resistance enough to withstand the heat treatment. The source electrode or drain electrode 130a and the source electrode or drain electrode 130b can be formed together with electrodes in contact with the gate electrode 110a, etc. There is no particular limitation on the materials that can be used as the source electrode or drain electrode 130a and the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Also, considering the heat treatment to be performed later, it is desirable to form the source electrode or drain electrode 130a and the source electrode or drain electrode 130b using materials having heat resistance enough to withstand the heat treatment. titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Also, considering the heat treatment to be performed later, it is desirable to form the source electrode or drain electrode 130a and the source electrode or drain electrode 130b using materials having heat resistance enough to withstand the heat treatment. The source electrode or drain electrode 130a and the source electrode or drain electrode 130b are preferably formed using materials having heat resistance enough to withstand the heat treatment. As described above, the transistor 160 using the substrate 100 including the semiconductor material is formed (see FIG. 8(H)). The transistor 160 using a semiconductor material other than the oxide semiconductor has high-speed operation.

[0120] As described above, the transistor 160 using the substrate 100 including the semiconductor material is formed (see FIG. 8(H)). The transistor 160 using a semiconductor material other than the oxide semiconductor has high-speed operation. As described above, the transistor 160 using the substrate 100 including the semiconductor material is formed (see FIG. 8(H)). The transistor 160 using a semiconductor material other than the oxide semiconductor has high-speed operation. It is possible to perform the operation.

[0121] In addition, after the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure composed of a laminated structure of an interlayer insulating layer and a conductive layer as the wiring structure, a highly integrated semiconductor device can be provided.

[0122] <Method for fabricating upper transistor> Next, with reference to FIG. 9, the process of fabricating the transistor 162 on the interlayer insulating layer 128 will be described. Note that FIG. 9 shows the fabrication processes of various electrodes on the interlayer insulating layer 128 and the transistor 162, etc., so the transistors 16 0 etc. existing below the transistor 162 are omitted.

[0123] First, a conductive layer is formed on the interlayer insulating layer 128, and the conductive layer is selectively etched to form a source electrode or drain electrode 142a and a source electrode or drain electrode 142b (see FIG. 9(A)).

[0124] The conductive layer can be formed by PVD methods such as sputtering, and CVD methods such as plasma CVD. Also, as the material of the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, alloys containing the above-described elements as components, etc. can be used. Materials containing any one of manganese, magnesium, zirconium, beryllium, or a combination of a plurality of these may be used. Also, materials containing an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium in aluminum, or a combination of a plurality of these may be used.

[0125] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. may be mentioned. Incidentally, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, there is an advantage that it is easy to process into a source electrode or a drain electrode 142a having a tapered shape, and a source electrode or a drain electrode 142b. Furthermore, the conductive layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In 2 O 3 ), tin oxide (SnO 2

[0126] ), zinc oxide (ZnO), indium tin oxide alloy (In 2 2 O 3 3 2 ―SnO 2 2 O 3 ―SnO 2 2 、which may be abbreviated as ITO), indium zinc oxide alloy (In 2 2 3 O 3

[0127] ―ZnO), or those obtained by adding silicon or silicon oxide to these metal oxide materials can be used. Etching of the conductive layer is preferably performed so that the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b to be formed have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b ​​By etching to form a tapered shape, the gate insulating layer 14 formed later The coverage of 6 can be improved, and step discontinuities can be prevented.

[0128] The channel length (L) of the transistor is determined by the distance between the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142b. When forming a transistor with a channel length (L) of less than 25 nm, it is desirable to use extreme ultraviolet light with a wavelength of several nm to several tens of nm for mask formation exposure. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistor formed later to be 10 nm or more and 1000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Also, by miniaturization, it is possible to reduce the power consumption of the semiconductor device. Note that an insulating layer that functions as a base may be provided on the interlayer insulating layer 128. The insulating layer can be formed using a PVD method, a CVD method, or the like. Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 9(B)). Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistor formed later to be 10 nm or more and 1000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Also, by miniaturization, it is possible to reduce the power consumption of the semiconductor device. Note that an insulating layer that functions as a base may be provided on the interlayer insulating layer 128.

[0129] The insulating layer can be formed using a PVD method, a CVD method, or the like. Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b.

[0130] By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 9(B)). Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b.

[0131] Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 9(B)). Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 9(B)).

[0132] The oxide semiconductor layer 144 is formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O system which is a quaternary metal oxide, or an In-Ga-Zn-O system, an In-Sn-Zn-O system, an In-Al- Zn-O system, a Sn-Ga-Zn-O system, an Al-Ga-Zn-O system, a Sn-Al-Zn-O system which are ternary metal oxides, or an In-Zn-O system, a Sn-Zn-O system, an Al-Zn-O system which are binary metal oxides, a Zn-Mg-O system, a Sn-Mg-O system, an In-Mg-O system, or an In-O system, a Sn-O system, a Zn-O system which are monovalent metal oxides. Among these, an In-Ga-Zn-O based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field effect mobility compared to a normal silicon semiconductor, so it is suitable as a semiconductor material used in a semiconductor device. .

[0133] Among them, as a representative example of an In-Ga-Zn-O based oxide semiconductor material, there is one represented by InGaO (ZnO) (m>0). Also, there is an oxide semiconductor material represented as InMO

[0134] (Zn 3 (ZnO) m (m>0). Here, M represents one metal element or a plurality of metal elements selected from gallium 3 (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), O) m (m>0). For example, as M, Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn , Ga and Co, etc. can be applied. Note that the above composition is derived from the crystal structure. It should be noted that the following is only an example and nothing more.

[0135] As a target for forming the oxide semiconductor layer 144 by sputtering, those represented by the composition formula of In:Ga: Zn = 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less) are preferably used. For example, targets having a composition ratio of In:Ga:Zn = 1:1:1 [atomic ratio] (x = 1, y = 1), (that is, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio]) can be used. Also, targets having a composition ratio of In:Ga:Zn = 1:1 :0.5 [atomic ratio] (x = 1, y = 0.5), (that is, In O 2 :Ga 3 O 2 :ZnO = 1:1:1 [mole ratio]) or targets having a composition ratio of In:Ga:Z 3 n = 1:1:2 [atomic ratio] (x = 1, y = 2), (that is, In O 2 :Ga 3 O 2 :ZnO = 1:1:4 [mole ratio]) or targets having a composition ratio of In:Ga: 3 Zn = 1:0:1 [atomic ratio] (x = 0, y = 1), (that is, In O 2 :ZnO 3 = 1:2 [mole ratio]) can also be used. In this embodiment, the amorphous oxide semiconductor layer 144 is formed by sputtering using an In-Ga-Zn-O-based metal oxide target.

[0136]

[0137] ​​The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, more preferably 99.9% or more. By using a metal oxide target with a high relative density, it is possible to form an oxide semiconductor layer 144 with a dense structure.

[0138] The formation atmosphere of the oxide semiconductor layer 144 is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (desirably 10 ppb or less).

[0139] When forming the oxide semiconductor layer 144, for example, a workpiece is held in a processing chamber maintained in a reduced-pressure state, and the workpiece is heated so that the temperature of the workpiece is 100°C or more and less than 550°C, preferably 200°C or more and 4 00°C or less. Alternatively, the temperature of the workpiece during the formation of the oxide semiconductor layer 144 may be room temperature. Then, while removing moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and the oxide semiconductor layer 144 is formed using the above target. By forming the oxide semiconductor layer 144 while heating the workpiece, impurities contained in the oxide semiconductor layer 144 can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo pump with a cold trap added can be used. formed. By forming the oxide semiconductor layer 144 while heating the workpiece, impurities contained in the oxide semiconductor layer 144 can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo pump with a cold trap added can be used. ​​​It is also possible. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor layer 144 can be reduced. Since it can be removed, the impurity concentration in the oxide semiconductor layer 144 can be reduced.

[0140] As the formation conditions of the oxide semiconductor layer 144, for example, the distance between the object to be processed and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the atmosphere is an oxygen (oxygen 100%) atmosphere, or an argon (argon 100%) atmosphere, or a mixed atmosphere of oxygen and argon can be applied. Note that when using a pulsed direct current (DC) power supply it is preferable because dust (such as powdery substances formed during film formation) can be reduced and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor layer 144 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less. By using the oxide semiconductor layer 144 with such a thickness it is possible to suppress the short-channel effect accompanying miniaturization. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied, the use of the semiconductor device, etc., the thickness can also be selected according to the material and use to be used etc. .

[0141] Note that before forming the oxide semiconductor layer 144 by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove deposits on the formation surface (for example, the surface of the interlayer insulating layer 128). Here, reverse sputtering means in normal sputtering, where ions are made to collide with the sputtering target, conversely, a method of modifying the surface by making ions collide with the processing surface is referred to. By making ions collide with the processing surface the surface is modified. ​As a method, a high-frequency voltage is applied to the processing surface side under an argon atmosphere to generate plasma near the object to be processed and the like. Note that an atmosphere of nitrogen, helium, oxygen, etc. may be applied instead of the argon atmosphere .

[0142] Thereafter, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 144 . By this first heat treatment, excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer 144 is removed, the structure of the oxide semiconductor layer is adjusted, and the defect levels in the energy gap can be reduced . The temperature of the first heat treatment is, for example, 300°C or higher and less than 550°C, or 40 0°C or higher and 500°C or lower .

[0143] For the heat treatment, for example, the object to be processed is introduced into an electric furnace using a resistance heating element or the like, and the heat treatment is performed under a nitrogen atmosphere at 450°C for 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the atmosphere to prevent the mixing of water and hydrogen .

[0144] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be processed by heat conduction from a medium such as heated gas or heat radiation may be used. For example, an RTA (Rapid Thermal Anneal ) apparatus such as a GRTA (Gas Rap id Thermal Anneal) apparatus or an LRTA (Lamp Rapid The ) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be processed by the radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps , xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps . The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. As the gas, argon and other noble gases, or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used.

[0145] For example, as the first heat treatment, the object to be treated may be put into a heated inert gas atmosphere and heated for several minutes and then the GRTA treatment of taking out the object to be treated from the inert gas atmosphere may be performed. When the GRTA treatment is used, high-temperature heat treatment in a short time becomes possible. Also, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the object to be treated. During the treatment, the inert gas may be switched to a gas containing oxygen. By performing the first heat treatment in an atmosphere containing oxygen, it is possible to reduce the defect levels in the energy gap caused by oxygen deficiency. This is because.

[0146] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc. ) and not containing water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0147] In any case, by reducing impurities by the first heat treatment and forming an oxide semiconductor layer 144 that is extremely close to the i-type (intrinsic semiconductor) or the i-type , a transistor with extremely excellent characteristics can be realized. This is because.

[0148] By the way, since the above-mentioned heat treatment (the first heat treatment) has the effect of removing hydrogen, water, etc., This heat treatment can also be referred to as a dehydration treatment, a dehydrogenation treatment, etc. This dehydration treatment and this dehydrogenation treatment can also be performed at timings such as after the formation of the oxide semiconductor layer, after the formation of the gate insulating layer, and after the formation of the gate electrode. Also such dehydration treatment and dehydrogenation treatment may be performed not only once but also multiple times.

[0149] Next, a gate insulating layer 146 in contact with the oxide semiconductor layer 144 is formed (see Fig. 9(C)). The gate insulating layer 146 can be formed using a CVD method, a sputtering method, or the like. Also the gate insulating layer 146 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf Si x O y (x>0, y>0)), hafnium silicate with nitrogen added (HfSi x O y (x>0, y>0)), hafnium aluminate with nitrogen added (HfAl x O y (x>0, y>0)), etc. The gate insulating layer 146 may have a single-layer structure or a laminated structure. Also, its thickness is not particularly limited but when miniaturizing the semiconductor device, it is desirable to make it thin in order to ensure the operation of the transistor. For example, when using silicon oxide, it can be 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0150] As described above, when the gate insulating layer is made thin, gate leakage caused by the tunneling effect or the like becomes a problem. To solve the problem of gate leakage, hafnium oxide is added to the gate insulating layer 146 Mu, tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0 , y>0)), hafnium silicate (HfSi with nitrogen added x O y (x>0, y> 0)), hafnium aluminate (HfAl with nitrogen added x O y (x>0, y>0) ), etc. It is advisable to use high-k (high dielectric constant) materials. High-k (high dielectric constant) By using the material for the gate insulating layer 146, while ensuring electrical characteristics, it becomes possible to increase the film thickness to suppress gate leakage . In addition, a laminated structure may be formed between a film containing a high-k (high dielectric constant) material and a film containing any one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide , etc.

[0151] After forming the gate insulating layer 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 0°C or higher and 350°C or lower. For example, a heat treatment at 250°C for 1 hour in a nitrogen atmosphere may be performed . By performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced . Further, when the gate insulating layer 146 contains oxygen, oxygen can be supplied to the oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is infinitely close to the i-type can be formed .

[0152] Note that in this embodiment, a second heat treatment is performed after forming the gate insulating layer 146, but The timing of the second heat treatment is not particularly limited thereto. For example, the second heat treatment may be performed after the formation of the gate electrode. Alternatively, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may be made to also serve as the second heat treatment, or the second heat treatment may be made to also serve as the first heat treatment.

[0153] Next, a gate electrode 148a is formed in a region overlapping with the oxide semiconductor layer 144 on the gate insulating layer 146, and an electrode 148b is formed in a region overlapping with the source electrode or drain electrode 142a (see FIG. 9(D)). The gate electrode 148a and the electrode 148b can be formed by selectively etching the conductive layer after forming the conductive layer on the gate insulating layer 146. The conductive layer that becomes the gate electrode 148a and the electrode 148b can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Details are the same as in the case of the source electrode or drain electrode 142a, etc., and these descriptions can be referred to.

[0154] Next, an interlayer insulating layer 150 and an interlayer insulating layer 152 are formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b (see FIG. 9(E)). The interlayer insulating layer 150 and the interlayer insulating layer 152 can be formed using a PVD method or a CVD method. Further, they can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. In the present embodiment, a laminated structure of the interlayer insulating layer 150 and the interlayer insulating layer 152 is adopted, but one aspect of the disclosed invention is not limited thereto. It may be a single layer or a laminated structure of three or more layers. It is also possible to adopt a structure in which no interlayer insulating layer is provided.

[0155] It is preferable that the interlayer insulating layer 152 is formed so that its surface is flat. By forming the interlayer insulating layer 152 so as to have a flat surface, when the semiconductor device is miniaturized, Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 152. The interlayer insulating layer 152 is planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0156] Through the above steps, the transistor 162 including the purified oxide semiconductor layer 144 is completed. (See FIG. 9(E)). Furthermore, the capacitor element 164 is completed.

[0157] The transistor 162 illustrated in FIG. 9E includes an oxide semiconductor layer 144 and an oxide semiconductor layer 14 4, a source electrode or drain electrode 142a electrically connected to the source electrode or drain The source electrode 142b, the oxide semiconductor layer 144, the source or drain electrode 142a, A gate insulating layer 146 covers the source or drain electrode 142b. The capacitance element 164 has a source electrode or a drain electrode. A source electrode 142a, an oxide semiconductor layer 144, and a source or drain electrode 142a A gate insulating layer 146 covers the oxide semiconductor layer 144, and an electrode 1 on the gate insulating layer 146. 48b.

[0158] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Hereinafter, more preferably 5×10 17 atoms / cm 3 or less is satisfied. Further, the carrier density of the oxide semiconductor layer 144 is the carrier density (about 1×10 14 / cm 3 ) in a general silicon wafer, and is sufficiently small (for example, 1 ×10 12 / cm 3 or less, more preferably 1.45×10 10 / cm 3 or less). As a result, the off-current becomes sufficiently small. For example, the off-current at room temperature of the transistor 162 (here, the value per unit channel width (1 μm)) is 100 zA / μm (1 zA (zeptoampere) is 1×10 -21 A) or less, preferably 10 zA / μm or less.

[0159] By using the oxide semiconductor layer 144 that has been purified and made intrinsic in this way, the off-current of the transistor can be sufficiently reduced. And by using such a transistor, a semiconductor device capable of retaining memory contents for an extremely long time can be obtained.

[0160] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined with the configurations, methods, etc. shown in other embodiments and used.

[0161] (Embodiment 4) In this embodiment, a semiconductor device according to an aspect of the disclosed invention, which is different from Embodiment 3, and a method for manufacturing the same

[0162] 〈Cross-sectional and planar configurations of the semiconductor device〉​ Figure 10 shows an example of the configuration of a semiconductor device. In Fig. 10(A), a cross-section of the semiconductor device is shown, and in Fig. 10(B), a plan view of the semiconductor device is shown, respectively. Here, Fig. 10(A) corresponds to the cross-sections at A1 - A2 and B1 - B2 in Fig. 10 (B). The semiconductor device shown in Fig. 10(A) and Fig. 10(B) has a transistor 160 using a semiconductor material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part. (The transistor 160 using a semiconductor material other than an oxide semiconductor can achieve high-speed operation by using a material with a higher value of field-effect mobility than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material enables long-term charge retention due to its characteristics. It should be noted that although the above transistors are all described as n-channel transistors, it goes without saying that p-channel transistors can also be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor for the transistor 162 to hold information, there is no need to limit the specific configuration of the semiconductor device shown here.

[0163] The transistor 160 in Fig. 10 includes a channel formation region 116 provided on a substrate 100 containing a semiconductor material (e.g., silicon, etc.), impurity regions 114 and high-concentration impurity regions 120 (collectively also simply called impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and electrically connected to the impurity regions.

[0164] The transistor 160 in Fig. 10 is provided with a channel formation region 116 on a substrate 100 containing a semiconductor material (e.g., silicon, etc.), and impurity regions 114 and high-concentration impurity regions 120 (collectively also simply called impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and electrically connected to the impurity regions. gate insulating layer 108a, and a gate electrode 110a provided on the The source electrode or drain electrode 130a, and the source electrode or drain electrode 130 b. Also, on the source electrode or drain electrode 130a, and the source electrode or d rain electrode 130b, there are wiring 142c and wiring 142d.

[0165] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Also, in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed from a direction perpendicular to the surface, there is a high-concentration impurity region 120, and a metal compound region 124 exists in contact with the high-concentration impurity region 120. Also, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided on the gate electrode 110a with an opening and covering the transistor 160. The source electrode or drain electrode 130a, and the source electrode or drain electrode 130b are electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130b are electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. Note that the sidewall insulating layer 118 may not be formed for reasons such as integration of the transistor 160. The source electrode or drain electrode 130a, and the source electrode or drain electrode 130b are electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130b are electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. Note that the sidewall insulating layer 118 may not be formed for reasons such as integration of the transistor 160. and the source electrode or drain electrode 130b are electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. Note that the sidewall insulating layer 118 may not be formed for reasons such as integration of the transistor 160. The transistor 162 in FIG. 10 has a source electrode or a drain electrode 142a provided on the interlayer insulating layer 128, and a source electrode or a drain electrode 142b, and is electrically connected to the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b.

[0166] or the drain electrode 142a, and the source electrode or the drain electrode 142b. is provided on the interlayer insulating layer 128, and a source electrode or a drain electrode 142b, and is electrically connected to the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b. The connected island-shaped oxide semiconductor layer 144 and the source electrode or drain electrode 142 a. The source electrode or drain electrode 142 b. The gate covering the island-shaped oxide semiconductor layer 144 The insulating layer 146 and the gate electrode 148a provided so as to overlap the island-shaped oxide semiconductor layer 144 on the gate insulating layer 146 have.

[0167] Here, the lower transistor 160 and the upper transistor 162 are electrically connected by directly forming the source electrode or drain electrode 142a on the gate electrode 110a That is, the semiconductor device shown in this embodiment is the semiconductor device shown in Embodiment 3 wherein the upper part from the upper surface of the gate electrode 110a is removed, and the upper transistor 162 is formed on the lower transistor 160 It has a configuration.

[0168] Note that the oxide semiconductor layer 144 is preferably highly purified by sufficiently removing impurities such as hydrogen or by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 or less, desirably 5×10 18 atoms / cm 3 or less, more desirably 5×10 17 atoms / cm 3 or less. The hydrogen concentration in the above-described oxide semiconductor layer 144 is measured by secondary ion mass spectrometry (SIMS) :Secondary Ion Mass Spectroscopy). In this way, the hydrogen concentration is sufficiently reduced and highly purified, and the defect levels in the energy gap caused by oxygen deficiency due to the supply of sufficient oxygen are ​​​In the reduced oxide semiconductor layer 144, the carrier concentration is less than 1×10 12 / cm 3 , preferably less than 1×10 / cm 11 , more preferably less than 1.45×10 3 / cm 10 and becomes. For example, the off-current at room temperature (here, the value per unit channel width (1 μm)) is , 100 zA / μm or less (1 zA (zeptoampere) is 1×10 A), preferably -21 , 10 zA / μm or less. Thus, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained .

[0169] The capacitor element 164 is composed of a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate insulating layer 146, and an electrode 148b. That is, the source electrode or the drain electrode 142a functions as one electrode of the capacitor element 164, and the electrode 148b functions as the other electrode of the capacitor element 164 .

[0170]

[0171] In the capacitor element 164 of FIG. 10, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured .

[0171] In the transistor 162 and the capacitor element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably in a tapered shape . Here, the taper angle is, for example, 30° or more and 60° or less. Note that , the taper angle is the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 1 42a) when observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate). By tapering the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b, the coverage of the oxide semiconductor layer 144 can be improved, and steps can be prevented. This is because

[0172] Also, an interlayer insulating layer 150 is provided over the transistor 162 and the capacitor element 164, and an interlayer insulating layer 152 is provided over the interlayer insulating layer 150.

[0173] <Fabrication Method of Semiconductor Device> Next, an example of the fabrication method of the semiconductor device will be described. Hereinafter, the process after forming the lower transistor 160 and the fabrication method of the upper transistor 162 will be described with reference to FIG. 11. For the lower transistor 160, it can be fabricated by the same method as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. First, after forming the lower transistor 160 by the method shown in Embodiment 3, the upper part above the upper surface of the gate electrode 110a of the transistor

[0174] 160 is removed (see FIG. 11(A)). The removal of the relevant part of the transistor 160 is performed by performing a polishing process (CMP process) on the lower transistor 160 until the upper surface of the gate electrode 110a is exposed. As a result, the interlayer insulating layers 126, 128, and the source electrode or drain electrode above the gate electrode 110a, 130a, 130b are removed. At this time, the interlayer insulating layers 126, 128, and the source electrode or drain electrode 130a, 130b are removed. At this time, the interlayer insulating layers 126, 128, and the source electrode or drain electrode Alternatively, by planarizing the surface including the drain electrodes 130a and 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Also, since the electrode 130c shown in Embodiment 3 is completely removed by this CMP process, there is no need to form it. In this way, by performing the CMP process and exposing the upper surface of the gate electrode 110a, the gate electrode 110a and the source electrode or drain electrode 142a can be directly connected, so that the electrical connection between the transistor 160 and the transistor 162 can be easily achieved. Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to.

[0175] Thus, by performing the CMP process and exposing the upper surface of the gate electrode 110a, the gate electrode 110a and the source electrode or drain electrode 142a can be directly connected, so that the electrical connection between the transistor 160 and the transistor 162 can be easily achieved. In this way, by performing the CMP process and exposing the upper surface of the gate electrode 110a, the gate electrode 110a and the source electrode or drain electrode 142a can be directly connected, so that the electrical connection between the transistor 160 and the transistor 162 can be easily achieved. Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to.

[0176] Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to.

[0177] Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d (see FIG. 11(B)). Here, the source electrode or drain electrode 142a is formed to be directly connected to the gate electrode 110a, the wiring 142c is formed to be directly connected to the source electrode or drain electrode 130a, and the wiring 142d is formed to be directly connected to the source electrode or drain electrode 130b. Here, the conductive layer for forming the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d can use the same material as that shown in Embodiment 3, and the description of Embodiment 3 can be referred to. Also, the etching of the conductive layer can be performed in the same manner as the method shown in Embodiment 3, and the description of Embodiment 3 can be referred to.

[0178] Also, as shown in Embodiment 3, an insulating layer may be formed over the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the subsequently formed gate electrode and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b.

[0179] Next, an oxide semiconductor layer is formed so as to cover the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the wiring 142c, and the wiring 142d, and the oxide semiconductor layer is selectively etched to form an oxide semiconductor layer 144 in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 11(C)).

[0180] The oxide semiconductor layer can be formed of the same material as that shown in Embodiment 3 and by the same method. Therefore, Embodiment 3 can be referred to for the material and film formation method of the oxide semiconductor layer.

[0181] The thus formed oxide semiconductor layer is processed into an island shape by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 144.

[0182] For etching the oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both of them can be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that the oxide semiconductor layer can be etched into a desired shape.

[0183] Further, as shown in Embodiment 3, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 144. The first heat treatment can be performed by the method shown in Embodiment 3, and Embodiment 3 can be referred to. By reducing impurities through the first heat treatment and forming an oxide semiconductor layer 144 that is of the i-type (intrinsic semiconductor) or extremely close to the i-type, a transistor with extremely excellent characteristics can be realized. Note that the first heat treatment may be performed before etching the oxide semiconductor layer, or may be performed after etching to process the oxide semiconductor layer into an island shape.

[0184] Next, a gate insulating layer 146 in contact with the oxide semiconductor layer 144 is formed (see FIG. 11(C)).

[0185] The gate insulating layer 146 can be formed by using the same material as that shown in Embodiment 3 and by the same method. Therefore, Embodiment 3 can be referred to for the material and film formation method of the gate insulating layer 146.

[0186] Also, after the formation of the gate insulating layer 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere as shown in Embodiment 3. The second heat treatment can be performed by the method shown in Embodiment 3, and Embodiment 3 can be referred to. By performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced. Further, when the gate insulating layer 146 contains oxygen, oxygen is supplied to the oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an oxide semiconductor layer that is of the i-type (intrinsic semiconductor) or extremely close to the i-type can also be formed.

[0187] Note that in this embodiment, a second heat treatment is performed after the formation of the gate insulating layer 146. The timing of the second heat treatment is not particularly limited thereto. For example, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may be made to serve also as the second heat treatment, or the second heat treatment may be made to serve also as the first heat treatment.

[0188] Next, a gate electrode 148a is formed in a region overlapping with the oxide semiconductor layer 144 on the gate insulating layer 146, and an electrode 148b is formed in a region overlapping with the source electrode or drain electrode 142a (see FIG. 11(D)). The gate electrode 148a and the electrode 148b can be formed by selectively etching the conductive layer after forming the conductive layer on the gate insulating layer 146. The conductive layer to be the gate electrode 148a and the electrode 148b can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Details are the same as in the case of the source electrode or drain electrode 142a, etc., and these descriptions can be referred to.

[0189] Next, as shown in Embodiment 3, an interlayer insulating layer 150 and an interlayer insulating layer 152 are formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. The interlayer insulating layer 150 and the interlayer insulating layer 152 can be formed of the same materials as those shown in Embodiment 3 and by the same method. Therefore, Embodiment 3 can be referred to for the materials and film formation methods of the interlayer insulating layer 150 and the interlayer insulating layer 152.

[0190] Note that it is desirable to form the interlayer insulating layer 152 so that its surface is flat. By forming the interlayer insulating layer 152 so that its surface is flat, even in a case where the semiconductor device is miniaturized, electrodes, wirings, etc. can be suitably formed on the interlayer insulating layer 152. This is because of this. Note that the planarization of the interlayer insulating layer 152 can be performed using a method such as CMP (chemical mechanical polishing).

[0191] As described above, the transistor 162 using the highly purified oxide semiconductor layer 144 is completed (see FIG. 10). Also, the capacitor element 164 is completed.

[0192] The transistor 162 shown in FIG. 10 includes an oxide semiconductor layer 144, a source electrode or a drain electrode 142a that is electrically connected to the oxide semiconductor layer 144, a source electrode or a drain electrode 142b, a gate insulating layer 146 that covers the oxide semiconductor layer 144, the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b, and a gate electrode 148a on the gate insulating layer 146. Also, the capacitor element 164 includes a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate insulating layer 146 that covers the source electrode or the drain electrode 142a, and an electrode 148b on the gate insulating layer 146.

[0193] In the transistor 162 shown in this embodiment, since the oxide semiconductor layer 144 is highly purified, its hydrogen concentration is 5×10 atoms / cm 19 3 or less, desirably 5× 10 18 atoms / cm 3 or less, more desirably 5×10 17 atoms / cm 3 or less. It is so. Further, the carrier density of the oxide semiconductor layer 144 is the carrier density in a general silicon wafer (1×10 14 / cm 3 or so), and is a sufficiently small value (for example, 1 ×10 12 / cm 3 less than, more preferably, 1.45×10 10 / cm 3 less than). And thereby, the off-current becomes sufficiently small. For example, the off-current of the transistor 162 at room temperature (here, the value per unit channel width (1 μm)) is 100 zA / μm (1 zA (zeptoampere) is 1×10 -21 A) or less, desirably, 10 zA / μm or less and becomes so.

[0194] By using the oxide semiconductor layer 144 thus highly purified and made intrinsic, the off-current of the transistor can be sufficiently reduced. And by using such a transistor a semiconductor device capable of retaining memory contents for an extremely long period can be obtained.

[0195] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0196] (Embodiment 5) In this embodiment, the configuration of a semiconductor device according to an aspect of the disclosed invention, which is different from those of Embodiment 3 and Embodiment 4, and a method for manufacturing the same will be described with reference to FIGS. 4 to 6.

[0197] <Cross-sectional configuration and planar configuration of semiconductor device> FIG. 4 shows an example of the configuration of a semiconductor device. In FIG. 4(A), the cross-section of the semiconductor device is shown, and in FIG. 4( ​​(B) shows the plane of the semiconductor device, respectively. Here, FIG. 4(A) corresponds to the cross sections at 1-C2 and D1-D2 of FIG. 4(B). In the plan view of FIG. 4(B), some of the components such as the source electrode or drain electrode 154 and the wiring 156 are omitted to avoid complication. The semiconductor device shown in FIGS. 4(A) and 4(B) has a transistor 160 using a semiconductor material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics. It corresponds to the cross sections at 1-C2 and D1-D2. In the plan view of FIG. 4(B), some of the components such as the source electrode or drain electrode 154 and the wiring 156 are omitted to avoid complication. To avoid complication, some of the components such as the source electrode or drain electrode 154 and the wiring 156 are omitted. The semiconductor devices shown in FIGS. 4(A) and 4(B) have a transistor 160 using a semiconductor material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics. The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed by using a material with a higher field-effect mobility value than the oxide semiconductor material. On the other hand, the transistor 162 using an oxide semiconductor material can hold charges for a long time due to its characteristics.

[0198] Note that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor in the transistor 162 to hold information, it is not necessary to limit the specific configuration of the semiconductor device shown here. Note that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor in the transistor 162 to hold information, it is not necessary to limit the specific configuration of the semiconductor device shown here. Note that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor in the transistor 162 to hold information, it is not necessary to limit the specific configuration of the semiconductor device shown here. Note that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, since the technical essence of the disclosed invention lies in using an oxide semiconductor in the transistor 162 to hold information, it is not necessary to limit the specific configuration of the semiconductor device shown here.

[0199] One difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the planar layout of the semiconductor device. In this embodiment, the transistor 162 and the capacitor element 164 are provided so as to overlap the transistor 160. By adopting such a planar layout, high integration is possible. For example, taking the minimum processing dimension as F, the area occupied by the memory cell is 15F One difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the planar layout of the semiconductor device. In this embodiment, the transistor 162 and the capacitor element 164 are provided so as to overlap the transistor 160. By adopting such a planar layout, high integration is possible. One difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the planar layout of the semiconductor device. In this embodiment, the transistor 162 and the capacitor element 164 are provided so as to overlap the transistor 160. By adopting such a planar layout, high integration is possible. One difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the planar layout of the semiconductor device. In this embodiment, the transistor 162 and the capacitor element 164 are provided so as to overlap the transistor 160. By adopting such a planar layout, high integration is possible. One difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the planar layout of the semiconductor device. In this embodiment, the transistor 162 and the capacitor element 164 are provided so as to overlap the transistor 160. By adopting such a planar layout, high integration is possible. 2 ~25F 2 ​It is possible to do so.

[0200] Another difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the presence or absence of the sidewall insulating layer 118 in the transistor 160. That is, the semiconductor device shown in FIG. 4 does not have a sidewall insulating layer. Also, by not forming the sidewall insulating layer the impurity region 114 is not formed. In this way, when the sidewall insulating layer is not provided, integration is easier compared to the case where the sidewall insulating layer 118 is provided. Also, compared to the case where the sidewall insulating layer 118 is provided, the manufacturing process can be simplified.

[0201] Another difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the presence or absence of the interlayer insulating layer 125 in the transistor 160. That is, the semiconductor device shown in FIG. 4 has an interlayer insulating layer 125. By applying an insulating layer containing hydrogen as the interlayer insulating layer 125 it is possible to supply hydrogen to the transistor 160 and improve the characteristics of the transistor 160. As such an interlayer insulating layer 125, for example, there is a silicon nitride layer containing hydrogen formed by plasma CVD method. Further, by applying an insulating layer with sufficiently reduced hydrogen as the interlayer insulating layer 1 26, it is possible to prevent the mixing of hydrogen, which may deteriorate the characteristics of the transistor 162, into the transistor 162. As such an interlayer insulating layer 126, for example, there is a silicon nitride layer formed by sputtering method. By adopting such a configuration, the characteristics of the transistor 160 and the transistor 162 can be sufficiently enhanced. ​​​​​

[0202] Another difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is the presence or absence of the insulating layer 143a and the insulating layer 143b in the transistor 162. That is , the semiconductor device shown in FIG. 4 has the insulating layer 143a and the insulating layer 143b. In this way , by providing the insulating layer 143a and the insulating layer 143b, the so-called gate capacitance between the gate electrode 148a and , the source electrode or the drain electrode 142a (or between the gate electrode 148a and the source electrode or the drain electrode 142b) can be reduced, and the operating speed of the transistor 1 62 can be improved.

[0203] Note that, similar to the fourth embodiment, the lower transistor 160 and the upper transistor 162 are electrically connected by directly forming the source electrode or the drain electrode 142a on the gate electrode 110a . By adopting such a configuration, the integration degree is improved as compared with the case where electrodes and wirings are separately provided . Also, the manufacturing process is simplified.

[0204] Note that, in the present embodiment, a configuration having the above-described differences integrally is shown, but a configuration having only any one of the differences may be adopted.

[0205] <Method for manufacturing a semiconductor device> Next, an example of the method for manufacturing the above semiconductor device will be described. Hereinafter, the process after forming the lower transistor 160 and the method for manufacturing the upper transistor 162 will be described with reference to FIGS. 5 and 6. For the lower transistor 160, it can be manufactured by the same method as the method shown in the third embodiment . For details, refer to the description of the third embodiment This is possible. In this embodiment, three types of interlayer insulating layers, namely, the interlayer insulating layer 125, the interlayer insulating layer 126, and the interlayer insulating layer 128, are formed so as to cover the transistor 160 ( see FIG. 8(G)). Also, in this embodiment, in the manufacturing process of the transistor 160, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are not formed (see FIG. 8(H)). However, even in a state where the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are not formed, for convenience, it is referred to as the transistor 160.

[0206] First, after forming the lower transistor 160 by the method shown in Embodiment 3, the upper part above the upper surface of the gate electrode 110a of the transistor 160 is removed. For this removal process, a polishing process such as CMP (chemical mechanical polishing) may be applied. As a result, the interlayer insulating layer 125, the interlayer insulating layer 126, and the interlayer insulating layer 128 above the upper surface of the gate electrode 110a are removed. In addition, by sufficiently flattening the surface related to the polishing process, in subsequent processes, it becomes possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0207] Next, a conductive layer is formed on the gate electrode 110a, the interlayer insulating layer 125, the interlayer insulating layer 126, and the interlayer insulating layer 128, and the conductive layer is selectively etched to form the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 5(A)). Here, the source electrode or drain electrode 142a is formed so as to be directly connected to the gate electrode 110a.

[0208] Form the source electrode or drain electrode 142a and the source electrode or drain electrode 142b The conductive layer for this can be formed using a material similar to the material shown in Embodiment 3. Also, for the etching of the conductive layer, a method similar to the method shown in Embodiment 3 can be used. For details, the description of Embodiment 3 can be referred to. .

[0209] Next, an insulating layer is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b, and the insulating layer is selectively etched to form an insulating layer 143a on the source electrode or drain electrode 142a and an insulating layer 143b on the source electrode or drain electrode 142b, respectively (see FIG. 5(B)). By providing the insulating layer 143a and the insulating layer 143b, it is possible to reduce the parasitic capacitance between the gate electrode formed later and the source electrode or drain electrode 142a, and between the gate electrode formed later and the source electrode or drain electrode 142b. (See FIG. 5(B)).

[0210] By providing the insulating layer 143a and the insulating layer 143b, it is possible to reduce the parasitic capacitance between the gate electrode formed later and the source electrode or drain electrode 142a, and between the gate electrode formed later and the source electrode or drain electrode 142b.

[0211] Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b, and a gate insulating layer 146 is formed on the oxide semiconductor layer 144 (see FIG. 5(C)). (See FIG. 5(C)).

[0212] The oxide semiconductor layer 144 can be formed by the materials and methods shown in Embodiment 3. Also, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 144. For details, the description of Embodiment 3 can be referred to.

[0213] The gate insulating layer 146 can be formed using the material and the method described in Embodiment 3. After the gate insulating layer 146 is formed, the gate insulating layer 146 is annealed in an inert gas atmosphere or an oxygen atmosphere. It is preferable to perform a heat treatment (second heat treatment). For details, refer to the description of the third embodiment. It is possible.

[0214] Next, a region to be a channel formation region of the transistor 162 is formed on the gate insulating layer 146. A gate electrode 148a is formed in a region overlapping the source electrode or drain electrode 142. An electrode 148b is formed in a region overlapping with a (see FIG. 5(D)).

[0215] The gate electrode 148a and the electrode 148b are formed after forming a conductive layer on the gate insulating layer 146. The gate electrode can be formed by selectively etching the conductive layer. The conductive layers that become the electrodes 148a and 148b can be formed by a PVD method such as a sputtering method, The source electrode can be formed by using a CVD method such as a plasma CVD method. or the drain electrode 142a, etc., and the descriptions therefor can be taken into consideration.

[0216] Next, an interlayer insulating layer is formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. 150 and an interlayer insulating layer 152 are formed (see FIG. 6(A)). The interlayer insulating layer 152 can be formed by the material and method shown in the third embodiment. For details, please refer to the description in embodiment 3.

[0217] It is preferable that the interlayer insulating layer 152 is formed so that its surface is flat. By forming the interlayer insulating layer 152 so as to have a flat surface, when the semiconductor device is miniaturized, Even in the case of a laminate or the like, electrodes, wirings, etc. can be suitably formed on the interlayer insulating layer 152. This is because the planarization of the interlayer insulating layer 152 can be carried out using a method such as CMP (chemical mechanical polishing).

[0218] Next, the interlayer insulating layer 125, the interlayer insulating layer 126, the interlayer insulating layer 128, the oxide semiconductor layer 144, the gate insulating layer 146, the interlayer insulating layer 150, and the interlayer insulating layer 152 are selectively etched to form an opening reaching the metal compound region 124 of the transistor 160 (see Fig. 6(B)). As the etching, either dry etching or wet etching can be used, but from the viewpoint of miniaturization, it is desirable to use dry etching.

[0219] Then, a source electrode or a drain electrode 154 is formed so as to fill the above opening. And a wiring 156 connected to the source electrode or the drain electrode 154 is formed (see Fig. 6(C)).

[0220] The source electrode or the drain electrode 154 can be formed, for example, by forming a conductive layer in a region including the opening using a method such as PVD or CVD, and then removing a part of the conductive layer using a method such as etching treatment or CMP. More specifically, for example, a method can be applied in which a titanium film is thinly formed by PVD in a region including the opening, a titanium nitride film is thinly formed by CVD, and then a tungsten film is formed so as to fill the opening. Here, the titanium film formed by PVD reduces the oxide film (such as a natural oxide film) on the surface to be formed and reduces the contact resistance with the lower electrode or the like (here, the metal compound region 124). ​​​​​​​​​It has a certain function. Further, the titanium nitride film formed later suppresses the diffusion of the conductive material. It has a barrier function. Further, after forming a barrier film made of titanium or titanium nitride, etc. a copper film may be formed by a plating method.

[0221] After forming a conductive layer in contact with the source electrode or drain electrode 154, the wiring 156 can be formed by selectively etching the conductive layer. The conductive layer can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The details are the same as those in the case of the source electrode or drain electrode 142a, etc. are the same.

[0222] As described above, a semiconductor device having the transistor 160, the transistor 162, and the capacitor element 164 is completed. is completed.

[0223] In the semiconductor device shown in this embodiment, the transistor 162 and the capacitor element 164 are configured to overlap the transistor 160, the transistor 160 has no sidewall insulating layer, and the source electrode or drain electrode 142a is directly formed on the gate electrode 110a, etc., enabling high integration. Also, the manufacturing process is simplified. In the semiconductor device shown in this embodiment, the transistor 162 and the capacitor element 164 are configured to overlap the transistor 160, the transistor 160 has no sidewall insulating layer, and the source electrode or drain electrode 142a is directly formed on the gate electrode 110a, etc., enabling high integration. Also, the manufacturing process is simplified. In the semiconductor device shown in this embodiment, the transistor 162 and the capacitor element 164 are configured to overlap the transistor 160, the transistor 160 has no sidewall insulating layer, and the source electrode or drain electrode 142a is directly formed on the gate electrode 110a, etc., enabling high integration. Also, the manufacturing process is simplified. In the semiconductor device shown in this embodiment, the transistor 162 and the capacitor element 164 are configured to overlap the transistor 160, the transistor 160 has no sidewall insulating layer, and the source electrode or drain electrode 142a is directly formed on the gate electrode 110a, etc., enabling high integration. Also, the manufacturing process is simplified. is simplified.

[0224] Also, in the semiconductor device shown in this embodiment, by applying an insulating layer containing hydrogen as the interlayer insulating layer 125 and applying an insulating layer with sufficiently reduced hydrogen as the interlayer insulating layer 126, the characteristics of the transistor 160 and the transistor 162 are enhanced. Also, by having the insulating layers 143a and 143b, the so-called gate capacitance is reduced, and the transistor In the semiconductor device shown in this embodiment, by applying an insulating layer containing hydrogen as the interlayer insulating layer 125 and applying an insulating layer with sufficiently reduced hydrogen as the interlayer insulating layer 126, the characteristics of the transistor 160 and the transistor 162 are enhanced. Also, by having the insulating layers 143a and 143b, the so-called gate capacitance is reduced, and the transistor In the semiconductor device shown in this embodiment, by applying an insulating layer containing hydrogen as the interlayer insulating layer 125 and applying an insulating layer with sufficiently reduced hydrogen as the interlayer insulating layer 126, the characteristics of the transistor 160 and the transistor 162 are enhanced. Also, by having the insulating layers 143a and 143b, the so-called gate capacitance is reduced, and the transistor In the semiconductor device shown in this embodiment, by applying an insulating layer containing hydrogen as the interlayer insulating layer 125 and applying an insulating layer with sufficiently reduced hydrogen as the interlayer insulating layer 126, the characteristics of the transistor 160 and the transistor 162 are enhanced. Also, by having the insulating layers 143a and 143b, the so-called gate capacitance is reduced, and the transistor The operating speed of tab 162 has been improved.

[0225] By the above-described features shown in this embodiment, it is possible to provide a semiconductor device with extremely excellent characteristics. It is possible.

[0226] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. It can be used in appropriate combination.

[0227] (Embodiment 6) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, it will be described with reference to FIG. 12. In this embodiment, for the case of applying the above semiconductor device to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a TV or a television receiver), it will be described. Using FIG. 12, it will be described. In this embodiment, for the case of applying the above semiconductor device to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a TV or a television receiver), it will be described. Using FIG. 12, it will be described. In this embodiment, for the case of applying the above semiconductor device to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a TV or a television receiver), it will be described. Using FIG. 12, it will be described. In this embodiment, for the case of applying the above semiconductor device to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a TV or a television receiver), it will be described. Using FIG. 12, it will be described. In this embodiment, for the case of applying the above semiconductor device to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a TV or a television receiver), it will be described. Using FIG. 12, it will be described. In this embodiment, for the case of applying the above semiconductor device to electronic devices such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproduction device, etc.), a digital camera, a digital video camera, an electronic paper, and a television device (also referred to as a TV or a television receiver), it will be described.

[0228] FIG. 12(A) is a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. Inside the housing 701 and the housing 702, the semiconductor device shown in the previous embodiment is provided. Therefore, a notebook personal computer with high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. FIG. 12(A) is a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. Inside the housing 701 and the housing 702, the semiconductor device shown in the previous embodiment is provided. Therefore, a notebook personal computer with high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. FIG. 12(A) is a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. Inside the housing 701 and the housing 702, the semiconductor device shown in the previous embodiment is provided. Therefore, a notebook personal computer with high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. FIG. 12(A) is a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. Inside the housing 701 and the housing 702, the semiconductor device shown in the previous embodiment is provided. Therefore, a notebook personal computer with high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. FIG. 12(A) is a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. Inside the housing 701 and the housing 702, the semiconductor device shown in the previous embodiment is provided. Therefore, a notebook personal computer with high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized.

[0229] FIG. 12(B) is a portable information terminal (PDA). The main body 711 is provided with a display unit 713, an external interface 715, operation buttons 714, etc. FIG. 12(B) is a portable information terminal (PDA). The main body 711 is provided with a display unit 713, an external interface 715, operation buttons 714, etc. It is equipped with a stylus 712 for operating the tip. Inside the main body 711, a semiconductor device shown in the previous embodiment is provided. Therefore, a portable information terminal capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. The semiconductor device shown in the previous embodiment is provided. Therefore, a portable information terminal capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. The semiconductor device shown in the previous embodiment is provided. Therefore, a portable information terminal capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized.

[0230] Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized. Fig. 12(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. Display units 725 and 727 are provided on the housing 721 and the housing 723, respectively. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening and closing operation around the shaft portion 737. Further, the housing 721 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with a semiconductor device shown in the previous embodiment. Therefore, an electronic book capable of high-speed writing and reading of information, long-term memory retention, and sufficiently reduced power consumption is realized.

[0231] Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. Fig. 12(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Further, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in Fig. 12(D) to a state of overlapping each other, enabling miniaturization suitable for portability. Further, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, a pointing device 746, a camera lens 747, an external connection terminal 748, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone, an external memory slot 750, etc. The antenna is built in the housing 741. ​At least one of 40 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. Therefore, a mobile phone is realized in which information can be written and read at high speed, long-term memory retention is possible, and power consumption is sufficiently reduced.

[0232] FIG. 12(E) is a digital camera, which is composed of a main body 761, a display unit 767, an eyepiece unit 763, an operation switch 764, a display unit 765, a battery 766, and the like. Inside the main body 761, the semiconductor device shown in the previous embodiment is provided. Therefore, a digital camera is realized in which information can be written and read at high speed, long-term memory retention is possible, and power consumption is sufficiently reduced.

[0233] FIG. 12(F) is a television device 770, which is composed of a housing 771, a display unit 773, a stand 775, and the like. The operation of the television device 770 can be performed by switches provided in the housing 771 or a remote control operation unit 780. The housing 771 and the remote control operation unit 780 are mounted with the semiconductor device shown in the previous embodiment. Therefore, a television device is realized in which information can be written and read at high speed, long-term memory retention is possible, and power consumption is sufficiently reduced.

[0234] As described above, the electronic devices shown in this embodiment are mounted with the semiconductor devices according to the previous embodiment. For this reason, electronic devices with reduced power consumption are realized.

Example

[0235] The rewritable number of times of the semiconductor device according to one aspect of the disclosed invention was investigated. In this example, the investigation results will be described with reference to FIG. 13. ​​​​​​​​​

[0236] The semiconductor device used in the investigation is a semiconductor device with the circuit configuration shown in Fig. 1(A-1). Here , an oxide semiconductor was used for the transistor corresponding to transistor 162, and a capacitor element with a capacitance value of 0.33 pF was used as the capacitor element corresponding to capacitor element 164.

[0237] The investigation was conducted by comparing the initial memory window width with the memory window width after retaining and writing information a predetermined number of times. Retaining and writing information was performed by applying either 0 V or 5 V to the wiring corresponding to the third wiring in Fig. 1(A-1) and applying either 0 V or 5 V to the wiring corresponding to the fourth wiring. When the potential of the wiring corresponding to the fourth wiring is 0 V, the transistor (writing transistor) corresponding to transistor 162 is in the off state, so the potential applied to node FG is retained. When the potential of the wiring corresponding to the fourth wiring is 5 V, the transistor corresponding to transistor 162 is in the on state, so the potential of the wiring corresponding to the third wiring is applied to node FG.

[0238] The memory window width is one of the indices indicating the characteristics of the storage device. Here, the shift amount ΔVcg of the curve (V cg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor (reading transistor) corresponding to transistor 160 between different storage states is referred to. Different storage states refer to the state where 0 V is applied to node FG (hereinafter referred to as the Low state) and the state where 5 V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width is Low ​ It can be confirmed by sweeping the potential Vcg in the Low state and the High state.

[0239] Fig. 13 shows the investigation results of the memory window width in the initial state and after 1×10 9 write operations. In Fig. 13, the horizontal axis represents Vcg (V), and the vertical axis represents Id (A). From Fig. 13, it can be confirmed that the memory window width does not change before and after 1×10 9 write operations. The fact that the memory window width does not change before and after 1×10 write operations indicates that the semiconductor device does not deteriorate at least during this period. 9 before and after write operations means that the semiconductor device has extremely high write endurance, that is, it can be said that a semiconductor device with extremely high reliability is realized according to one aspect of the disclosed invention.

[0240] As described above, the semiconductor device according to one aspect of the disclosed invention has extremely high write endurance and does not change its characteristics even after being repeatedly written 10 9 times or more.

Embodiment

[0241] In this embodiment, the results of obtaining the off-current of a transistor using a highly purified oxide semiconductor will be described.

[0242] In this embodiment, a transistor was fabricated using a highly purified oxide semiconductor according to Embodiment 3. First, considering that the off-current of a transistor using a highly purified oxide semiconductor is extremely small, a transistor with a sufficiently large channel width W of 1 m was prepared to measure the off-current. The results of measuring the off-current of a transistor with a channel width W of 1 m is shown in FIG. 14. In FIG. 14, the horizontal axis is the gate voltage VG, and the vertical axis is the drain current ID. When the drain voltage VD is +1V or +10V, in the range where the gate voltage VG is from -5V to -2 0V, the off-current of the transistor is 1×10 -13 A or less, which is the detection limit. Also, the off-current of the transistor (here, the value per unit channel width (1μm )) was found to be 1 aA / μm (1×10 -18 A / μm) or less.

[0243] Next, the results of more accurately obtaining the off-current of a transistor using a highly purified oxide semiconductor will be described. As described above, the off-current of a transistor using a highly purified oxide semiconductor is 1×10 A or less, which is the detection limit of the measuring instrument. Therefore, a device for characteristic evaluation was fabricated, and the results of obtaining a more accurate off-current value (a value below the detection limit of the measuring instrument in the above measurement) will be described. A or less. -13 It was found that Therefore, a device for characteristic evaluation was fabricated, and the results of obtaining a more accurate off-current value (a value below the detection limit of the measuring instrument in the above measurement) will be described.

[0244] First, the device for characteristic evaluation used in the current measurement method will be described with reference to FIG. 15.

[0245] The device for characteristic evaluation shown in FIG. 15 has three measurement systems 800 connected in parallel. The measurement system 80 0 includes a capacitor element 802, transistors 804, 805, 806 , and a transistor 808. Transistors 804, 805, and 806 used transistors fabricated according to Embodiment 3.

[0246] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, one of the terminals of the capacitor element 802, and the source terminal and the drain terminal of the transistor 805 One side is connected to a power supply (the power supply that provides V2). Also, the source terminal and the other of the drain terminals of transistor 804, one of the source terminal and the drain terminal of transistor 808, the other of the terminals of capacitor element 802, and the gate terminal of transistor 805 are connected in sequence. Also, the other of the source terminal and the drain terminal of transistor 808, one of the source terminal and the drain terminal of transistor 806, and the gate terminal of transistor 806 are connected to a power supply (the power supply that provides V1). Also, the other of the source terminal and the drain terminal of transistor 805, and the other of the source terminal and the drain terminal of transistor 806 are connected to form an output terminal Vout.

[0247] Note that a potential Vext_b2 for controlling the on state and the off state of transistor 804 is supplied to the gate terminal of transistor 804, and a potential Vext_b1 for controlling the on state and the off state of transistor 808 is supplied to the gate terminal of transistor 808. Also, a potential Vout is output from the output terminal.

[0248] Next, a current measurement method using the above measurement system will be described.

[0249] First, an overview of the initialization period for applying a potential difference to measure the off current will be described. During the initialization period, a potential Vext_b1 that turns on transistor 808 is input to the gate terminal of transistor 808, and a node (that is, one of the source terminal and the drain terminal of transistor 808, the other of the terminals of capacitor element 802, and the gate terminal of Apply a potential V1 to node A, which is a node connected to the child node). Here, the potential V1 is, for example, a high potential. Also, keep transistor 804 in the off state.

[0250] After that, input a potential Vext_b1 that turns off transistor 808 to the gate terminal of transistor 808 to turn off transistor 808. After turning off transistor 808, set the potential V1 to a low potential. Here too, keep transistor 804 in the off state. Also, set the potential V2 to the same potential as V1. Thus, the initialization period ends. In the state where the initialization period has ended, a potential difference occurs between node A and one of the source electrode and drain electrode of transistor 804, and a potential difference also occurs between node A and the other of the source electrode and drain electrode of transistor 808. Therefore, a small amount of charge flows through transistors 804 and 808. That is, an off-current is generated. Next, an outline of the off-current measurement period will be described. During the measurement period, the potential of one of the source terminal or drain terminal of transistor 804 (i.e., V2), and the potential of the other of the source terminal or drain terminal of transistor 808 (i.e., V1) are fixed at a low potential. On the other hand, during the measurement period, the potential of the above node A is not fixed (set to the floating state). As a result, charge flows through transistor 804, and the amount of charge held in node A varies with the passage of time. And as the amount of charge held in node A varies, the potential of node A varies. That is, the output potential Vout of the output terminal also varies.

[0251]

[0252] ​​​​​​​​​​​​​Details of the relationship between the potentials during the initialization period in which the potential difference is applied and the measurement period thereafter The details (timing chart) are shown in Figure 16.

[0253] In the initialization period, first, the transistor 804 is turned on to supply the potential Vext_b2. This makes the potential of node A V2, that is, the low potential ( VSS). After that, the potential Vext_b2 is set to the off state by the transistor 804. The transistor 804 is turned off by applying a voltage (low potential) to the transistor 804. The potential Vext_b1 is set to a potential (high potential) that turns on the transistor 808. This causes the potential of node A to become V1, i.e., the high potential (VDD). The potential Vext_b1 is set to a potential at which the transistor 808 is turned off. As a result, node A goes into a floating state, and the initialization period ends.

[0254] In the subsequent measurement period, electric charges flow into node A, causing potentials V1 and V2 to Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). Note that the period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0255] When a potential difference is applied as described above and the measurement period starts, the voltage at node A increases over time. The amount of charge held by the transistor fluctuates, and the potential at node A fluctuates accordingly. Since it means that the potential of the gate terminal of the switch 805 fluctuates, the output potential Vout of the output terminal will also change with the passage of time.

[0256] A method for calculating the off-current from the obtained output potential Vout will be described below.

[0257] Prior to calculating the off-current, the relationship between the potential VA of node A and the output potential Vout is obtained and stored. Thereby, the potential VA of node A can be obtained from the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout as follows in the following equation.

[0258]

Equation

[0259] Also, the charge QA of node A can be expressed as follows using the potential VA of node A, the capacitance CA connected to node A, and a constant (const). Here, the capacitance CA connected to node A is the sum of the capacitance of the capacitive element 802 and other capacitances. CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0260]

Equation

[0261] Since the current IA of node A is the time derivative of the charge flowing into (or flowing out of) node A, the current IA of node A is expressed as follows. Since the current IA of node A is the time derivative of the charge flowing into (or flowing out of) node A, the current IA of node A is expressed as follows.

[0262]

Equation

[0263] Thus, the current IA of node A can be obtained from the capacitance CA connected to node A and the output potential Vout of the output terminal.

[0264] By the method shown above, the leakage current (off-current) flowing between the source and drain of the transistor in the off state can be measured.

[0265] In this embodiment, transistors 804, 805, 806, and 808 were fabricated using a highly purified oxide semiconductor with a channel length L = 10 μm and a channel width W = 50 μm. Also, in each parallel measurement system 800, the capacitance values of the capacitive elements 802a, 802b, and 802c were set to 100 fF for the capacitive element 802a, 1 pF for the capacitive element 802b, and 3 pF for the capacitive element 802c, respectively.

[0266] In the measurement according to this embodiment, VDD = 5 V and VSS = 0 V. Also, during the measurement period, the potential V1 was set to VSS as a principle, and Vout was measured as VDD only for a period of 100 msec every 10 to 300 sec. Further, Δt used for calculating the current I flowing through the element was set to approximately 30000 sec.

[0267] FIG. 17 shows the relationship between the elapsed time Time related to the above current measurement and the output potential Vout. From FIG. 17, it can be confirmed that the potential changes as time elapses.

[0268] FIG. 18 shows the off-current calculated by the above current measurement. Note that FIG. 18 shows the relationship between the source-drain voltage V and the off-current I. From FIG. 18, it can be seen that the off-current is about 40 zA / μm at room temperature under the condition that the source-drain voltage is 4 V. ​ In addition, under the condition that the source-drain voltage is 3.1 V, the off-current was found to be 10 zA or less at room temperature. / μm. Note that 1 zA represents 10 -21 A.

[0269] As described above, according to this embodiment, in the transistor using the highly purified oxide semiconductor, it was confirmed that the off-current is sufficiently small.

Description of Reference Numerals

[0270] 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108a Gate insulating layer 110a Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound region 125 Interlayer insulating layer 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c Electrode 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 Interlayer insulating layer 152 Interlayer insulating layer 154 Source electrode or drain electrode 160 transistors 162 transistors 164 capacitive elements 701 housing 702 housing 703 display unit 704 keyboard 711 main body 712 stylus 713 display unit 714 operation button 715 external interface 720 e - book 721 housing 723 housing 725 display unit 727 display unit 731 power supply 733 operation key 735 speaker 737 shaft part 740 housing 741 housing 742 display panel 743 speaker 744 microphone 746 pointing device 747 camera lens 748 external connection terminal 749 solar cell 750 external memory slot 761 main body 763 eyepiece 764 operation switch 765 display unit 766 battery 767 display unit 770 television device 771 housing 773 display unit 775 stand 780 remote control operation unit 802 capacitive elements 802a capacitive elements 802b capacitive elements 802c capacitive elements 804 Transistor 805 Transistor 806 Transistor 808 Transistor

Claims

1. A semiconductor device including a first transistor including a channel formation region made of silicon, a second transistor including a channel formation region made of an oxide semiconductor, and a capacitor, a first insulating layer having a function as a gate insulating layer of the first transistor; a first conductive layer having a region located on the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region overlying the first conductive layer; a third insulating layer having a region overlying the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the third insulating layer and a region in contact with the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the third insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth insulating layer having a region located over the oxide semiconductor layer, a region located over the second conductive layer, and a region located over the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as the other electrode of the capacitor; a fifth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; having The second conductive layer is always electrically connected to the first conductive layer.

2. A semiconductor device including a first transistor including a channel formation region made of silicon, a second transistor including a channel formation region made of an oxide semiconductor, and a capacitor, a first insulating layer having a function as a gate insulating layer of the first transistor; a first conductive layer having a region located on the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region overlying the first conductive layer; a third insulating layer having a region overlying the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the third insulating layer and a region in contact with the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the third insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth insulating layer having a region located over the oxide semiconductor layer, a region located over the second conductive layer, and a region located over the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as the other electrode of the capacitor; a fifth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; having the second conductive layer is always electrically connected to the first conductive layer; the other of the source electrode and the drain electrode of the second transistor has a region in contact with an upper surface of the third insulating layer; The other of the source electrode and the drain electrode of the first transistor has a region in contact with an upper surface of the third insulating layer.

3. A semiconductor device including a first transistor including a channel formation region made of silicon, a second transistor including a channel formation region made of an oxide semiconductor, and a capacitor, a first insulating layer having a function as a gate insulating layer of the first transistor; a first conductive layer having a region located on the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region overlying the first conductive layer; a third insulating layer having a region overlying the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the third insulating layer and a region in contact with the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the third insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth insulating layer having a region located over the oxide semiconductor layer, a region located over the second conductive layer, and a region located over the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as the other electrode of the capacitor; a fifth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; having the second conductive layer is always electrically connected to the first conductive layer; the fifth conductive layer has an area overlapping with the first conductive layer, The second conductive layer has a region overlapping with the first conductive layer.

4. A semiconductor device including a first transistor including a channel formation region made of silicon, a second transistor including a channel formation region made of an oxide semiconductor, and a capacitor, a first insulating layer having a function as a gate insulating layer of the first transistor; a first conductive layer having a region located on the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region overlying the first conductive layer; a third insulating layer having a region overlying the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the third insulating layer and a region in contact with the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the third insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth insulating layer having a region located over the oxide semiconductor layer, a region located over the second conductive layer, and a region located over the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as the other electrode of the capacitor; a fifth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; having the second conductive layer is always electrically connected to the first conductive layer; the other of the source electrode and the drain electrode of the second transistor has a region in contact with an upper surface of the third insulating layer; the other of the source electrode and the drain electrode of the first transistor has a region in contact with an upper surface of the third insulating layer; the fifth conductive layer has an area overlapping with the first conductive layer, The second conductive layer has a region overlapping with the first conductive layer.

5. In any one of claims 1 to 4, The oxide semiconductor layer includes In, Ga, and Zn.

6. In any one of claims 1 to 4, The oxide semiconductor layer is an In-O based oxide semiconductor.

Images