Semiconductor device

Abstract

To provide a semiconductor device with high on-current and fast operation speed.SOLUTION: A semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate. The first gate and the second gate include regions which overlap each other with a semiconductor layer in between. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor includes a function for acquiring temperature information and outputting temperature information to the voltage control circuit. The voltage control circuit includes a function for converting temperature information into control voltage. The first circuit applies control voltage to the second gate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] In addition, one aspect of the present invention relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. One aspect of the present invention relates to a driving method or a manufacturing method thereof.

[0003] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A storage device, a display device, an electro-optical device, a power storage device, a semiconductor circuit, and an electronic device may have a semiconductor device.

Background Art

[0004] As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known. However, an oxide semiconductor (OS: Oxide Semiconductor ) has attracted attention as another material. As the oxide semiconductor, for example, not only oxides of single-element metals such as indium oxide and zinc oxide, but also oxides of multi-element metals are known. Among the oxides of multi-element metals, in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

[0005] According to research on IGZO, in an oxide semiconductor, a CA AC (c-axis aligned crystalline) structure and an nc (na nocrystalline) structure that are neither single crystal nor amorphous have been found (see Non-Patent Documents 1 to 3). ​​​​​)。In Non-Patent Document 1 and Non-Patent Document 2, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are also disclosed. Furthermore, it is shown in Non-Patent Document 4 and Non-Patent Document 5 that even an oxide semiconductor having a lower crystallinity than the CAAC structure and the nc structure has minute crystals. Furthermore, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are also disclosed. In addition, Non-Patent Document 4 and Non-Patent Document 5 show that even an oxide semiconductor having a lower crystallinity than the CAAC structure and the nc structure has minute crystals.

[0006] Furthermore, a transistor using IGZO as an active layer has an extremely low off-current (see Non-Patent Document 6), and LSIs and displays utilizing such characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8).

[0007] In addition, various semiconductor devices using a transistor having an oxide semiconductor in a channel formation region (hereinafter also referred to as an "OS transistor") have been proposed.

[0008] Patent Document 1 discloses an example of using an OS transistor in a DRAM (Dynamic Random Access Memory). Since the leakage current (off-current) in the off state of an OS transistor is extremely small, a DRAM with a long refresh period and low power consumption can be fabricated.

[0009] In addition, Patent Document 2 discloses a non-volatile memory using an OS transistor. These non-volatile memories, unlike flash memories, have no limit on the number of rewrites, can easily achieve high-speed operation, and consume less power.

[0010] By increasing the threshold voltage of these OS transistors used in memories, it becomes possible to reduce the off-current and improve the data retention characteristics of the memories. It is possible. Patent Document 2 discloses an example in which a second gate is provided to an OS transistor to control the threshold voltage of the OS transistor and reduce the off-current.

[0011] In order for the memory to hold data for a long time, it is necessary to continuously apply a certain negative potential to the second gate of the OS transistor. Patent Documents 2 and 3 disclose configuration examples of circuits for driving the second gate of the OS transistor.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0013]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Non-Patent Document 7

Non-Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0014] One aspect of the present invention is to provide a semiconductor device with a high on-current as one of the problems. Also, One aspect of the present invention is to provide a semiconductor device with a high operating speed as one of the problems. Also, One of the problems is to provide a semiconductor device that can be used in a wide temperature range. Also, one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period as one of the problems to be solved. Also, one aspect of the present invention is to provide a semiconductor device with reduced power consumption as a problem Let it be one of them. One aspect of the present invention aims to provide a novel semiconductor device as one of the problems.

[0015] Note that the description of multiple problems does not prevent the existence of each other's problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Also, problems other than those listed will naturally become clear from the descriptions in the specification, drawings, claims, etc., and these problems can also be problems of one aspect of the present invention.

Means for Solving the Problems

[0016] One aspect of the present invention is a semiconductor device having a transistor and a first circuit. The transistor has a first gate and a second gate, and the first gate and the second gate have a region overlapping each other with a semiconductor layer therebetween. The first circuit has a temperature sensor and a voltage control circuit. The temperature sensor has a function of acquiring temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage, and the first circuit applies the control voltage to the second gate.

[0017] In the semiconductor device described above, it is preferable that the voltage control circuit converts the temperature information into the control voltage based on a conversion formula.

[0018] In the semiconductor device described above, it is preferable that the voltage control circuit has a microcomputer or an amplifier.

[0019] In the semiconductor device described above, it is preferable that the semiconductor layer has a metal oxide.

[0020] In the semiconductor device described above, it further has a second circuit, and it is preferable that the second circuit applies a negative voltage to the second gate. ​​​​

[0021] In the semiconductor device described above, the second circuit can hold a negative voltage.

[0022] In the semiconductor device described above, the second circuit preferably has a transistor including a metal oxide in a channel formation region. It preferably has a transistor.

[0023] The semiconductor device described above preferably has a function of applying a positive voltage or a negative voltage to the first gate and a function of applying a negative voltage to the second gate. It preferably has a function of applying a negative voltage to the second gate.

Advantages of the Invention

[0024] According to one aspect of the present invention, a semiconductor device having a high on-current can be provided. Also, according to one aspect of the present invention, a semiconductor device having a high operating speed can be provided. Also, according to one aspect of the present invention, a semiconductor device that can be used in a wide temperature range can be provided. Also, according to one aspect of the present invention, a semiconductor device capable of holding data for a long period of time can be provided. Also, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Also, according to one aspect of the present invention, a novel semiconductor device can be provided. According to one aspect of the present invention, a semiconductor device with a high operating speed can be provided. According to one aspect of the present invention, a semiconductor device that can be used in a wide temperature range can be provided. According to one aspect of the present invention, a semiconductor device capable of holding data for a long period of time can be provided. According to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. According to one aspect of the present invention, a novel semiconductor device can be provided.

[0025] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0026]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Embodiments for Carrying Out the Invention

[0027] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description and can be variously modified in its form and details without departing from the spirit and scope of the present invention, which can be easily understood by those skilled in the art. Therefore, the present invention should not be construed as being limited to the forms and descriptions of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof will be omitted. Also, when referring to the same function, the hatching pattern may be the same and may not be particularly labeled.

[0029] In each of the drawings described in this specification, the size, layer thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0030] In this specification, the high power supply voltage may be referred to as the H level (or VDD), and the low power supply voltage may be referred to as the L level (or GND).

[0031] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in the electrostatic field at a certain point. However, generally, the potential difference between the potential at a certain point and the reference potential (e.g., ground potential) is simply referred to as potential or voltage, and potential and voltage are often used as synonyms. Therefore, in this specification and the like, unless otherwise specified, potential may be read as voltage or voltage may be read as potential.

[0032] ​​Also, this specification can appropriately combine the following embodiments and examples. Also, when multiple configuration examples are shown within one embodiment, the configuration examples can be appropriately combined with each other.

[0033] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. Also, when referring to an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor. Also, in this specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides.

[0034] (Embodiment 1) A semiconductor device, which is one aspect of the present invention, has a temperature sensor and a voltage correction circuit. The semiconductor device is electrically connected to a transistor included in a memory device or the like, and has a function of applying a voltage corresponding to temperature to the back gate of the transistor. By controlling the back gate voltage so that the cutoff current of the transistor is substantially the same regardless of temperature, a memory device or the like having a high operating frequency in a wide temperature range can be obtained.

[0035] <Semiconductor device 100> FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device 100, which is one aspect of the present invention. The semiconductor device 100 has a voltage generation circuit 11, a voltage holding circuit 12, and a correction circuit 20. The voltage generation circuit 11 is electrically connected to the voltage holding circuit 12, and the voltage holding circuit 12 The node between the correction circuit 20 and the voltage holding circuit 12 is called a node N. The voltage holding circuit 12 and the correction circuit 20 are connected to an output terminal VOU via a node ND. Electrically connected to T.

[0036] In addition, the semiconductor device 100 outputs a first output of the plurality of transistors M10 through the output terminal VOUT. The first gate ("front gate") of each transistor M10 is electrically connected to the second gate of the transistor M10. The first gate (also called the "first gate" or simply the "gate") and the second gate (also called the "back gate"). ) of the respective transistors M10. V th0 In the transistor M10, the first gate and the second gate The gates preferably have an overlapping region with a semiconductor layer interposed therebetween. 100 is electrically connected to the second gate of the transistor M10 via the output terminal VOUT. It has been done.

[0037] The transistor M10 is used in various circuits included in memory devices, pixel devices, arithmetic devices, etc. For example, the transistors in NOR and NAND type memory devices In addition, for example, a liquid crystal display device or an EL display device The transistors included in each display device are also shown. GPU (Graphic Processing Unit), GPU (Graphic Processing Unit) ng Unit), or FPGA (Field Programmable Gate Figure 1 shows three transistors in a 3-phase MOS FET. Although M10 is shown, the semiconductor device 100 may include many transistors. It may be connected to the transistor M10. In the following description, the transistor M10 is described as an n-channel transistor.

[0038] Compared with a transistor using silicon for the semiconductor layer in which a channel is formed (also referred to as a "Si transistor"), the OS transistor has a smaller increase in off-current even in operation at high temperatures. Also, in the OS transistor, as the operating temperature rises, Vth shifts in the negative direction, and the on-current increases. On the other hand, in the Si transistor, as the temperature rises, the off-current increases. Also, in the Si transistor, as the temperature rises, Vth shifts in the positive direction, and the on-current decreases. Therefore, by using the OS transistor as the transistor M10, the power consumption of the entire semiconductor device including the transistor M10 can be reduced even in operation at high temperatures.

[0039] The semiconductor device 100 has a function of writing a voltage V BG to the second gate of the transistor M10 and further holding it. For example, when a negative potential is applied as the voltage V BG , the transistor M10 can shift V to the plus side while the negative potential of the second gate is being held. By keeping V th0 high, the transistor M10 can prevent normal-on and reduce the power consumption of the entire semiconductor device including the transistor M10. th0 For example, when the transistor M10 is used as the selection transistor of a memory cell, the charge of the capacitive element functioning as a storage can be held for a long time.

[0040] 〔Voltage generation circuit 11〕 An example of the circuit configuration of the voltage generation circuit 11 is shown in FIGS. 2(A) and 2(B). These circuit diagrams are step-down charge pumps, with GND input to the input terminal IN and V BG0 output from the output terminal OUT. Here, as an example, the number of stages of the basic circuit of the charge pump circuit is 4 stages, but it is not limited to this, and the charge pump circuit may be configured with any number of stages.

[0041] The voltage generation circuit 11a shown in FIG. 2(A) includes transistors M21 to M24, and capacitor elements C21 to C24. Hereinafter, transistors M21 to M24 will be described as n-channel transistors.

[0042] Transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT, and their gates and first electrodes are connected so as to function as diodes. The gates of transistors M21 to M24 are each connected to capacitor elements C21 to C24. CLK is input to the first electrodes of the odd-stage capacitor elements C21 and C23, and CLKB is input to the first electrodes of the even-stage

[0043] capacitor elements C22 and C24. CLKB is an inverted clock signal obtained by inverting the phase of CLK. The voltage generation circuit 11a has the function of stepping down the GND input to the input terminal IN and generating V

[0044] . The voltage generation circuit 11a can generate a negative potential only by supplying CLK and CLKB. BG0 The voltage generation circuit 11a can generate a negative potential only by supplying CLK and CLKB.

[0045] The above-described transistors M21 to M24 may also be formed of OS transistors. By using OS transistors, it is preferable that the reverse current of the diod-connected transistors M21 to M24 can be reduced.

[0046] The voltage generation circuit 11b shown in FIG. 2(B) is composed of transistors M31 to M34 which are p-channel transistors. Regarding other components, the description of the voltage generation circuit 11a is incorporated.

[0047] 〔Voltage holding circuit 12〕 The voltage holding circuit 12 includes a transistor M11 (see FIG. 1). The transistor M11 has a first gate and a second gate. The first gate and the second gate preferably have a region overlapping with each other with a semiconductor layer therebetween. In the following description, the transistor M11 will be described as an n-channel transistor.

[0048] The first terminal of the transistor M11 is electrically connected to the voltage generation circuit 11, and the second terminal of the transistor M 11 is electrically connected to the node ND. The second terminal of the transistor M11 is electrically connected to the first gate of the transistor M11 and the second gate of the transistor M11. The transistor M11 has a function as a diode.

[0049] The voltage holding circuit 12 has a function of applying and holding the voltage V BG0 generated by the voltage generation circuit 11 to the second gate of the transistor M10 as the voltage V BG0 . Assuming that the threshold voltage of the transistor M11 is V BG th1 BG0 BG th1 BG0 BG0 =V BG -Vth1 The relationship is established. It holds.

[0050] Transistor M11 has the function of writing and holding a potential at the second gate of transistor M10. FIG. 3(A) shows, as an example, an example in which a negative potential (-5V) is written at the second gate of transistor M10. The negative potential written at the second gate of transistor M10 shifts V of transistor M10 to positive. By setting its first terminal to GND, transistor M11 holds the written negative potential, and transistor M10 can maintain normal-off. In FIG. 3(A), for transistor M11, V becomes 0V. If the drain current at V = 0V (hereinafter referred to as "cut-off current" or "Icut") is sufficiently small, transistor M11 blocks the flow of charge, and voltage holding circuit 12 can hold the above negative potential for a long time. The negative potential written at the second gate of transistor M10 shifts V of transistor M10 to positive. The negative potential written at the second gate of transistor M10 shifts V of transistor M10 to positive. th0 Transistor M11 By setting its first terminal to GND, transistor M11 holds the written negative potential, and transistor M10 can maintain normal-off. Transistor M10 can maintain normal-off.

[0051] In FIG. 3(A), for transistor M11, V G becomes 0V. G At V = 0V, if the drain current (hereinafter referred to as "cut-off current" or "Icut") is sufficiently small, transistor M11 blocks the flow of charge, and voltage holding circuit 12 can hold the above negative potential for a long time. Voltage holding circuit 12 can hold the above negative potential for a long time.

[0052] The channel length of transistor M11 is preferably longer than the channel length of transistor M10. For example, when the channel length of transistor M10 is less than 1 μm, the channel length of transistor M11 is 1 μm or more, more preferably 3 μm or more, still more preferably 5 μm or more, and even more preferably 10 μm or more. By making the channel length of transistor M11 long, transistor M11 is not affected by the short-channel effect, and the cut-off current can be kept low. Also, the breakdown voltage between the source and drain of transistor M11 can be increased. When the breakdown voltage between the source and drain of transistor M11 is high, a high voltage For example, when the channel length of transistor M10 is less than 1 μm, the channel length of transistor M11 is 1 μm or more, more preferably 3 μm or more, still more preferably 5 μm or more, and even more preferably 10 μm or more. For example, when the channel length of transistor M10 is less than 1 μm, the channel length of transistor M11 is 1 μm or more, more preferably 3 μm or more, still more preferably 5 μm or more, and even more preferably 10 μm or more. 5 μm or more, and even more preferably 10 μm or more. By making the channel length of transistor M11 long, transistor M11 is not affected by the short-channel effect, and the cut-off current can be kept low. By making the channel length of transistor M11 long, transistor M11 is not affected by the short-channel effect, and the cut-off current can be kept low. can be applied. A voltage generation circuit 11 that can facilitate the connection with the transistor M10 is preferable. Preferably.

[0053] For the transistor M11, it is preferable to use an OS transistor or a transistor using a wide bandgap semiconductor in the channel formation region. The OS transistor or the transistor using a wide bandgap semiconductor has a small cut-off current and a high breakdown voltage between the source and the drain. In this specification, the wide bandgap semiconductor means a semiconductor having a bandgap of 2.2 eV or more. For example, silicon carbide, gallium nitride, diamond, etc. can be mentioned. Preferably. Preferably. Preferably. Preferably. Preferably.

[0054] The transistor M11 is required to have a smaller cut-off current than the transistor M10. On the other hand, the transistor M10 is required to have a larger on-current than the transistor M11. When transistors with different required properties are fabricated on the same substrate, different semiconductors can be used to form each transistor. The transistor M11 preferably uses a semiconductor with a larger bandgap in the channel formation region than the transistor M10. Also, the transistor M10 preferably uses a semiconductor with a higher electron mobility in the channel formation region than the transistor M11. Preferably. Preferably. Preferably. Preferably. Preferably. Preferably.

[0055] In addition, the second gate of the transistor M11 may be omitted in some cases.

[0056] Also, the voltage holding circuit 12 may be composed of a plurality of transistors M11 connected in series (see Fig. 3(B)). Preferably.

[0057] 〔Correction Circuit 20〕 The correction circuit 20 measures the temperature and has a function of controlling the voltage applied to the second gate of the transistor M10 according to the obtained temperature information. The correction circuit 20 controls the voltage applied to the second gate so that the off-current of the transistor M10 is approximately equal even when the temperatures are different. When the temperatures are different, the correction circuit 20 controls the voltage applied to the second gate so that the off-current of the transistor M10 is approximately equal.

[0058] Figure 4 is a schematic diagram showing the temperature dependence of the I D (drain current)-V G (gate voltage) characteristics of the OS transistor. The I -V D characteristics indicate the change in the drain current (I G ) with respect to the change in the gate voltage (V G ). In Figure 4, the horizontal axis shows Vg on a linear scale, and the vertical axis shows I on a logarithmic scale. D D

[0059] In Figure 4, the examples of the I -V D characteristics of the OS transistor measured at temperature A of 85°C, temperature B of 27°C, and temperature C of -40°C are shown. Note that the back gate voltage is the same at each temperature. For the OS transistor, the threshold voltage shifts positively and the on-current decreases as the temperature decreases. As a result, the operating speed of the circuit decreases. Also, the threshold voltage shifts negatively and the subthreshold slope increases as the temperature increases. As a result, the cut-off current increases. In Figure 4, the cut-off current at temperature A is denoted as IcutA, the cut-off current at temperature B is denoted as IcutB, and the cut-off current at temperature C is denoted as IcutC. As shown in Figure 4, the cut-off current increases as the temperature increases. G When an OS transistor is used for the transistor M10, as shown in Figure 4, depending on the temperature the threshold voltage shifts positively and the on-current decreases. As a result, the operating speed of the circuit decreases. Also, the threshold voltage shifts negatively and the subthreshold slope increases as the temperature increases. As a result, the cut-off current increases. In Figure 4, the cut-off current at temperature A is denoted as IcutA, the cut-off current at temperature B is denoted as IcutB, and the cut-off current at temperature C is denoted as IcutC. As shown in Figure 4, the cut-off current increases as the temperature increases. the cut-off current increases.

[0060] when an OS transistor is used for the transistor M10, as shown in Figure 4, depending on the temperature The threshold voltage (V th0 ) fluctuates. As the temperature decreases, V th0 shifts in the positive direction , and as the temperature increases, V th0 shifts in the negative direction. This becomes a factor that narrows the operable temperature range for the circuit. Therefore, it is preferable that the semiconductor device 100 has a correction circuit 20. The semiconductor device 100 has, for example, a function of applying a higher back gate voltage to the transistor M10 as the temperature decreases, and can shift the V of the transistor M10 in the negative th0 direction to increase the on-current. Thereby, the operating speed of the circuit can be increased .

[0061] The correction circuit 20 includes a temperature sensor 17, a voltage control circuit 18, a buffer 15, and a capacitive element 14 (see FIG. 1).

[0062] The temperature sensor 17 has a function of sensing the temperature of the semiconductor device 100 and outputting temperature information V Temp . The temperature information V is analog data and corresponds to the temperature sensed by the temperature sensor 17. The temperature information V Temp may be a voltage or a current . Temp

[0063] As the temperature sensor 17, for example, a resistance temperature detector such as platinum, nickel, or copper, a thermistor , a thermocouple, an IC temperature sensor, etc. can be used.

[0064] The voltage control circuit 18 has a function of controlling the voltage applied to the second gate of the transistor M10 according to the temperature information V Temp obtained from the temperature sensor 17. The voltage control circuit 18 ​​​​has a microcomputer, a microprocessor or an amplifier, and based on a conversion formula, it converts the temperature information V Temp and outputs a control voltage V CTR . In this specification etc., a microcomputer or a microprocessor may be referred to as a microcontroller.

[0065] The control voltage V CTR controls the back gate voltage V so that the cut-off current of the transistor M10 becomes approximately the same regardless of the temperature. The aforementioned conversion formula is a formula that BG converts from the temperature information V Temp to a control voltage V CTR corresponding to the temperature. By using different back gate voltages V BG to make the cut-off current of the transistor M10 approximately the same, the circuit electrically connected to the output terminal VOUT can have a high operating frequency in a wide temperature range.

[0066] The I BG -V characteristics when the back gate voltage V D is controlled so that the cut-off current of the transistor M10 becomes approximately the same are shown in FIG. 5. FIG. 5 shows an example of adjusting the back gate voltage V G so that the cut-off current at each of the temperatures A, B, and C becomes Icut0. As Icut0, for example, a cut-off current value required for the transistor may be used based on the specifications of the semiconductor device. BG shown. As Icut0, for example, the cut-off current value that becomes the highest in the specified temperature range may be used. In the examples shown in FIGS. 4 and 5, Icut of temperature A where the cut-off current is the highest

[0067] ​​​​​​A can be used as Icut0. To set the cut-off current to Icut0 at temperature B, a control voltage V higher than temperature A is output, and a back-gate voltage V CTR higher than temperature A is used. To set the cut-off current to Icut0 at temperature C, a control voltage V higher than temperature B is output, and a back-gate voltage V BG higher than temperature B is used. An example of the conversion from temperature information V CTR to control voltage V BG is shown in FIGS. 6(A), 6(B), and

[0068] 6(C). As shown in FIG. 6(A), temperature information V Temp and control voltage V CTR can have a linear relationship. As shown in FIG. 6(B), temperature information V and control voltage V Temp and CTR can also have a non-linear relationship. As shown in FIGS. 6(A) and 6(B), by using the conversion formula between temperature information V Temp and control voltage V CTR , the difference in temperature can be finely corrected. FIGS. 6(A) and 6(B) show examples where the higher the temperature, the higher the temperature information V Temp and CTR control voltage V . Also, as shown in FIG. 6(C), it can be configured to perform the conversion using a table of temperature information V V Temp and control voltage V Temp and CTR . For example, for each of temperature information V to V Temp1 and Tempn , it can be configured to output control voltage V CTR1 to V CTR n (n is an integer of 2 or more).

[0069] From the characteristics of a transistor having the same or similar structure as the transistor M10, FIG. The conversion formula shown in FIG. 6(B) or the table shown in FIG. 6(C) is prepared in advance. The table is stored in the voltage control circuit 18. By using a table, the voltage control circuit 18 obtains the temperature information V Temp Control according to Voltage V CTR can be output.

[0070] The control voltage V output by the voltage control circuit 18 CTR is fed to the input of buffer 15. One electrode of the capacitance element 14 is electrically connected to the output of the buffer 15, and the other electrode is connected to a node The buffer 15 is electrically connected to the ND. In some cases, it may be omitted.

[0071] The voltage applied to the node ND from the voltage control circuit 18 is determined by the capacitance of the capacitive element 14 and the The capacitance of the capacitance element 14 is determined by the ratio of the parasitic capacitances generated in the It is preferable that the capacitance of the capacitance element 14 is sufficiently large. It is preferable that the correction factor is 5 times or more, and more preferably 10 times or more. A voltage according to temperature can be supplied to the node ND from the line 20. The voltage VOUT of the output terminal BG can be changed.

[0072] If the temperature change of the electrical characteristics of transistor M10 is not taken into consideration, a voltage larger than necessary will be applied to the transistor. A voltage larger than necessary is applied to the second gate of transistor M10. If a voltage is applied to the second gate of transistor M10 for a long period of time, the electrical characteristics of transistor M10 will deteriorate. and there is a risk of impairing reliability. According to one aspect of the present invention, the voltage applied to the second gate of the transistor M 10 can be changed. Therefore, the minimum necessary voltage can be applied to the second gate of the transistor M10. According to one aspect of the present invention, the reliability of the semiconductor device including the transistor M11 can be improved.

[0073] The temperature sensor 17 may include a voltage control circuit 18 inside. The circuit diagram in that case is shown in FIG 7. In FIG. 7, the temperature sensor 19 includes a power control circuit (not shown) inside, and V CTR can be directly output.

[0074] As described above, by using the semiconductor device 100 shown in this embodiment, a semiconductor device with a high on-current can be provided. Also, a semiconductor device with a high operating speed can be provided. Also a semiconductor device capable of holding data for a long period can be provided. Also, a semiconductor device with reduced power consumption can be provided.

[0075] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments etc. It is possible.

[0076] (Embodiment 2) In this embodiment, a memory device using the semiconductor device 100 described in Embodiment 1 will be described .

[0077] <Memory device> FIG. 8 is a block diagram showing a configuration example of a memory device. The memory device 300 includes a peripheral circuit 311 , a cell array 401, and a semiconductor device 100. The peripheral circuit 311 includes a load decoder Word line driver circuit 321, word line driver circuit 322, bit line driver circuit 330, output circuit 340 and has a control logic circuit 360.

[0078] The word line driver circuit 322 has a function of supplying a potential to the wiring WL. The bit line driver circuit 330 has a column decoder 331, a precharge circuit 332, an amplifier circuit 333, and a write circuit 334. The precharge circuit 332 has a function of precharging the wiring SL (not shown) and the like. The amplifier circuit 333 has a function of amplifying the data signal read from the wiring BIL or the wiring RBL . Note that the wiring WL, the wiring SL, the wiring BIL, and the wiring RBL are wirings connected to the memory cell 411 included in the cell array 401, and will be described in detail later. The amplified data signal is output to the outside of the storage device 300 as a digital data signal RDATA via the output circuit 340.

[0079] A low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 311, and a high power supply voltage (VIL) for the cell array 401 are supplied to the storage device 300.

[0080] In addition, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 300 from the outside. The address signal ADDR is input to the row decoder 32 1 and the column decoder 331, and the WDATA is input to the write circuit 334.

[0081] The control logic circuit 360 processes the input signals (CE, WE, RE) from the outside and generates control signals for the row decoder 321 and the column decoder 331. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The WE is a write enable signal, and the RE is a read enable signal. The signals processed by the control logic circuit 360 are not limited to these, and other control signals may be input as necessary. The signals processed by the control logic circuit 360 are not limited to these, and other control signals may be input as necessary. The signals processed by the control logic circuit 360 are not limited to these, and other control signals may be input as necessary.

[0082] In addition, each of the above circuits or signals can be appropriately selected or discarded as necessary.

[0083] OS transistors can be applied to the transistors constituting the cell array 401. Also, OS transistors can be applied to the transistors constituting the peripheral circuit 311. By forming the cell array 401 and the peripheral circuit 311 using OS transistors, it becomes possible to fabricate the cell array 401 and the peripheral circuit 311 in the same manufacturing process, and the manufacturing cost can be reduced. By forming the cell array 401 and the peripheral circuit 311 using OS transistors, it becomes possible to fabricate the cell array 401 and the peripheral circuit 311 in the same manufacturing process, and the manufacturing cost can be reduced. By forming the cell array 401 and the peripheral circuit 311 using OS transistors, it becomes possible to fabricate the cell array 401 and the peripheral circuit 311 in the same manufacturing process, and the manufacturing cost can be reduced.

[0084] 〔Configuration Example of Cell Array〕 The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The details of the cell array 401 are described in FIG. 9. The cell array 401 has a total of m×n memory cells 411, where m (m is an integer of 1 or more) cells are arranged in a column and n (n is an integer of 1 or more) cells are arranged in a row, and the memory cells 411 are arranged in a matrix. In FIG. 9, the addresses of the memory cells 411 are also shown, and the memory cells 411 located at the addresses [1,1], [m,1], [i,j], [1,n], and [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are illustrated. Note that the number of wirings connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in a column, and the like. Also, the cell array 401 and The number of wirings connecting the bit line driver circuit 330 is determined by the configuration of the memory cell 411, the number of memory cells 411 included in one row, and the like.

[0085] 〔Configuration Example of Memory Cell〕 FIG. 10 shows configuration examples of memory cells 411A to 411E applicable to the above-described memory cell 411.

[0086] [DOSRAM] FIG. 10(A) shows a circuit configuration example of a DRAM-type memory cell 411A. In this specification and the like, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 411A includes a transistor M11 and a capacitor element CA.

[0087] The first terminal of the transistor M11 is connected to the first terminal of the capacitor element CA, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitor element CA is connected to the wiring GNDL. The wiring GNDL is a wiring that supplies a low-level potential (which may be referred to as a reference potential).

[0088] The wiring BIL functions as a bit line, and the wiring WL functions as a word line. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. Also, the wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased. ​​​​​​​​​​​

[0089] Data writing and reading are performed by applying a high-level potential to the wiring WL, turning on the transistor M 1 to the conducting state, and electrically connecting the wiring BIL and the first terminal of the capacitor element CA thereby.

[0090] Also, the memory cells included in the above-described memory device 300 are not limited to the memory cell 411A and the circuit configuration can be changed.

[0091] When using the transistor M11 as a memory cell, it is preferable to use an OS transistor for the transistor M11. Also, on the semiconductor layer of the OS transistor, indium, element M (element M is aluminum, gallium, yttrium, or tin), or any one of zinc is preferably used as the oxide semiconductor. In particular, an oxide semiconductor composed of indium, gallium, and zinc is preferably used.

[0092] An OS transistor to which an oxide semiconductor containing indium, gallium, and zinc is applied has the characteristic that the off-current is extremely small. By using an OS transistor as the transistor M11 the leakage current of the transistor M11 can be made very low . That is, the written data can be held by the transistor M11 for a long time . Therefore, the frequency of refreshing the memory cell can be reduced. Also, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very low, multi-valued data or analog log data can be held for the memory cell 411A, the memory cell 420, and the memory cell 430.

[0093] ​​​​By applying an OS transistor as the transistor M11, a DOSRAM can be configured. This can be achieved.

[0094] [NOSRAM] Fig. 10(B) shows a circuit configuration example of a gain cell type (also referred to as "2Tr1C type") memory cell 411B having two transistors and one capacitive element. The memory cell 411B includes a transistor M11, a transistor M3, and a capacitive element CB.

[0095] The first terminal of the transistor M11 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M11 is connected to the wiring WBL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitive element CB is connected to the wiring RL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.

[0096] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WL functions as a word line. The wiring RL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CB. During data writing and data holding, it is preferable to apply a reference potential to the wiring RL.

[0097] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. Also, the wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0098] Data writing is performed by applying a high-level potential to the wiring WL, turning on the transistor M11, and electrically connecting the wiring WBL and the first terminal of the capacitor element CB. Specifically, when the transistor M11 is in the conductive state, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitor element CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WL to turn off the transistor M11, thereby holding the potential of the first terminal of the capacitor element CB and the potential of the gate of the transistor M3.

[0099] Data reading is performed by applying predetermined potentials to the wiring RL and the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, by reading the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held at the first terminal of the capacitor element CB (or the gate of the transistor M3) can be read. That is, the information written in this memory cell can be read from the potential held at the first terminal of the capacitor element CB (or the gate of the transistor M3). Or, it is possible to know whether there is information written in this memory cell.

[0100] Also, the memory cells included in the above-described storage device 300 are not limited to the memory cell 411B. ​​​​​​​​​​​​​​The configuration of the circuit can be changed as appropriate.

[0101] For example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of the memory cell is shown in FIG. 10(C). The memory cell 411C has the wiring WBL and the wiring RBL of the memory cell 411B combined into a single wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. That is, the memory cell 411C operates with a single wiring BIL for the write bit line and the read bit line. That is, the memory cell 411C has a configuration in which the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. That is, the memory cell 411C is configured to operate with a single wiring BIL for the write bit line and the read bit line. That is, the memory cell 411C is configured to operate with a single wiring BIL for the write bit line and the read bit line.

[0102] In the memory cells 411B and 411C as well, it is preferable to use an OS transistor for the transistor M11. When an OS transistor is used for the transistor M11, a storage device using a 2Tr1C type memory cell such as the memory cells 411B and 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory). In the memory cells 411B and 411C as well, it is preferable to use an OS transistor for the transistor M11. When an OS transistor is used for the transistor M11, a storage device using a 2Tr1C type memory cell such as the memory cells 411B and 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory). In the memory cells 411B and 411C as well, it is preferable to use an OS transistor for the transistor M11. When an OS transistor is used for the transistor M11, a storage device using a 2Tr1C type memory cell such as the memory cells 411B and 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory). In the memory cells 411B and 411C as well, it is preferable to use an OS transistor for the transistor M11. When an OS transistor is used for the transistor M11, a storage device using a 2Tr1C type memory cell such as the memory cells 411B and 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory). In the memory cells 411B and 411C as well, it is preferable to use an OS transistor for the transistor M11. When an OS transistor is used for the transistor M11, a storage device using a 2Tr1C type memory cell such as the memory cells 411B and 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

[0103] Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTPS: Low Temperature Poly-Silicon) (hereinafter referred to as an Si transistor). Since the Si transistor may have a higher field effect mobility than the OS transistor, it is preferable to apply the Si transistor as the read transistor. Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTPS: Low Temperature Poly-Silicon) (hereinafter referred to as an Si transistor). Since the Si transistor may have a higher field effect mobility than the OS transistor, it is preferable to apply the Si transistor as the read transistor. Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTPS: Low Temperature Poly-Silicon) (hereinafter referred to as an Si transistor). Since the Si transistor may have a higher field effect mobility than the OS transistor, it is preferable to apply the Si transistor as the read transistor. Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTPS: Low Temperature Poly-Silicon) (hereinafter referred to as an Si transistor). Since the Si transistor may have a higher field effect mobility than the OS transistor, it is preferable to apply the Si transistor as the read transistor. Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTPS: Low Temperature Poly-Silicon) (hereinafter referred to as an Si transistor). Since the Si transistor may have a higher field effect mobility than the OS transistor, it is preferable to apply the Si transistor as the read transistor. Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTPS: Low Temperature Poly-Silicon) (hereinafter referred to as an Si transistor). Since the Si transistor may have a higher field effect mobility than the OS transistor, it is preferable to apply the Si transistor as the read transistor.

[0104] When an OS transistor is used as the transistor M3, the memory cell can be configured with a unipolar circuit can be configured.

[0105] In addition, FIG. 10(D) shows a circuit configuration example of a gain cell type (also referred to as "3Tr1C type") memory cell 411D of three transistors and one capacitor element. The memory cell 411D includes a transistor M11, a transistor M5, and a transistor M6, and a capacitor element CC. has .

[0106] The first terminal of the transistor M11 is connected to the first terminal of the capacitor element CC, the second terminal of the transistor M 11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL is connected, and the back gate of the transistor M11 is electrically connected to the wiring BGL . The second terminal of the capacitor element CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6 is electrically connected, and the gate of the transistor M5 is connected to the first terminal of the capacitor element CC. The second terminal of the transistor M 6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring R L

[0107] The wiring BIL functions as a bit line, the wiring WL functions as a write word line, and the wiring RL functions as a read word line.

[0108] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11 functions. Also, the wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100 . By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 The pressure can be increased or decreased.

[0109] Data writing is performed by applying a high-level potential to the wiring WL to turn on the transistor M11 and connecting the wiring BIL and the first terminal of the capacitive element CC. Specifically when the transistor M11 is in the conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL and this potential is written to the first terminal of the capacitive element CC and the gate of the transistor M5. Thereafter, a low-level potential is applied to the wiring WL to turn off the transistor M11 thereby holding the potential of the first terminal of the capacitive element CC and the potential of the gate of the transistor M5.

[0110] Data reading is performed by pre-charging a predetermined potential to the wiring BIL and then electrically floating the wiring BIL and applying a high-level potential to the wiring RL. Since the wiring RL becomes a high-level potential, the transistor M6 is turned on and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, although the potential of the wiring BIL is applied to the second terminal of the transistor M5, the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change according to the potential held at the first terminal of the capacitive element CC ( or the gate of the transistor M5). Here, by reading the potential of the wiring BIL the potential held at the first terminal of the capacitive element CC (or the gate of the transistor M5) can be read. That is, the information written in this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of the transistor M5). Or, the presence or absence of the information written in this memory cell can be determined. read. It can be known.

[0111] In addition, the memory cells included in the memory device 300 described above can have their circuit configurations changed as appropriate. It is possible.

[0112] Note that it is also preferable to use an OS transistor for the transistor M11 in the memory cell 411D. The 3Tr1C-type memory cell 411D to which an OS transistor is applied as the transistor M11 is one aspect of the NOSRAM described above. It is preferable. The 3Tr1C-type memory cell 411D to which an OS transistor is applied as the transistor M11 is one aspect of the NOSRAM described above.

[0113] Note that it is preferable that the channel formation regions of the transistors M5 and M6 described in this embodiment have silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon. Since the field-effect mobility of an Si transistor may be higher than that of an OS transistor, it can be said that it is suitable to apply an Si transistor as the read transistor. Since the field-effect mobility of an Si transistor may be higher than that of an OS transistor, it is suitable to apply an Si transistor as the read transistor. Since the field-effect mobility of an Si transistor may be higher than that of an OS transistor, it can be said that it is suitable to apply an Si transistor as the read transistor. is suitable.

[0114] In addition, when OS transistors are used as the transistors M5 and M6, the memory cell can be configured with a unipolar circuit. It can be configured with a unipolar circuit.

[0115] [oxSRAM] FIG. 10(E) shows a circuit configuration example of a memory cell 411E of an SRAM (Static Random Access Memory) type using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxSRAM. Note that the memory cell 411E shown in FIG. 10(E) is a backup-capable SRAM-type memory cell. In this specification and the like, an SRAM using an OS transistor is referred to as an oxSRAM. Note that the memory cell 411E shown in FIG. 10(E ) is a backup-capable SRAM-type memory cell.

[0116] The memory cell 411E includes transistors M7 to M10 and a transistor MS It includes transistor MS4, capacitor element CD1, and capacitor element CD2. Also, transistors M7 and M8 correspond to transistor M11. Note that transistors M7 to M10 are transistors with a back gate. Also, transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0117] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WL, and the back gate of transistor M7 is connected to wiring BGL1.

[0118] The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WL, and the back gate of transistor M8 is connected

[0119] to wiring BGL2. The second terminal of transistor MS1 is electrically connected to wiring VDL. The second terminal of transistor MS2 is electrically connected The terminal is electrically connected to the wiring GNDL. The second terminal of the transistor MS4 is connected to the wiring GNDL.

[0120] The second terminal of the transistor M9 is connected to the first terminal of the capacitor element CD1. The gate of the transistor M9 is connected to the wiring BRL. The back gate of the transistor M9 is connected to the wiring BGL3. The second terminal of the transistor M10 is connected to the first terminal of the capacitor element CD2. The gate of the transistor M10 is connected to the wiring BRL. The back gate of the transistor M10 is connected to the wiring BGL4.

[0121] The second terminal of the capacitor element CD1 is connected to the wiring GNDL. The second terminal of the capacitor element CD2 is connected to the wiring GNDL.

[0122] The wirings BIL and BILB function as bit lines. The wiring WL functions as a word line. The wiring BRL is a wiring for controlling the conductive state and non-conductive state of the transistors M9 and M10.

[0123] The wirings BGL1 to BGL4 function as wirings for applying a potential to the back gates of the transistors M7 to M10, respectively.

[0124] The wirings BGL1 to BGL4 are electrically connected to the output terminal VOUT of the semiconductor device 100. Note that a plurality of semiconductor devices 100 may be provided in the storage device 300, and the wirings BGL1 to BGL4 may be electrically connected to different semiconductor devices 100, respectively. By applying an arbitrary potential to the wirings BGL1 to BGL4, the transistors M7 to M ​​​​​​​​​​​The threshold voltage of the transistor M10 can be increased or decreased.

[0125] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential. to it.

[0126] Writing of data is performed by applying a high-level potential to the wiring WL and applying a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in the conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.

[0127] By the way, since the memory cell 411E forms an inverter loop by the transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is in the conductive state, an inverted signal of the potential applied to the wiring BIL, that is, the signal input to the wiring BIL, is output to the wiring BILB. Also, since the transistors M9 and M10 are in the conductive state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are respectively held at the first terminal of the capacitor element CD2 and the first terminal of the capacitor element CD1. Then, by applying a low-level potential to the wiring WL and applying a low-level potential to the wiring BRL to make the transistors M7 to M10 non-conductive, the first terminal of the capacitor element CD1 and the first terminal of the capacitor element CD2 are held.

[0128] Reading of data is performed by precharging the wiring BIL and the wiring BILB to a predetermined potential in advance. ​​​​​​​​​After precharging, a high-level potential is applied to the wiring WL, and a high-level potential is applied to the wiring BRL. As a result, the potential of the first terminal of the capacitor element CD1 is refreshed by the inverter loop of the memory cell 411E and output to the wiring BILB. Also, the potential of the first terminal of the capacitor element CD2 is refreshed by the inverter loop of the memory cell 411E and output to the wiring BIL. In the wirings BIL and BILB, since the potential varies from the precharged potential to the potential of the first terminal of the capacitor element CD2 and the potential of the first terminal of the capacitor element CD1, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0129] Note that it is preferable to use OS transistors as the transistors M7 to M10. By using OS transistors for the transistors M7 to M10, the data written in the memory cell 411E can be held for a long time, so that the refresh frequency of the memory cell 411E can be reduced. Also, the refresh operation of the memory cell 411E can be made unnecessary. Also, since the leakage current is very low, multi-valued data or analog data can be held in the memory cell 411E.

[0130] Note that the channel formation regions of the transistors MS1 to MS4 preferably contain silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon. Since the field-effect mobility of Si transistors may be higher than that of OS transistors, it is preferable to apply Si transistors as the transistors included in the inverter. ​​​​​​​​​​​​​​​

[0131] Also, by using an OS transistor for the memory cell, the power supply to the memory cell can be stopped and the information written in the memory cell can be retained for a long period of time. Therefore, during a period when read / write of information is not necessary, the power supply to part or all of the peripheral circuit 311 can be stopped.

[0132] One semiconductor device 100 may be electrically connected to all the memory cells. Also, a plurality of semiconductor devices 100 may be provided in the storage device 300, and one semiconductor device 100 may be electrically connected to a plurality of memory cells for each column or for a plurality of columns. Also, one semiconductor device 100 may be electrically connected to a plurality of memory cells for each row or for a plurality of rows. Also, a plurality of memory cells included in the cell array may be divided into a plurality of blocks, and one semiconductor device 100 may be provided for each block or for a plurality of blocks.

[0133]

[0134] The memory cell described in this embodiment can be used for storage elements such as registers and caches included in a CPU, GPU, etc.

[0135] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc.

[0136] (Embodiment 3) In this embodiment, an example of the cross-sectional configuration of the storage device will be described with reference to the drawings.

[0136] <Example of the Structure of the Storage Device> FIG. 11 shows a partial cross-section of the storage device 300. The storage device 300 shown in FIG. 11 has a layer 310 and a layer 320 laminated on a substrate 231. In FIG. 11, the substrate 231 is a single crystal ​​The case of using a semiconductor substrate (for example, a single crystal silicon substrate) is shown.

[0137] [Layer 310] In FIG. 11, layer 310 has transistors 233a, 23 3b, and transistor 233c. In FIG. 11, the cross-section in the channel length direction of transistors 233a, tra nsistor 233b, and transistor 233c is shown.

[0138] The channels of transistors 233a, 233b, and 233c are formed in a part of the substrate 231. When high-speed operation is required for the integrated circuit, it is preferable to use a single crystal semiconductor substrate as the substrate 23 1.

[0139] Transistors 233a, 233b, and 233c are electrically separated from other transistors by the element isolation layer 232 respectively. For the formation of the element isolation layer , the LOCOS (Local Oxidation of Silicon) method, the S TI (Shallow Trench Isolation) method, etc. can be used .

[0140] Also, an insulating layer 234 is provided on the substrate 231, and insulating layers 235 and 237 are provided on transistors 233a, 2 33b, and transistor 233c, and an electrode 238 is embedded in the insulating layer 237. The electrode 238 is electrically connected to one of the source or drain of the transistor 233a via the contact plug 236 .

[0141] Also, on the electrode 238 and the insulating layer 237, insulating layers 239, 240, and insulating ​​Layer 241 is provided, and electrode 242 is embedded in insulating layer 239, insulating layer 240, and insulating layer 241. Electrode 242 is electrically connected to electrode 238.

[0142] Also, on electrode 242 and insulating layer 241, insulating layer 243 and insulating layer 244 are provided, and electrode 245 is embedded in insulating layer 243 and insulating layer 244. Electrode 245 is electrically connected to electrode 242.

[0143] Also, on electrode 245 and insulating layer 244, insulating layer 246 and insulating layer 247 are provided, and electrode 249 is embedded in insulating layer 246 and insulating layer 247. Electrode 249 is electrically connected to electrode 245.

[0144] Also, on electrode 249 and insulating layer 247, insulating layer 248 and insulating layer 250 are provided, and electrode 251 is embedded in insulating layer 248 and insulating layer 250. Electrode 251 is electrically connected to electrode 249.

[0145] 〔Layer 320〕 Layer 320 is provided on layer 310. Layer 320 has transistor 368a, transistor 368b, capacitor element 369a, and capacitor element 369b. In FIG. 11, a cross-section in the channel length direction of transistor 368a and transistor 368b is shown. Note that transistor 368a and transistor 368b are transistors having a back gate. Transistor 368a and transistor 368b correspond to transistor M11 shown in the above embodiment. Thus, transistor 368a and transistor 368b

[0146] ​​​​​​​​​​​​It is preferable to use an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer. That is , it is preferable to use an OS transistor for transistor 368a and transistor 368b .

[0147] Transistor 368a and transistor 368b are provided on insulating layer 361 and insulating layer 36 2. Further, insulating layer 363 and insulating layer 364 are provided on insulating layer 362 . The back gates of transistor 368a and transistor 368b are embedded in insulating layer 363 and insulating layer 364. Further, electrode 367 is embedded in insulating layer 361 to insulating layer 364. Electrode 367 is electrically connected to electrode 251 . On insulating layer 364, insulating layer 365, insulating layer 366, insulating layer 371, insulating layer 372 , insulating layer 373, insulating layer 375, and insulating layer 376 are provided

[0148] Insulating layer 375 and insulating layer 376 are provided on transistor 368a and transistor 368b . Further, electrode 374 is embedded in insulating layer 365, insulating layer 366, insulating layer 371 , insulating layer 372, insulating layer 373, insulating layer 375, insulating layer 376. Electrode 374 functions as a contact plug

[0149] Electrode 377 is provided on insulating layer 376, and electrode 377 is electrically connected to electrode 367 via electrode 374 .

[0150] . Further, insulating layer 378 and insulating layer 379 are provided on electrode 377. Capacitor elements 369a and capacitor element 369b are formed in openings formed in insulating layer 378 and insulating layer 379 The electrode 391 disposed therein, the insulating layer 392 on the electrode 391 and the insulating layer 379, and the insulation It has an electrode 393 on the layer 392. At least a part of the electrode 391, at least a part of the insulating layer 392, and the electrode 3 are disposed in the opening formed in the insulating layer 378 and the insulating layer 379. At least a part of 93 is disposed.

[0151] The electrode 391 functions as the lower electrode of the capacitor element, the electrode 393 functions as the upper electrode of the capacitor element functions, and the insulating layer 392 functions as the dielectric of the capacitor element. The capacitor element is formed in the insulating layer 378 and the opening of the insulating layer 379, not only on the bottom surface, but also on the side surface, the upper electrode and the lower electrode are configured to face each other with the dielectric interposed therebetween, and the capacitance per unit area can be increased. Therefore, the deeper the opening, the greater the capacitance of the capacitor element. By increasing the capacitance per unit area of the capacitor element in this way, miniaturization or high integration of the semiconductor device can be promoted.

[0152] The shape of the opening formed in the insulating layer 378 and the insulating layer 379 as viewed from above may be a quadrangle or a polygon other than a quadrangle, or a shape in which the corners are curved in the polygon or a circular shape including an ellipse.

[0153] Further, an insulating layer 381 and an insulating layer 382 are provided on the insulating layer 392 and the electrode 393. Further, an electrode 383 is embedded in the insulating layer 378, the insulating layer 379, the insulating layer 392, the insulating layer 381, and the insulating layer 382 The electrode 383 is electrically connected to the electrode 377. The electrode 383 can function as a contact plug. Further, an electrode 384 is provided on the insulating layer 382 is provided. The electrode 384 is electrically connected to the electrode 383. Also, on the electrode 384 an insulating layer 385 is provided.

[0154] <Modified Example> FIG. 12 shows a partial cross section of the memory device 300A. The memory device 300A is a modification of the memory device 300. The memory device 300A has a layer 310A and a layer 320. In the memory device 300 A, an insulating substrate (for example, a glass substrate) is used as the substrate 231.

[0155] The layer 310A has a transistor 268a, a transistor 268b, a capacitor element 369a, and also a capacitor element 369b. Thin film transistors (for example, OS transistors) are used for the transistors included in the layer 310A. By making all the transistors included in the layer 310A be OS transistors, the layer 310A can be made into a unipolar integrated circuit. By making all the transistors included in the memory device 300A be OS transistors, the memory device 30 0A can be made into a unipolar memory device. <Regarding Constituent Materials>

[0156] [Substrate] There is no great limitation on the material used as the substrate, but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon, silicon carbide, etc. as the material, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc. can be used. Also, an SOI substrate, or one with semiconductor elements such as strained transistors or FIN type transistors provided on a semiconductor substrate can also be used. Or, a high electron mobility transistor (HEMT: High Electro ​​​​​​​Gallium arsenide, aluminum arsenide, gallium indium arsenide, gallium nitride, indium phosphide, silicon germanium, etc. applicable to n-Mobility Transistor Gallium aluminum nitride, indium gallium arsenide, gallium nitride, indium phosphide, silicon Germanium, etc. may be used. That is, the substrate is not limited to a mere support substrate, and may be a substrate on which other devices such as transistors are formed.

[0157] Also, as the substrate, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can also be used. Note that a flexible substrate (flexible substrate) may be used as the substrate. When using a flexible substrate, transistors, capacitor elements, etc. may be directly fabricated on the flexible substrate, or transistors, capacitor elements, etc. may be fabricated on another fabrication substrate and then peeled off and transferred to the flexible substrate. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, it is advisable to provide a release layer between the fabrication substrate and the transistors, capacitor elements, etc.

[0158] As the flexible substrate, for example, metals, alloys, resins or glasses, or their fibers can be used. The flexible substrate used for the substrate is preferably one with a lower coefficient of linear expansion to suppress deformation due to the environment. The flexible substrate used for the substrate has, for example, a coefficient of linear expansion of 1×10 / K or less, 5×10 / K or less, or 1×10 -3 / K or less. -5

[0159] -5 Any material with such a coefficient of linear expansion can be used. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. In particular, aramid is suitable as a flexible substrate because it has a low coefficient of linear expansion.

[0159]

[0159] 〔Insulating layer〕 The insulating layer is made of a material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc., and is used either as a single layer or as a laminate. Also, among oxide materials, nitride materials, oxynitride materials, and nitride oxide materials, a material in which a plurality of materials are mixed may be used. In this specification, etc., aluminum nitride oxide refers to a compound in which the nitrogen content is higher than the oxygen content. Also, oxynitride refers to a compound in which the oxygen content is higher than the nitrogen content. The content of each element can be measured, for example, using the Rutherford backscattering spectrometry (RBS) or the like.

[0160] .

[0161] When an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the hydrogen concentration in the insulating layer in order to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulating layer is 2×10 atoms / cm 20 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, and even more preferably 5×10 18atoms / cm 3 shall be as follows In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0162] Also, in order to prevent an increase in the nitrogen concentration in the semiconductor layer, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer is 5×10 19 atom s / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 1× 10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less, and shall be as follows. shall be as follows

[0163] Also, at least the region of the insulating layer in contact with the semiconductor layer preferably has few defects. Typically, it is preferable that there are few signals observed by the electron spin resonance method (ESR: Electron Spin Resonance ). For example, as the above-mentioned signal, an E' center where the g value is observed at 2.001 can be mentioned. The E' center is caused by the dangling bond of silicon . For example, when using a silicon oxide layer or a silicon oxynitride layer as the insulating layer, a silicon oxide layer or a silicon oxynitride layer in which the spin density due to the E' center is 3×10 17 spins / cm 3 or less, preferably 5×10 16 spins / cm 3 or less can be used. or a silicon oxynitride layer

[0164] Also, when a signal caused by nitrogen dioxide (NO 2 ) other than the above-mentioned signal is observed There is such a signal. The signal is split into three signals by the nuclear spin of N, and each has a g-value of 2.037 or more and 2.039 or less (referred to as the first signal), a g-value of 2.001 or more and 2.003 or less (referred to as the second signal), and a g-value of 1.964 or more and 1.966 or less (referred to as the third signal) is observed.

[0165] For example, as the insulating layer, an insulating layer in which the spin density of the signal caused by nitrogen dioxide (NO 2 ) is 1× 10 17 spins / cm 3 or more and 1×10 18 spins / cm 3 less is preferably used. It is suitable.

[0166] Note that nitrogen oxides (NO 2 ) containing nitrogen dioxide (NO x ) form energy levels in the insulating layer. The energy levels are located within the energy gap of the oxide semiconductor layer. Therefore, when nitrogen oxides (NO ) diffuse to the interface between the insulating layer and the oxide semiconductor layer, the energy levels may trap electrons on the insulating layer side. As a result, the trapped electrons stay near the interface between the insulating layer and the oxide x semiconductor layer, shifting the threshold voltage of the transistor in the positive direction. Therefore, using an insulating layer and a film with a low content of nitrogen oxides as the insulating layer can reduce the shift of the threshold voltage of the transistor. Therefore, using an insulating layer and a film with a low content of nitrogen oxides as the insulating layer can reduce the shift of the threshold voltage of the transistor.

[0167] As an insulating layer with a low emission amount of nitrogen oxides (NO x ), for example, a silicon oxynitride layer can be used. The silicon oxynitride layer is analyzed by temperature-programmed desorption gas analysis (TDS: The ) In real time desorption spectroscopy, nitrogen oxides ( NO x ) is a membrane that releases more ammonia than water. The amount is 1×10 18 molecule / cm 3 5×10 or more 19 molecule / cm 3 The following is the case. The amount of ammonia released is higher when the heat treatment temperature in TDS is between 50°C and 650°C, and is the total amount in the range of 50°C to 550°C.

[0168] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating layer with a high monia emission rate, nitrogen oxides (NO x ) is reduced.

[0169] At least one of the insulating layers in contact with the oxide semiconductor layer is a layer that releases oxygen by heating. Specifically, the insulating layer is preferably formed so that the surface temperature of the insulating layer is 100° C. The TDS is performed at a temperature of 100°C to 500°C or lower. The amount of oxygen released, calculated as oxygen atoms, is 1.0 × 10 18 atoms / cm 3 That's it, part 1. 0×10 19 atoms / cm 3 or more, or 1.0×10 20 atoms / cm 3 End It is preferable to use an insulating layer in which the The oxygen that is released is called "excess oxygen."

[0170] The insulating layer containing excess oxygen can also be formed by performing a process of adding oxygen to the insulating layer. It can be carried out by heat treatment or plasma treatment in an oxidizing atmosphere. Or oxygen may be added using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. As the gas used for the treatment of adding oxygen, oxygen gas such as O or 16 O 2 or 18 ozone gas, nitrous oxide gas, or the like, that is, a gas containing oxygen can be mentioned. In this specification, the treatment of adding oxygen is also referred to as "oxygen doping treatment". The oxygen doping treatment may be carried out by heating the substrate. 2

[0171] In addition, as the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that an insulating layer may be formed by laminating a plurality of insulating layers formed of these materials.

[0172] The siloxane resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0173] The method for forming the insulating layer is not particularly limited. Note that depending on the material used for the insulating layer, a firing process may be required. In this case, by combining the firing process of the insulating layer with other heat treatment processes, it becomes possible to efficiently fabricate a transistor. ​​​​​​​​​​​​

[0174] 〔electrode〕 Conductive materials for forming electrodes include aluminum, chromium, copper, silver, gold, platinum, Tantalum, Nickel, Titanium, Molybdenum, Tungsten, Hafnium, Vanadium, Ni Selected from obium, manganese, magnesium, zirconium, beryllium, indium, etc. Materials containing one or more metal elements such as phosphorus can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon, nickel silicide, etc. Alternatively, a silicide such as the above may be used.

[0175] In addition, a conductive material containing the above metal element and oxygen may be used. Conductive materials containing silicon and nitrogen may also be used, such as titanium nitride and tantalum nitride. A conductive material containing nitrogen may be used. um Tin Oxide), Indium Oxide with Tungsten Oxide, Tungsten Oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, indium gallium zinc oxide, silicon Indium tin oxide doped with nitrogen may also be used. Zinc oxide may also be used.

[0176] In addition, a plurality of conductive layers made of the above materials may be laminated. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining the above-mentioned material containing a metal element and a conductive material containing nitrogen is also available. The above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen It may also be a laminated structure combining a conductive material containing with... Further, it may be a laminated structure combining a conductive material

[0177] containing nitrogen and a conductive material containing oxygen. When using an oxide semiconductor for the semiconductor layer and using a laminated structure combining the material containing the metal element described above as the gate electrode and a conductive material containing oxygen, it is preferable to provide

[0178] the conductive material containing oxygen on the semiconductor layer side. By providing the conductive material containing oxygen on the semiconductor layer side, oxygen released from the conductive material is easily supplied to the semiconductor layer. As the electrode, for example, a highly embeddable

[0179] conductive material such as tungsten or polysilicon may be used. Further, a highly embeddable conductive material may be combined with a barrier layer

[0180] such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer (diffusion prevention layer) and used. The electrode may be referred to as a "contact plug" in some cases. In particular, it is preferable to use a conductive material through which impurities hardly permeate for the electrode

[0181] in contact with the gate insulating layer. Examples of the conductive material through which impurities hardly permeate include tantalum nitride. By using can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, and organic semiconductors etc. can be used.

[0182] Further, when an organic semiconductor is used as the semiconductor layer, a low-molecular organic material having an aromatic ring or a π-electron conjugated conductive polymer etc. can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene polyparaphenylene vinylene etc. can be used.

[0183] Note that the semiconductor layers may be stacked. When stacking the semiconductor layers, semiconductor materials having different crystal states may be used, or different semiconductor materials may be used.

[0184] Also, since the bandgap of the oxide semiconductor which is a kind of metal oxide is 2 eV or more, when an oxide semiconductor is used for the semiconductor layer, a transistor with an extremely small off-current can be realized . Specifically, when the voltage between the source and the drain is 3.5 V and at room temperature (typically 25 °C ), the off-current per 1 μm channel width can be less than 1×10 A, less than 1×10 -20 A, or less than 1×10 - 22 A. That is, the on-off ratio -24 can also be 20 digits or more. Also, a transistor (OS transistor) using an oxide semiconductor for the semiconductor layer has a high breakdown voltage between the source and the drain. Therefore, it has good reliability . A transistor can be provided. Further, a transistor with a large output voltage and high breakdown voltage can be provided. Also, a memory device with good reliability can be provided. Further, a memory device with a large output voltage and high breakdown voltage can be provided. In addition, in this specification and the like, a transistor using silicon having crystallinity in a semiconductor layer in which a channel is formed is also referred to as a "crystalline Si transistor". A crystalline Si transistor can relatively easily obtain a higher mobility than an OS transistor. On the other hand, it is difficult for a crystalline Si transistor to achieve an extremely small off-current like an OS transistor. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose and application. For example, an OS transistor and a crystalline Si transistor may be combined and used according to the purpose and application.

[0185] When an oxide semiconductor layer is used as the semiconductor layer, it is preferable to form the oxide semiconductor layer by a sputtering method. When the oxide semiconductor layer is formed by the sputtering method, the density of the oxide semiconductor layer can be increased, which is preferable. When forming the oxide semiconductor layer by the sputtering method, as the sputtering gas, a noble gas (typically argon), oxygen, or a mixed gas of a noble gas and oxygen may be used. Also, it is necessary to purify the sputtering gas to a high purity. For example, as the oxygen gas and noble gas used as the sputtering gas, gases purified to a dew point of -60°C or lower, preferably -100°C or lower, are used. By forming a film using the highly purified sputtering gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor layer as much as possible. A transistor using silicon having crystallinity in a semiconductor layer in which a channel is formed is also referred to as a "crystalline Si transistor".

[0186] A crystalline Si transistor can relatively easily obtain a higher mobility than an OS transistor. On the other hand, it is difficult for a crystalline Si transistor to achieve an extremely small off-current like an OS transistor. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose and application. For example, an OS transistor and a crystalline Si transistor may be combined and used according to the purpose and application. On the other hand, a crystalline Si transistor has difficulty achieving an extremely small off-current like an OS transistor. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose and application. For example, an OS transistor and a crystalline Si transistor may be combined and used according to the purpose and application. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose and application. For example, an OS transistor and a crystalline Si transistor may be combined and used according to the purpose and application. For example, an OS transistor and a crystalline Si transistor may be combined and used according to the purpose and application. For example, an OS transistor and a crystalline Si transistor may be combined and used according to the purpose and application.

[0187] When an oxide semiconductor layer is used as the semiconductor layer, it is preferable to form the oxide semiconductor layer by a sputtering method. The oxide semiconductor layer is suitable because the density of the oxide semiconductor layer can be increased when formed by the sputtering method. When forming the oxide semiconductor layer by the sputtering method, the density of the oxide semiconductor layer can be increased, which is preferable. When forming the oxide semiconductor layer by the sputtering method, as the sputtering gas, a noble gas (typically argon), oxygen, or a mixed gas of a noble gas and oxygen may be used. Also, it is necessary to purify the sputtering gas to a high purity. For example, as the oxygen gas and noble gas used as the sputtering gas, gases purified to a dew point of -60°C or lower, preferably -100°C or lower, are used. By forming a film using the highly purified sputtering gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor layer as much as possible. By forming a film using the highly purified sputtering gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor layer as much as possible. By forming a film using the highly purified sputtering gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor layer as much as possible.

[0188] Also, when forming an oxide semiconductor layer by a sputtering method, it is preferable to remove as much moisture as possible in the sputtering apparatus chamber. For example, using an adsorption-type vacuum exhaust pump such as a cryopump, the inside of the film formation chamber is maintained at a high vacuum (5 × 10 Pa to 1 × 10 -7 Pa) and evacuated preferably. In particular, when the sputtering apparatus is on standby, the partial pressure of gas molecules corresponding to H - 4 O in the film formation chamber (gas molecules corresponding to m / z = 18) is set to 1 × 10 2 Pa or less, preferably 5 × 10 Pa or less. -4 Pa or less is preferable. -5

[0189] 〔Metal Oxide〕 The oxide semiconductor, which is a kind of metal oxide, preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Furthermore, it may contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0190] Here, consider the case where the oxide semiconductor has indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. In addition, elements applicable to element M include boron, silicon, titanium, iron, nickel, germanium zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or the like. There are tungsten, magnesium, etc. However, as the element M, it may be possible to combine a plurality of the aforementioned elements. There may be cases where they can be combined.

[0191] In addition, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides (metal oxide). Further, metal oxides containing nitrogen may be referred to as metal oxynitrides. de). al oxynitride).

[0192] [Constitution of Metal Oxide] Hereinafter, the constitution of CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one aspect of the present invention will be described. There are cases where it is described as CAAC (c-axis aligned crystal

[0193] ), and CAC (Cloud-Aligned Composite) in this specification and the like. CAAC represents an example of a crystal structure, and CAC represents an example of the function or the constitution of the material.

[0194] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. function) is imparted to CAC-OS or CAC-metal oxide. function) can be imparted to CAC-OS or CAC-metal oxide. ​​It can be cut. In CAC-OS or CAC-metal oxide, by separating their respective functions, the functions of both can be maximally enhanced. By separating them, the functions of both can be maximally enhanced.

[0195] Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanometer level. Also, the conductive region and the insulating region may be unevenly distributed in the material. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanometer level. Also, the conductive region and the insulating region may be unevenly distributed in the material. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape. In the material, the conductive region and the insulating region may be separated at the nanometer level. Also, the conductive region and the insulating region may be unevenly distributed in the material. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0196] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material at sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material at sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0197] Also, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to the insulating region and a component having a narrow band gap due to the conductive region. In this case of the configuration, carriers mainly flow in the component having the narrow band gap. Also, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Therefore, the above-mentioned CAC-OS or CA Also, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to the insulating region and a component having a narrow band gap due to the conductive region. Also, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to the insulating region and a component having a narrow band gap due to the conductive region. In this case of the configuration, carriers mainly flow in the component having the narrow band gap. Also, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Also, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Therefore, the above-mentioned CAC-OS or CA ​​When C-metal oxide is used in the channel formation region of a transistor, high current driving force, that is, a large on-current, and high field effect mobility can be obtained in the on-state of the transistor. In other words, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0198] (matrix composite), or a metal matrix composite.

[0199] [Structure of Metal Oxide] Oxide semiconductors, which are a type of metal oxide, can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor) and and amorphous oxide semiconductors.

[0200] CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected and distorted in the a-b plane direction. Note that the distortion refers to a location where the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of nanocrystals are connected. In the region where the plurality of nanocrystals are connected, the distortion refers to a location where the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned.

[0201] Nanocrystals are based on hexagons, but are not necessarily regular hexagons and may be non-regular hexagons. Yes. In addition, in the case of strain, there may be a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, it is also difficult to confirm a clear grain boundary (also called a grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS allows strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements. (Also called a grain boundary.) It can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS allows strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements. It can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS allows strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements. It can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS allows strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0202] In addition, CAAC-OS has a tendency to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are laminated. Note that indium and element M can be substituted for each other. When element M in the (M, Zn) layer is substituted with indium, it can also be represented as an (In, M, Zn) layer. When indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer. In addition, CAAC-OS has a tendency to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are laminated. Note that indium and element M can be substituted for each other. When element M in the (M, Zn) layer is substituted with indium, it can also be represented as an (In, M, Zn) layer. When indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer. In addition, CAAC-OS has a tendency to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are laminated. Note that indium and element M can be substituted for each other. When element M in the (M, Zn) layer is substituted with indium, it can also be represented as an (In, M, Zn) layer. When indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer. In addition, CAAC-OS has a tendency to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are laminated. Note that indium and element M can be substituted for each other. When element M in the (M, Zn) layer is substituted with indium, it can also be represented as an (In, M, Zn) layer. When indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer. In addition, CAAC-OS has a tendency to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are laminated. Note that indium and element M can be substituted for each other. When element M in the (M, Zn) layer is substituted with indium, it can also be represented as an (In, M, Zn) layer. When indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer. In addition, CAAC-OS has a tendency to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are laminated. Note that indium and element M can be substituted for each other. When element M in the (M, Zn) layer is substituted with indium, it can also be represented as an (In, M, Zn) layer. When indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer.

[0203] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects. Therefore, it can also be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects. Therefore, it can also be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects. Therefore, it can also be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects. Therefore, it can also be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects. Therefore, it can also be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0204] nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS has no regularity in crystal orientation among different nano crystals. Therefore, no orientation is observed in the entire film. Thus, nc-OS may not be distinguishable from a-like OS or amorphous oxide semiconductors depending on the analysis method.

[0205] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has a loose or low-density region. That is, a-lik e OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0206] Oxide semiconductors (metal oxides) have various structures and each has different characteristics. Oxide semiconductors may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc- OS, and CAAC-OS.

[0207] [Transistor having a metal oxide] Next, the case where the above metal oxide is used for the channel formation region of a transistor will be described.

[0208] Note that by using the above metal oxide for the channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0209] Also, for a transistor, it is preferable to use a metal oxide with a low carrier density. When reducing the carrier density of the metal oxide film, the impurity concentration in the metal oxide film is reduced. ​​​​​​​​Then, the density of defect levels should be lowered. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, a metal oxide has a carrier density of less than 8×10 , preferably less than 1×10 / cm 11 , more preferably less than 1×10 3 / cm 11 , and still more preferably less than 1×10 3 / cm . It is sufficient to be 1×10 10 / cm 3 or more. -9 / cm 3 .

[0210] In addition, a metal oxide film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, so the density of trap levels may also be low.

[0211] In addition, the charge trapped in the trap levels of the metal oxide may take a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor having a metal oxide with a high trap level density in the channel formation region may have unstable electrical characteristics.

[0212] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In addition, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0213] [Impurities] Here, the effects of various impurities in the metal oxide will be described.

[0214] In a metal oxide, when silicon or carbon, which is one of the Group 14 elements, is included, defect levels are formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon near the interface with the metal oxide (the concentration obtained by secondary ion mass spectrometry (SIMS :Secondary Ion Mass Spectrometry)) are set to 2×10 or less, preferably 2×10 or less. 18 atoms / cm 3 atoms / cm 17 atoms / cm 3 Hereinafter.

[0215] In addition, when an alkali metal or an alkaline earth metal is included in the metal oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in the channel formation region is likely to have a normally-on characteristic. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or the alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 or less, preferably 2×10 or less. atoms / cm atoms / cm 18 atoms / cm 3 Hereinafter. Preferably 16 2×10 3 or less.

[0216] In addition, in a metal oxide, when nitrogen is included, electrons as carriers are generated, the carrier density increases, and it is likely to be n-type. As a result, a transistor using a metal oxide containing nitrogen in the channel formation region is likely to have a normally-on characteristic. Therefore, in the metal oxide, it is preferable that the nitrogen in the channel formation region is reduced as much as possible. For example For example, the nitrogen concentration in the metal oxide is less than 5×10 19 atoms / cm 3 in SIMS, preferably less than 5×10 18 atoms / cm 3 hereinafter, more preferably less than 1×10 18 a toms / cm 3 hereinafter, even more preferably less than 5×10 17 atoms / cm 3 hereinafter.

[0217] In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to form water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, carriers such as electrons may be generated. In addition, a part of hydrogen may bond with oxygen bonded to the metal atom to generate carriers such as electrons. Therefore, a transistor using a metal oxide containing hydrogen in the channel formation region tends to have normal-on characteristics. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 atoms / cm preferably less than 1×10 atoms / cm hereinafter, more preferably less than 5×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 hereinafter, even more preferably less than 5×10 18 atom s / cm 3 hereinafter, even more preferably less than 1×10 18 atoms / cm 3 hereinafter.

[0218] By using a metal oxide with a sufficiently reduced impurity concentration in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0219] <Regarding the film formation method> An insulating material for forming an insulating layer, a conductive material for forming an electrode, or a semiconductor material for forming a semiconductor layer The insulating material, conductive material, or semiconductor material can be formed using a sputtering method, spin coating method, CVD (Chemical Vapor Deposition) method (including thermal CVD method, MOCVD (Metal Organic Chemical Vapor Deposition) method, PE CVD (Plasma Enhanced CVD) method, high density plasma CVD method, LPCVD (low pressure CVD) method, APCVD (atmospheric pressure CVD) method, etc.), ALD (Atomic Layer Deposition) method, or MBE (Molecular Beam Epitaxy) method, or PLD (Pulsed Laser Deposition) method, dipping method, spray coating method, droplet ejection method (such as inkjet method), printing method (such as screen printing, offset printing), etc. The plasma CVD method can obtain a high-quality film at a relatively low temperature. When using a film-forming method without using plasma during film formation, such as the MOCVD method, ALD method, or thermal CVD method, it is less likely to cause damage to the surface to be formed. For example, the wiring, electrodes, and elements (such as transistors and capacitors) included in a memory device may be charged up by receiving charges from the plasma In this case, the wiring, electrodes, and elements included in the memory device may be damaged by the accumulated charges On the other hand, in the case of a film-forming method without using plasma, such plasma damage can be avoided.

[0220] The plasma CVD method can obtain a high-quality film at a relatively low temperature. When using a film-forming method without using plasma during film formation, such as the MOCVD method, ALD method, or thermal CVD method, it is less likely to cause damage to the surface to be formed. For example, the wiring, electrodes, and elements (such as transistors and capacitors) included in a memory device may be charged up by receiving charges from the plasma In this case, the wiring, electrodes, and elements included in the memory device may be damaged by the accumulated charges On the other hand, in the case of a film-forming method without using plasma, such plasma damage can be avoided. For example, the wiring, electrodes, and elements included in a memory device may be charged up by receiving charges from the plasma In this case, the wiring, electrodes, and elements included in the memory device may be damaged by the accumulated charges ​Since no sputtering occurs, the yield of the memory device can be increased. Also, since no plasma damage occurs during film formation, a film with few defects can be obtained. Since no plasma damage occurs during film formation, a film with few defects can be obtained.

[0221] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of an object to be processed. Therefore, it is a film formation method that is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method with a high film formation speed. the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method with a high film formation speed. it may be preferable to use it in combination with other film formation methods such as the CVD method with a high film formation speed.

[0222] The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, compared to the case of forming a film using a plurality of film formation chambers, the time required for film formation can be shortened by the time required for transfer and pressure adjustment. Therefore, it may be possible to increase the productivity of the memory device. When forming a film while changing the flow rate ratio of the source gases, compared to the case of forming a film using a plurality of film formation chambers, the time required for film formation can be shortened by the time required for transfer and pressure adjustment. Therefore, it may be possible to increase the productivity of the memory device. it may be possible to increase the productivity of the memory device.

[0223] When forming a film by the ALD method, it is preferable to use a gas that does not contain chlorine as the material gas. When forming a film by the ALD method, it is preferable to use a gas that does not contain chlorine as the material gas.

[0224] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like. It is possible.

[0225] (Embodiment 4) In this embodiment, a structural example of a transistor that can be used in the semiconductor device and the like shown in the above embodiment will be described.

[0226] <Structural Example 1 of Transistor> A structural example of the transistor 500A will be described with reference to FIGS. 13(A), (B), and (C). FIG. 13(A) is a top view of the transistor 500A. FIG. 13(B) is a cross-sectional view of the portion indicated by the dashed line L1 - L2 in FIG. 13(A). FIG. 13(C) is a cross-sectional view of the portion indicated by the dashed line W1 - W2 in FIG. 13(A). In the top view of FIG. 13(A), some elements are omitted for clarity of the drawing.

[0227] In FIGS. 13(A), (B), and (C), the transistor 500A, and the insulating layers 511, 512, 514, 516, 580, 582, and 584 that function as interlayer films are shown. Also, the conductive layers 546 (conductive layer 546a and conductive layer 546b) that are electrically connected to the transistor 500A and function as contact plugs, and the conductive layer 503 that functions as a wiring are shown.

[0228] The transistor 500A includes a conductive layer 560 (conductive layer 560a and conductive layer 560b) that functions as a first gate electrode, a conductive layer 505 (conductive layer 505a and conductive layer 505b) that functions as a second gate electrode, and an insulating layer 550 that functions as a first gate insulating layer. ​​​​​​​​​​and an insulating layer 521, an insulating layer 522, and an insulating layer 52 that function as a second gate insulating layer 4, an oxide 530 (oxide 530a, oxide 530 b, and oxide 530c) having a region where a channel is formed, a conductive layer 54 that functions as one of a source or a drain 0a, a conductive layer 540b that functions as the other of the source or the drain, and an insulating layer 574 are provided.

[0229] In the transistor 500A shown in FIG. 13, the oxide 530c, the insulating layer 550, and the conductive layer 560 are disposed via the insulating layer 574 within an opening provided in the insulating layer 580 and are disposed between the conductive layer 540a and the conductive layer 540b.

[0230] The insulating layer 511 and the insulating layer 512 function as an interlayer film.

[0231] As the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT ), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST) 3 or the like can be used alone or in a stacked manner. Alternatively, these insulators can be added with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide , titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide. Alternatively, these insulators can be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can be stacked on the above insulators and used.

[0232] ​​​For example, the insulating layer 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from mixing into the transistor 500 from the substrate side into A. Therefore, the insulating layer 511 preferably has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). It is preferable to use an insulating material. Or, it preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). It is preferable to use an insulating material. Also, for example, aluminum oxide, silicon nitride, etc. may be used as the insulating layer 5 11. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 500A side through the insulating layer 511.

[0233] For example, the insulating layer 512 preferably has a lower dielectric constant than the insulating layer 511. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0234] The conductive layer 503 is formed so as to be embedded in the insulating layer 512. Here, the height of the upper surface of the conductive layer 503 and the height of the upper surface of the insulating layer 512 can be made approximately the same. Although the configuration of the conductive layer 503 being a single layer is shown, the present invention is not limited to this. For example, the conductive layer 503 may have a multilayer film structure of two or more layers. In addition, it is preferable to use a highly conductive material mainly composed of tungsten , copper, or aluminum for the conductive layer 503.

[0235] In the transistor 500A, the conductive layer 560 is a first gate (also referred to as a top gate .) may function as an electrode. In the transistor 500A, the conductive layer 560 is self-alignedly formed so as to fill an opening formed in the insulating layer 580 or the like. By forming the conductive layer 56 0 in this way, it is possible to surely arrange the conductive layer 560 in the region between the conductive layer 540a and the conductive layer 540b without alignment.

[0236] Also, the conductive layer 505 may function as a second gate (also referred to as a bottom gate) electrode. In that case, by changing the potential applied to the conductive layer 505 independently without linking it to the potential applied to the conductive layer 560, the threshold voltage of the transistor 500A can be controlled. In particular, by applying a negative potential to the conductive layer 505, the threshold voltage of the transistor 500A can be made greater than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductive layer 505 can make the drain current smaller when the potential applied to the conductive layer 560 is 0 V than when no potential is applied.

[0237] Also, for example, by providing the conductive layer 505 and the conductive layer 560 in a superimposed manner, when a potential is applied to the conductive layer 560 and the conductive layer 505, the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 5 05 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0238] That is, the electric field of the conductive layer 560 having the function as the first gate electrode and the electric field of the conductive layer 505 having the function as the second gate electrode can electrically surround the channel formation region. In this specification, the electric fields of the first gate electrode and the second gate electrode ​​​​​​The structure of the transistor that electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure. nded channel(S-channel) structure.

[0239] The insulating layer 514 and the insulating layer 516 function as an interlayer film in the same manner as the insulating layer 511 or the insulating layer 512. For example, the insulating layer 514 preferably functions as a barrier film that suppresses the incorporation of impurities such as water or hydrogen from the substrate side into the transistor 500A. The insulating layer 514 preferably functions as a barrier film that suppresses the incorporation of impurities such as water or hydrogen from the substrate side into the transistor 500A. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 500A side through the insulating layer 514. Further, for example, the insulating layer 516 preferably has a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 500A side through the insulating layer 514. Further, for example, the insulating layer 516 preferably has a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. 00A. Also, for example, the insulating layer 516 preferably has a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The conductive layer 505 that functions as the second gate has a conductive layer 505a formed in contact with the inner walls of the openings of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b formed further inside. Here, the height of the upper surfaces of the conductive layer 505a and the conductive layer 505b can be made approximately the same as the height of the upper surface of the insulating layer 516. In the transistor 500A, a configuration in which the conductive layer 505a and the conductive layer 505b are laminated is shown, but the present invention is not limited to this.

[0240] The conductive layer 505 that functions as the second gate has a conductive layer 505a formed in contact with the inner walls of the openings of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b formed further inside. Here, the height of the upper surfaces of the conductive layer 505a and the conductive layer 505b can be made approximately the same as the height of the upper surface of the insulating layer 516. In the transistor 500A, a configuration in which the conductive layer 505a and the conductive layer 505b are laminated is shown, but the present invention is not limited to this. The conductive layer 505 that functions as the second gate has a conductive layer 505a formed in contact with the inner walls of the openings of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b formed further inside. Here, the height of the upper surfaces of the conductive layer 505a and the conductive layer 505b can be made approximately the same as the height of the upper surface of the insulating layer 516. In the transistor 500A, a configuration in which the conductive layer 505a and the conductive layer 505b are laminated is shown, but the present invention is not limited to this. Here, the height of the upper surfaces of the conductive layer 505a and the conductive layer 505b can be made approximately the same as the height of the upper surface of the insulating layer 516. In the transistor 500A, a configuration in which the conductive layer 505a and the conductive layer 505b are laminated is shown, but the present invention is not limited to this. Here, the height of the upper surfaces of the conductive layer 505a and the conductive layer 505b can be made approximately the same as the height of the upper surface of the insulating layer 516. In the transistor 500A, a configuration in which the conductive layer 505a and the conductive layer 505b are laminated is shown, but the present invention is not limited to this. 505b is shown, but the present invention is not limited to this. For example, the conductive layer 505 may be provided in a single-layer or a laminated structure of three or more layers. For example, the conductive layer 505 may be provided in a single-layer or a laminated structure of three or more layers.

[0241] Here, it is preferable to use a conductive material for the conductive layer 505a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Here, it is preferable to use a conductive material for the conductive layer 505a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). In the present specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen. For example, since the conductive layer 505a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductive layer 505b and the decrease in conductivity. In the present specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0242] For example, since the conductive layer 505a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductive layer 505b and the decrease in conductivity.

[0243] When the conductive layer 505 also serves as a wiring function, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductive layer 505b. In that case, the conductive layer 503 does not necessarily have to be provided. Although the conductive layer 505b is shown as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium, titanium nitride, and the above conductive material. In that case, the conductive layer 503 does not necessarily have to be provided. Although the conductive layer 505b is shown as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium, titanium nitride, and the above conductive material. The insulating layers 521, 522, and 524 have a function as a second gate insulating layer.

[0244] The insulating layers 521, 522, and 524 have a function as a second gate insulating layer.

[0245] In addition, the insulating layer 522 preferably has a barrier property. By the insulating layer 522 having a barrier property, it functions as a layer that suppresses the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500A into the transistor 500A. In addition, the insulating layer 522 preferably has a barrier property. By the insulating layer 522 having a barrier property, it functions as a layer that suppresses the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500A into the transistor 500A.

[0246] The insulating layer 522 includes, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium ​​​​​​Lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba ,Sr)TiO 3 (BST) and other so-called high-k materials are preferably used as a single layer or laminated. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulator that functions as the gate insulating layer, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0247] For example, the insulating layer 521 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulating layer 521 with a laminated structure having a high relative permittivity and being thermally stable can be obtained.

[0248] Note that in FIG. 13, a three-layer laminated structure is shown as the second gate insulating layer, but it may also be a single layer or a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material and may be a laminated structure made of different materials.

[0249] The oxide 530 having a region that functions as a channel formation region includes the oxide 530a, the oxide 530b on the oxide 530a, and the oxide 530c on the oxide 530b. By having the oxide 530a under the oxide 530b, diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b can be suppressed. Also, by having the oxide 530c on the oxide 530b, the structure formed above the oxide 530c can be formed. Diffusion of impurities from the substrate into the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor which is one of the metal oxides shown in the above embodiment can be used. .

[0250] In a transistor using an oxide semiconductor for the oxide in which a channel is formed, the leakage current (off-current) is extremely small in the non-conducting state. Therefore, a semiconductor device with reduced power consumption can be realized. Further, since the oxide semiconductor can be formed using a sputtering method or the like, it becomes easy to realize a highly integrated semiconductor device.

[0251] For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is one or more selected from gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) can be used. In particular, it is preferable to use gallium, yttrium, or tin as the element M. Also, as the semiconductor layer 530, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used.

[0252] Note that the oxide 530c is preferably provided in the opening provided in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, diffusion of impurities from the insulating layer 580 into the oxide 530 can be suppressed.

[0253] One side of the conductive layer 540 functions as a source electrode and the other side functions as a drain electrode.

[0254] The conductive layer 540a and the conductive layer 540b can be made of aluminum, titanium, chromium, nickel, copper , yttrium, zirconium, molybdenum, silver, tantalum, tungsten, or the like metal, or an alloy mainly composed of this metal. In particular, a metal nitride film such as tantalum nitride has a barrier property against hydrogen or oxygen and high oxidation resistance, so it is preferable.

[0255] In addition, although a single-layer structure is shown in FIG. 13, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated . Also, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0256] In addition, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon , a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, such as a three-layer structure. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0257] In addition, a barrier layer may be provided on the conductive layer 540. It is preferable to use a material having a barrier property against oxygen or hydrogen for the barrier layer. With this configuration, when forming the insulating layer 574, oxidation of the conductive layer 540 can be suppressed. ​

[0258] For the barrier layer, for example, metal oxides can be used. In particular, an insulating film having barrier properties against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide, is preferably used. Alternatively, silicon nitride formed by CVD may be used. By having the barrier layer, the range of material selection for the conductive layer 540 can be widened. For example, for the conductive layer 540, a material with low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used. Also, for example, a conductor that is easy to form or process can be used.

[0259]

[0260] The insulating layer 550 functions as a first gate insulating layer. The insulating layer 550 is preferably provided in an opening provided in the insulating layer 580 via the oxide 530c and the insulating layer 574.

[0261] As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating layer. In that case, the insulating layer 550 may also have a stacked structure, similar to the second gate insulating layer. By forming a stacked structure of an insulator that functions as a gate insulating layer using a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a stacked structure that is thermally stable and has a high relative dielectric constant can be formed.

[0262] The conductive layer 560 that functions as a first gate electrode has a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. The conductive layer 560a is the same as the conductive layer 505a and contains hydrogen atoms. ​​​​​​​​​​​​​, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen molecules, water molecules, and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By having the conductive layer 560a have a function of suppressing the diffusion of oxygen, the material selection selectivity of the conductive layer 560b can be improved. That is, by having the conductive layer 560a, the oxidation of the conductive layer 560b

[0263] can be suppressed, and it is possible to prevent the conductivity from decreasing.

[0264] As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, as the conductive layer 560 a, an oxide semiconductor that can be used as the oxide 530 can be used. In that case, by forming the conductive layer 560b by sputtering, the electrical resistance value of the conductive layer 560a can be reduced to make it a conductor. This can be called an OC (Oxide Conduc tor) electrode.

[0265] The conductive layer 560b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductive layer 560 functions as a wiring, it is preferable to use a conductor with high conductivity

[0266] For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductive layer 560b may have a laminated structure,

[0266] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 500A. The insulating layer 574 An insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, any metal oxide, silicon oxynitride or silicon nitride can be used.

[0267] By having the insulating layer 574, it is possible to suppress the diffusion of water and impurities such as hydrogen in the insulating layer 580 through the oxide 530c and the insulating layer 550 to the oxide 530b. In addition, it is possible to suppress the oxidation of the conductive layer 560 by the excess oxygen in the insulating layer 580.

[0268] The insulating layer 580, the insulating layer 582, and the insulating layer 584 function as an interlayer film.

[0269] Similar to the insulating layer 514, the insulating layer 582 preferably functions as a barrier insulating film that suppresses the entry of impurities such as water or hydrogen from the outside into the transistor 500A.

[0270] In addition, similar to the insulating layer 516, the insulating layer 580 and the insulating layer 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0271] In addition, the transistor 500A may be electrically connected to other structures through plugs and wirings such as the conductive layer 546 embedded in the insulating layer 580, the insulating layer 582, and the insulating layer 584. ​​​​​​​

[0272] In addition, as the material of the conductive layer 546, similar to the conductive layer 505, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used alone or in a stacked manner. For example, it is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity. Alternatively, it is preferable to form it with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced .

[0273] For example, as the conductive layer 546, for example, by using a laminated structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity, it is possible to suppress the diffusion of impurities from the outside while maintaining the conductivity as a wiring.

[0274] By having the above structure, a semiconductor device having a transistor having a large on-current oxide semiconductor can be provided. Alternatively, a semiconductor device having a transistor having a small off-current oxide semiconductor can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability .

[0275] <Example Structure 2 of Transistor> The structural example of the transistor 500B will be described with reference to FIGS. 14(A), (B), and (C). FIG. 14(A) is a top view of the transistor 500B. FIG. 14(B) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 14(A). FIG. 14(C) is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 14(A). In the top view of FIG. 14(A), for clarity of the figure ​​​​​​​​ Some elements are omitted for illustration purposes.

[0276] Transistor 500B is a modified example of transistor 500A. Therefore, to avoid repeating the description, mainly the differences from transistor 500A will be

[0277] Transistor 500B has a region where a conductive layer 540 (conductive layer 540a and conductive layer 540b), an oxide 530c, an insulating layer 550, and a conductive layer 560 overlap. By adopting such a structure, a transistor with a high on-current can be provided. Also, a transistor with high controllability

[0278] The conductive layer 560 that functions as the first gate electrode has a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. Similar to the conductive layer 505a, the conductive layer 560a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and

[0279] copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0280] By the conductive layer 560a having a function of suppressing the diffusion of oxygen, the material selectivity of the conductive layer 560b can be It is advisable to use an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Also , among others, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon oxynitride or silicon nitride, etc. can be used.

[0281] By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. Also, by having the insulating layer 574, diffusion of water and impurities such as hydrogen that the insulating layer 580 has into the transistor 500B can be suppressed.

[0282] Also, an insulating layer 576 (insulating layers 576a and 576b) having a barrier property may be disposed between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, reaction of oxygen in the insulating layer 580 with the conductive layer 546 and oxidation of the conductive layer 546 can be suppressed.

[0283] Also, by providing the insulating layer 576 having a barrier property, the range of material selection for conductors used in plugs and wirings can be widened. For example, by using a metal material that has the property of absorbing oxygen while having high conductivity for the conductive layer 546, a semiconductor device with low power consumption can be provided. Specifically, materials with low oxidation resistance but high conductivity such as tungsten and aluminum can be used. Also, for example, conductors that are easy to film or process can be used.

[0284] <Example Structure of Transistor 3> ​​​​​​​​The structural example of the transistor 500C will be described with reference to FIGS. 15(A), 15(B), and 15(C). FIG. 15(A) is a top view of the transistor 500C. FIG. 15(B) is a cross-sectional view of the transistor 500C in the channel length direction, and is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 15(A). FIG. 15(C) is a cross-sectional view of the transistor 500C in the channel width direction, and is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 15(A). In the top view of FIG. 15(A), some elements are omitted for clarity of the drawing. Also, in the transistor 500C shown in FIG. 15, the same reference numerals are given to the structures having the same functions as the transistor 500A shown in FIG. 13, and for details, reference can be made to the description related to the transistor 500A shown in FIG. 13. The transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 in that a conductive layer 547a is disposed between the conductive layer 540a and the oxide 530b, and a conductive layer 547b is disposed between the conductive layer 540b and the oxide 530b. Here, the conductive layer 540a (conductive layer 540b) is provided in contact with the upper surface of the conductive layer 547a (conductive layer 547b), the side surface on the conductive layer 560 side, and the upper surface of the oxide 530b. Here, the conductive layer 547 may be formed of a conductor that can be used for the conductive layer 540. Further, the film thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 540. FIG. 15(B) is a cross-sectional view of the transistor 500C in the channel length direction, and is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 15(A). FIG. 15(C) is a cross-sectional view of the transistor 500C in the channel width direction, and is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 15(A). Note that in the top view of FIG. 15(A), some elements are omitted for clarity of the drawing. In the transistor 500C shown in FIG. 15, the same reference numerals are given to the structures having the same functions as the transistor 500A shown in FIG. 13, and for details, reference can be made to the description related to the transistor 500A shown in FIG. 13. The transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 in that a conductive layer 547a is disposed between the conductive layer 540a and the oxide 530b, and a conductive layer 547b is disposed between the conductive layer 540b and the oxide 530b. Here, the conductive layer 540a (conductive layer 540b) is provided in contact with the upper surface of the conductive layer 547a (conductive layer 547b), the side surface on the conductive layer 560 side, and the upper surface of the oxide 530b. Here, the conductive layer 547 may be formed of a conductor that can be used for the conductive layer 540.

[0285] The transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 in that a conductive layer 547a is disposed between the conductive layer 540a and the oxide 530b, and a conductive layer 547b is disposed between the conductive layer 540b and the oxide 530b. Here, the conductive layer 540a (conductive layer 540b) is provided in contact with the upper surface of the conductive layer 547a (conductive layer 547b), the side surface on the conductive layer 560 side, and the upper surface of the oxide 530b. Here, the conductive layer 547 may be formed of a conductor that can be used for the conductive layer 540. Further, the film thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 540. Here, the conductive layer 540a (conductive layer 540b) is provided in contact with the upper surface of the conductive layer 547a (conductive layer 547b), the side surface on the conductive layer 560 side, and the upper surface of the oxide 530b. Here, the conductive layer 547 may be formed of a conductor that can be used for the conductive layer 540. Further, the film thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 540. Here, the conductive layer 547 may be formed of a conductor that can be used for the conductive layer 540. Further, the film thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 540. Here, the conductive layer 547 may be formed of a conductor that can be used for the conductive layer 540. Further, the film thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 540.

[0286] Also, the transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 in that the distance between the conductive layer 540a and the conductive layer 540b is shorter than the length of the opening formed in the insulating layer 580, the insulating layer 574, and the insulating layer 545 in the channel length direction. The transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 in that the distance between the conductive layer 540a and the conductive layer 540b is shorter than the length of the opening formed in the insulating layer 580, the insulating layer 574, and the insulating layer 545 in the channel length direction. The transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 in that the distance between the conductive layer 540a and the conductive layer 540b is shorter than the length of the opening formed in the insulating layer 580, the insulating layer 574, and the insulating layer 545 in the channel length direction.

[0287] The transistor 500C shown in FIG. 15 has the above-described configuration, and thus, in the region near the conductive layer 540a and the conductive layer 540b of the oxide 5 30, the contribution of the electric field of the conductive layer 560 can also be increased. Thereby, the substantial channel length of the transistor 500C can be shortened, and the on-current and frequency characteristics can be improved.

[0288] Further, the conductive layer 547a (conductive layer 547b) is preferably provided so as to overlap with the conductive layer 546a (conductive layer 546b). With such a configuration, in the etching for forming an opening for embedding the conductive layer 546a (conductive layer 546b), since the conductive layer 54 7a (conductive layer 547b) is provided at the bottom of the opening, over-etching of the oxide 530b can be prevented.

[0289] Further, the transistor 500C shown in FIG. 15 may be configured such that the insulating layer 545 is disposed in contact with the insulating layer 574. As the insulating layer 574, it is preferable that the insulating layer 574 functions as a barrier insulating film that suppresses the mixing of impurities such as water or hydrogen and excessive oxygen into the transistor 500C from the insulating layer 580 side. As the insulating layer 574, an insulator that can be used for the insulating layer 545 can be used. Further, as the insulating layer 574, for example, aluminum nitride niobium, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon oxynitride any of these nitride insulators may be used.

[0290] Further, the transistor 500C shown in FIG. 15 is different from the transistor 500A shown in FIG. 13 ​​​​Alternatively, the conductive layer 505 may be provided with a single-layer structure. In this case, an insulating film that becomes the insulating layer 516 may be formed on the patterned conductive layer 50 5, and the upper portion of the insulating film may be removed using a CMP method or the like until the upper surface of the conductive layer 505 is exposed. Here, it is preferable to improve the flatness of the upper surface of the conductive layer 505. For example, the average surface roughness (Ra) of the upper surface of the conductive layer 505 may be set to 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. By doing so, the flatness of the insulating layer 524 formed on the conductive layer 505 can be improved, and the crystallinity of the oxide 5 30b and the oxide 530c can be improved. nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. By doing so, the flatness of the insulating layer 524 formed on the conductive layer 505 can be improved, and the crystallinity of the oxide 5 30b and the oxide 530c can be improved. 30b and the oxide 530c can be improved.

[0291] The conductive layers 546a, 546b, 548a, and 548b function as plugs or wirings connected to a capacitor element or a transistor. As the materials of the conductive layers 546a, 546b, 548a, and 548b, conductive materials such as metal materials, alloy materials , metal nitride materials, or metal oxide materials can be used singly or in a laminated manner. It is preferable to use high melting point materials such as tungsten and molybdenum that can achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance. or copper. Using a low-resistance conductive material can reduce the wiring resistance. or copper. Using a low-resistance conductive material can reduce the wiring resistance. or copper. Using a low-resistance conductive material can reduce the wiring resistance. or copper. Using a low-resistance conductive material can reduce the wiring resistance. or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0292] <Example Structure 4 of Transistor> The structural example of the transistor 500D will be described with reference to FIGS. 16(A), (B), and (C). FIG. 16(A) is a top view of the transistor 500D. FIG. 16(B) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 16(A). FIG. 16(C) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 16(A). The structural example of the transistor 500D will be described with reference to FIGS. 16(A), (B), and (C). FIG. 16(A) is a top view of the transistor 500D. FIG. 16(B) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 16(A). FIG. 16(C) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 16(A). The structural example of the transistor 500D will be described with reference to FIGS. 16(A), (B), and (C). FIG. 16(A) is a top view of the transistor 500D. FIG. 16(B) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 16(A). FIG. 16(C) is a cross-sectional view of the portion indicated by the dashed line L1-L2 in FIG. 16(A). It is a cross-sectional view of the part indicated by the chain line W1-W2. In the top view of Fig. 16(A), some elements are omitted for clarity of the drawing. For clarity of the drawing, some elements are omitted.

[0293] Transistor 500D is a modified example of the above transistor. Therefore, to avoid repeating the description, mainly the differences from the above transistor will be described. To avoid repeating the description, mainly the differences from the above transistor will be described.

[0294] In Figs. 16(A) to (C), regions 531a and 531b are provided on a part of the surface of the exposed oxide 530b without providing the conductive layer 540 and the conductive layer 547. One of region 531a or region 531b functions as a source region, and the other functions as a drain region. Moreover, an insulating layer 573 is provided between the oxide 530b and the insulating layer 574. As the insulating layer 573, a material that can be used for the insulating layer 574 can be used. Moreover, an insulating layer 573 is provided between the oxide 530b and the insulating layer 574. As the insulating layer 573, a material that can be used for the insulating layer 574 can be used. Moreover, an insulating layer 573 is provided between the oxide 530b and the insulating layer 574. As the insulating layer 573, a material that can be used for the insulating layer 574 can be used. Moreover, an insulating layer 573 is provided between the oxide 530b and the insulating layer 574. As the insulating layer 573, a material that can be used for the insulating layer 574 can be used.

[0295] The region 531 (region 531a and region 531b) shown in Fig. 16 is a region in which the above elements are added to the oxide 530b. The region 531 can be formed, for example, using a dummy gate. The region 531 (region 531a and region 531b) shown in Fig. 16 is a region in which the above elements are added to the oxide 530b. The region 531 can be formed, for example, using a dummy gate. The region 531 can be formed, for example, using a dummy gate.

[0296] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask, and an element for reducing the resistance of the oxide 530b is added. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As the method of adding the element, an ion implantation method of mass-separating an ionized source gas and adding it, an ion doping method of adding an ionized source gas without mass-separating it, a plasma immersion ion implantation method, etc. can be used. Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask, and an element for reducing the resistance of the oxide 530b is added. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As the method of adding the element, an ion implantation method of mass-separating an ionized source gas and adding it, an ion doping method of adding an ionized source gas without mass-separating it, a plasma immersion ion implantation method, etc. can be used. Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask, and an element for reducing the resistance of the oxide 530b is added. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As the method of adding the element, an ion implantation method of mass-separating an ionized source gas and adding it, an ion doping method of adding an ionized source gas without mass-separating it, a plasma immersion ion implantation method, etc. can be used. Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask, and an element for reducing the resistance of the oxide 530b is added. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As the method of adding the element, an ion implantation method of mass-separating an ionized source gas and adding it, an ion doping method of adding an ionized source gas without mass-separating it, a plasma immersion ion implantation method, etc. can be used. Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask, and an element for reducing the resistance of the oxide 530b is added. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As the method of adding the element, an ion implantation method of mass-separating an ionized source gas and adding it, an ion doping method of adding an ionized source gas without mass-separating it, a plasma immersion ion implantation method, etc. can be used. Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask, and an element for reducing the resistance of the oxide 530b is added. That is, the element is added to the region where the oxide 530 does not overlap with the dummy gate, and the region 531 is formed. As the method of adding the element, an ion implantation method of mass-separating an ionized source gas and adding it, an ion doping method of adding an ionized source gas without mass-separating it, a plasma immersion ion implantation method, etc. can be used.

[0297] As elements for reducing the resistance of the oxide 530, typically, boron or phosphorus is cited. Also, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gas elements, etc. may be used. Typical examples of noble gas elements include helium, neon, argon, krypton, and xenon, etc. The concentration of the element may be measured using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), etc.

[0298] In particular, boron and phosphorus are preferable because an apparatus for manufacturing amorphous silicon or low-temperature polysilicon can be used. Existing facilities can be diverted, and equipment investment can be suppressed.

[0299] Subsequently, an insulating film that becomes the insulating layer 573 and an insulating film that becomes the insulating layer 574 may be formed on the oxide 530b and the dummy gate. By laminating and providing the insulating layer 573 and the insulating layer 574, a region where the region 531 overlaps with the oxide 530c and the insulating layer 550 can be provided.

[0300] Specifically, after providing an insulating film that becomes the insulating layer 580 on the insulating film that becomes the insulating layer 574, by performing chemical mechanical polishing (CMP) on the insulating film that becomes the insulating layer 580, a part of the insulating film that becomes the insulating layer 580 is removed to expose the dummy gate. Subsequently, when removing the dummy gate, a part of the insulating layer 573 in contact with the dummy gate may also be removed. Therefore, on the side surface of the opening provided in the insulating layer 580, the insulating layer 574 and the insulating layer 573 are exposed, and on the bottom surface of the opening, it is provided on the oxide 530b ​​​​​​​​​​​ A part of the obtained region 531 is exposed. Next, an oxide film that becomes the oxide 530c, an insulating film that becomes the insulating layer 550, and a conductive film that becomes the conductive layer 560 are sequentially formed. Then, until the insulating layer 580 is exposed, by CMP processing or the like, a part of the oxide film that becomes the oxide 530c, the insulating layer 55 0, and the conductive film that becomes the conductive layer 560 is removed, so that the transistor shown in FIG. 16 can be formed.

[0301] Note that the insulating layer 573 and the insulating layer 574 are not essential components. They may be appropriately designed according to the required transistor characteristics.

[0302] The transistor shown in FIG. 16 can use existing devices. Furthermore, since the conductive layers 54 2 and 547 are not provided, cost reduction can be achieved.

[0303] <Example Structure 5 of Transistor> The structural example of the transistor 500E will be described with reference to FIGS. 17(A), (B), and (C). FIG. 17(A) is a top view of the transistor 500E. FIG. 17(B) is a cross-sectional view of the L1-L2 portion indicated by the dashed line in FIG. 17(A). FIG. 17(C) is a cross-sectional view of the W1-W2 portion indicated by the dashed line in FIG. 17(A). In the top view of FIG. 17(A), some elements are omitted for clarity of the drawing and shown. The transistor 500E is a modified example of the transistor 500A. Therefore, to avoid repeating the description, mainly the differences from the transistor 500A will be described.

[0304] In the transistor 500A, a part of the insulating layer 574 is within the opening provided in the insulating layer 580

[0305] It is provided and is provided so as to cover the side surface of the conductive layer 560. On the other hand, the transistor 50 In 0E, a part of the insulating layer 580 and the insulating layer 574 is removed to form an opening.

[0306] Further, an insulating layer 576 (insulating layer 576a and insulating layer 576b) having a barrier property may be disposed between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, it is possible to suppress the oxygen in the insulating layer 580 from reacting with the conductive layer 546 and oxidizing the conductive layer 546.

[0307] When an oxide semiconductor is used as the oxide 530, it preferably has a stacked structure with oxides having different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530 b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530 a. Also, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530 a. Further, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b. is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a. Also, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0308] The oxides 530a, 530b, and 530c preferably have crystallinity, and in particular, it is preferable to use CAAC-OS. Having crystallinity such as CAAC-OS ​​​​​The oxide has a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, so that the transistor 500E is stable against the high temperature (so-called thermal budget) in the manufacturing process.

[0309] Note that one or both of the oxide 530a and the oxide 530c may be omitted. The oxide 530 may be a single layer of the oxide 530b. When the oxide 530 is a laminate of the oxide 530a, the oxide 530b, and the oxide 530c, it is preferable that the energy of the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b. In this case, for the oxide 530c, it is preferable to use a metal oxide that can be used for the oxide 530a. Specifically, in the metal oxide used for the oxide 530c, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530c, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530c.

[0310] Here, at the junctions of oxide 530a, oxide 530b, and oxide 530c, The energy level of the lower band edge changes gradually. The energy level of the conduction band minimum at the junction of 530b and oxide 530c is continuous. In order to achieve this, the oxide 5 At the interface between oxide 30a and oxide 530b, and at the interface between oxide 530b and oxide 530c, In this case, the defect level density of the mixed layer formed by the above-mentioned method is preferably reduced.

[0311] Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c are oxides. By having a common element other than the element (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 5 30a and oxide 530c, In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used. The oxide 530c may have a laminated structure. For example, I A laminated structure of n-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide or In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide. In other words, a laminated structure of In-Ga-Zn oxide and a layer containing no In can be used. A stacked structure with an oxide that is not a barrier layer may be used as the oxide 530c.

[0312] Specifically, the oxide 530a is In:Ga:Zn=1:3:4 [atomic ratio], The oxide 530b may be a metal oxide having an atomic ratio of 1:1:0.5. In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] metal An oxide may be used. As the oxide 530c, In:Ga:Zn = 1:3:4 atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or a metal oxide with Ga:Zn = 2:5 [atomic ratio] may be used. Also, as a specific example of the case where the oxide 530c has a laminated structure, a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:1 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2 :3 [atomic ratio] and Ga:Zn = 2:5 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and gallium oxide, etc. can be mentioned.

[0313] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a and the oxide 53 0c as described above, the defect level density at the interface between the oxide 530a and the oxide 530b, and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500E can obtain a high on-current and high frequency characteristics. Note that when the oxide 530c has a laminated structure, in addition to the effect of reducing the defect level density at the interface between the above-described oxide 530b and the oxide 530c, it is expected to suppress the diffusion of the constituent elements of the oxide 530c to the insulating layer 550 side. More specifically, since the oxide 530c has a laminated structure and an oxide containing no In is positioned above the laminated structure, In that can diffuse to the insulating layer 550 side can be suppressed. Since the insulating layer 550 functions as a gate insulating layer, if In diffuses, the characteristics of the transistor deteriorate. Therefore, when the oxide 530c has a laminated structure ​​​​​​By doing so, it becomes possible to provide a highly reliable display device.

[0314] As the oxide 530, it is preferable to use a metal oxide that functions as an oxide semiconductor. For example, as the metal oxide that forms the channel region of the oxide 530, those having a band gap of 2 eV or more, preferably 2.5 eV or more are preferably used. In this way, by using a metal oxide with a large band gap, the off-current of the transistor can be reduced. By using such a transistor, a low-power consumption semiconductor device can be provided. .

[0315] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0316] (Embodiment 5) This embodiment shows an example of an electronic component and an electronic device in which a storage device and the like shown in the above embodiment are incorporated.

[0317] <Electronic component> First, an example of an electronic component in which a storage device 300 is incorporated will be described with reference to FIGS. 18(A) and (B).

[0318] FIG. 18(A) shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 18(A) is an IC chip and has leads and a circuit portion. The electronic component 700 is mounted on a printed circuit board 702, for example. A plurality of such IC chips are combined, and each is electrically connected on the printed circuit board 702, thereby completing the mounting substrate 704.

[0319] As the circuit section of the electronic component 700, the storage device 300 shown in the above embodiment is provided. In FIG. 18(A), a QFP (Quad Flat Package) is applied to the package of the electronic component 700, but the package form is not limited to this.

[0320] FIG. 18(B) shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). On the package substrate 732 (printed circuit board) of the electronic component 730, an interposer 731 is provided, and a semiconductor device 735 and a plurality of storage devices 300 are provided on the interposer 731.

[0321] In the electronic component 730, an example of using the storage device 300 as a high bandwidth memory (HBM) is shown. Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

[0322] As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

[0323] The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or a multilayer. Further, the interposer 731 has a function of electrically connecting the integrated circuits provided on the interposer 731 to the electrodes provided on the package substrate 732. From these, the interposer ​​​​​​​​​​​The "Z" may be referred to as a "redistribution substrate" or an "intermediate substrate". Also, the interposer 731 is provided with through electrodes, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrodes. Also, in a silicon interposer, a TSV (T hrough Silicon Via) can also be used as the through electrode.

[0324] It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult in a resin interposer.

[0325] In HBM, many wirings need to be connected to realize a wide memory bandwidth. Therefore, for the interposer on which HBM is mounted, fine and high-density wiring formation is required. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0326] Also, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer is less likely to occur. Also, since the silicon interposer has high flatness on the surface, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0327] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the memory device 300 and the semiconductor device 735 It is preferable to make the heights of the electrodes uniform.

[0328] In order to mount the electronic component 730 on another substrate, electrodes 733 are provided on the bottom of the package substrate 732. 18B shows an example in which the electrode 733 is formed using a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, a BGA (Ba In addition, the electrodes 733 can be formed with conductive pins. The bottom of the package substrate 732 may be provided with conductive pins arranged in a matrix. This allows for PGA (Pin Grid Array) implementation.

[0329] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ay), LGA (Land Grid Array), QFP (Quad Flat P ackage), QFJ(Quad Flat J-leaded package), Or QFN (Quad Flat Non-leaded package) A mounting method can be used.

[0330] <Electronic equipment> Next, an example of an electronic device including the above electronic components will be described with reference to FIG.

[0331] The robot 7100 is equipped with a light sensor, a microphone, a camera, a speaker, a display, It is equipped with various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezo sensor, optical sensor, gyro sensor, etc.), and a moving mechanism, etc. The electronic component 730 has a processor, etc., and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing the data acquired by the sensor.

[0332] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sound. Also, the speaker has a function of emitting audio signals such as voice and warning sound. The robot 7100 can analyze the audio signal input via the microphone and emit the necessary audio signal from the speaker. In the robot 7100, it is possible to communicate with the user using the microphone and the speaker.

[0333] The camera has a function of imaging the surroundings of the robot 7100. Also, the robot 7100 has a function of moving using the moving mechanism. The robot 7100 can image the surrounding images using the camera and detect the presence or absence of obstacles when moving by analyzing the images.

[0334] The flying object 7120 has a propeller, a camera, a battery, etc., and has a function of autonomous flight. The electronic component 730 has a function of controlling these peripheral devices.

[0335] For example, the image data captured by the camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of obstacles when moving. Also, the electronic component 730 can estimate the remaining battery level from the change in the battery's storage capacity. It can be done.

[0336] The cleaning robot 7140 has a display arranged on the upper surface, a plurality of cameras, brushes, operation buttons, various sensors, etc. arranged on the side surface. Although not shown, the cleaning robot 7300 is equipped with tires, a suction port, etc. The cleaning robot 7300 can travel automatically, detect dust, and suck dust from the suction port provided on the lower surface.

[0337] For example, the electronic component 730 can analyze the image captured by the camera and determine the presence or absence of obstacles such as walls, furniture, or steps. Also, when an object that may get entangled in the brush, such as wiring, is detected by image analysis, the rotation

[0338] of the brush can be stopped. The automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 optimizes the driving state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state,

[0339] usage frequency of brakes, etc. For example, the image data captured by the camera is stored in the electronic component 700. The electronic component 700 and / or the electronic component 730 can be incorporated into

[0340] a TV device 7200 (television receiver), a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, etc. For example, the electronic component 730 incorporated in the TV device 7200 can function

[0341] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 has a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the electronic component 730.

[0342] The PCs 7220 and 7230 are examples of a notebook PC and a desktop PC, respectively. The PC 7230 can be connected with a keyboard 7232 and a monitor device 7233 wirelessly or wiredly. The game machine 7240 is an example of a portable game machine. The game machine 7260 is an example of a desktop game machine. A controller 7 262 is connected to the game machine 7260 wirelessly or wiredly. The electronic component 700 and / or the electronic component 730 can also be incorporated into the controller 7262.

[0343] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0344] (Embodiment 6) In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale Various removable storage devices such as cards), USB memories, SSDs (Solid State Drives), etc. It is applied to removable storage devices. Some configuration examples of the removable storage device are schematically shown in Fig. 20. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0345] Fig. 20(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 , a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 11 05 etc. on the substrate 1104.

[0346] Fig. 20(B) is a schematic diagram of the appearance of an SD card, and Fig. 20(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114, a controller chip 1115 are attached to the substrate 111 3. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113 . Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 111 4 etc. on the substrate 1113.

[0347] FIG. 20(D) is a schematic diagram of the appearance of the SSD, and FIG. 20(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153 . The substrate 1153 is housed in the housing 1151. For example, on the substrate 1153, memory chips 1154, memory chips 1155, and a controller chip 1156 are attached . The memory chip 1155 is a working memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 115 4 on the back side of the substrate 1153 as well, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiments can be incorporated into the memory chips 1154, etc. of the substrate 1153.

[0348] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. .

[0349] In this specification, unless otherwise specified, the on-current refers to the drain current when the transistor is in the on state. The on state (which may be abbreviated as on) refers to, unless otherwise specified, in an n-channel type transistor, the voltage (V ) between the gate and the source is greater than or equal to the threshold value voltage (V G ), and in a p-channel type transistor, the state where V is less than or equal to V th . For example, the on-current of an n-channel type transistor refers to the drain current when V G is greater than or equal to V th . Also, the on-current of a transistor may depend on the voltage between the drain and the source (V G ). th . The on-current of a transistor refers to the drain current when V (V D ) is greater than or equal to a certain value. Also, the on-current of a transistor may depend on the voltage between the drain and the source

[0350] In this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state. The off state (which may also be abbreviated as off) refers to the state where, unless otherwise specified, for an n-channel transistor, V is lower than V G and for a p-channel transistor, V th is higher than V . For example, the off-current of an n-channel transistor G refers to the drain current when V th is lower than V . The off-current of a transistor may depend on V G . Therefore, when it is stated that the off-current of a transistor is less than 10 th A, it may mean that there exists a value of V for which the off-current of the transistor is less than 10 G A. -21 A When it is stated that the off-current of a transistor is less than 10 -21 A, it may mean that there exists a value of V G for which the off-current of the transistor is less than 10 A.

[0351] Also, the off-current of a transistor may depend on V D . In this specification, unless otherwise specified, the off-current represents the off-current at V with an absolute value of 0.1V, 0.8V, 1V, 1.2V, 1 D .8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, it may represent the off-current at V used in a semiconductor device or the like in which the transistor is included. Or it may represent the off-current at V used in a semiconductor device or the like in which the transistor is included. D

[0352] In this specification or the like, when it is explicitly stated that X and Y are connected, it is assumed that X and Y are electrically connected and that X and Y are directly connected, as disclosed in this specification or the like.

[0353] Here, let X and Y be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0354] As an example of the case where X and Y are directly connected, X and Y are connected without an element (for example, a switch, transistor, capacitor element, inductor, resistor element, diode , display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y when they are connected. That is.

[0355] As an example of the case where X and Y are electrically connected, one or more elements (for example, a switch, transistor, capacitor element, inductor, resistor element, diode , display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y can be connected between X and Y . Note that the switch has a function of controlling whether to conduct current (on state) or not (off state ). Or, the switch has a function of selecting and switching the path through which current flows. Note that when X and Y are electrically connected , it shall include the case where X and Y are directly connected.

Example

[0356] In this example, the operating frequency of the DOSRAM shown in Embodiment 2 was estimated. The DOSRAM was assumed to have a configuration including a transistor with a channel length (L) of 60 nm and a channel width (W) of 60 nm and a capacitor element with a holding capacitance of 3.5 fF.

[0357] The "allowable voltage variation", which is one of the specifications required for the DOSRAM, refers to the capacitance of the DOSRAM The voltage applied to the element is the allowable value of the amount of change after data writing. Also, DOSRA The "data retention time" of the M of DOSRAM means the time required until the amount of change in the voltage applied to the capacitive element of DOSRAM reaches the change allowable voltage. In this embodiment, the "change allowable voltage" is set to 0. 2V, and the "data retention time" is defined as the time required for the voltage applied to the capacitive element (holding capacitance 3.5 fF) to decrease by 0.2V from the state after data writing. For example, in this embodiment, when the data retention of D OSRAM is 1 hour, it means that the time required for the voltage applied to the capacitive element of DOSRAM to decrease by 0.2V from the state after data writing is 1 hour. .

[0358] The data retention time of DOSRAM depends on the magnitude of the cutoff current of the transistor of DOSRAM. As described above, the cutoff current (Icut) of the transistor means the I when the V G of the transistor is 0V. D For example, when the data retention characteristics of DOSRAM depend only on the magnitude of Icut of the transistor of DOSRAM, the data retention time of DOS RAM is inversely proportional to the magnitude of Icut of the transistor of DOSRAM.

[0359] When the Icut of the transistor of DOSRAM is known, the data retention time of DOSRAM can be calculated by dividing the amount of charge lost from the capacitive element during data retention (0.7 fC, which corresponds to the product of the holding capacitance (3.5 fF) of the capacitive element and the voltage drop (0.2V) across the capacitive element) by I cut. Also, by setting the target retention time of DOSRAM and dividing the above-mentioned charge amount of 0.7 fC by the retention time, DOSRAM can be obtained. ​ Estimate the value of Icut required for the transistor (hereinafter referred to as Icut0). It is also possible. When the target holding time is 1 hour, the Icut required for the transistor is about 200 zA (200×10 -21 A). By adjusting the back gate voltage so that Icut0 shown in FIG. 5 becomes 200 zA, an N-channel MOSRAM having a high operating frequency in a wide temperature range can be obtained. In this embodiment, the relationship between the back gate voltage and the operating frequency of the DOSRAM was evaluated. In estimating the operating frequency of the DOSRAM, the transistor 500A shown in FIG. 13 was tested, and the parameters necessary for the estimate were extracted from its electrical characteristics. In this embodiment, the transistor 500A was assumed as the transistor M11 shown in FIG. 10(A), and the operating frequency of the DOSRAM was estimated. In estimating the operating frequency of the DOSRAM, the transistor 500A shown in FIG. 13 was tested, and the parameters necessary for the estimate were extracted from its electrical characteristics. In this embodiment, the transistor 500A was assumed as the transistor M11 shown in FIG. 10(A), and the operating frequency of the DOSRAM was estimated.

[0360] In estimating the operating frequency of the DOSRAM, the transistor 500A shown in FIG. 13 was tested, and the parameters necessary for the estimate were extracted from its electrical characteristics. In this embodiment, the transistor 500A was assumed as the transistor M11 shown in FIG. 10(A), and the operating frequency of the DOSRAM was estimated. In estimating the operating frequency of the DOSRAM, the transistor 500A shown in FIG. 13 was tested, and the parameters necessary for the estimate were extracted from its electrical characteristics. In this embodiment, the transistor 500A was assumed as the transistor M11 shown in FIG. 10(A), and the operating frequency of the DOSRAM was estimated. As the transistor M11 shown in FIG. 10(A), the above transistor 500A was assumed, and the operating frequency of the DOSRAM was estimated. As the transistor M11 shown in FIG. 10(A), the above transistor 500A was assumed, and the operating frequency of the DOSRAM was estimated.

[0361] The size of the fabricated transistor 500A was such that L (channel length) was 0.38 μm and W (channel width) was 0.23 μm. Three types of samples, sample A, sample B, and sample C, were prepared. The size of the fabricated transistor 500A was such that L (channel length) was 0.38 μm and W (channel width) was 0.23 μm. Three types of samples, sample A, sample B, and sample C, were prepared. 。

[0362] In the fabricated transistor 500A, the oxide 530a is an In-Ga-Zn oxide with a film thickness of 5 nm. The film formation of the oxide 530a was performed by DC sputtering using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4. The sputtering was performed at a substrate temperature of 200°C with a mixed gas of argon and oxygen. In the fabricated transistor 500A, the oxide 530a is an In-Ga-Zn oxide with a film thickness of 5 nm. The film formation of the oxide 530a was performed by DC sputtering using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4. The sputtering was performed at a substrate temperature of 200°C with a mixed gas of argon and oxygen. In the fabricated transistor 500A, the oxide 530a is an In-Ga-Zn oxide with a film thickness of 5 nm. The film formation of the oxide 530a was performed by DC sputtering using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4. The sputtering was performed at a substrate temperature of 200°C with a mixed gas of argon and oxygen. In the fabricated transistor 500A, the oxide 530a is an In-Ga-Zn oxide with a film thickness of 5 nm. The film formation of the oxide 530a was performed by DC sputtering using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4. The sputtering was performed at a substrate temperature of 200°C with a mixed gas of argon and oxygen.

[0363] In the fabricated transistor 500A, the oxide 530b is an In-G film with a film thickness of 20 nm. It is composed of a-Zn oxide. The film formation of the oxide 530b was carried out by DC sputtering using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 4:2 :4.1. The sputtering method was carried out with the substrate temperature set at 200 °C using a mixed gas of argon and oxygen.

[0364] In the fabricated transistor 500A, the oxide 530c is composed of In-Ga-Zn oxide with a film thickness of 5 nm. The film formation of the oxide 530c was carried out by DC sputtering using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 4:2: 4.1. The sputtering method was carried out with the substrate temperature set at 130 °C using a mixed gas of argon and oxygen.

[0365] After the fabrication of the transistor 500A, samples A and B were heat-treated at 400 °C for 4 hours in a nitrogen gas atmosphere. Sample C was heat-treated at 400 °C for 8 hours in a nitrogen gas atmosphere.

[0366] Next, in samples A, B, and C, the I-V characteristics of the transistor 500A were measured. D -V G measurement was carried out The I-V measurement was performed by sweeping the drain voltage V of the transistor to +1.08 V, the source voltage V to 0 V, and the gate voltage V from -1.0 V to +3.3 V. D -V G The back gate voltage V was set at four levels of -2 V, -3 V, -4 V, and -5 V. The measurement temperature was carried out at three levels of -40 °C, 27 °C, and 85 °C. Specifically, the 5-inch square substrate on which the transistor to be measured was formed was fixed on a thermochuck set at each of the above temperatures. D to +1.08 V, the source voltage V S to 0 V, and the gate voltage V G from -1.0 V to +3.3 V. The back gate voltage V BG was at four levels of -2 V, -3 V, -4 V, and -5 V. The measurement temperature was at three levels of -40 °C, 27 °C, and 85 °C. Specifically, the 5-inch square substrate on which the transistor to be measured was formed was fixed on a thermochuck set at each of the above temperatures. ​​​​​In the state of the transistor I D -V G measurement was carried out. Also, for each back gate voltage V BG and the measurement temperature, measurements were made for every three elements.

[0367] The obtained I D -V G From the curve, the shift voltage (Vsh) and the subthreshold slope swing value (Svalue) of the transistor were calculated. The shift voltage (Vsh) is the V at the point where the tangent line at the point with the maximum slope on the I -V curve of the transistor intersects the straight line of I D = G = 1 pA, as defined. D = 1 pA and is defined as the V at the intersection of the tangent line at the point with the maximum slope on the I G -V curve of the transistor and the straight line of I

[0368] Transistor 500A uses a metal oxide in the channel formation region as shown in the <Method of manufacturing a semiconductor device> of Embodiment 1. A transistor using a metal oxide in the channel formation region has, for example, an extremely small leakage current in the non-conducting state compared to a transistor using Si in the channel formation region. Therefore, it may be difficult to detect Icut by actual measurement for a transistor using a metal oxide in the channel formation region. Since it was also difficult to actually measure Icut in transistor 500A, Icut was estimated by extrapolation using Equation (1) from the obtained Vsh and Svalue. As shown in Equation (1), it was assumed that I monotonically decreases according to Svalue until the off-current of the transistor reaches V = 0V. state. Therefore, for a transistor using a metal oxide in the channel formation region, it may be difficult to detect Icut by actual measurement. Since it was also difficult to actually measure Icut in transistor 500A, Icut was estimated by extrapolation using Equation (1) from the obtained Vsh and Svalue. As shown in Equation (1), it was assumed that I monotonically decreases according to Svalue until the off-current of the transistor reaches V = 0V. D -V G curve. Icut was estimated by extrapolation using Equation (1) from the obtained Vsh and Svalue. Note that, as shown in Equation (1), it was assumed that I monotonically decreases according to Svalue until the off-current of the transistor reaches V G = 0V. state. D was assumed to decrease monotonically according to Svalue until the off-current of the transistor reached V

[0369]

Equation

[0370] Here, a method for estimating the DOSRAM operating frequency will be described. The DOSRAM operating frequency is defined as the reciprocal of the data write cycle of the DOSRAM. The data write cycle of the DOSRAM is a parameter set by, for example, the charging time of the capacitive elements included in the DOSRAM. In this embodiment, it is set that the time corresponding to 40% of the data write cycle of the DOSRAM (the reciprocal of the DOSRAM operating frequency) is the charging time of the capacitive elements included in the DOSRAM. The DOSRAM operating frequency depends on the charging time of the capacitive elements included in the DOSRAM. Therefore, when estimating the DOSRAM operating frequency, it is necessary to know in advance the charging duration of the capacitive elements included in the DOSRAM. In this embodiment, a state where a potential of 0.55 V or more is applied to the capacitive elements included in the DOSRAM (holding capacitance: 3.5 fF) is defined as the state where the capacitive elements are "charged". Therefore, in this embodiment, the time from the start of the data write operation of the DOSRAM until the potential applied to the capacitive elements reaches 0.55 V corresponds to the charging time of the capacitive elements included in the DOSRAM. The charging time of the capacitive elements included in the DOSRAM depends on the magnitude of I of the transistors included in the DOSRAM during DOSRAM data writing. Therefore, in this embodiment, the potential assumed to be applied to the transistors included in the DOSRAM during DOSRAM data writing (see FIG. 21(A)) is applied to the transistor (L / W = 0.3) according to one aspect of the present invention. In this embodiment, the data write cycle of the DOSRAM (the reciprocal of the DOSRAM operating frequency) is set such that the time corresponding to 40% thereof is the charging time of the capacitive elements included in the DOSRAM. The DOSRAM operating frequency depends on the charging time of the capacitive elements included in the DOSRAM. Therefore, when estimating the DOSRAM operating frequency, it is necessary to know in advance the charging duration of the capacitive elements included in the DOSRAM.

[0371] In this embodiment, a state where a potential of 0.55 V or more is applied to the capacitive elements included in the DOSRAM (holding capacitance: 3.5 fF) is defined as the state where the capacitive elements are "charged". Therefore, in this embodiment, the time from the start of the data write operation of the DOSRAM until the potential applied to the capacitive elements reaches 0.55 V corresponds to the charging time of the capacitive elements included in the DOSRAM. The charging time of the capacitive elements included in the DOSRAM depends on the magnitude of I of the transistors included in the DOSRAM during DOSRAM data writing. Therefore, in this embodiment, the potential assumed to be applied to the transistors included in the DOSRAM during DOSRAM data writing (see FIG. 21(A)) is applied to the transistor (L / W = 0.3) according to one aspect of the present invention. In this embodiment, the data write cycle of the DOSRAM (the reciprocal of the DOSRAM operating frequency) is set such that the time corresponding to 40% thereof is the charging time of the capacitive elements included in the DOSRAM. The DOSRAM operating frequency depends on the charging time of the capacitive elements included in the DOSRAM. Therefore, when estimating the DOSRAM operating frequency, it is necessary to know in advance the charging duration of the capacitive elements included in the DOSRAM.

[0372] The charging time of the capacitive elements included in the DOSRAM depends on the magnitude of I of the transistors included in the DOSRAM during DOSRAM data writing. Therefore, in this embodiment, the potential assumed to be applied to the transistors included in the DOSRAM during DOSRAM data writing (see FIG. 21(A)) is applied to the transistor (L / W = 0.3) according to one aspect of the present invention. D In this embodiment, the potential assumed to be applied to the transistors included in the DOSRAM during DOSRAM data writing (see FIG. 21(A)) is applied to the transistor (L / W = 0.3) according to one aspect of the present invention. Therefore, in this embodiment, the potential assumed to be applied to the transistors included in the DOSRAM during DOSRAM data writing (see FIG. 21(A)) is applied to the transistor (L / W = 0.3) according to one aspect of the present invention. Therefore, in this embodiment, the potential assumed to be applied to the transistors included in the DOSRAM during DOSRAM data writing (see FIG. 21(A)) is applied to the transistor (L / W = 0.3) according to one aspect of the present invention. By actually applying it to 4 / 0.22μm), the DOSRAM data writing operation was reproduced, and the I of the transistor at this time D was measured. Figure 21(A) assumes the case of writing data to the capacitive element Cs through the transistor Tr1. Here, D represents the drain, G represents the gate, and S represents the source respectively. Let the potential of the source of the transistor Tr1 (the voltage applied to the capacitive element Cs) be V . By turning on the transistor Tr1, the current I S flows D , and the capacitive element Cs is charged. Specifically, the gate voltage V of the transistor is set to +2.97 G V, the drain voltage V is set to +1.08V, and the source voltage Vs is swept from 0V to +0.55V D to measure the I of the transistor. The back gate voltage V D was measured at four levels of -2V, - BG 3V, -4V, and -5V. The measurement temperature was performed at three levels of -40°C, 27°C, and 85°C .

[0373] In addition, the value of I D obtained from the transistor 500A (L / W = 0.34 / 0.22μm) was corrected according to the size of the transistor (L / W = 60 / 60nm) assumed to be possessed by the DOSRAM .

[0374] When the charging of the DOSRAM starts and V S reaches the write determination voltage V CS , it is determined that the charging is complete . Let the time at this time be the charging time t W (see Figure 21(B)). Let the charge charged to the capacitive element with the holding capacitance Cs [F] of the DOSRAM be Q [C], the charging time be t , and the potential applied to the capacitive element due to charging be Vcs (= V W [sec] ​S ) [V], those of DOSRAM When the drain current of the transistor is I D [A], the following equation holds among the parameters ( 2).

[0375]

Equation

[0376] By transforming Equation (2), the charging time t of the capacitive element of DOSRAM W can be expressed by the following equation ( 3) (see Figure 21(C)).

[0377]

Equation

[0378] In this embodiment, 3.5 fF is substituted for Cs in Equation (3), +0.55 V for Vcs, and the aforementioned I D -V S I obtained by measurement D is substituted, and the charging time t of the capacitive element of DOSRAM W is calculated .

[0379] The relationship between the operating frequency f of DOSRAM and the charging time t w can be expressed by Equation (4).

[0380]

Equation

[0381] In Equation (4), A is a coefficient. In DOSRAM, since it is assumed that the time required for writing accounts for 40% of one operating time, in this embodiment, the operating frequency f is calculated with the coefficient A being 0.4.

[0382] ​In Sample A, the operating frequencies of the DOSRAM at a power supply voltage of 2.5 V are shown in FIGS. 22(A), 22(B), and 23. FIG. 22(A) shows the estimated result at -40°C, FIG. 22(B) shows the estimated result at 27°C, and FIG. 23 shows the estimated result at 85°C. FIGS. 22(A), 22(B), and 23 each show the operating frequencies estimated with the back gate voltage V BG being -2.5 V, -3 V, -4 V, and -5.5 V respectively. In FIGS. 22(A), 22(B), and 23, the horizontal axis represents the D data retention time of the OSRAM, and the vertical axis represents the operating frequency of the DOSRAM. As shown in FIGS. 22( A), 22(B), and 23, it was confirmed that the operating frequency tends to increase as the back gate voltage V increases. Also, at a power supply voltage of 2.5 V, it was confirmed that the operating frequency is BG expected to be 100 MHz or more and the data retention time is expected to be 1 hour or more. By correcting the back gate voltage V using the semiconductor device 100, it was confirmed that the device can operate at a high operating frequency over a wide temperature range. In Sample A, the operating frequencies of the DOSRAM at a power supply voltage of 3.3 V are shown in FIGS. 24(A), BG 24(B), and 25. FIG. 24(A) shows the estimated result at -40°C, FIG. 24(B) shows the estimated result at 27°C, and FIG. 25 shows the estimated result at 85°C. FIGS. 24(A), 24(B), and 25 each show the

[0383] operating frequencies estimated with the back gate voltage V being -2.5 V, -3 V, -4 V, and -5.5 V respectively. In FIGS. 24(A), 24(B), and 25, the horizontal axis represents the D data retention time of the OSRAM, and the vertical axis represents the operating frequency of the DOSRAM. As shown in FIGS. 24( A), 24(B), and 25, the back gate voltage V BG being -2.5 V, -3 V, -4 V, and -5.5 V respectively. In FIGS. 24(A), 24(B), and 25, the horizontal axis represents the D data retention time of the OSRAM, and the vertical axis represents the operating frequency of the DOSRAM. As shown in FIGS. 24( A), 24(B), and 25, the back gate voltage V increases. As shown in FIGS. 24(A), 24(B), and 25, it was confirmed that the operating frequency tends to increase as the back gate voltage V BGThe higher it becomes, the more the operating frequency tends to increase. Also, at a power supply voltage of 3.3 V, it was confirmed that the operating frequency is expected to be 150 MHz or higher and the data retention time is expected to be 1 hour or longer. By using the semiconductor device 100 to correct the back gate voltage V BG , it was confirmed that it can operate at a high operating frequency over a wide temperature range.

[0384] For comparison, the data when the back gate voltage V BG is not adjusted is shown below. In sample A, when the power supply voltage is 3.3 V and the back gate voltage V BG is -5.5 V, the operating frequency of the DOSRAM is shown in Fig. 26. In Fig. 26, the horizontal axis represents the data retention time of the DOSRAM and the vertical axis represents the operating frequency of the DOSRAM. It was confirmed that the operating frequency decreases as the temperature drops.

[0385] In sample B, the operating frequencies of the DOSRAM at a power supply voltage of 2.5 V are shown in Figs. 27(A), 27(B) and Fig. 28. Fig. 27(A) is the result estimated at -40°C, Fig. 27(B) is at 27°C, and Fig. 28 is the result estimated at 85°C. Figs. 27(A), 27(B) and Fig. 28 respectively show the estimated operating frequencies when the back gate voltage V BG is -1.5 V, -2 V, -2.5 V, -3 V, -4 V, -4.8 V respectively. In Figs. 27(A), 27(B) and Fig. 2 8, the horizontal axis represents the data retention time of the DOSRAM and the vertical axis represents the operating frequency of the DOSRAM. Similar to sample A, in sample B as well, at a power supply voltage of 2.5 V, it was confirmed that the operating frequency is expected to be 100 MHz or higher and the data retention time is expected to be 1 hour or longer over a wide temperature range.

[0386] In Sample B, the operating frequencies of the DOSRAM at a power supply voltage of 3.3V are shown in FIGS. 29(A), 29(B), and 30. FIG. 29(A) shows the estimated results at -40°C, FIG. 29(B) shows the estimated results at 27°C, and FIG. 30 shows the estimated results at 85°C. FIGS. 29(A), 29(B), and 30 respectively show the operating frequencies estimated at back gate voltages V BG of -1.5V, -2V, -2.5V, -3V, -4V, -4.8 V respectively. In FIGS. 29(A), 29(B), and 3 0, the horizontal axis represents the data retention time of the DOSRAM, and the vertical axis represents the operating cycle frequency of the DOSRAM. Similar to Sample A, in Sample B as well, at a power supply voltage of 3.3V, within a wide temperature range it is expected that the operating frequency will be 150 MHz or higher and the data retention time will be 1 hour or longer. This was confirmed.

[0387] For comparison, the data when the back gate voltage V BG is not adjusted is shown below. In Sample B, when the power supply voltage is 3.3V and the back gate voltage V BG is -4.8V, the operating frequency of the DOSRAM is shown in FIG. 31. In FIG. 31, the horizontal axis represents the data retention time of the DOSRAM and the vertical axis represents the operating frequency of the DOSRAM. Similar to Sample A, in Sample B as well, it was confirmed that the operating frequency decreases as the temperature decreases.

[0388] In Sample C, the operating frequency of the DOSRAM when the power supply voltage is 2.5V and the temperature is -40°C is shown in FIG. 32. FIG. 32 shows the operating frequencies estimated at back gate voltages V BG of -2V, -3V, -4V, -5V respectively. In FIG. 32, the horizontal axis represents the data retention time of the DOSRAM and the vertical axis represents the operating frequency of the DOSRAM. Similar to Sample A and Sample B, Even for Sample C, at a power supply voltage of 2.5 V and -40 °C, the operating frequency is 100 MHz or higher, and it was confirmed that the data retention time is expected to be 1 hour or more.

[0389] For comparison, the data when the back gate voltage V BG is not adjusted is shown below. For Sample C, when the power supply voltage is 3.3 V and the back gate voltage V BG is -5 V, the operation of the DOSRAM frequency is shown in Fig. 33(A). When the power supply voltage is 2.5 V and the back gate voltage V BG is -5 V the operation frequency of the DOSRAM is shown in Fig. 33(B). In Fig. 33(A) and Fig. 33( B), the horizontal axis represents the temperature and the vertical axis represents the operation frequency of the DOSRAM. It was confirmed that, similar to Samples A and B, in Sample C too, the operation frequency decreases as the temperature drops .

[0390] The configurations, methods, etc. shown in this example can be implemented in appropriate combination with at least some of the other embodiments described in this specification .

Example

[0391] In this example, for the DOSRAM shown in Embodiment 2 (see Fig. 10(A)), with the back gate voltage V BG kept constant, the data retention time and operation frequency at different operating temperatures were estimated.

[0392] In estimating the operation frequency of the DOSRAM, the transistor 500E shown in Fig. 17 was tested and the parameters necessary for the estimate were extracted from its electrical characteristics. In this example, assuming the transistor 500E as the transistor M11 in Fig. 10 (A), for the DOSRAM ​The operating frequency was estimated.

[0393] In this embodiment, the size of the prototype transistor 500E had a channel length (L) of 80 nm and a channel width (W) of 55 nm.

[0394] In the prototype transistor 500E fabricated in this embodiment, the oxide 530a had a film thickness of 5 nm and was made of In-Ga-Zn oxide. The oxide 530a was formed using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4 by DC sputtering. The sputtering was performed at a substrate temperature of 200°C using a mixed gas of argon and oxygen.

[0395] Also, the oxide 530b of the prototype transistor 500E fabricated in this embodiment had a film thickness of 15 nm and was made of In-Ga-Zn oxide. The oxide 530b was formed using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 by DC sputtering. The sputtering was performed at a substrate temperature of 200°C using a mixed gas of argon and oxygen.

[0396] Also, the oxide 530c of the prototype transistor 500E fabricated in this embodiment had a film thickness of 3 nm of I n-Ga-Zn oxide. The oxide 530c was formed using a target of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 by DC sputtering. The sputtering was performed at a substrate temperature of 130°C using a mixed gas of argon and oxygen.

[0397] After fabricating the transistor 500E, heat treatment was performed at 400°C for 8 hours in a nitrogen gas atmosphere. ​​​​​​​

[0398] Next, the I D -V G Measurements were carried out. D -V G The measurement is Drain voltage V of the 500E D to +1.08V, source voltage V S With the gate voltage set to 0V, Pressure V G The back gate voltage V was swept from -1.0 V to +3.3 V. BG The measurements were performed at two levels: -5.7V and -10.5V. The temperatures were 125℃, 85℃, and 27℃. The test was performed at four temperatures: 40° C., 40° C., and −40° C. Specifically, The inch square substrate was fixed on a thermo chuck set to each of the above temperatures, and the transistor 500E I D -V G Measurements were carried out. In addition, measurements were carried out on three elements at each measurement temperature ( n=3).

[0399] Next, in the same manner as in Example 1, the obtained I D -V G From the curve, the Vsh and S Based on the calculated data, we assume a DOSRAM with a memory capacity of 1Mb. The data retention time and DOSRAM operating frequency were estimated.

[0400] Table 1 shows the specifications of the assumed DOSRAM. Figure 34 shows the assumed DOSRAM. A schematic diagram of the above is shown.

[0401] [Table 1]

[0402] 35A to 35D, the voltage applied to the gate of transistor 500E is applied to the gate of transistor 50 The voltage V that turns 0E on GON is 2.25V, and the voltage V that turns transistor 500E off is GOFF -0.72V. The back gate voltage V of transistor 500E BG is - 5.7V. The estimated data retention time and operating frequency are shown.

[0403] Figure 35(A) shows the estimated data retention time and operating frequency when the measurement temperature is 125°C. Figure 35(B) shows the estimated data retention time and operating frequency when the measurement temperature is 85°C. Figure 35(C) shows the estimated data retention time and operating frequency when the measurement temperature is 27°C. Figure 35(D) shows the estimated data retention time and operating frequency when the measurement temperature is -40°C. is.

[0404] From Figures 35(A) to (D), operating frequencies of 100 MHz or more are estimated at all measurement temperatures. Also, retention times of approximately 1 hour or more are obtained at all measurement temperatures. It can be seen that the lower the measurement temperature, the longer the retention time obtained.

[0405] Figures 36(A) to (D) show the estimated data retention time and operating frequency under operating conditions different from those in Figures 35(A) to (D). Specifically, voltage V GON is 1.65V, voltage V G OFF is -1.32V, and voltage V BG is -3.0V. Figure 36(A) shows the estimated data retention time and operating frequency when the measurement temperature is 1 25°C. Figure 36(B) shows the estimated data retention time and operating frequency when the measurement temperature is 85°C. Figure 36(C) shows the estimated data retention time and operating frequency when the measurement temperature is 27°C. Figure 36(D) shows the measurement It is an estimate of the data retention time and operating frequency at a temperature of -40°C. Also, for each measurement temperature , the measurement was performed one element at a time (n = 1).

[0406] From FIGS. 36(A) to (D), an operating frequency of 100 MHz or higher is estimated at all measurement temperatures. Also, similar to FIGS. 35(A) to (D), it can be seen that the lower the measurement temperature, the longer the retention time is obtained. When the measurement temperature is 125°C, the retention time is about 1 year, but when the measurement temperature is 85°C or lower, a data retention time of 10 years or more is obtained.

[0407] From this example, it was found that by adjusting the gate voltage V G and the back gate voltage V BG , the operating frequency and data retention time of the DOS RAM can be adjusted.

Example

[0408] A field effect transistor using IGZO containing a CAAC structure in the semiconductor layer (also referred to as a "CAAC- IGZO FET") was fabricated, and the off-current and cut-off frequency f etc. were investigated under a high-temperature environment of 150°C. T

[0409] <Structure and characteristics of CAAC-IGZO FET> The transistor has a self-aligned transistor structure similar to the transistor 500E shown in FIG. 17 . Also, the thickness of the gate insulating layer on the top gate (front gate) side was set to 6 nm in terms of EOT (Equivalent Oxide Thickness) . Also, the thickness of the gate insulating layer on the back gate side was set to 31 n m in terms of EOT.

[0410] ​​The investigation was conducted using a CAAC-IGZO FET with a channel length (L) of 25 nm and a channel width (W) of 21 nm, and a C AAC-IGZO FET with a channel length (L) of 60 nm and a channel width (W) of 60 nm, etc.

[0411] Fig. 37 shows the I D -V G characteristics of the CAAC-IGZO FET with L / W = 25 nm / 21 nm. The measurement of the I D -V G characteristics was carried out with the drain voltage V D set to 1.2 V, the source voltage V S set to 0 V , the back gate voltage V BG set to -10 V, and the gate voltage V G varied from 0 V to 2.5 V .

[0412] From the measurement results of the I D -V G characteristics, the Svalue was 79 mV / dec, the field effect mobility was 1 0.2 cm 2 / Vs, the on-current was 2.8 μA (V G = 2.5 V), and the threshold voltage Vth was 1.44 V.

[0413] Also, in current measurement, the lower limit value of the measuring instrument is usually about 1×10 -12 ~1×10 -13 A. Therefore, it is impossible to accurately measure the off-current with a single CAAC-IGZO FET having the characteristic of extremely low off-current. For example, in order to measure a current value of 1×10 - 24 A, a method of connecting and measuring a plurality of transistors in parallel can be considered. However, in this case, 10 11 transistors are required to be connected in parallel ​It is not realistic.

[0414] In this embodiment, current measurement was performed using the circuit shown in FIG. 38(A) or (B). Specifically, 20,000 CAAC-IGZO FETs were connected in parallel to form a DUT (Device Under Test), and the time dependence of the node FN potential change was measured to derive the leakage current value. By using the circuit shown in FIG. 38(A), the value of the gate leakage current Ig (the sum of the gate-source current, gate-drain current, and gate-back gate current) can be known. By using the circuit shown in FIG. 38(B), the value of the off-current can be known.

[0415] FIG. 39 shows the measurement results of the gate leakage current Ig measured in temperature environments of 85°C, 125°C, and 150°C respectively. As the DUT, 20,000 CAAC-IGZO FETs with L / W = 60 nm / 60 nm were connected in parallel. The horizontal axis in FIG. 39 shows the value obtained by multiplying the reciprocal of the temperature by 1000 times, and the vertical axis shows the Ig per CAAC-IGZO FET in logarithm. The measurement was performed with the source voltage V set to 2.4 V, the drain voltage V set to 2.4 V, and the gate voltage V G set to 1.2 V. This is the same as when the source voltage V is 0 V, the drain voltage Vd is 0 V S D G and the gate voltage V S is -1.2 V, which means that the CAAC-IGZO FET used as the DUT is in the off state. The back gate voltage V G was set to -10 V. BG

[0416] From FIG. 39, even in the temperature environment of 150°C, per CAAC-IGZO FET​​​​​​​​​​ The Ig is 3.3×10 -20 A, and it was found that the gate leakage current Ig is sufficiently low .

[0417] The CAAC-IGZO FET fabricated in this example has a back gate electrode BGE (Back Gate Electrode). As shown in FIG. 40, by changing the back gate voltage V supplied to the back gate electrode BGE, it was confirmed that the threshold voltage Vth BG changes. The variation amount dVth / dV of the threshold voltage is -0.15V BG / V. Also, as shown in FIG. 41, it was confirmed that the change in the mutual conductance g with respect to the change in the back gate voltage V BG is small. On the other hand, it was confirmed that the maximum value of the mutual conductance g with respect to the change in the back gate voltage V m shifts in the same manner as Vth BG . can be m confirmed .

[0418] By providing the back gate electrode BGE, dynamic Vth control becomes possible. Therefore, there is no need to change the manufacturing process of the transistor according to the circuit application. On the other hand, there are also disadvantages to providing the back gate electrode BGE. Parasitic capacitance is generated between the back gate electrode BGE and the source-drain of the transistor, and there is a possibility that the gate delay time will increase. To verify this possibility, the cutoff frequency f of a transistor with a back gate electrode BGE and a transistor without it was compared. The cutoff frequency f is derived by Equation (5). To verify this possibility, the cutoff frequency f of a transistor with a back gate electrode BGE and a transistor without it was compared. The cutoff frequency f T is derived by Equation (5). T is derived by Equation (5).

[0419]

Equation

[0420] In Equation (5), C tg is the gate capacitance on the top gate (front gate) side, and C bg is the gate capacitance on the back gate side. C g is the sum of C tg and C bg . From Equation (5), in the comparison of the presence or absence of the back gate electrode BGE, when the cutoff frequencies f T are the same , it can be seen that g m normalized by the gate capacitance is the same.

[0421] In a CAAC-IGZO FET with L / W = 25 nm / 21 nm, the cutoff frequency f was measured for the element with the back gate electrode BGE and the element without BGE. The measurement was performed at room temperature (27 °C). Also, for the element with the back gate electrode BGE , the measurement was carried out for each case where the back gate voltage V BG is 0 V, -3 V, and -6 V . The measurement was performed by connecting 672 CAAC-IGZO FETs in parallel (M = 672).

[0422] The measurement results are shown in Fig. 42. For the element with the back gate electrode BGE, the cutoff frequency f is 30 GHz, and for the element without the back gate electrode BGE, the cutoff frequency f T is 27 GHz. Also, when the back gate voltage V BG is -6 V, the cutoff frequency f T is 27.7 GHz, and the same cutoff frequency f as when the back gate voltage V BG is 0 V is obtained. From these results, it can be seen that the cutoff frequency f varies depending on the presence or absence of the back gate electrode BGE TIt was found that the change was small. Thus, it was found that even when the back gate electrode BGE was added, the delay time did not increase. Also, it was found that by adding the back gate electrode BGE, it was possible to suppress the Vth shift caused by temperature changes.

[0423] Also, the cut-off frequency f T was measured using an element different from that in FIG. 42. Specifically, a CAAC-IGZO FET without a back gate electrode BGE with L / W = 39 nm / 28 nm was used to measure the cut-off frequency f. T The measurement was performed at room temperature (27 °C). Also, the measurement was performed by connecting 672 CAAC-IGZO FETs in parallel (M = 672).

[0424] FIG. 43 shows the measurement results. Also in this measurement, a cut-off frequency f of 30 GHz T was obtained.

[0425] <High-temperature characteristics of CAAC-IGZO FET> CAAC-IGZO FET can be fabricated in the BEOL (Back End Of Line) process of semiconductor manufacturing processes such as CMOS. Thus, it is possible to form a stacked layer with a Si transistor (among Si transistors, a field-effect Si transistor is also referred to as a "Si FET"). For example, applications such as fabricating a circuit that requires high-speed operation in a CMOS process and fabricating a circuit that requires a low leakage current in a CAAC-IGZO process are possible. Also, while the off-current of a Si FET increases with an increase in temperature, CAAC-IGZO

[0426] ​​​​​​​​In the FET, the off-current is always at the measurement lower limit. Therefore, the temperature characteristics of the off-current of a Si FET with L / W = 60 nm / 120 nm and a CAAC-IGZO FET with L / W = 60 nm / 60 nm were compared. The measurement of the off-current of both was performed using the circuit shown in Fig. 38(B). The off-current of the Si FET and the off-current of the CAAC-IGZO FET were compared. The measurement of the off-current of both was performed using the circuit shown in Fig. 38(B).

[0427] The off-current of the Si FET was measured at a gate voltage V G = -1.0 V, a source voltage V S = 0 V, a drain voltage V = 1.2 V, and a body voltage V D = 0 V. The off-current of the CAAC-IGZO FET was measured at a gate voltage V B = -2.0 V, a source voltage V = 0 V, a drain voltage V G = -2.0 V, a back gate voltage V S = 0 V, and a drain voltage V V D = 2.0 V, and a back gate voltage V BG = -3.0 V.

[0428] The measurement results are shown in Fig. 44. At a measurement temperature of 150 °C, the off-current of the Si FET was approximately 2.2×10 2×10 -6 A, and the off-current of the CAAC-IGZO FET was approximately 3.9×10 -20 A. The CAAC-IGZO FET can maintain a low off-current even in a high-temperature environment. Also, by adjusting the back gate voltage, it is possible to further lower the off-current.

[0429] Next, Fig. 45 shows the temperature dependence of the Hall mobility and carrier density of the CAAC-IGZO film. From Fig. 45, it can be seen that the Hall mobility of the CAAC-IGZO film hardly changes with temperature changes. Since the Coulomb scattering is assumed to be dominant over the phonon scattering in the Hall mobility of the CAAC-IGZO film, it does not decrease even at high temperatures. From Fig. 45, it can be seen that the Hall mobility of the CAAC-IGZO film hardly changes with temperature changes. Since the Coulomb scattering is assumed to be dominant over the phonon scattering in the Hall mobility of the CAAC-IGZO film, it does not decrease even at high temperatures. The Hall mobility of the CAAC-IGZO film is assumed to be dominated by Coulomb scattering rather than phonon scattering, so it does not decrease even at high temperatures. ​​​​

[0430] Next, the cut-off frequencies f of the CAAC-IGZO FET and the Si FET at 25°C and 150°C were measured. The DUTs for measurement were made using an Si FET with L / W = 60 nm / 480 nm and an T L / W = 25 nm / 21 nm CAAC-IGZO FET. Also, the measurement of the Si FET was performed by connecting 21 Si FETs in parallel (M = 21). The measurement of the CAAC-IGZO FET was performed by connecting 672 CAAC-IGZO FETs in parallel (M = 672). in parallel (M = 672).

[0431] The measurement results are shown in Fig. 46. The change rate of the maximum cut-off frequency f of the Si FET T was 36%, and the change rate of the maximum cut-off frequency f of the CAAC-IGZO FET was 13%. Compared with the Si FET, the CAAC-IGZO FET had a characteristic of less difference between the cut-off T frequency f at 25°C and the cut-off frequency f at 150°C. Also, in the CAAC-IGZO FET measured this time, the maximum cut-off frequency f at a measurement temperature of 150°C and V = 2.5 V T was 33 GHz. frequency f T D = 2.5 V was 33 GHz. T

[0432] From these results, it was found that the CAAC-IGZO FET has less temperature dependence of the cut-off T frequency f than the Si FET. Also, it was found that by providing a back gate electrode to the CAAC-IGZO FET, fluctuations in Vth due to temperature changes can be suppressed. Also, the CAAC-IGZO FET has a smaller change amount of the cut-off frequency f with respect to temperature changes T than the Si F ​​​​​It was found to be lower than that of ET. Also, the CAAC-IGZO FET has an off-current of 10 A, which was found to be extremely small, even at high temperatures. By using the CAAC-IGZO -20 FET, low-power circuits and memories can be realized in an environment with a wide operating temperature range.

[0433] The configurations, methods, etc. shown in the above embodiments can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

Description of Reference Numerals

[0434] 11 Voltage generation circuit, 11a Voltage generation circuit, 11b Voltage generation circuit, 12 Voltage holding circuit, 14 Capacitor element, 15 Buffer, 17 Temperature sensor, 18 Voltage control circuit, 20 Correction circuit 、100 Semiconductor device​​​

Claims

[Claim 1] The voltage regulator includes a plurality of transistors, a correction circuit, a voltage generating circuit, and a voltage holding circuit, an output of the correction circuit is electrically connected to gates of the plurality of transistors; an output of the voltage generating circuit is electrically connected to an input of the voltage holding circuit; an output of the voltage holding circuit is electrically connected to gates of the plurality of transistors; the voltage holding circuit has a function of applying the voltage generated by the voltage generating circuit to gates of the plurality of transistors and holding the voltage; the correction circuit has a function of acquiring temperature information and a function of converting the temperature information into a control voltage; The control voltage is a voltage that controls the voltage generated by the voltage generating circuit.

Images