In-plane switching type liquid crystal display device

Abstract

To suppress degradation of a liquid crystal display device.SOLUTION: A liquid crystal display device includes: pixels; scan signal lines and common signal lines arranged correspondingly to the array in a row direction of the pixels; data signal lines arranged correspondingly to the array in a column direction of the pixels; a scan signal line drive circuit that outputs scan signals to the scan signal lines; a common signal line drive circuit that outputs common signals to the common signal lines; and a data signal line drive circuit that outputs video signals to the data signal lines. Each pixel includes a pixel electrode, a common electrode, and a transistor. The transistor is connected between the data signal line and the pixel electrode, a gate is connected to the scan signal line, the common electrode is connected to common wiring, and the pixel electrode is in the form of a flat plate. The common electrode includes slits. The common signal line drive circuit outputs a common voltage of the same polarity with voltage levels that vary for each frame to the common signal lines. The data signal line drive circuit outputs video signals of the same polarity with voltage levels that vary in synchronization with the common voltage.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] An embodiment of the present invention relates to a pixel structure of a liquid crystal display device. [Background technology]

[0002] A transparent active matrix type LCD with a dielectric constant of 3.3 or less. The video signal lines are covered with a transparent insulating material, and the image is formed on the elongated insulating bumps using a transparent conductor. A liquid crystal display device is disclosed in which a common electrode is formed for shielding image signal wiring (Patent (See Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-341465 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the liquid crystal display device of the prior art, a shield common electrode is provided to shield the electric field of the signal line. However, the structure with the shield electrode makes the layer structure complicated and the pixel opening On the other hand, if we try to simplify the layer structure, the current of the signal line becomes lower. The problem is that the magnetic field acts on the liquid crystal layer, reducing its long-term reliability. One of the objectives of this embodiment is to solve such problems. [Means for solving the problem]

[0005] A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate; a second gate electrode having an area overlapping the first electrode; and a second gate electrode between the first gate electrode and the second gate electrode. An oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode between the first insulating layer and the second insulating layer, and a common electrode on the second insulating layer overlapping the pixel electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is continuously provided from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. 、has. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and is further provided with a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is continuously provided from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A transistor including an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a pixel electrode between the first insulating layer and the second insulating layer, and a common electrode on the second insulating layer overlapping the pixel electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is continuously provided from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. and is further included. The pixel electrode is continuously provided from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. The first gate electrode and the second gate electrode are in a region outside the oxide semiconductor layer and are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer. A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer.

[0006] A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. An oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode between the first insulating layer and the second insulating layer, and a common electrode on the second insulating layer overlapping the pixel electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is continuously provided from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A transistor including an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a pixel electrode between the first insulating layer and the second insulating layer, and a common electrode on the second insulating layer overlapping the pixel electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is continuously provided from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer.

[0007] A liquid crystal display device according to an embodiment of the present invention includes a first gate electrode on a first substrate, a second gate electrode having a region overlapping the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including the second insulating layer, a pixel electrode on the second insulating layer, and a common electrode. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. A second gate electrode having a region overlapping with the gate electrode, and between the first gate electrode and the second gate electrode an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. an oxide semiconductor layer, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a transistor including a first pixel electrode between the first substrate and the first insulating layer, and a second pixel electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the first gate electrode and the second gate electrode. The first pixel electrode and the second pixel electrode are electrically connected to a wiring continuous from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer.

Advantages of the Invention

[0008] According to an embodiment of the present invention, a dual-gate transistor is provided in a pixel, and by embedding a wiring connected to the transistor in an insulating layer, the reliability of the liquid crystal display device can be improved without providing a shield electrode or the like. According to an embodiment of the present invention, a dual-gate transistor is provided in a pixel, and by embedding a wiring connected to the transistor in an insulating layer, the reliability of the liquid crystal display device can be improved without providing a shield electrode or the like. According to an embodiment of the present invention, a dual-gate transistor is provided in a pixel, and by embedding a wiring connected to the transistor in an insulating layer, the reliability of the liquid crystal display device can be improved without providing a shield electrode or the like.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention includes many different aspects and is not to be construed as limited to the embodiments illustrated below. The drawings attached to this specification are for making the explanation clearer, and may be schematically represented with respect to the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not necessarily limit the content of the present invention. Also, in the present invention, when a specific element described in a certain drawing and a specific element described in another drawing are in the same or corresponding relationship, the same reference numeral (or a reference numeral with a, b, etc. appended after the number described as a reference numeral) may be attached, and repeated explanations may be appropriately omitted as needed. Furthermore, the characters "first" and "second" attached to each element are convenient identifiers used to distinguish each element and have no further meaning unless otherwise specified.

[0011] In this specification, when a certain member or region is said to be "above (or below)" another member or region, unless otherwise specifically limited, this includes not only the case where it is directly above (or directly below) another member or region but also the case where it is above (or below) another member or region. That is, it also includes the case where another component is included between a certain member or region and another member or region above (or below) the other member or region

[0012] 1. Configuration of Liquid Crystal Display Device The circuit configuration of a liquid crystal display device according to an embodiment of the present invention will be shown. In the following, F Applicable to the FS (Fringe Field Switching) method and the IPS (In Plane Switching) method Circuit configuration, and applicable to the PSVA (Polymer Stabilized Vertical Alignment) method Exemplify the circuit configuration.

[0013] 1-1. Liquid crystal display device of FFS method and IPS method FIG. 1 shows the configuration of a liquid crystal display device 200a of the FFS method and the IPS method according to an embodiment of the present invention The liquid crystal display device 200a has a structure in which a liquid crystal layer (not shown) is provided between a first substrate 100 and a second substrate 102 arranged opposite to each other, and includes a display unit 104 that displays an image by utilizing the electro-optical effect of the liquid crystal The display unit 104 is provided with at least one Pixel 106, scanning signal line 116, common signal line 117, and data signal line 118 are arranged . At least one pixel 106 is composed of a plurality of pixels. The plurality of pixels 106 are Appropriately arranged in the display unit 1 04. The plurality of pixels 106 are arranged, for example, to correspond to a stripe arrangement, a mosaic arrangement

[0014] The liquid crystal display device 200a may also have a scanning signal line driving circuit 10 8, a common signal line driving circuit 109, and a data signal line driving circuit 110 appropriately arranged in the area outside the display unit 104. The scanning signal line 116 arranged in the display unit 104 is connected to the scanning signal line driving circuit 108, and the common Signal line 117 is connected to the common signal line driving circuit 109, and the data signal line 118 is connected to the data Signal line driving circuit 110. The scanning signal line driving circuit 108 outputs a scanning signal to the scanning signal line 116, and the common signal line driving circuit 109 outputs a common signal to the common signal line 117 Output Output, and the data signal line driving circuit 110 outputs a data signal to the data signal line 118 Then, the data signal line driving circuit 110 outputs a video signal to the data signal line 118.

[0015] The liquid crystal display device 200a includes an input terminal portion 112 provided at an end of the first substrate 100. . The input terminal portion 112 includes at least one terminal electrode 114. At least one terminal electrode 114 is composed of a plurality of terminal electrodes 114. The plurality of terminal electrodes 114 are appropriately arranged in the input terminal portion 112. The input terminal portion 112 is a connection portion with an external circuit and is a portion where a flexible printed wiring board (not shown) is connected.

[0016] FIG. 1 also shows an equivalent circuit of the pixel 106. The pixel 106 includes a transistor 202, a liquid crystal element 204, and a holding capacitor element 206. The transistor 202 has a control terminal called a gate and input / output terminals called a source and a drain. The transistor 202 arranged in the pixel 106 has its gate (control terminal) electrically connected to the scanning signal line 116, one of the source and the drain (the first input / output terminal) electrically connected to the data signal line 118, and the other of the source and the drain (the second input / output terminal) electrically connected to the liquid crystal element 204 and the holding capacitor element 206. Also, the liquid crystal element 204 and the holding capacitor element 206 are electrically connected to the common signal line 1 17. The transistor 202 has its on-state and off-state controlled by a scanning signal input to the gate (control terminal) from the scanning signal line 116. When in the on-state, a video signal is input from the data signal line 118 to the pixel 106. In this state, a voltage based on the data signal is applied to the liquid crystal element 204, and the holding capacitor element 206 is charged with a voltage based on the data signal.

[0017] The transistor 202 is controlled to be in an on-state and an off-state by a scanning signal input to the gate (control terminal) from the scanning signal line 116. When in the on-state, a video signal is input from the data signal line 118 to the pixel 106. In this state, a voltage based on the data signal is applied to the liquid crystal element 204, and the holding capacitor element 206 is charged with a voltage based on the data signal. Based on the data signal, a voltage is applied to the liquid crystal element 204, and the holding capacitor element 206 is charged with a voltage based on the data signal. It is obtained. The liquid crystal element 204 includes a pair of electrodes and a liquid crystal layer. One electrode of the liquid crystal element 204 ( also called a pixel electrode) is electrically connected to the transistor 202, and the other electrode (common electrode) is electrically connected to the common signal line 117. The liquid crystal element 204 controls the alignment of liquid crystal molecules by the voltage based on the video signal and the voltage applied to the common signal line 117. The liquid crystal display device 200a has a function of displaying an image on the display unit 104 by individually controlling the alignment states of liquid crystals in a plurality of pixels 106.

[0018] FIG. 2 shows the circuit configuration of the display unit 104 in the FFS method and the IPS method. FIG. 2 shows that in the n-th row of the display unit 104, pixels 106 ( n R m ), 106 ( n G m ), 106 ( n B m+ 1 ), 106 ( n R m+1 ) are arranged, and in the (n + 1)-th row, pixels 106 ( n+1 R m ) are arranged, 106 ( n+1 G m ), 106 ( n+1 B m+1 ), 106 ( n+1 R m+1 ) are arranged . A transistor 202 is provided for each pixel. The transistor 202 provided for each pixel is connected to the scan signal line 116 and the data signal line 118. A pixel electrode and a common electrode are provided for each pixel.

[0019] FIG. 2 shows an aspect in which each pixel is arranged corresponding to a stripe arrangement. That is, FIG. 2 shows an example in which red (R) pixels, green pixels (G), and blue pixels (B) are arranged according to each column. Yes. In relation to the scanning signal line 116, each pixel, pixel 106( n G m ), 106( n R m+1 ) is connected to the first scanning signal line 116(G An ) arranged corresponding to the n-th row, , pixel 106( n R m ), 106( n B m+1 ) is connected to the second scanning signal line(G Bn ) arranged corresponding to the n-th row, pixel 106( n+1 G m ), 106( n+1 R m+1 ) is connected to the scanning signal line 116(G An+1 ) arranged corresponding to the (n + 1)-th row, pixel 106( n+1 R m ), 106( n+1 B m+1 ) is arranged corresponding to the (n + 1)-th row and connected to the second scanning signal line 116(G Bn+1 ). Also, each pixel, in relation to the data signal line 118, pixels 106( n R m ), 106( n G m ), 106( n+1 R m ), 106( n+1 G m ) are connected to the first data signal line 118 (D m ) arranged corresponding to the m-th column, pixels 106( n B m+1 ), 106( n R m+1 ), 106( n+ 1 B m+ 1), 106( n+1 R m+1 ) are connected to the second data Theタ signal line 118 (D m+1 ) is connected. Also, the pixel arranged in the nth row has a common electrode connected to the first common signal line 117 (COM n ), and the pixel arranged in the (n + 1)th row has its common electrode connected to the second common signal line (COM n+1 ).

[0020] As shown in FIG. 2, by providing two scanning signal lines in each row, the number of data signal lines can be reduced. For example, the pixel 106 ([[]] belonging to the nth row n R m ) and the pixel 106 ([[]] n G m ) are connected to the first data signal line 118 (D m ), and video signals are input from the same data signal line. Similarly, the pixel 106 ([[]] n B m+1 ) and the pixel 106 ([[]] n R m+1 ) belonging to the nth row are connected to the second data signal line 118 (D m+1 ), and video signals are input from the same data signal line .

[0021] FIG. 3 shows a configuration example of the data signal line driving circuit 110. FIG. 3 shows an example in which the data signal line driving circuit 110 is configured by a driver IC 111 mounted on a flexible printed wiring board (FPC board) 101 and a demultiplexer 209 formed on the first substrate 100. The FPC 101 is connected by a terminal electrode 114 provided on the first substrate 100. The output signal line 115 connected to the driver IC 111 is input to the demultiplexer 209 and distributed to a plurality of data signal lines. FIG. 3 shows that one output signal line 115 extending from the driver IC 111 is input to one block of the demultiplexer 209, and three data signal lines are output. Shows the mode of distribution to the T signal lines 118(D1), 118(D2), and 118(D3). Also, the number of outputs of the demultiplexer 209 is arbitrary.

[0022] The demultiplexer 209 can be formed by transistors having the same structure as the transistor 202 provided in the pixel 106. In this way, assuming that the processing of the video signal is performed by the driver IC, this is implemented by COF (Chip On Film), and by providing the demultiplexer 209 on the first substrate 100 on which the display unit 104 is formed and distributing it to the data signal line 118, the circuit scale of the driver IC111 can be reduced. Also, the power consumption of the driver IC111 can be reduced.

[0023] FIG. 4(A) shows the timing chart of the signals input to the first scanning signal line 116(G An ), the second scanning signal line 116(G Bn ), the first data signal line 118(D m ), and the common signal line 117(COM n ). The timing chart shown in FIG. 4(A) shows an example of the frame inversion driving method. In a certain frame, when the common voltage of the common signal line 117 is inverted, the first scanning signal line of the nth row (for example, the first scanning signal line 116(G An )) is selected, and a video signal is written to the pixels in the even columns. The second scanning signal line of the nth row (for example, the second scanning signal line (G Bn )) turns on with a half-pulse delay from the selection signal of the first scanning signal line, the pixels in the odd columns are precharged, and when the selection signal of the first scanning signal line turns off, a video signal is written. In this way, a video signal is written to the pixels in each row of the display unit 104. This occurs. In the next frame, the common voltage of the common signal line 117 is inverted, and accordingly, the voltage level of the video signal is inverted, and the same operation is performed. Thus, the liquid crystal display device 200a of the FFS method or the IPS method can apply the frame inversion driving method.

[0024] 1-2. Liquid Crystal Display Device of PSVA Method FIG. 5 shows the configuration of a liquid crystal display device 200b of the PSVA method according to an embodiment of the present invention. The liquid crystal display device 200b has a structure in which a liquid crystal layer (not shown) is provided between a first substrate 100 and a second substrate 102 that are arranged opposite to each other, and an image is displayed using the electro-optical effect of the liquid crystal. The liquid crystal display device 200a also has a scanning signal line driving circuit 108 and a data signal line driving circuit 110 appropriately arranged in an outer region of the display unit 104. The scanning signal lines 116 arranged in the display unit 104 are connected to the scanning signal line driving circuit 108, and the data signal lines 118 are connected to the data signal line driving circuit 110. The scanning signal line driving circuit 108 outputs a scanning signal to the scanning signal lines 116, and the data signal line driving circuit 110 outputs a video signal to the data signal lines 118. One end of the liquid crystal element 204 and the holding capacitor element 206 is electrically connected to the transistor 202, and a common voltage is applied to the other end.

[0025] FIG. 6 shows the circuit configuration of the display unit 104 in the PSVA method. FIG. 6 shows pixels 106 ( on the n-th row of the display unit 104. n R m ), 106 ( n G m ), 106 ( n B m+1 ), 106 ( n R m+1 ) are arranged, and pixels 106 are arranged on the (n + 1)-th row.n+1 R m )、106( n+ 1 G m )、106( n+1 B m+1 )、106( n+1 R m+1 ) is arranged to show Yes. Each pixel is provided with a transistor 202 connected to the data signal line 118.

[0026] FIG. 6 shows a mode in which each pixel is arranged corresponding to a stripe array. Pixel 106( n G m )、106( n R m+1 ) is connected to the first scanning signal line 116( G An ) arranged corresponding to the nth row, and pixel 106( n R m )、106( n B m+1 ) corresponds to the nth row and is connected to the second scanning signal line (G Bn ) arranged corresponding to it, and pixel 106( n+1 Gm), 10 6( n+1 R m+1 ) is connected to the scanning signal line 116(G An +1 ) arranged corresponding to the (n + 1)th row, and pixel 106( n+1 R m )、106( n+1 B m+1 ) is the (n + 1) row and is connected to the second scanning signal line 116(G Bn+1 ) arranged corresponding to it. Also, each pixel, in relation to the data signal line 118, pixel 106( n R m )、106( n G m )、106( n+1 R m )、106( n+1 Gm ) is arranged corresponding to the m-th column, the first data signal line 118 (D m ) is connected, and the pixel 106 ( n B m+1 ), 106 ( n R m+ 1 ), 106 ( n+1 B m+1 ), 106 ( n+1 R m+1 ) are arranged corresponding to the (m + 1)-th column and connected to the second data signal line 118 (D m+1 ). In this way, the pixel circuit shown in FIG. 6 , similar to the pixel circuits of the FFS method and the IPD method, can reduce the number of data signal lines by providing two scanning signal lines in each row.

[0027] FIG. 4(B) shows a timing chart of signals input to the first scanning signal line 116 (G An ), the second scanning signal line 116 (G Bn ), and the first data signal line 118 (D m ). The timing chart shown in FIG. 4(B) shows an example of the dot inversion driving method, and the common voltage is constant. In a certain frame, the first scanning signal line of the n-th row (for example, the first scanning signal line 116 (G An )) is selected, and a video signal is written to the pixels in the even-numbered columns. Next , the second scanning signal line of the n-th row (for example, the second scanning signal line (G Bn )) is selected, and a video signal with a polarity opposite to that of the even-numbered columns is input when viewed with reference to the common voltage. In this way , the liquid crystal display device 200b of the PSVA method can apply the dot inversion driving method.

[0028] 1-3. Issues in High Definition The transistor 202 is a thin film transistor in which the channel region is formed of a semiconductor thin film. The transistor 202 is manufactured using a photolithography-based micro-patterning technique together with the scanning signal line 116 and the data signal line 118. In order to reduce the manufacturing cost of the liquid crystal display devices 200a and 200b, it is considered necessary to reduce the number of photomasks. However, the scanning signal line 116 and the data signal line 118 must be arranged to intersect. Also, a part of these wirings needs to be provided so as to intersect with a seal pattern for sealing the liquid crystal layer. The scanning signal line 116 and the data signal line 118 are formed of metal wirings, but since the metal wiring cannot be exposed at the portion overlapping with the seal pattern, it is necessary to coat the wiring with an inorganic insulating film. If the sealant and the metal wiring are in direct contact, moisture (H 2O) in the air easily penetrates into the liquid crystal layer through the interface between the sealant and the metal wiring, which causes a decrease in reliability. The liquid crystal display devices 200a and 200b can display a high-definition image by increasing the density of the plurality of pixels 106 arranged in the display unit 104. However, when the number of pixels in the display unit 104 increases, the signal writing time per frame becomes shorter, so that the high-speed operation of the transistor 2 02 is required. Generally, it is known that the field effect mobility of a transistor varies depending on the type of the semiconductor forming the channel. For example, the field effect mobility of a thin film transistor using amorphous silicon (amorphous silicon TFT) is about 0 .5 cm / Vsec, and it can drive a full high vision (2K) liquid crystal display. Since the metal wiring cannot be exposed at the portion overlapping with the seal pattern, it is necessary to coat the wiring with an inorganic insulating film. If the sealant and the metal wiring are in direct contact, moisture (H 2O) in the air easily penetrates into the liquid crystal layer through the interface between the sealant and the metal wiring, which causes a decrease in reliability. 2 O) penetrates into the liquid crystal layer easily and causes a decrease in reliability.

[0029] The liquid crystal display devices 200a and 200b can display a high-definition image by increasing the density of the plurality of pixels 106 arranged in the display unit 104. However, when the number of pixels in the display unit 104 increases, the signal writing time per frame becomes shorter, so that the high-speed operation of the transistor 2 02 is required. Generally, it is known that the field effect mobility of a transistor varies depending on the type of the semiconductor forming the channel. For example, the field effect mobility of a thin film transistor using amorphous silicon (amorphous silicon TFT) is about 0 .5 cm / Vsec, and it can drive a full high vision (2K) liquid crystal display. It is known that the field effect mobility of a transistor generally varies depending on the type of the semiconductor forming the channel. For example, the field effect mobility of a thin film transistor using amorphous silicon (amorphous silicon TFT) is about 0 .5 cm .5 cm 2 / Vsec, and it can drive a full high vision (2K) liquid crystal display. On the other hand, the writing time for an 8K resolution LCD display is The driving time must be shortened to about 1.9 μsec, so the driving The capacity is insufficient, and the driving capacity is increased by split driving (a method of dividing the screen into multiple areas and driving them). However, the division drive method requires a complicated drive circuit configuration and This increases the manufacturing cost and power consumption of the display device.

[0030] As pixels become more dense, the transistors that make up the pixels must be able to operate at high speeds. In addition, liquid crystal display devices are not just about improving the performance of transistors. There is a demand for lower manufacturing costs while improving image quality. An embodiment of a liquid crystal display device that can satisfy such requirements will be described below.

[0031] 2. Transistor and backplane structure Transistors used in the liquid crystal display devices 200a and 200b according to an embodiment of the present invention The details of the transistor 202 will be described. In this embodiment, the transistor 202 is a thin film transistor. There are at least two types of structures, as shown below.

[0032] 2-1. First example of transistor structure 7A and 7B show a first example of a structure of a transistor. 7B is a plan view of the transistor 202. FIG. 7B corresponds to the line X1-X2 shown in FIG. 2 shows a cross-sectional structure of a transistor 202.

[0033] The transistor 202 includes an oxide semiconductor layer 128, a first gate electrode 120, and a second gate It includes a top electrode 132. The transistor 202 has a first gate with respect to the oxide semiconductor layer 128. The first gate electrode 120 is disposed on the side of the first substrate 100, and the second gate electrode 132 has a structure disposed on the side opposite to the first substrate 100. A first insulating layer 122 is provided between the first gate electrode 120 and the oxide semiconductor layer 128, and a second insulating layer 130 is provided between the oxide semiconductor layer 128 and the second gate electrode 132. A first insulating layer 122 is provided between the first gate electrode 120 and the oxide semiconductor layer 128, and a second insulating layer 130 is provided between the oxide semiconductor layer 128 and the second gate electrode 132. The first insulating layer 122 and the second insulating layer 130 function as gate insulating films that insulate the first gate electrode 120 and the second gate electrode 132 from the oxide semiconductor layer 128. The first insulating layer 122 and the second insulating layer 130 function as gate insulating films that insulate the first gate electrode 120 and the second gate electrode 132 from the oxide semiconductor layer 128. It has a function as a gate insulating film.

[0034] The transistor 202 has a structure in which a first oxide conductive layer 124a and a second oxide conductive layer 124b are provided between the first insulating layer 122 and the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b have a structure provided between the first insulating layer 122 and the oxide semiconductor layer 128. One end (tip portion) of each of the first oxide conductive layer 124a and the second oxide conductive layer 124b is arranged to overlap with the first gate electrode 120 and the second gate electrode 132. The first oxide conductive layer 124a and the second oxide conductive layer 124b are arranged to overlap with the first gate electrode 120 and the second gate electrode 132. The first oxide conductive layer 124a and the second oxide conductive layer 124b are provided in contact with the surface (first surface) of the oxide semiconductor layer 128 on the side of the first gate electrode 120. The first oxide conductive layer 124a and the second oxide conductive layer 124b are provided in contact with the surface (first surface) of the oxide semiconductor layer 128 on the side of the first gate electrode 120. The first oxide conductive layer 124a and the second oxide conductive layer 124b are formed of a material belonging to the same metal oxide as the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b are formed of a material belonging to the same metal oxide as the oxide semiconductor layer 128. Since the first oxide conductive layer 124a and the second oxide conductive layer 124b are in ohmic contact with the oxide semiconductor layer 128, they can be regarded as source electrodes and drain electrodes. Since the first oxide conductive layer 124a and the second oxide conductive layer 124b are in ohmic contact with the oxide semiconductor layer 128, they can be regarded as source electrodes and drain electrodes. Moreover, since the first oxide conductive layer 124a and the second oxide conductive layer 124b have higher conductivity than the oxide semiconductor layer 128, it can also be regarded that source regions and drain regions are formed at the interface in contact with the oxide semiconductor layer 128. Moreover, since the first oxide conductive layer 124a and the second oxide conductive layer 124b have higher conductivity than the oxide semiconductor layer 128, it can also be regarded that source regions and drain regions are formed at the interface in contact with the oxide semiconductor layer 128.

[0035] One end of the first oxide conductive layer 124a and one end of the second oxide conductive layer 124b are spaced apart and face each other. Moreover, they are arranged so as to overlap with the first gate electrode 120 and the second gate electrode 132. With such a structure, the transistor 202 has a so-called gate overlap structure in which substantially one end of the source region and the drain region overlaps with the gate electrode. Due to such a structure, the transistor 202 can obtain a high on-current.

[0036] The first metal layer 126a is disposed between the first oxide conductive layer 124a and the oxide semiconductor layer 128, and the second metal layer 126b is disposed between the second oxide conductive layer 124b and the oxide semiconductor layer 128. The first metal layer 126a and the second metal layer 126b are optional members and can be provided as appropriate. The first metal layer 126a and the second metal layer 126b are used, for example, as wirings for electrically connecting the transistor 202 to other elements. The first metal layer 126a and the second metal layer 126b are disposed at positions away from the region where a channel is formed in the oxide semiconductor layer 128. With such a structure, the transistor 202 has a structure for connecting to a wiring in a circuit, and at the same time, has a structure capable of preventing contamination of the channel region by the metal forming the first metal layer 126a and the second metal layer 126b.

[0037] The transistor 202 has a structure in which the first gate electrode 120 and the second gate electrode 132 are electrically connected. The first contact hole 134 shown in FIG. 7(A) is a hole that penetrates the first insulating layer 1 22 and the second insulating layer 130, and is provided outside the region where a channel of the oxide semiconductor layer 128 is formed.

[0038] The transistor 202 is a dual-gate transistor in which gate electrodes are arranged above and below the oxide semiconductor layer 128. Since it has a MOSFET structure, it can operate in a fully depleted state. In addition, even if the transistor 202 is not a fully depleted type, the first oxide semiconductor layer 128 The first surface side (the first gate electrode 120 side) and the second surface side (the second gate electrode 132 side) are channeled. The transistor 202 can operate in a partially depleted state. In either the fully depleted or partially depleted state, the insulating layer (first insulating layer 1 22, the influence of the electric field from the metal layer 126 present at the interface with the second insulating layer 130 and in the vicinity thereof Therefore, the influence of the MOS transistor can be eliminated, and the fluctuation of the threshold voltage can be prevented.

[0039] As described above, the oxide semiconductor layer 128 and the oxide conductive layer 1 24 (first oxide conductive layer 124a, second oxide conductive layer 124b), insulating layer (first insulating layer 1 22, the second insulating layer 130), the gate electrode (the first gate electrode 120 and the second gate electrode 13 2) Details of the metal layer 126 (first metal layer 126a and second metal layer 126b) are shown. .

[0040] 2-1-1.Oxide semiconductor layer The oxide semiconductor layer 128 contains elements such as indium (In), zinc (Zn), and gallium (Ga). (Ga), tin (Sn), aluminum (Al), magnesium (Mg) For example, the oxide semiconductor material for forming the oxide semiconductor layer 128 may be The present study considers ternary, binary, and mono-element oxide materials that exhibit semiconducting properties. As the quaternary oxide material, In 2 O 3 -Ga 2 O3 -SnO 2 - Examples of ZnO-based oxide materials. As ternary oxide materials, In 2 O 3 -Ga 2 O 3 -ZnO-based oxide materials, In 2 O 3 -SnO 2 -ZnO-based oxide materials, In 2 O 3 -Al 2 O 3 -ZnO-based oxide materials, Ga 2 O 3 -SnO 2 -ZnO-based oxide materials, Ga 2 O 3 -Al 2 O 3 -ZnO-based oxide materials, SnO 2 -Al 2 O 3 -ZnO-based oxide materials are exemplified Examples of binary oxide materials include In 2 O 3 -ZnO-based oxide materials, SnO 2 -Zn O-based oxide materials, Al 2 O 3 -ZnO-based oxide materials, MgO-ZnO-based oxide materials, Sn O 2 -MgO-based oxide materials, In 2 O 3 -MgO-based oxide materials are exemplified. As single-component oxide Examples of materials include In 2 O 3 -based metal oxide materials, SnO 2 -based metal oxide materials, ZnO-based metal oxide materials are exemplified. These oxide materials may contain silicon (Si), nickel (Ni ), tungsten (W), hafnium (Hf), titanium (Ti), samarium (Sm), iron (Fe), tantalum (Ta). Note that In-Ga-Zn- shown above The O-based oxide material is an oxide material containing at least In, Ga, and Zn, and there is no particular limitation on its composition ratio. In other words, the oxide semiconductor layer 128 can use a thin film represented by the chemical formula InMO 3 (ZnO) m (m>0). Here, M represents one or more metal elements selected from Ga, Al, Mg, Ti, Sm, Ta, W, Hf, and Si. The above quaternary oxide material, ternary oxide material, binary oxide material, and monovalent oxide material are not limited to those in which the contained oxide has a stoichiometric composition, and may be composed of an oxide material having a composition deviated from the stoichiometric composition.

[0041] The oxide semiconductor layer 128 is formed by a sputtering method. As the sputtering apparatus, a magnetron sputtering apparatus or a sputtering apparatus using inductively coupled plasma is used. The sputtering target uses a sintered body of the above quaternary oxide material, ternary oxide material, binary oxide material, or monovalent oxide material, and as the sputtering gas, a pure noble gas such as argon (Ar) or xenon (Xe), or a mixed gas of a noble gas and oxygen (O ) or a mixed gas of a noble gas, oxygen (O 2 ) and hydrogen (H ) is used. Further, the oxide semiconductor 2 2 layer 128 is formed by a coating method (wet method). When the oxide semiconductor layer 128 is formed by a coating method, a composition solution containing the above quaternary oxide material, ternary oxide material, binary oxide material, monovalent oxide material, or a precursor thereof is applied onto a substrate, and drying and firing treatments are performed.

[0042] The oxide semiconductor layer 128 is used to form the channel region of the transistor 202, and the carrier concentration is desirably on the order of 1×10 15 / cm 3 ~5×10 18 / cm 3 . If the carrier concentration of the oxide semiconductor layer 128 is within this range, a normally-off transistor can be realized. Also, the on / off ratio (the ratio of the on-current to the off-current) can be on the order of 10 ~10 7 ~10 1 0 .

[0043] 2-1-2. Oxide Conductive Layer The first oxide conductive layer 124a and the second oxide conductive layer 124b are made of a conductive metal oxide material, a metal nitride material, or a metal oxynitride material. Examples of the metal oxide material include indium tin oxide (In 2 O 3 ·SnO 2 : ITO), indium zinc oxide (In O 2 ·ZnO: IZO), and tin oxide (SnO 3 2 ). The first oxide conductive layer 124a and the second oxide conductive layer 124b formed of such a metal oxide material can form a good ohmic contact with the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b can use titanium oxide (TiO x

[0044] x x x ) etc. as the metal oxide material, titanium nitride (T iN x ), zirconium nitride (ZrN x ) etc. as the metal nitride material, and titanium oxynitride (TiO x N) etc. as the metal oxynitride material.y ) tantalum oxynitride (TaO x N y ), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ) etc. can be used. These metal oxide materials, metal nitride materials, and metal oxynitride materials may have trace metal elements added to improve conductivity. For example, niobium may be added to titanium oxide (TiO x ) (TiO :Nb). By using such metal oxide materials, metal nitride materials, and x metal oxynitride materials, even when in contact with the first metal layer 126a and the second metal layer 126b, the chemical stability of the contact portion can be ensured. That is, as the first oxide conductive layer 124a and the second oxide conductive layer 124b, by using the metal oxide materials, metal nitride materials, or metal oxynitride materials exemplified here, the redox reaction (local battery reaction) with a metal having a low potential (for example, aluminum (Al)) can be prevented.

[0045] 2-1-3. Insulating layer The first insulating layer 122 and the second insulating layer 130 are made of an inorganic insulating material. As the inorganic insulating material, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. are used. The first insulating layer 122 and the second insulating layer 130 have a single-layer structure of an insulating film formed by these inorganic insulating materials, or a laminated structure in which a plurality of insulating films are laminated. For example, the first insulating layer 122 may have a structure in which a silicon nitride film and a silicon oxide film are laminated from the side of the first substrate 100. Also, the second insulating layer 130 is from the side of the oxide semiconductor layer 128 , it may have a structure in which a silicon oxide film and a silicon nitride film are laminated. The first insulating layer 1 22 and the second insulating layer 130 can relax internal stress and enhance the barrier property against water vapor and the like by laminating a plurality of inorganic insulating films having different compositions.

[0046] In one embodiment of the present invention, the film thickness of the first insulating layer 122 is thicker than the film thickness of the second insulating layer 130 . As a result, the short circuit between the scanning signal line 116 and the data signal line 118 can be significantly reduced, and the manufacturing yield can be improved. Furthermore, with this configuration, the on-current of the transistor 202 can be increased. The film thickness of the first insulating layer 122 is preferably in the range of 25 0 nm to 500 nm, and the film thickness of the second insulating layer 130 is preferably about half of that, for example, in the range of 125 nm to 250 nm. With such a configuration of the insulating layer, good transistor characteristics can be obtained.

[0047] 2-1-4. Gate electrode The first gate electrode 120 and the second gate electrode 132 are made of a metal material such as aluminum (Al), molybdenum (Mo), tungsten (W), zirconium (Zr), etc. . For example, the first gate electrode 120 and the second gate electrode 132 are made of a film such as aluminum (Al) , molybdenum-tungsten (MoW) alloy. Also, the first gate electrode 120 and the second gate electrode 132 may be made of an aluminum alloy, a copper alloy, or a silver alloy. Examples of the aluminum alloy include aluminum-neodymium alloy (Al -Nd), aluminum-cerium alloy (Al-Ce), aluminum-neodymium-nickel alloy. ​Kell alloy (Al-Nd-Ni), aluminum-carbon-nickel alloy (Al-C-N i), copper-molybdenum alloy (Cu-Mo), copper-manganese alloy (Cu-Mn), etc. are applicable Furthermore, the first gate electrode 120 and the second gate electrode 132 may be made of a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. It may be made.

[0048] 2-1-5. Metal layer The first metal layer 126a and the second metal layer 126b are made of a metal material with high conductivity such as aluminum (Al), copper (Cu), etc. For example, the first metal layer 126a and the second metal layer 12 6b are made using an aluminum alloy, a copper alloy, or a silver alloy. As the aluminum alloy There are aluminum-neodymium alloy (Al-Nd), aluminum-titanium alloy (A l-Ti), aluminum-silicon alloy (Al-Si), aluminum-neodymium-n ickel alloy (Al-Nd-Ni), aluminum-carbon-nickel alloy (Al-C- Ni), copper-nickel alloy (Cu-Ni), and other metal materials. The first metal layer 126 a and the second metal layer 126b are made of such a metal material, so they have heat resistance and The wiring resistance can be reduced.

[0049] Figures 8(A) and 8(B) show a modified example of the first structure of the transistor 202. Figure 8 (A) shows a plan view of the transistor 202. Figure 8(B) shows a cross-sectional structure of the transistor 202 corresponding to the X1- X2 line shown in Figure 8(A).

[0050] The transistor 202 shown in Figures 8(A) and 8(B) has a ray in the oxide semiconductor layer 128 The structure in which the oxide semiconductor layer 128 is irradiated with light to form a low-resistance region 127 is shown. The low resistance The region 127 is formed in a region outside the region where the oxide semiconductor layer 128 overlaps with the second gate electrode 132 .

[0051] The laser light used for this process preferably has a short wavelength in order to cause an oxide semiconductor with a wide bandgap to absorb light. For example, it is preferable to irradiate ultraviolet laser light such as KrF excimer laser light (wavelength 2 48 nm), XeCl excimer laser light (wavelength 308 nm), XeF excimer laser light ( wavelength 351 nm), etc. When the oxide semiconductor layer 128 is irradiated with laser light, for example, oxygen vacancies (donors) are generated, and the resistance of that region is reduced. Further, instead of irradiating with laser light, the same effect (reduction of resistance) can be obtained by irradiating the oxide semiconductor layer 128 with ions of an inert gas such as argon (Ar). .

[0052] The low-resistance region 127 can be self-alignedly formed inside the oxide semiconductor layer 128 . That is, by irradiating laser light from the side of the second gate electrode 132, the second gate electrode 132 functions as a mask that blocks the laser light, and the low-resistance region 127 can be formed outside the region where the oxide semiconductor layer 128 overlaps with the second gate electrode 132.

[0053] Further, by providing the low-resistance region 127, the ends of the first oxide conductive layer 124a and the second oxide conductive layer 124b are prevented from overlapping with the first gate electrode 120 and the second gate electrode 132 . Thus, an offset width W can be provided and arranged. In this case, the offset L width W can be set to 0.5 μm to 2.0 μm. L ​

[0054] In this way, by self-alignedly forming the low-resistance region 127 in the oxide semiconductor layer 128, the channel length of the transistor 202 is self-alignedly controlled, so that the characteristic variations can be reduced. Further, since source and drain regions in which the oxide semiconductor layer 128 has a reduced resistance are formed in the transistor 202, the on-current can be increased.

[0055] 2-2. Second Structural Example of Transistor FIG. 9 is a schematic cross-sectional view showing a second structural example of the transistor 202. Compared with the first structural example, the second structural example has a different configuration of the oxide semiconductor layer 128. In the following, the description will be centered on the parts different from the first structural example.

[0056] The oxide semiconductor layer 128 includes at least two regions. Specifically, as shown in FIG. 9, the oxide semiconductor layer 128 includes a first region 129a and a second region 129b. In the oxide semiconductor layer 128, the first region 129a is present on the side of the first gate electrode 120, and the second region 129b is present on the side of the second gate electrode 132. FIG. 9 shows the oxide semiconductor layer 128 as if the first region 129 a and the second region 129b have a clear boundary, but there may be a case where the first region 129a and the second region 129b do not have a clear boundary. The oxide semiconductor layer 12 8 is such that the first region 129a occupies most of it, and the second region 129b exists as a thin surface layer region. The second region 129b is an extremely thin region with respect to the first region 129a. For example, when the first region 129a has a film thickness of 30 nm to 100 nm, the second region 129b has a film thickness of 2 n m to 10 nm, which is one-tenth or less of the film thickness.

[0057] In the oxide semiconductor layer 128, the first region 129a and the second region 129b have different physical properties. For example, the carrier concentration (majority carrier concentration) of the oxide semiconductor layer 128 is different between the first region 129a and the second region 129b. Specifically, the carrier concentration of the second region 129b is lower than that of the first region 129a. For example, when the carrier concentration of the first region 129a is in the range of 1×10 / cm 15 or more and 5×10 3 / cm 18 or less, the carrier concentration of the second region 129b is in the range of 1×10 3 / cm or more and less than 1× 11 / cm 3 10 / cm 15 / cm 3 Correspondingly, the conductivity of the first region 129a is in the range of 1×10 S / cm or more and 1×10 -5 S / cm or less, while 1 the conductivity of the second region 129b is in the range of 1×10 S / cm or more and less than 1×10 -10 S / cm -5 .

[0058] Also, the crystallization rate of the oxide semiconductor layer 128 may be different between the first region 129a and the second region 129b. The first region 129a has an amorphous state, or a state in which amorphous and nano microcrystals are mixed, while the second region 129b has a nano microcrystalline state, or a state in which nano microcrystals and amorphous are mixed. When both the first region 129a and the second region 129b are in a state in which amorphous and nano microcrystals are mixed, the proportion of nano microcrystalline in the second region 129b is higher than that in the first region 129a. Also, the second region 129b is ​​​​​​In addition to or instead of the nano-crystals, faceted crystal grains having a larger particle size may be included. It may contain.

[0059] The first region 129a and the second region 129b are formed by changing the film formation conditions of sputtering. For example, when the oxide semiconductor layer 128 is formed by sputtering, the first region 129a is formed using a noble gas such as argon (Ar) as a sputtering gas. On the other hand, the second region 129b is formed using a noble gas such as argon (Ar) and oxygen (O 2 ) gas. When the oxide semiconductor layer 128 is formed by sputtering , the first region 129a and the second region 129b are continuously formed while maintaining glow discharge. However, by increasing the oxygen partial pressure (the ratio of oxygen (O to argon (Ar)) when forming the second region 129b, donor defects can be reduced, 2 the crystallization rate can be improved, and a dense region (a region with high density) can be formed.

[0060] The oxide semiconductor layer 128 may have the same composition in the first region 129a and the second region 129b and only different crystallization rates. Also, the oxide semiconductor layer 128 may have the same type of metal oxide in the first region 129 a and the second region 129b but different compositions. Furthermore, the first region 129a and the second region 129b may have different compositions and different crystallization rates. For example, when the oxide semiconductor layer 128 is formed of an In 2 O 3 -Ga 2 O 3 -ZnO-based oxide material by changing the sputtering conditions as described above, the first region 129 Set a to an amorphous state or a state in which amorphous and nanocrystals coexist, and the second region 12 9b can be in a nanocrystalline state or a state in which nanocrystals and polycrystals coexist. The first Both the region 129a and the second region 129b are in a state where amorphous and nanocrystals coexist In some cases, the ratio of nanocrystals in the second region 129b can be increased compared to the first region 129a .

[0061] As shown in FIG. 10, the transistor 202 is provided with a first metal layer 126a and a second metal layer 12 6b on the first insulating layer 122, and a first oxide conductive layer 124a and a second oxide conductive layer 124b may be arranged on the upper layer side thereof. According to such a structure, the first substantially entire upper surface (and side surface) of the oxide conductive layer 124a and the second oxide conductive layer 124b comes into contact with the oxide semiconductor layer 128, and the contact resistance can be further reduced. The transistor 202 shown in FIG. 10 has a structure in which the first metal layer 126a and the second metal layer 126b, and the first oxide conductive layer 124a and the second oxide conductive layer 124b need to be patterned using different photomasks, so the number of photomasks increases compared to the transistor shown in FIG. 9 (although the photolithography process increases). However, regarding the reliability of the transistor 2 02, good characteristics can be obtained in the same manner as the transistor shown in FIG. 9 . Since the first metal layer 126a and the second metal layer 126b, and the first oxide conductive layer 124a and the second oxide conductive layer 124b need to be patterned using different photomasks, the number of photomasks increases compared to the transistor shown in FIG. 9 (although the photolithography process increases). However, regarding the reliability of the transistor 2 02, good characteristics can be obtained in the same manner as the transistor shown in FIG. 9 .

[0062] FIG. 11 shows a modified example of the second structure of the transistor 202. As shown in FIG. 11, the oxide semiconductor layer 128 may include a low-resistance region 127. The low-resistance region 127 can be formed to include the first region 129a and the second region 129b. That is, the oxide semiconductor ​​​Even when the tomographic layer 128 includes the first region 129a and the second region 129b, the source region and the drain region can form the transistor 202 that is self-alignedly formed. .

[0063] In FIG. 9, even when the oxide semiconductor layer 128 has the same composition in the first region 129a and the second region 129b, if the ratio of nano-crystals (crystallization rate) is different in these two regions, the magnitudes of the band gaps of the respective regions are different. That is, the band gap of the oxide semiconductor layer 128 is such that the first region 129a is smaller than the second region 129b. For example, when the composition of the oxide semiconductor layer 128 is the same and the band gap of the first region 129a is in the range of 2.8 eV or more and less than 3.0 eV, the band gap of the second region 129b is in the range of 3.0 eV or more and 3.2 eV or less because of the high crystallization rate. Also, along with the difference in the crystallization rate, the work function of the first region 129a becomes larger than the work function of the second region 129b. When this state is represented by an energy band diagram, as shown in FIG. 12(A), in the state where the first region 129a and the second region 129b are joined, the energy of the bottom of the conduction band ( Ec) is higher in the second region 129b than in the first region 129a. For example, the energy of the bottom of the conduction band (Ec) in the first region 129a is higher than the energy of the bottom of the conduction band (Ec) in the second region 129b, and it is preferable that the absolute value of the difference is 0.3 eV or more. region 129a and the energy of the bottom of the conduction band (Ec) in the second region 129b. band (Ec) in the second region 129b, and the absolute value of the difference is 0.3 eV or more. is preferable.

[0064] Considering the case where the oxide semiconductor layer 128 having such a band structure is applied to the transistor 202, as will be described below, it can be seen that an embedded channel is formed. As will be described below, it can be seen that an embedded channel is formed. 。The second region 129b existing between the first insulating layer 122 corresponding to the gate insulating film and the first region 129a forms an energy barrier for the electrons in the valence band. Since the carrier concentration of the first region 129a is higher than that of the second region 129b in the oxide semiconductor layer 12 8, the channel region of the transistor 202 is formed in the first region 129a. In other words, the channel region of the transistor 202 is formed at a position away from the interface between the first insulating layer 122 functioning as a gate insulating film and the oxide semiconductor layer 128 (a position away by the film thickness of the second region 129b). That is, by using the oxide semiconductor layer 128 having the first region 129a and the second region 129b an embedded channel is formed in the transistor 202. As a result the transistor 202 can flow carriers between the source and the drain without being affected by the interface between the first insulating layer 122 and the oxide semiconductor layer 128 That is, the transistor 202 can flow carriers between the source and the drain without being affected by the interface between the first insulating layer 122 and the oxide semiconductor layer 128 . As a result, carriers can flow between the source and the drain in the transistor 202 without being affected by the interface between the first insulating layer 122 and the oxide semiconductor layer 128 . As a result, the transistor 202 can flow carriers between the source and the drain without being affected by the interface between the first insulating layer 122 and the oxide semiconductor layer 128 .

[0065] FIG. 12(B) shows an example of a band diagram when oxide materials with different compositions are used for the first region 129a and the second region 129b of the oxide semiconductor layer 128. For example, in the oxide semiconductor layer 128, the first region 129a is an In O 2 O 3 -Ga 2 O 3 -SnO 2 -ZnO-based oxide material, an In 2 O 3 -Ga 2 O 3 -SnO 2 -based oxide material, or an In 2 O 3 -Ga 2 O 3 -ZnO-based oxide material, and the second region 129b is a Ga 2 O 3 -based oxide material, a Ga SnO x oxide material, or GaSiO x formed of a gallium oxide material such as an oxide material is. Gallium oxide is a wide-gap material and has a bandgap of 4 eV or more By forming the first region 129a and the second region 129b of different materials in this way, the bandgap of the first region 129a can be set to 3.6 eV or more, and the bandgap of the second region 129b can be made different to be 4.1 eV. For example, the first region 129a is formed of In forming 2 O 3 -Ga 2 O 3 -SnO 2 The bandgap of the oxide material is 3.6 eV ~3.9 eV, while when the second region 129b is formed of a-Ga 2 O 3 its bandgap becomes 4.3 eV. Also, when the second region 129b is formed of a-GaSnO its bandgap is 4.0 eV, and when formed of a-GaSiO x formed its bandgap is 4.5 eV or more. Thus, when the second region 129b is formed of a gallium oxide, its bandgap becomes 1.0 x formed eV or more larger than that of the first region 129a.

[0066] Fig. 12(B) shows the band diagram when the oxide materials as described above are used for the first region 129a and the second region 129b. The bandgap of the first region 129a is smaller than that of the second region 129b, and the work function of the first region 129a is larger than that of the second region 129b. Thus, similar to the band diagram shown in Fig. 12(A), between the first region 129a and ​​​​​In the state where the second region 129b is joined, the energy (Ec) of the bottom of the conduction band in the second region 129b becomes higher than that in the first region 129a. Since the oxide semiconductor layer 128 has such a structure, the channel region of the transistor 202 is formed at a position away from the interface between the first insulating layer 122 and the oxide semiconductor layer 128. In other words, the transistor 202 has a structure in which carriers (electrons) are not trapped at the interface between the first insulating layer 122 and the oxide semiconductor layer 128. When the second region 129b is formed of a gallium-based oxide material, the oxide semiconductor layer 128 can obtain a band gap that is 1 eV or more larger than that of the first region 129a. For example, when the second region 129b is formed of polycrystalline gallium oxide (Ga O ), its band gap is 4.8 eV to 4.9 eV. When the first region 129a is formed of an In O -Ga

[0067] O -ZnO-based oxide material, its band gap is 2.8 to 3.0 eV. Therefore, the difference in the band gap between the first region 129a and the second region 129b can be 1 eV or more. By forming the first region 129a and the second region 129b of the above-described materials as the oxide semiconductor layer 128, an embedded channel can be surely formed in the transistor 202. For example, when the second region 129b is formed of polycrystalline gallium oxide (Ga 2 O 3 ), its band gap is 4.8 eV to 4.9 eV. When the first region 129a is formed of an In O 2 -Ga 3 O 2 -ZnO-based oxide material, its band gap is 2.8 to 3.0 eV. Therefore, the difference in the band gap between the first region 129a and the second region 129b can be 1 eV or more. By forming the first region 129a and the second region 129b of the above-described materials as the oxide semiconductor layer 128, an embedded channel can be surely formed in the transistor 202. 3 In addition, the oxide material constituting the first region 129a may further contain silicon (Si) at a ratio of 0.5 atomic% or more and 5 atomic% or less. In addition, the oxide material constituting the first region 129a may further contain silicon (Si) at a ratio of 0.5 atomic% or more and 5 atomic% or less. By forming the first region 129a and the second region 129b of the above-described materials as the oxide semiconductor layer 128, an embedded channel can be surely formed in the transistor 202. By forming the first region 129a and the second region 129b of the above-described materials as the oxide semiconductor layer 128, an embedded channel can be surely formed in the transistor 202.

[0068] Moreover, the oxide material constituting the first region 129a may further contain silicon (Si) at a ratio of 0.5 atomic% or more and 5 atomic% or less. By including silicon in the oxide material constituting 9a, the carrier concentration in the first region 129a can be increased, the field-effect mobility of the transistor 202 can be increased, the heat resistance can be increased, and the threshold voltage can be controlled. The oxide semiconductor layer 128 has a structure in which the conductivity of the second region 129b is lower and the carrier concentration is lower than that of the first region 129a. Further, the oxide semiconductor layer 128 has a structure in which the crystallization rate of the second region 129b is increased with respect to the first region 129a, so that the surface layer portion has a dense structure with high density. Furthermore, the oxide semiconductor layer 128 has a structure in which the energy gap of the second region 129b is widened with respect to the first region 129a. The transistor 202 has a structure in which a channel region is formed inside the oxide semiconductor layer 128 having such a structure. When the oxide semiconductor layer is formed by sputtering, when the glow discharge is stopped to finish the film formation, the ion sheath disappears, whereas the sputtered particles remaining in the gas phase thereafter are deposited on the surface of the oxide semiconductor layer, forming a surface layer region with low density. Since this surface layer region with low density contains defects, it has an adverse effect on the characteristics of the transistor. On the other hand, in this embodiment mode, the second region 129b is intentionally formed in the region corresponding to the surface layer region of the oxide semiconductor layer 128, and by distancing the channel region from the interface between the gate insulating film and the oxide semiconductor layer as described above, deterioration of the characteristics of the transistor 202 can be prevented.

[0069] The oxide semiconductor layer 128 has a structure in which the conductivity of the second region 129b is smaller and the carrier concentration is lower than that of the first region 129a. Also, the oxide semiconductor layer 128 has a structure in which the crystallization rate of the second region 129b is increased with respect to the first region 129a, so that the surface layer portion has a dense structure with high density. The oxide semiconductor layer 128 has a structure in which the crystallization rate of the second region 129b is increased with respect to the first region 129a, so that the surface layer portion has a dense structure with high density. Furthermore, the oxide semiconductor layer 128 has a structure in which the energy gap of the second region 129b is widened with respect to the first region 129a. The transistor 202 has a structure in which a channel region is formed inside the oxide semiconductor layer 128 having such a structure. The transistor 202 has a structure in which a channel region is formed inside the oxide semiconductor layer 128 having such a structure. The transistor 202 has a structure in which a channel region is formed inside the oxide semiconductor layer 128 having such a structure.

[0070] When the oxide semiconductor layer is formed by sputtering, when the glow discharge is stopped to finish the film formation, the ion sheath disappears, whereas the sputtered particles remaining in the gas phase thereafter are deposited on the surface of the oxide semiconductor layer, forming a surface layer region with low density. Since this surface layer region with low density contains defects, it has an adverse effect on the characteristics of the transistor. This surface layer region with low density contains defects, so it has an adverse effect on the characteristics of the transistor. This surface layer region with low density contains defects, so it has an adverse effect on the characteristics of the transistor. In this embodiment mode, the second region 129b is intentionally formed in the region corresponding to the surface layer region of the oxide semiconductor layer 128, and by distancing the channel region from the interface between the gate insulating film and the oxide semiconductor layer as described above, deterioration of the characteristics of the transistor 202 can be prevented. In this embodiment mode, the second region 129b is intentionally formed in the region corresponding to the surface layer region of the oxide semiconductor layer 128, and by distancing the channel region from the interface between the gate insulating film and the oxide semiconductor layer as described above, deterioration of the characteristics of the transistor 202 can be prevented.

[0071] The transistor 202 has an oxide semiconductor layer 128 that includes a first region 129a and a second region 129 By having b, the charges trapped at the interface between the first insulating layer 122 and the oxide semiconductor layer 128 are reduced. As a result, the shift (variation) amount of the threshold voltage of the transistor 202 can be made small. Also, since the transistor 202 has an embedded channel structure, the leakage current flowing at the interface between the first insulating layer 122 and the oxide semiconductor layer 128 can be suppressed, and the off-current can be reduced. Further, as shown in FIG. 9, since the first oxide conductive layer 124a and the second oxide conductive layer 124b are in contact with the first region 129a having a high conductivity, the on-current of the transistor 202 can be increased. Thereby, the transistor 202 can obtain an on-current to off-current ratio (on-off ratio) of about 1×10 to 1×10. The amount of shift (variation) of the threshold voltage The transistor 202 has an embedded channel structure Thereby, the leakage current flowing at the interface between the first insulating layer 122 and the oxide semiconductor layer 128 can be suppressed As shown in FIG. 9, since the first oxide conductive layer 124a and the second oxide conductive layer 124b are in contact with the first region 129a having a high conductivity The on-current of the transistor 202 can be increased. Thereby, the transistor 202 Can obtain an on-current to off-current ratio (on-off ratio) of about 1×10 to 1×10. From 1×10 9 To 1×10 12 Degree of on-current to off-current ratio (on-off Ratio)

[0072] As shown in FIG. 12(C), when InGaSnO having a bandgap of 3.8 eV or InGaSmO is used for the first region 129a of the oxide semiconductor layer 128, and GaO having a bandgap of 4.7 eV is used for the second region 129b, even if the substrate temperature when forming the second insulating layer 130 is raised to 250 °C or higher, the hydrogen (H) contained in silane (SiH) used as the film-forming gas does not reduce GaO, so the oxide semiconductor layer 128 does not become conductive. Therefore, a high-quality second insulating layer 130 can be formed. Of 3.8 eV in the first region 129a of the oxide semiconductor layer 128 x Or InGaSmO x Is used, and in the second region 129b Ga having a bandgap of 4.7 eV 2 O 3 When forming the second insulating layer 130 The substrate temperature is raised to 250 °C or higher, and the hydrogen (H) contained in silane (SiH) used as the film-forming gas 4 Does not reduce GaO So the oxide semiconductor layer 12 2 O 3 8 does not become conductive. Therefore, a high-quality second insulating layer 130 can be formed Of.

[0073] Furthermore, as the oxide semiconductor layer 128, an oxide semiconductor having a bandgap of 3.6 eV or more By using the material, the component of blue light with a wavelength of 45 0 nm in the light irradiated from the backlight is no longer absorbed, and the reliability in the actual operation of the liquid crystal display device can be significantly improved This can be achieved

[0074] Although not shown, an intermediate region of an oxide semiconductor in which the carrier concentration changes stepwise or continuously may exist between the first region 129a and the second region 129b. Also, the intermediate region of the oxide semiconductor may be formed together with the first region 129a and the second region 129b in the same oxide semiconductor layer, or may be formed separately as different oxide semiconductor layers. Note that the transistor 202 shown in this embodiment is not limited to liquid crystal display devices, but can also be applied as an element constituting the backplane of an organic electroluminescence display device (also referred to as an organic EL display device or an organic EL display), a micro LED display device (also called a micro LED display).

[0075]

[0076]

[0077] 3. Driving Method of Liquid Crystal Display Device Details of the liquid crystal display device according to this embodiment are shown. The liquid crystal display device includes the transistor described in the previous section. In this section, the structure of the liquid crystal display device corresponding to various methods is shown

[0077] 3-1. Liquid Crystal Display Device of FFS Method As an aspect of the liquid crystal display device according to an embodiment of the present invention, a liquid crystal display device having pixels of the FFS method is exemplified

[0078] 3-1-1. First Embodiment This embodiment shows the structure of a liquid crystal display device 200a including FFS-mode pixels using the transistors shown in FIG. 9 or FIG. 12, and a method of manufacturing the liquid crystal display device 200a.

[0079] 3-1-1-1. Pixel Configuration FIG. 13 is a schematic plan view of a pixel 106a in the liquid crystal display device 200a according to this embodiment. Also, the cross-sectional structures along lines A1-A2 and B1-B2 shown in FIG. 13 are shown in FIG. 14(A), and the cross-sectional structure along line C1-C2 is shown in FIG. 14(B).

[0080] In this embodiment, the element substrate refers to a substrate (also called a backplane) on which transistors for driving liquid crystal and pixel electrodes are formed. On the other hand, the counter substrate refers to a substrate that is disposed opposite to the element substrate and on which a color filter is appropriately formed. Also, the liquid crystal display device 200a according to this embodiment is assumed to be a transmissive type.

[0081] As shown in FIG. 13, the pixel 106a includes a transistor 202, a pixel electrode 136, and a common electrode 138. The pixel electrode 136 is electrically connected to the transistor 202. Also, the pixel electrode 136 is insulated from the common electrode 138 by an insulating layer (not shown). A scanning signal line 116, data signal lines 118a, 118b, and a common wiring 144 are arranged so as to surround the pixel electrode 136 and the common electrode 138. The scanning signal line 116 and the common wiring 144 are arranged so as to extend in a first direction, and the data signal lines 118a, 118b are arranged so as to extend in a second direction intersecting the first direction. The data signal lines 1 116 and the common wiring 144 are arranged so as to extend in a first direction, and the data signal lines 118a 18a and 118b are arranged to cross the scanning signal line 116 and the common wiring 14 with an insulating layer (not shown) interposed therebetween. 4. Note that the data signal line 118a is electrically connected to the transistor 20 2, and the data signal line 118b is electrically connected to the transistor of an adjacent pixel.

[0082] The transistor 202 has a dual gate structure in which the oxide semiconductor layer 128 is sandwiched between the first gate electrode 120 and the second gate electrode 132. As shown in FIG. 13, the oxide semiconductor layer 128 is provided so as to overlap the patterns of the data signal line 118a and the pixel electrode 136. The scanning signal line 116 is disposed on the first surface side of the oxide semiconductor layer 128. The scanning signal line 116 has a region overlapping with the oxide semiconductor layer 128, and this overlapping region functions substantially as the first gate electrode 120. The scanning signal line 116 serves both as a wiring for transmitting a scanning signal and as a gate electrode (the first gate electrode 120) of the transistor 202. By providing a conductive pattern having such two functions, the aperture ratio of the pixel 106a can be improved. The second gate electrode 132 is disposed so as to overlap at least a part of the first gate electrode 120. The first gate electrode 120 and the second gate electrode 132 are provided with an insulating layer (not shown) interposed therebetween, and are electrically connected via the first contact hole 134.

[0083] The first oxide conductive layer 124a has a pattern continuous from the data signal line 118a, and the second oxide conductive layer 124b has a pattern continuous from the pixel electrode 136. In other words, the first oxide conductive layer 124a forms the data signal line 118a, and the second oxide conductive layer 124b ​​​​​​​​​​​​​​A pixel electrode 136 is formed. In other words, the transistor 202 has a structure in which the first oxide conductive layer 124a is electrically connected to the data signal line 118a, and the second oxide conductive layer 124b is electrically connected to the pixel electrode 136.

[0084] As shown in FIG. 13, the pixel electrode 136 has a solid structure without slits. The pixel electrode 136 is formed of the same oxide conductive material as the second oxide conductive layer 124b. Specifically, the pixel electrode 136 is formed of a conductive film having translucency such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide added with aluminum (AZO), zinc oxide added with gallium (G ZO), titanium oxide added with niobium (TiO x :Nb), titanium oxide added with tantalum (TiO :Ta), etc. x is formed of a conductive film having translucency.

[0085] The common electrode 138 is arranged so as to overlap the pixel electrode 136. The common electrode 138 has a first slit 139. The first slit 139 is formed by a through hole penetrating the common electrode 138. The common electrode 138 has at least one, preferably a plurality of first slits 139. The common electrode 138 is formed of an oxide conductive material having the same translucency as the pixel electrode 136. Further, since the common electrode 138 has the first slit 139, it may be formed of a metal material (non-translucent conductive material) such as aluminum (Al). The common electrode 138 is electrically connected to the common wiring 144. The common electrode 138 is electrically connected to the common wiring 144 through a second contact hole 146 provided in an insulating layer not shown.

[0086] The common electrode 138 provided with the first slit 139 is above the solid pixel electrode 136 On the layer side (liquid crystal layer side), an electric field generated between the pixel electrode 136 and the common electrode 138 acts on the liquid crystal layer As shown in FIG. 13, the first slit 139 extends longitudinally in the same second direction as the direction in which the data signal line 118a extends, and has a structure bent at a substantially central portion (P1 -P2 line) of the pixel 106a. The direction in which the liquid crystal molecules rotate due to the action of the electric field is It can also be controlled by the structure of the first slit 139. The first slit 139 extending longitudinally in the second direction has a structure bent at a substantially central portion (P1-P2 line) of the pixel 106a By having this structure, the directions in which the liquid crystal molecules rotate can be made different between the upper half and the lower half of the pixel 106a That is, a plurality of regions ( Also called multi-domains) in which the directions of rotation of the liquid crystal molecules are different can be formed in the liquid crystal layer. The liquid crystal display device 200a can widen the viewing angle because the pixel 1 06a has such a configuration 06a has such a configuration

[0087] FIGS. 14(A) and 14(B) show schematic cross-sectional views of the element substrate 210. As shown in FIG. 14(A) The element substrate 210 includes a transistor 202 provided on the first substrate 100, a pixel electrode 136, and a common electrode 138. The transistor 202 has the same structure as the structure shown in any of FIGS. 7(A), FIG 7(B), FIG. 8, FIG. 9, FIG. 10, and FIG. 11, and has a structure in which a first gate electrode 120, a first insulating layer 122, a first oxide conductive layer 124a, a second oxide conductive layer 124b, an oxide semiconductor layer 128, a second insulating layer 130, and a second gate electrode 132 are stacked FIG. 14(A) shows that the oxide semiconductor layer 128 is in the first region 129a and the first region 129a and the second The configuration including the second region 129b is shown, but as shown in FIG. 7(B), it may be formed substantially with one layer (only the first region 129a). There is no limitation on the materials of the first insulating layer 122 and the second insulating layer 130. For example, it is preferably formed of an oxide-based insulating material such as silicon oxide

[0088] and aluminum oxide. Further, it may have a structure in which a silicon nitride film and a silicon oxide film or an aluminum oxide film are laminated. The first insulating layer 122 is preferably formed with a thickness of 200 nm to 800 nm, for example, 400 nm. The second insulating layer 130 is formed with a thickness of 100 nm to 400 nm, for example, 200 nm if the screen size of the liquid crystal display device 200a is about 4 to 6 inches, and 200 nm to 600 nm, for example, 300 nm if the screen size is about 10 inches to 27 inches. When the screen size is 30 inches or more, it is preferably formed with a thickness of 200 nm to 800 nm, for example, 350 nm. Different voltages are applied to the pixel electrode 136 and the common electrode 138, and a capacitance is generated due to the provision of the second insulating layer 130 therebetween. This capacitance has the effect of keeping the potential of the pixel electrode 136 constant. That is, a holding capacitance element is formed by the structure in which the pixel electrode 136, the second insulating layer 130, and the common electrode 138 are laminated. When the screen size of the liquid crystal display device 200a is small, the pixel size also becomes small accordingly, so it can be said that it is preferable to reduce the film thickness of the second insulating layer 130 to increase the capacitance. On the other hand, when the screen size of the liquid crystal display device 200a is increased to 30 inches or more, the pixel electrode 136 and the common electrode 13

[0089] In order to reliably insulate the second insulating layer 130 from the semiconductor device 8, it is preferable to make the film thickness of the second insulating layer 130 large.

[0090] As described above, the first oxide conductive layer 124a is a first gate electrode 120 and a second gate electrode 122. A pole 132 extends outward from the overlapping region (opposite the channel region) and the data signal line 118 In other words, the first oxide conductive layer 124a is electrically connected to the data signal line 118a. On the other hand, the second oxide conductive layer 124b is electrically connected to the first gate electrode 120 and the second gate The gate electrode 132 is provided so as to extend from the overlapping area to the pixel electrode 136 area. As described with reference to FIG. 9(A) and FIG. 9(B), the first oxide conductive layer 124a and the second oxide conductive layer 124b are The oxide conductive layer 124b forms an input / output terminal of the transistor 202. The transistor 202 is connected to the data signal line 118a by the first oxide conductive layer 124a. and the second oxide conductive layer 124b connects the first oxide conductive layer 124c to the pixel electrode 136. In this way, the contact hole is omitted. The structure is simplified, and the aperture ratio can be improved. As in the conventional liquid crystal display panel, a contact hole is formed to connect the pixel electrode 136 and the transistor. Since no structure is applied to connect the capacitor 202, contact failure does not occur in principle. Therefore, even if the number of pixels increases with the increase in resolution, defective pixels are less likely to be formed. As a result, the manufacturing yield of liquid crystal display devices can be improved.

[0091] Although there is no limitation on the structure of the first gate electrode 120 and the second gate electrode 132, For example, the first gate electrode may have a structure in which a plurality of conductive layers are stacked as shown in FIG. The pole 120 has a structure in which a first conductive layer 250 and a second conductive layer 252 are laminated, and the second gate The electrode 132 may have a structure in which a fourth conductive layer 256 and a fifth conductive layer 258 are laminated. The first conductive layer 250 is provided in contact with the first substrate 100 (or, if an insulating film is formed on the first substrate 100, then that insulating film). Further, the fourth conductive layer 256 is provided in contact with the second insulating layer 130. The first conductive layer 250 is preferably made of a high melting point metal such as titanium (Ti), molybdenum (Mo), tantalum (Ta), molybdenum-titanium alloy (Mo -Ti) etc. to enhance the adhesion to the underlying surface. Since the fourth conductive layer 256 is also used as a conductive layer for forming the common electrode 13 8, it is preferably formed of a conductive material having translucency such as ITO, IZO, etc.

[0092] The second conductive layer 252 is laminated on the first conductive layer 250, and the fifth conductive layer 258 is laminated on the fourth conductive layer 256. The second conductive layer 252 and the fifth conductive layer 258 are preferably made of a low resistance metal material such as aluminum (Al) or its alloy, copper (Cu), etc. for reducing the resistance of the gate electrode. In a liquid crystal display device with a screen size of 15 inches or less, molybdenum (Mo ), molybdenum-tantalum alloy (MoTa), molybdenum-tungsten alloy (MoW) ) etc. can also be applied. etc. can also be applied.

[0093] The thicknesses of the first conductive layer 250, the second conductive layer 252, the fourth conductive layer 256, and the fifth conductive layer 258 are arbitrary. For example, the first conductive layer 250 and the fourth conductive layer 256 may be formed to have a thickness of 20 nm to 200 nm, and the second conductive layer 252 and the fifth conductive layer 258 may be formed to have a thickness of 200 nm to 1000 nm. The structure of the first gate electrode 120 is also applicable to the scanning signal line 116. They are used. By forming the first gate electrode 120 and the scanning signal line 116 in such a laminated structure, it is possible to enhance the adhesion to the underlying surface and reduce the wiring resistance (or electrode resistance). This is achievable.

[0094] The data signal line 118a has a structure in which a third conductive layer 254 is laminated on the first oxide conductive layer 124a. The third conductive layer 254 is formed of copper (Cu), aluminum (Al), or an alloy thereof in order to reduce the wiring resistance. For example, in a liquid crystal display device with a screen size of 15 inches or less, molybdenum (Mo) can be applied. Also, although not shown, the third conductive layer 254 may have a laminated structure in which high melting point metal layers such as titanium (Ti) and molybdenum (Mo) are provided on the upper and lower sides of aluminum (Al) in order to enhance the heat resistance. Further, the data signal line 118a may have a structure covered with the oxide semiconductor layer 128. By having such a layer structure, the data signal line 118a can prevent peeling from the underlying surface and prevent oxidation during the manufacturing process to increase the resistance. Also, the data signal line 118a is not connected to the first oxide conductive layer 124a via a contact hole, but the two layers are directly laminated, so the contact area is increased and the contact resistance can be reduced. Such a wiring and transistor connection structure also effectively acts when miniaturizing the pixel. This is achievable. This can be prevented. Also, since the data signal line 118a is not connected to the first oxide conductive layer 124a via a contact hole, but the two layers are directly laminated, the contact area is increased and the contact resistance can be reduced. Such a wiring and transistor connection structure also effectively acts when miniaturizing the pixel. This is achievable.

[0095] As shown in FIGS. 14(A) and 14(B), the common electrode 138 is provided on the second insulating layer 130. The common electrode 138 is a fourth conductive layer 2 that forms the second gate electrode 132. It is formed of the same conductive film as 56. Also, in FIG. 14(A), as shown as the section between lines B1 - B2, the common electrode 138 is electrically connected to the common wiring 144 by a second contact hole 146 that penetrates through the first insulating layer 122 and the second insulating layer 130. The common electrode 138 has a structure in which a fourth conductive layer 256 and a fifth conductive layer 258 are laminated in a region overlapping with the second contact hole 146, thereby preventing an increase in contact resistance. That is, by providing the fifth conductive layer 258 formed with a thicker film than the fourth conductive layer 256 so as to overlap with the second contact hole 146, it is possible to improve the step coverage and form a structure in which the contact resistance does not increase. Note that the common wiring 144 is provided between the first substrate 100 and the first insulating layer 122 and is formed with the same layer structure as the scanning signal line 116. On the other hand, the common electrode 138 is formed of the fourth conductive layer 256 in a region overlapping with the pixel electrode 136. With such a structure, it is possible to prevent a large step from being formed in the region where the liquid crystal is driven by the pixel electrode 136, and it is possible to reduce the alignment disorder (disclination) of the liquid crystal. It is formed of the same conductive film as 56. Also, in FIG. 14(A), as shown as the section between lines B1 - B2, the common electrode 138 is electrically connected to the common wiring 144 by a second contact hole 146 that penetrates through the first insulating layer 122 and the second insulating layer 130. The common electrode 138 has a structure in which a fourth conductive layer 256 and a fifth conductive layer 258 are laminated in a region overlapping with the second contact hole 146, thereby preventing an increase in contact resistance. That is, by providing the fifth conductive layer 258 formed with a thicker film than the fourth conductive layer 256 so as to overlap with the second contact hole 146, it is possible to improve the step coverage and form a structure in which the contact resistance does not increase. Note that the common wiring 144 is provided between the first substrate 100 and the first insulating layer 122 and is formed with the same layer structure as the scanning signal line 116. On the other hand, the common electrode 138 is formed of the fourth conductive layer 256 in a region overlapping with the pixel electrode 136. With such a structure, it is possible to prevent a large step from being formed in the region where the liquid crystal is driven by the pixel electrode 136, and it is possible to reduce the alignment disorder (disclination) of the liquid crystal. It is formed of the same conductive film as 56. Also, in FIG. 14(A), as shown as the section between lines B1 - B2, the common electrode 138 is electrically connected to the common wiring 144 by a second contact hole 146 that penetrates through the first insulating layer 122 and the second insulating layer 130. The common electrode 138 has a structure in which a fourth conductive layer 256 and a fifth conductive layer 258 are laminated in a region overlapping with the second contact hole 146, thereby preventing an increase in contact resistance. That is, by providing the fifth conductive layer 258 formed with a thicker film than the fourth conductive layer 256 so as to overlap with the second contact hole 146, it is possible to improve the step coverage and form a structure in which the contact resistance does not increase. Note that the common wiring 144 is provided between the first substrate 100 and the first insulating layer 122 and is formed with the same layer structure as the scanning signal line 116. On the other hand, the common electrode 138 is formed of the fourth conductive layer 256 in a region overlapping with the pixel electrode 136. With such a structure, it is possible to prevent a large step from being formed in the region where the liquid crystal is driven by the pixel electrode 136, and it is possible to reduce the alignment disorder (disclination) of the liquid crystal. It is formed of the same conductive film as 56. Also, in FIG. 14(A), as shown as the section between lines B1 - B2, the common electrode 138 is electrically connected to the common wiring 144 by a second contact hole 146 that penetrates through the first insulating layer 122 and the second insulating layer 130.

[0096] FIG. 14(B) shows a cross-sectional structure of a portion where the transistor 202 of the pixel 106a is not provided. The pixel electrode 136 is provided between the data signal line 118a and the data signal line 118b of an adjacent pixel. The pixel electrode 136 is formed of a conductive film having translucency such as ITO or IZO as described above. As shown in FIG. 14(B), the upper surface of the pixel electrode 136 may be covered with the oxide semiconductor layer 128. The oxide semiconductor layer 128 has translucency because its bandgap is about the same as that of the transparent conductive film. Also, the oxide semiconductor layer 128 is a semiconductor It is formed of the same conductive film as 56. Also, in FIG. 14(A), as shown as the section between lines B1 - B2, the common electrode 138 is electrically connected to the common wiring 144 by a second contact hole 146 that penetrates through the first insulating layer 122 and the second insulating layer 130. The common electrode 138 has a structure in which a fourth conductive layer 256 and a fifth conductive layer 258 are laminated in a region overlapping with the second contact hole 146, thereby preventing an increase in contact resistance. That is, by providing the fifth conductive layer 258 formed with a thicker film than the fourth conductive layer 256 so as to overlap with the second contact hole 146, it is possible to improve the step coverage and form a structure in which the contact resistance does not increase. Note that the common wiring 144 is provided between the first substrate 100 and the first insulating layer 122 and is formed with the same layer structure as the scanning signal line 116. On the other hand, the common electrode 138 is formed of the fourth conductive layer 256 in a region overlapping with the pixel electrode 136. With such a structure, it is possible to prevent a large step from being formed in the region where the liquid crystal is driven by the pixel electrode 136, and it is possible to reduce the alignment disorder (disclination) of the liquid crystal. It has conductivity as a body. Therefore, the oxide semiconductor layer overlapping with the pixel electrode 136 can also be regarded as a part of the pixel electrode.

[0097] FIG. 15 shows a cross-sectional structure of the pixel 106a along the line C1-C2 shown in FIG. 13. Specifically, with respect to the structure of the element substrate 210 shown in FIG. 14(B), it has a structure in which a counter substrate 212 and a liquid crystal layer 222 are provided.

[0098] On the element substrate 210 side, an alignment film 220a is provided so as to cover the common electrode 138. Further, on the counter substrate 212, a light-shielding layer 224, a color filter layer 226, , an overcoat layer 228, and an alignment film 220b are provided. The light-shielding layer 224 is provided so as to surround the boundary region of the pixel 106a, and the color filter layer 226 is provided so as to overlap with the pixel electrode 136. In the present embodiment, since the liquid crystal display device 200a is of the FFS type, the alignment films 220a and 220b are horizontal alignment films. The liquid crystal layer 222 is provided between the element substrate 210 and the counter substrate 212.

[0099] As is clear from the structures shown in FIGS. 14(A) and 14(B) and FIG. 15, the liquid crystal display device 200a according to the present embodiment has a structure in which the transistor 202 is of a dual-gate type and the scanning signal line 116 is not exposed to the liquid crystal layer 222. Also, the data signal line 118 also has a structure in which it is not exposed to the liquid crystal layer 222. In particular, since the pixel 106a is covered by the first insulating layer 122 and the second insulating layer 130, the liquid crystal layer 222 has a structure that is hardly affected by the signal (voltage) applied to the scanning signal line 116.

[0100] ​​​​​​​The second gate electrode 132 is electrically connected to the first gate electrode 120 and is disposed close to the liquid crystal layer 222. However, since it is separately and independently disposed for each pixel, the influence on the entire liquid crystal layer 222 is reduced. Rather, the second gate electrode 132 acts to locally collect impurity ions in the liquid crystal layer 222, thereby suppressing the deterioration of the liquid crystal layer 222 and preventing the occurrence of display unevenness.

[0101] 3-1-1-2. Configuration of Terminal Portion FIG. 16(A) shows the configuration of the input terminal portion 112 of the liquid crystal display device 200a. The input terminal portion 112 includes a terminal electrode 114. The terminal electrode 114 is formed of a first conductive layer 250 and a second conductive layer 252. That is, the terminal electrode 114 is formed of the same conductive layers as the first gate electrode 120 (the first conductive layer 250 and the second conductive layer 252). The terminal electrode 114 is electrically connected to a wiring 230 that extends from the region where pixels are formed toward the end of the first substrate 100 (in other words, the terminal electrode 114 and the wiring 230 have a continuous structure). On the upper layer side of the wiring 230 are provided a first insulating layer 122 and a second insulating layer 130. In the region of the input terminal portion 112 , an opening 232 is provided where the first insulating layer 122 and the second insulating layer 130 are removed so that the terminal electrode 114 is exposed. A metal oxide conductive layer 234 may be provided on the terminal electrode 114 so as to overlap the opening 232. The metal oxide conductive layer 234 is formed of, for example, IT O, IZO, and is provided to protect the surface of the second conductive layer 252 formed of a relatively soft metal such as aluminum (Al).

[0102] While the liquid crystal layer 222 is provided between the element substrate 210 and the counter substrate 212, the counter substrate It is provided so as to be exposed from the board 212. The element substrate 210 and the counter substrate 212 are fixed by the sealing material 23 6. The sealing material 236 is provided in contact with the second insulating layer 130 on the element substrate 210 side and in contact with the overcoat layer 228 on the counter substrate 212 side. By providing the sealing material 236 in contact with the second insulating layer 130 formed of an inorganic insulating film, the adhesive force is increased and peeling can be prevented. Thereby, it is possible to prevent moisture from entering the liquid crystal layer 222 .

[0103] The wiring 230 electrically connected to the terminal electrode 114 is covered with the first insulating layer 122 and the second insulating layer 130 formed of an inorganic insulating film, so it is provided at a position where it does not directly contact the sealing material 236 . If the wiring connected to the terminal electrode 114 is formed of the fourth conductive layer 256 and the fifth conductive layer 258 that form the second gate electrode 132 , it will have a structure that directly contacts the sealing material 236 unless a new inorganic insulating film is added. In this structure, the wiring formed of a metal material becomes a factor in reducing the adhesion of the sealing material 236. Also, the step (concavo-convex) formed by the wiring on the second insulating layer 130 causes a decrease in adhesion and can also be a factor in moisture entering the liquid crystal layer 222 . To prevent such problems, as shown in FIG. 16(A) , it is effective to form the terminal electrode 114 and the wiring 230 by the first conductive layer 250 and the second conductive layer 252 that form the first gate electrode 120 . According to the liquid crystal display device 200a according to this embodiment, since the adhesion of the sealing material 23 6 for bonding the element substrate 210 and the counter substrate 212 can be increased, deterioration of the liquid crystal layer 222 can be prevented and the reliability can be improved .

[0104] ​FIG. 16(B) shows another example of the terminal electrode 114. The terminal electrode 114 is formed of a first conductive layer 2 50 and a second conductive layer 252, and has a structure in which a third oxide conductive layer 124c is provided so as to overlap the opening 232. The third oxide conductive layer 124c is formed of the same layer as the first oxide conductive layer 124a and the second oxide conductive layer 124b that form the transistor 202 . According to such a configuration, since there is no need for a step of newly (separately) forming a metal oxide conductive layer for the terminal electrode 114, the manufacturing process can be simplified.

[0105] As described above, according to the liquid crystal display device 200a according to the present embodiment, in a structure in which a dual-gate transistor is provided in a pixel, wirings (scanning signal lines 116 and data signal lines 118) connected to the transistor can be embedded in the insulating layer. Thereby, the reliability of the liquid crystal display device 200a can be enhanced.

[0106] 3-1-1-3. Manufacturing Method The manufacturing process of the liquid crystal display device 200s according to the present embodiment will be described in detail with reference to the drawings . As described below, the liquid crystal display device 200a according to the present embodiment can be manufactured using five photomasks .

[0107] FIGS. 17(A) and 17(B) show the step of forming the first gate electrode 120 and the common wiring 144 on the first substrate 100. Although not shown, at this stage, scanning signal lines are also formed simultaneously with the first gate electrode 120.

[0108] A first conductive layer 250 and a second conductive layer 252 are formed on the first substrate 100. The first conductive layer 250 is made of titanium (Ti), molybdenum (Mo), tantalum (Ta), molybdenum·​ It is formed of a metallic material such as a titanium alloy (MoTi), and the second conductive layer 252 is formed of a metallic material such as aluminum ( Al) or an alloy thereof, copper (Cu), etc. The first conductive layer 250 and the second conductive layer 252 are formed, for example, by sputtering over substantially the entire surface of the first substrate 100. . For example, the first conductive layer 250 is formed to a thickness of 20 nm to 200 nm, and the second conductive layer 2 52 is formed to a thickness of 200 nm to 1000 nm.

[0109] With the first conductive layer 250 and the second conductive layer 252 formed over substantially the entire surface of the first substrate 100, a first resist mask 451 is formed on the second conductive layer 252. The first resist mask 4 51 is formed by the first photomask 401. The first photomask 401 is a binary mask on which a first mask pattern 411 including the pattern of the first gate electrode 120, the common wiring 144, and a scanning signal line (116) (not shown) is formed. FIG. 17(A) shows a case where a positive photoresist is used, and shows a mode in which the first mask pattern 411 forms a light-shielding portion. On the other hand, FIG. 17(B) shows a cross-sectional view near the center of the pixel 106a, but since no gate electrode, scanning signal line, or common wiring is formed in this portion, it shows that no first resist mask is formed. . Note that the circled number "1" shown in FIG. 17(A) indicates that the first resist mask 451 is formed by the first photomask 401. By etching the first conductive layer 250 and the second conductive layer 252 using the first resist mask 451, the first gate electrode 120, the common wiring 144, and a scanning signal line (116) (not shown), etc. are formed. mask.

[0110] Note that the circled number "1" shown in FIG. 17(A) indicates that the first resist mask 451 is formed by the first photo mask 401. By etching the first conductive layer 250 and the second conductive layer 252 using the first resist mask 451, the first gate electrode 120, the co mmon wiring 144, and a scanning signal line (116) (not shown), etc. are formed.

[0111] ​​​​Figures 18(A) and 18(B) show a first gate electrode 120, a common wiring 144, and a first substrate 100 on which a scanning signal line (116) not shown, etc. are formed, and a first insulating layer 122 is formed, and an oxide conductive layer 124 and a third conductive layer 254 are formed thereon, and a second resist mask 45 2 is formed thereon. This shows the step of forming.

[0112] The first insulating layer 122 is formed by a thin film manufacturing technique such as plasma CVD (Chemical Vapor Deposition) method or sputtering ring method. The first insulating layer 122 is an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, and has a thickness of 200 nm to 800 nm, for example, 400 nm. is formed.

[0113] An oxide conductive layer 124 and a third conductive layer 254 are formed on the first insulating layer 122 . The oxide conductive layer 124 is formed to a thickness of 30 nm ~200 nm by sputtering, evaporation, or coating. The third conductive layer 254 is a thin film of a metal material such as aluminum (Al) or its alloy, copper (Cu), etc., and is formed to a thickness of 200 nm to 2000 nm.

[0114] A second resist mask 452 is formed on the upper surface of the third conductive layer 254. The second resist mask 452 is formed using a second photomask 402. The second photomask 402 has a second mask pattern 412 including a portion that blocks light (light blocking portion 424) and a portion that reduces and transmits the amount of transmitted light (semi-transmissive portion 422) in a portion that transmits light (transmission portion 420). The second photomask 402 is a binary mask (composed of a transmission portion and a light blocking portion) 412. Unlike the formed photomask), for forming the data signal lines 118a and 118b A halftone mask having a light-shielding portion 424, a first oxide conductive layer 124a, and a second oxide conductive layer 124b is used to form the second resist mask 452 by exposing the photoresist film. Note that the circled number "2" shown in FIGS. 18(A) and 18(B) indicates that the second resist mask 45 2 is formed by the second photomask 402.

[0115] As shown in FIGS. 18(A) and 18(B), the second resist mask 452 has a pattern corresponding to the first oxide conductive layer 124a and the second oxide conductive layer 124b, and the pattern corresponding to the data signal line 118a is included in a thickened state overlaid on this pattern.

[0116] With the second resist mask 452 formed, the third conductive layer 254 and the oxide conductive layer 1 24 are etched. Although there is no limitation on the etching conditions, for example, the third conductive layer 254 formed of a metal material is etched by wet etching using a mixed acid etching solution, and the oxide conductive layer 124 formed of a metal oxide material or the like is etched by dry etching using a halogen-based gas. At this stage, the first oxide conductive layer 124a and the second oxide conductive layer 124b are formed. After this etching, by an ashing process, the regions with a thin film thickness of the second resist mask 452 are removed, and the etching of the third conductive layer 254 is further performed while leaving the thick film portion. This etching forms the data signal lines 118a and 118b.

[0117] Figures 19(A) and 19(B) show the stage where an oxide semiconductor layer 128 is formed on the upper layer sides of the first oxide conductive layer 124a and the second oxide conductive layer 1 24b, and data signal lines 118a and 118b, and a third resist mask 453 is formed on the oxide semiconductor layer 128 . The oxide semiconductor layer 128 is formed, for example, by a sputtering method. A sintered oxide semiconductor material is applied to the sputtering ring target. The oxide semiconductor layer 128 is formed, for example, with a film thickness of 20 nm or more and 100 nm or less, and as an example, 30 nm or more and 50 n m or less .

[0118] The third resist mask 453 is formed by applying a photoresist on the oxide semiconductor layer 128 formed on substantially the entire surface of the first substrate 100 and performing exposure using a third photomask 403 . The third photomask 403 is a binary mask on which a third mask pattern 413 for forming a pattern of the oxide semiconductor layer 128 is formed. FIG. 19(A) shows an aspect in which the third mask pattern 413 is formed as a light-shielding portion assuming that a positive-type photoresist is used. Note that the circled number “3” shown in FIGS. 19(A) and 19(B) indicates that the third resist mask 453 is formed by the third photomask 403. By etching the oxide semiconductor layer 128 using the third resist mask 453, a pattern corresponding to the arrangement of transistors, pixel electrodes, and data signal lines is formed . . . . . .

[0119] Figures 20(A) and 20(B) show the stage where a second insulating layer 130 is formed on the upper layer side of the oxide semiconductor layer 128 and a fourth resist mask 454 for forming contact holes is formed . .

[0120] Similar to the first insulating layer 122, the second insulating layer 130 is formed of an oxide-based insulating material such as silicon oxide or aluminum oxide. Alternatively, it may be formed in a structure in which a silicon nitride film and a silicon oxide film or an aluminum oxide film are laminated. The second insulating layer 130 is formed, for example, with a film thickness of 100 nm or more and 800 nm or less. However, the film thickness of the second insulating layer 130 can be appropriately set according to the screen size of the liquid crystal display device 200a. The fourth resist mask 454 is formed on the second insulating layer 130 by the fourth photomask 404. The fourth photomask 404 is a binary mask in which a fourth mask pattern 414 corresponding to a first contact hole (134) and a second contact hole 146 (not shown) is formed. FIGS. 20(A) and 20(B) show a form in which the fourth mask pattern 414 is formed as a light-shielding portion, assuming that a positive photoresist is used. The circled number "4" shown in FIG. 20(A) indicates that the fourth resist mask 454 is formed by the fourth photomask 404. By etching the second insulating layer 130 and the first insulating layer 122 using the fourth resist mask 454, a first contact hole (134) and a second contact hole 146 (not shown) are formed.

[0121]

[0122] FIGS. 21(A) and 21(B) show the stage in which the fourth conductive layer 256 and the fifth conductive layer 258 are formed on the second insulating layer 130 after the first contact hole (134) and the second contact hole 146 are formed, and then the fifth resist mask 455 is formed thereon.

[0123] The fourth conductive layer 256 is formed of a transparent conductive material such as ITO or IZO, and has a film thickness of 100 nm or more and 400 nm or less using a sputtering method or the like. The fifth conductive layer 2 58 is formed in the same manner as the first conductive layer 250.

[0124] The fifth resist mask 455 is formed using the fifth photomask 405. The fifth photo mask 405 is a halftone mask in which a fifth mask pattern 415 including a light-shielding portion 424 and a semi-transmissive portion 422 that reduces the amount of transmitted light and allows light to pass through is formed in the transmissive portion 420. By using the fifth photomask 405, a fifth resist mask 455 in which a portion corresponding to the pattern of the second gate electrode 132 and the common electrode 138 is thickened is formed. Note that the circled number "5" shown in FIGS. 21(A) and 21(B) indicates that the fifth resist mask 455 is formed using the fifth photomask 405. As shown in FIGS. 21(A) and 21(B), the fifth resist mask 455 corresponds to the second gate electrode 132 and the common electrode 138, and has a shape in which a portion that leaves the fifth conductive layer 258 is thickened. With the fifth resist mask 455 formed, the fifth conductive layer 258 and

[0125] the fourth conductive layer 256 are etched. Although there are no limitations on the etching conditions, for example, the fifth conductive layer 258 formed of a metal material is etched by wet etching using a mixed acid etching solution, and the fourth conductive layer 256 formed of a metal oxide material or the like is etched by dry etching using a halogen-based gas. After this etching process, by an ashing process, a region where the film thickness of the fifth resist mask 455 is thin is removed, and the fifth conductive layer is further left in a state where the thick film portion remains ​​​​​​​​​Etching of 258 is performed. By this etching, the second gate electrode 132 and the common electrode 138 are formed. The common electrode 138 is connected to the common wiring 144 at the site where the second contact hole 146 is formed. Also, although not shown, the second gate electrode 1 32 is connected to the first gate electrode 120 through the first contact hole (134).

[0126] By using a halftone mask in this process, the common electrode 138 is formed only by the fourth conductive layer 256 at the portion overlapping with the pixel electrode 136, and in the portion connecting the common electrode 138 and the common wiring 144, a structure in which the fourth conductive layer 256 and the fifth conductive layer 258 are stacked can be formed.

[0127] Through the above processes, the element substrate 210 of the liquid crystal display device 200a having the structures shown in FIGS. 14(A) and 14(B) can be manufactured using five photomasks. In this manufacturing process, by using a halftone mask, a structure connecting the data signal line 118a and the transistor 202 can be manufactured with one photomask, and a multilayer structure of the second gate electrode 132 and the common electrode 138 can be manufactured.

[0128] 3-1-2. Second Embodiment This embodiment shows a different shape of the pixel electrode with respect to the pixel 106a shown in the first embodiment. In the following, the description will focus on the parts different from the first embodiment, and the description of the same configuration will be omitted as appropriate.

[0129] FIG. 22 is a schematic plan view of the pixel 106b in the liquid crystal display device 200a according to this embodiment. ​​​​​​​​​is shown. Also, the cross-sectional structure along the A3-A4 line and the B3-B4 line shown in FIG. 22 is shown in FIG. 23( A), and the cross-sectional structure along the C3-C4 line is shown in FIG. 23(B).

[0130] As shown in FIG. 22, the pixel 106b has a pixel electrode 13 6 provided with a second slit 137. The second slit 137 is arranged at a position that does not overlap with the first slit 139 of the common electrode 138. That is, the pixel 106b has a structure in which the first slit 139 and the second slit 1 37 are alternately arranged.

[0131] As shown in FIGS. 23(A) and 23(B), the pixel electrode 136 has a structure in which a second oxide conductive layer 1 24b, an oxide semiconductor layer 128, are laminated. The pixel electrode 136 has a structure in which a second slit 137 is provided in a region where the second oxide conductive layer 124b is removed. The oxide semiconductor layer 128 provided on the upper layer of the second oxide conductive layer 124b may also be removed according to the pattern of the second slit 13 7. The second slit 137 can also be regarded as a region where the second oxide conductive layer 124b and the oxide semiconductor layer 128 are removed.

[0132] By providing the second slit 137 in the pixel electrode 136, the area overlapping the common electrode 138 is reduced. As a result, the capacitance formed between the pixel electrode 136 and the common electrode 138 is reduced. Thereby, it is possible to reduce the power consumption of the driver circuit for driving the liquid crystal. Note that the second slit 137 of the pixel electrode 136 can be formed simultaneously when patterning the second oxide conductive layer 124b and the oxide semiconductor layer 128, so it does not become a factor increasing the number of steps in the manufacturing process of the liquid crystal display device 200a. ​​​​​​​​​

[0133] The pixel 106b shown in this embodiment has a second slit 137 provided in the pixel electrode 136 and has the same configuration as the pixel 106a shown in the first embodiment except for this. Therefore, the liquid crystal display device 200a according to this embodiment exhibits the same effects as those of the first embodiment in addition to the effects due to the provision of the second slit 137.

[0134] 3-1-3. Third Embodiment This embodiment shows a different form of the common electrode with respect to the pixel 106b shown in the second embodiment. In the following, the description will be centered on the parts different from those of the second embodiment, and the description of the same configurations will be omitted as appropriate.

[0135] FIG. 24 shows a schematic plan view of a pixel 106c in the liquid crystal display device 200a according to this embodiment. Also, the cross-sectional structure along the line A5-A6 shown in FIG. 24 is shown in FIG. 25(A), and the cross-sectional structure along the line D1 -D2 is shown in FIG. 25(B).

[0136] As shown in FIG. 24, the common electrode 138 is electrically connected to the common wiring 144 at two locations, namely, the second contact hole 146a and the second contact hole 146b. The second contact hole 146a and the second contact hole 146b are spaced apart from each other, and the pixel electrode 136 has a structure extended so as to overlap the common electrode 138 in the region therebetween. On the other hand, the transistor 202 has the same configuration as that of the first embodiment. A second metal layer 126b may be provided overlapping the second oxide conductive layer 124b in the region connecting the input / output terminals of the transistor 202 and the pixel electrode 136.

[0137] FIG. 25(A) and FIG. 25(B) show a structure in which a second slit 137 is provided in the pixel electrode 136, and a first slit 139 is provided in the common electrode 138. Similar to the first embodiment, the pixel electrode 136 may be formed of a solid film. As shown in FIG. 25(B), in the region between the second contact hole 146a and the second contact hole 146b, there is a region where the pixel electrode 136 and the common electrode 138 overlap via the second insulating layer 130. Since this region becomes a region where capacitance is accumulated, without impairing the aperture ratio of the pixel 106c, the capacitance of the holding capacitor element formed in the region where the pixel electrode 136 and the common electrode 138 overlap can be increased. In this embodiment as well, since only the arrangement of the second contact holes 146a, 146b and the shapes of the pixel electrode 136 and the common electrode 138 are changed, it does not become a factor

[0138] for increasing the number of processes in the manufacturing process of the liquid crystal display device. The pixel 106c shown in this embodiment can increase the capacitance of the holding capacitor element without reducing the aperture ratio, so it is suitable for a liquid crystal display device with a relatively small screen size. Except for the arrangement of the second contact holes 146a, 146b and the pixel electrode 136, it has the same configuration as the second embodiment.

[0139] 3-1-4. Fourth Embodiment This embodiment shows a mode in which the form of the common electrode is different from that of the pixel 106a shown in the first embodiment. In the following, the description will be centered on the parts different from the first embodiment, and the description of the same configuration

[0140] Figure 26 is a schematic plan view of the pixel 106d in the liquid crystal display device 200a according to the present embodiment. is shown. Further, the cross-sectional structure along the line A7 - A8 shown in FIG. 26 is shown in FIG. 27(A), and C7 - The cross-sectional structure along the C8 line is shown in FIG. 27(B).

[0141] The pixel 106d shown in FIG. 26 has a structure in which the common electrode 138 is continuous across a plurality of pixels. The common electrode 138 has a stripe pattern so as to be continuous with adjacent pixels (pixels adjacent in the row direction). Further, the common electrode 138 is provided with a first slit 139 at a position overlapping the pixel electrode 136. The pixel 106d Since the common electrode 138 has a structure that is continuous across a plurality of pixels, the common wiring is omitted. In the first embodiment, when compared with the pixel 106a shown in FIG. 13, the pixel 106d shown in FIG. 26 does not have common wiring, and therefore, the contact hole for connecting the common electrode and the common wiring is also unnecessary. With such a configuration, the pixel 106d according to the present embodiment can increase the aperture ratio.

[0142] As shown in FIG. 27(A), the structure of the portion along the line A7 - A6 is the same as the structure of the pixel 106a in the first embodiment. On the other hand, as shown in FIG. 27(B), the structure along the C7 - C8 line is provided so as to cross the data signal lines 118a and 118b with the second insulating layer 130 interposed therebetween because the common electrode 138 is continuous across adjacent pixels. As described with reference to FIG. 26, the pixel 106d can omit the contact hole for connecting the common electrode and the common wiring within the pixel region. Therefore, the pixel 106 ​​​​​The area occupied by the pixel electrode 136 in the region d can be increased, and the aperture ratio of the pixel can be increased. Such a structure of the pixel 106d is suitable for a screen size of 4 to 6. This makes it suitable for small displays of around 1.5 inches.

[0143] In the pixel 106dd shown in this embodiment, the common electrode 138 is shared with the adjacent pixel. Other than that, the pixel 106 has the same configuration as the pixel 106a shown in the first embodiment. The liquid crystal display device 200a having the element 106d has the same effects as those of the first embodiment, Furthermore, the aperture ratio can be improved as described above.

[0144] Fifth embodiment In this embodiment, the transistor structure is different from that of the pixel 106a shown in the first embodiment. This embodiment shows the above.

[0145] FIG. 28 is a schematic plan view of a pixel 106e in a liquid crystal display device 200a according to this embodiment. 28. Also, the cross-sectional structure along the lines A9-A10 and B9-B10 shown in FIG. 9(A) is shown, and the cross-sectional structure taken along line C9-C10 is shown in FIG. 29(B).

[0146] The pixel 106e includes a transistor 203, a pixel electrode 136, and a common electrode 138. The electrode 136 is electrically connected to the transistor 203. The transistor 203 is a bottom gate type transistor. Therefore, the pixel 106e has a first The structure in which the second gate electrode 132 and the first contact hole 134 shown in the embodiment are omitted is Yes.

[0147] As shown in FIG. 29A, the transistor 203 has a first gate electrode 120 and a second gate electrode 123 on the first gate electrode 120. It has a structure in which an oxide semiconductor layer 128 is provided via an insulating layer 122. Also, a first oxide conductive layer 124a and a second oxide conductive layer 124b are provided between the first insulating layer 122 and the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b are provided in contact with the surface (first surface) of the oxide semiconductor layer 128 on the side of the first gate electrode 120. The oxide semiconductor layer 128 may include the aforementioned first region 129a and second region 129b. The first oxide conductive layer 124a and the second oxide conductive layer 124b can reduce the contact resistance by contacting the first surface (first region 129a) of the oxide semiconductor layer 128. On the upper layer side (the second surface side opposite to the first surface) of the oxide semiconductor layer 128, a second insulating layer 130 is provided. By interposing a second region 129b between the oxide semiconductor layer 128 and the first insulating layer 122, the defect density at the interface can be reduced. Thereby, fluctuations in the threshold voltage can be prevented. The pixel 106e according to this embodiment has the same configuration as the pixel 106a according to the first embodiment except that the configuration of the transistor 203 is different, and exhibits the same operation and effect. 3-2-1. Sixth Embodiment This embodiment shows the pixel structure of a liquid crystal display device 200a in which a color filter layer is provided on the lower layer side of a transistor. FIG. 30 shows a schematic plan view of a pixel 106f in the liquid crystal display device 200a according to this embodiment. Also, the cross-sectional structure along the lines A11-A12 and B11-B12 shown in FIG. 30 is shown.

[0148]

[0149]

[0150]

[0151] ​ As shown in FIG. 31(A), the cross-sectional structure along the C11-C12 line is shown in FIG. 31(B).

[0152] As shown in FIG. 21, the pixel 106f includes a transistor 208, a pixel electrode 136, and a common electrode 138. The pixel electrode 136 is electrically connected to the transistor 208. The transistor 208 includes an oxide semiconductor layer 128, a second gate electrode 132, a first oxide conductive layer 1 24a, and a second oxide conductive layer 124b. The second gate electrode 132 also serves as the scanning signal line 116 and is formed in the same layer as the common electrode 138. That is, the transistor 208 has a top-gate structure. Also, the pixel 106f is provided with a light-shielding layer 178 that overlaps the scanning signal line 116, the data signal lines 118a, 118b, and the transistor 208. Although not shown, a color filter layer is provided in the region overlapping the pixel electrode 136 is provided.

[0153] As shown in FIGS. 31(A) and 31(B), a light-shielding layer 178 and a color filter layer 180 are provided between the first insulating layer 122 and the first substrate 100. The light-shielding layer 178 is provided in the region overlapping the transistor 208 and the data signal lines 118a, 118b (and the scanning signal line, although not shown). The color filter layer 180 is provided in the region overlapping the pixel electrode 136.

[0154] An overcoat layer 182 formed of a resin material such as polyimide is provided on the light-shielding layer 178 and the color filter layer 180. The overcoat layer 182 fills the unevenness caused by the patterns of the light-shielding layer 178 and the color filter layer 180 to form a flat surface. ​​​This is achieved. Further, by providing a silicon nitride film as the third insulating layer 184 on the overcoat layer 182, the influence of impurities from the color filter layer 180 can be reduced. By doing so, the influence of impurities from the color filter layer 180 can be reduced.

[0155] In applications of portable electronic devices such as smartphones and tablet terminals, when the pixels are miniaturized for high-precision refinement of the display screen, the sizes of transistors, wirings, and contact holes need to be miniaturized accordingly. For example, in the case of a dual-gate transistor, the aperture diameter of the contact hole that electrically connects the top gate and the bottom gate should be 2 μm or less. In that case, considering the aperture diameter of the contact hole and the film thickness of the insulating layer that sandwiches the oxide semiconductor layer above and below, it is necessary to form a contact hole with a high aspect ratio on the mother glass, which increases the difficulty of the manufacturing process. Therefore, in this embodiment, the light-shielding layer 178 disposed to overlap the transistor 208 is formed of a material having conductivity, and by applying a predetermined bias (for example, ground potential), the characteristics of the transistor 208 are stabilized. In other words, by disposing the light-shielding layer 178 on the surface of the oxide semiconductor layer 128 opposite to the second gate electrode 132 to function as a back gate electrode, the characteristic variations (for example, the shift of the threshold voltage) of the transistor 208 are suppressed. The light-shielding layer 178 can be made conductive and heat-resistant by forming it of a metal silicide material such as titanium silicide (TiSi

[0156] x ), tantalum silicide (TaSi x ), molybdenum silicide (MoSi x x (TaSi x ), molybdenum silicide (MoSi x ), etc. By forming it in this way, it can have conductivity and heat resistance.

[0157] According to this embodiment, by providing a light-shielding layer having conductivity overlaid on the transistor, the characteristics of the transistor can be stabilized and miniaturization of the pixel can be achieved. The characteristics of the transistor can be stabilized and miniaturization of the pixel can be achieved.

[0158] 3-2. IPS mode liquid crystal display device As an aspect of a liquid crystal display device according to an embodiment of the present invention, a liquid crystal display device having an IPS mode pixel will be exemplified. The liquid crystal display device will be exemplified.

[0159] 3-2-1. Seventh embodiment This embodiment shows the structure of a liquid crystal display device 200a including an IPS mode pixel in which the transistor shown in any of FIGS. 7(B), 8, 9, 10, and 11 can be used. The structure of the liquid crystal display device 200a including an IPS mode pixel in which the transistor shown in any of FIGS. 7(B), 8, 9, 10, and 11 can be used will be shown. will be shown.

[0160] FIG. 32 is a schematic plan view of a pixel 106g in the liquid crystal display device 200a according to this embodiment. In addition, the cross-sectional structure along line A13-A14 shown in FIG. 32 is shown in FIG. 33(A), and the cross-sectional structure along line C13-C14 is shown in FIG. 33(B). In the following description, the description of the parts common to the first embodiment will be omitted, and the description will focus on the different parts. In the following description, the description of the parts common to the first embodiment will be omitted, and the description will focus on the different parts. In the following description, the description of the parts common to the first embodiment will be omitted, and the description will focus on the different parts.

[0161] As shown in FIG. 32, the pixel 106g includes a transistor 202, a pixel electrode 150, and a common electrode 152. The pixel electrode 150 has a comb-shaped (a plurality of strip-shaped) pattern and has a shape bent in one direction at the central portion (a shape like a Japanese katakana character "く"). Similarly, the common electrode 152 also has a comb-shaped (a plurality of strip-shaped) pattern and has a shape bent in one direction at the central portion (a shape like a Japanese katakana character "く"). The pixel electrode 150 and the common electrode 152 are arranged such that the comb-shaped portions mesh with each other. The pixel electrode 150 has a comb-shaped (a plurality of strip-shaped) pattern and has a shape bent in one direction at the central portion (a shape like a Japanese katakana character "く"). The pixel electrode 150 has a comb-shaped (a plurality of strip-shaped) pattern and has a shape bent in one direction at the central portion (a shape like a Japanese katakana character "く"). Similarly, the common electrode 152 also has a comb-shaped (a plurality of strip-shaped) pattern and has a shape bent in one direction at the central portion (a shape like a Japanese katakana character "く"). Similarly, the common electrode 152 also has a comb-shaped (a plurality of strip-shaped) pattern and has a shape bent in one direction at the central portion (a shape like a Japanese katakana character "く"). The pixel electrode 150 and the common electrode 152 are arranged such that the comb-shaped portions mesh with each other.

[0162] The pixel electrode 150 is electrically connected to the transistor 202 through the third contact hole 148. The common electrode 152 is electrically connected to the common wiring 144 through the second contact hole 146. As shown in FIG. 32, the common wiring 144 is disposed adjacent to the scanning signal line 116 and extends in the first direction. The second contact hole 146 that electrically connects the common electrode 152 to the common wiring 144 is disposed near the transistor 202. Such a layout can improve the aperture ratio of the pixel 106g.

[0163] As shown in FIG. 33(A), the pixel electrode 150 and the common electrode 152 are provided on the second insulating layer 130. The pixel electrode 150 is electrically connected to the transistor 202 through the third contact hole 148 that penetrates the second insulating layer 130 and the oxide semiconductor layer 128. A second metal layer 126b may be provided on the upper surface of the second oxide conductive layer 124b. The third contact hole 148 is preferably provided at a position overlapping the second metal layer 126b. With the structure in which the fourth conductive layer 256 contacts the second metal layer 126b through the third contact hole 148, the electrical connection between the pixel electrode 150 and the transistor 202 can be ensured. On the other hand, the common electrode 152 is electrically connected to the common wiring 144 through the second contact hole 146, similar to the first embodiment.

[0164] As shown in FIG. 33(B), the pixel electrode 150 and the common electrode 152 are arranged to alternate with a gap 154 therebetween on the second insulating layer 130. By arranging them in such a manner, the pixel electrode 150 and the common electrode 152 can be formed in the same process, simplifying the manufacturing process. It can be transformed. Further, the pixel electrode 150 and the common electrode 152 are formed using the transistor 20 The conductive layers (the fourth conductive layer 256 and the fifth conductive layer 258) forming the second gate electrode 132 of 2 can be used to form them, so that an increase in the manufacturing process can be prevented.

[0165] FIG. 34 shows a cross-sectional structure of the pixel 106g along the line C9-C10 shown in FIG. 33. Specifically with respect to the structure of the element substrate 210 shown in FIG. 33(B), it has a structure in which a counter substrate 212 and a liquid crystal layer 2 22 are provided.

[0166] On the element substrate 210 side, an alignment film 22 0a is provided so as to cover the pixel electrode 150 and the common electrode 152. The configuration of the counter substrate 212 is the same as that shown in FIG. 15 in the first embodiment. Also in this embodiment, the alignment films 220a and 220b use horizontal alignment films.

[0167] Also in the liquid crystal display device 200a according to this embodiment, the scanning signal lines are embedded in the first insulating layer 122 and the second insulating layer 130, and the data signal lines 118a and 118b have a structure embedded in the second insulating layer 130. Therefore, the adhesion of the sealing material for bonding the element substrate 210 and the counter substrate 2 12 can be enhanced, and the reliability can be enhanced.

[0168] 3-2-2. Eighth Embodiment This embodiment shows an aspect in which the shapes of the pixel electrode and the common electrode are different from those of the pixel 106g shown in the seventh embodiment. In the following, the description will be centered on the parts different from the seventh embodiment, and the description of the same configuration will be omitted as appropriate.

[0169] ​​​​​​​FIG. 35 is a schematic plan view of a pixel 106h in the liquid crystal display device 200a according to the present embodiment. The cross-sectional structure along the lines A15 - A16 and B15 - B16 shown in FIG. 35 is shown in FIG. 36(A), and the cross-sectional structure along the line C15 - C16 is shown in FIG. 36(B).

[0170] As shown in FIG. 35, the connection part of the common electrode 152 and the common wiring 144 of the pixel 106h is provided at a position away from the transistor 202. Specifically, the common wiring 14 4 is arranged adjacent to the scanning signal lines of adjacent pixels. Also, the common electrode 152 is provided in a layer different from the pixel electrode 150 via an insulating layer.

[0171] As shown in FIG. 36(A), the pixel electrode 150 has a structure continuous from the second oxide conductive layer 124b of the transistor 202. In other words, the pixel electrode 150 is electrically connected to the transistor 202 without passing through a contact hole. On the other hand, the common electrode 152 is electrically connected to the common wiring 144 via the second contact hole 146. A second insulating layer 130 is provided between the pixel electrode 150 and the common electrode 152. The second insulating layer 130 is provided between the pixel electrode 150 and the common electrode 152, so that even if the width of the gap 154 is narrowed, the short circuit of the two

[0172] electrodes can be prevented. Also, by narrowing the gap 154 between the pixel electrode 150 and the common electrode 152, the electric field strength can be increased, and the driving voltage of the liquid crystal element can be reduced . Also, the pixel electrode 150 is electrically connected to the transistor 2 without passing through a contact hole. By providing the second insulating layer 130 between the pixel electrode 150 and the common electrode 152, even if the width of the gap 154 is narrowed, the short circuit of the two electrodes can be prevented. Also, by narrowing the gap 154 between the pixel electrode 150 and the common electrode 152, the electric field strength can be increased, and the driving voltage of the liquid crystal element can be reduced . Also, by narrowing the gap 154 between the pixel electrode 150 and the common electrode 152, the electric field strength can be increased, and the driving voltage of the liquid crystal element can be reduced . Also, the pixel electrode 150 is electrically connected to the transistor 2 without passing through a contact hole. Since it has a structure electrically connected to 02, the pixel electrode area is increased by the amount of the contact hole omission The effective area of the electrode can be increased, and the aperture ratio can be increased.

[0173] The pixel 106h shown in this embodiment has the same configuration as the pixel 106g shown in the seventh embodiment, except that the configuration of the pixel electrode 150 and the common electrode 152 is different. Therefore, the liquid crystal display device 200a according to this embodiment exhibits the same effects as those of the seventh embodiment in addition to the above effects.

[0174] 3-2-3. Ninth Embodiment This embodiment shows a mode in which the shapes of the pixel electrode and the common electrode are different from those of the pixel 106g shown in the seventh embodiment. In the following, the description will focus on the parts different from the seventh embodiment, and the description of the same configuration will be omitted as appropriate.

[0175] FIG. 37 is a schematic plan view of a pixel 106j in the liquid crystal display device 200a according to this embodiment. Further, the cross-sectional structure along the line A17-A18 shown in FIG. 37 is shown in FIG. 38(A), and the cross-sectional structure along the line B17-B18 is shown in FIG. 38(B).

[0176] As shown in FIG. 37, the pixel 106j is the same as the seventh embodiment in that the pixel electrode 150 and the common electrode 152 are provided on the same insulating surface. In an IPS-mode pixel, since the pixel electrode and the common electrode are arranged close to each other, the capacitance generated between these two electrodes is used as a holding capacitance. On the other hand, the pixel 106j according to this embodiment is formed of the fourth metal layer 126d (and the fourth oxide conductive layer 124d) so as to overlap the common wiring 144. ​​​​​​​​​An electrode is provided, and the pixel has a configuration in which a storage capacitor element 206 is formed. The fourth metal layer 12 6d is electrically connected to the pixel electrode 150 through the fourth contact hole 156 .

[0177] As shown in FIG. 38(A), the connection structure between the pixel electrode 150 and the transistor 202 is the same as that of the seventh embodiment. The common wiring 144 is disposed adjacent to the scanning signal line of the adjacent pixel and is electrically connected to the common electrode 152 through the second contact hole 146 . As shown in FIG. 38(B), the storage capacitor element 206 is formed in a region where the fourth metal layer 126d (and the fourth oxide conductive layer 124d) and the common wiring 144 overlap. The storage capacitor element 206 is electrically connected to the pixel electrode 150 through the fourth contact hole 156 . The fourth metal layer 126d (and the fourth oxide conductive layer 124d) can be provided along the longitudinal direction of the common wiring 144 on the first insulating layer 122. Therefore, the storage capacitor element 206 can adjust the magnitude of the accumulated capacitance by adjusting the length of the fourth metal layer 126d (and the fourth oxide conductive layer 124d) along the common wiring 144. The pixel 10 6j can more stably keep the voltage of the pixel electrode 150 constant due to the provision of the storage capacitor element 206 . The pixel 106j shown in this embodiment is substantially the same as the configuration according to the seventh embodiment except that the storage capacitor element 206 is intentionally provided. Therefore, the liquid crystal display device 200a according to this embodiment exhibits the same effects as the seventh embodiment in addition to the above effects.

[0178] The pixel 106j shown in this embodiment is substantially the same as the configuration according to the seventh embodiment except that the storage capacitor element 206 is intentionally provided. Therefore, the liquid crystal display device 200a according to this embodiment exhibits the same effects as the seventh embodiment in addition to the above effects. 200a has the same effects as the seventh embodiment in addition to the above effects.

[0179] 3-3. Liquid Crystal Display Device of PVSA Method As an aspect of a liquid crystal display device according to an embodiment of the present invention, a liquid crystal display device having pixels of the PSVA method will be exemplified. The liquid crystal display device will be described.

[0180] 3-3-1. Tenth Embodiment This embodiment shows the structure of a liquid crystal display device including pixels of the PSVA method that can use the transistors shown in any of FIGS. 7(A), 7(B), 8, 9, 10, and 11, and a method for manufacturing the liquid crystal display device 200b.

[0181] 3-3-1-1. Pixel Configuration (1) FIG. 39 is a schematic plan view of a pixel 106k in the liquid crystal display device 200b according to this embodiment. In addition, the cross-sectional structure along the line A19-A20 shown in FIG. 39 is shown in FIG. 40(A), and the cross-sectional structure along the line C19-C20 is shown in FIG. 40(B).

[0182] As shown in FIG. 39, the pixel 106k includes a transistor 202, a first pixel electrode 158, and a second pixel electrode 160. Although not shown in FIG. 39, a counter electrode (162) is provided on the second substrate 102 on which a color filter layer or the like is provided. The first pixel electrode 158 and the second pixel electrode 160 are arranged so as to overlap with substantially the same center position. Since the size of the second pixel electrode 160 in plan view is smaller than the size of the first pixel electrode 158 in plan view, the second pixel electrode 160 is arranged inside the first pixel electrode 158.

[0183] Slits 161 are provided in the first pixel electrode 158 and the second pixel electrode 160. The slits 161 have a fine structure having a width of about 3 μm and a pitch of about 6 μm, for example. In the first pixel electrode 158 and the second pixel electrode 160, the slits 161 are in four directions. It is provided so as to be inclined. In other words, the first pixel electrode 158 and the second pixel electrode 16 0 are provided with slits that radially spread from the center. When a voltage is applied to the pixel electrode, since the liquid crystal molecules have the property of inclining in a direction parallel to the slits, four domains can be formed in the pixel shown in FIG. 39 at 106k.

[0184] The first pixel electrode 158, the second pixel electrode 160, and the transistor 202 are electrically connected by the wiring 164. The first pixel electrode 158 and the second pixel electrode 160 are both electrically connected to the wiring 164 via the fifth contact hole 166. That is, the same voltage is applied to the first pixel electrode 158 and the second pixel electrode 160 via the transistor 202.

[0185] As shown in FIGS. 40(A) and 40(B), the first pixel electrode 158 is provided between the first substrate 100 and the first insulating layer 122, and the second pixel electrode 160 is provided on the second insulating layer 130. The first pixel electrode 158 and the second pixel electrode 160 are electrically connected at the fifth contact hole 166 that penetrates the first insulating layer 122 and the second insulating layer 130 (and further penetrates the second oxide conductive layer 124b and the oxide semiconductor layer 128), but the portions where the slits are provided are provided in different layers.

[0186] The second pixel electrode 160 is provided along the side surface of the fifth contact hole 166 and contacts the first pixel electrode 158 exposed at the bottom portion. The wiring 164 is exposed at the side surface portion of the fifth contact hole 166, and the second pixel electrode 160 is electrically connected to the wiring 164 at the exposed portion. As a result, the first pixel electrode 158 is also electrically connected to the wiring 164. ​

[0187] The first pixel electrode 158 is formed of the first conductive layer 250, but a conductive pattern formed by the second conductive layer 252 is provided in a portion where the fifth contact hole 166 is provided. The second pixel electrode 160 is formed of the fourth conductive layer 256, but a conductive pattern formed by the fifth conductive layer 258 is provided in a portion where the fifth contact hole 166 is provided. Note that the first conductive layer 250 and the fourth conductive layer 256 are transparent conductive films, and the second conductive layer 252 and the fifth conductive layer 258 are metal films. As shown in FIGS. 40(A) and 40(B), by providing the second conductive layer 252 and the fifth conductive layer 258 so as to overlap the fifth contact hole 166, electrical connection between the first pixel electrode 158 and the second pixel electrode 160 and the wiring 164 can be surely achieved, and contact resistance can be reduced. The first conductive layer 250 and the fourth conductive layer 256 are transparent conductive films, and the second conductive layer 252 and the fifth conductive layer 258 are metal films. As shown in FIGS. 40(A) and 40(B), by providing the second conductive layer 252 and the fifth conductive layer 258 so as to overlap the fifth contact hole 166, electrical connection between the first pixel electrode 158 and the second pixel electrode 160 and the wiring 164 can be surely achieved, and contact resistance can be reduced. electrical connection between the first pixel electrode 158 and the second pixel electrode 160 and the wiring 164 can be surely achieved, and contact resistance can be reduced. contact resistance can be reduced.

[0188] FIG. 41 shows a cross-sectional structure of the pixel 106k along the C15-C16 line shown in FIG. 39. Specifically, FIG. 41 shows the structure of the pixel 106k provided with the counter substrate 212 and the liquid crystal layer 222 with respect to the structure of the element substrate 210 shown in FIG. 40(B). Specifically, FIG. 41 shows the structure of the pixel 106k provided with the counter substrate 212 and the liquid crystal layer 222 with respect to the structure of the element substrate 210 shown in FIG. 40(B). The first pixel electrode 158 and the second pixel electrode 160 are provided on the element substrate 210 side, and the common electrode 138 is provided on the counter substrate 212.

[0189] The first pixel electrode 158 and the second pixel electrode 160 are provided so as to face the common electrode 138. Since the first pixel electrode 158 and the second pixel electrode 160 are provided such that the heights from the surface of the first substrate 100 are different, the distances from the common electrode 138 are also different. That is, if the distance between the first pixel electrode 158 and the common electrode 138 is d1 and the distance between the second pixel electrode 160 and the common electrode 138 is d2, then d1 > d2. The first pixel electrode 158 and the second pixel electrode 160 are provided so as to face the common electrode 138. Since the first pixel electrode 158 and the second pixel electrode 160 are provided such that the heights from the surface of the first substrate 100 are different, the distances from the common electrode 138 are also different. That is, if the distance between the first pixel electrode 158 and the common electrode 138 is d1 and the distance between the second pixel electrode 160 and the common electrode 138 is d2, then d1 > d2. is related to

[0190] The pixel 106k has voltages based on video signals applied to the first pixel electrode 158 and the second pixel electrode 160 and the common electrode 138 is held at a constant voltage. Since the same voltage is applied to the first pixel electrode 158 and the second pixel electrode 160, the intensity of the electric field E1 in the first pixel region 301 generated between the first pixel electrode 158 and the common electrode 138 is different from the intensity of the electric field E2 in the second pixel region 302 generated between the second pixel electrode 160 and the common electrode 138. In this case, due to the relationship of the electrode intervals, E2 > E1. As a result, in the liquid crystal layer 222, for the liquid crystal molecules in the first pixel region 301 the liquid crystal molecules in the second pixel region 302 that are affected by the electric field E2 are affected by the electric field E2 and the orientation angle changes greatly. Also, the area of the second pixel region 302 is smaller than the area of the first pixel region 301. For example, the area ratio between the first pixel region 301 and the second pixel region 302 has a relationship of 2:1. FIG. 42

[0191] schematically shows, in a graph, the relationship of the luminance characteristics with respect to the applied signal voltage when the area ratio between the first pixel region 301 and the second pixel region 302 in the pixel 106k is in the relationship as described above. Since the area of the first pixel region 301 is relatively large with respect to the second pixel region 302, the luminance is high in the saturated state where the applied signal voltage is high and the liquid crystal molecules are oriented. On the other hand, in the second pixel region 3 02, since the electric field strength generated by the applied signal voltage is high, the luminance increases from a low applied signal voltage. Thus, by providing two pixel electrodes (the first pixel electrode 158 , the second pixel electrode 160) with different intervals from the common electrode 138, as the image quality of the liquid crystal display device 200b, the die

[0192] In this way, by providing two pixel electrodes (the first pixel electrode 158 and the second pixel electrode 160) with different distances from the common electrode 138, as the image quality of the liquid crystal display device 200b, the die The dynamic range can be widened. Also, the pixel 106k can form at least eight domains in the liquid crystal layer 222 by providing slits inclined in four directions in the first pixel electrode 158 and the second pixel electrode 160. The liquid crystal display device 200b according to this embodiment can widen the viewing angle by including such a pixel 106k. Also, in the pixel of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole needs to be shielded because it causes disorder in the liquid crystal alignment. As shown in this embodiment, by

[0193] making the contact hole connecting the two pixel electrodes into one, a decrease in the aperture ratio can be suppressed, and the manufacturing process of the liquid crystal display device 200b can be simplified and

[0194] its reliability can be improved. The manufacturing process of the liquid crystal display device 200b according to this embodiment will be described in detail with reference to the drawings. As described below, the liquid crystal display device

[0195] 200b according to this embodiment can be manufactured using five photomasks. Although not shown, at this stage, scanning signal lines are also formed simultaneously with the first gate electrode 120.

[0196] On the first substrate 100, a first conductive layer 250 and a second 52 is formed. Next, with the first conductive layer 250 and the second conductive layer 252 formed over substantially the entire surface of the first substrate 100, a first resist mask 551 is formed on the second conductive layer 252. The first resist mask 551 is formed by the first photomask 501. The first pho tomask 501 is a halftone mask in which a first mask pattern 511 including patterns of the first gate electrode 120, the first pixel electrode 158, and a scanning signal line (116) (not shown) is formed. The first photomask 501 includes a light-shielding portion 524 and a semi-transmissive portion 522 that reduces the amount of transmitted light of light in a transmissive portion 520 of the first mask pattern 511 that forms the first pixel electrode 158. FIG. 43(A) shows a case where a positive photoresist is used and shows a mode in which the first mask pattern 511 forms a light-shielding portion. On the other hand, FIG. 43(B) shows a cross-sectional view near the center of pixel 10 6j and shows a region where the first pixel electrode 158 is formed. Note that the circled number "1" shown in FIG. 43(A) indicates that the first resist mask 551 is formed by the first pho tomask 501. By etching the first conductive layer 250 and the second conductive layer 252 using the first resist mask 551, the first gate electrode 120, the

[0197] first pixel electrode 158, and a scanning signal line (116) (not shown), etc. are formed. By using a halftone mask as the first photomask 501, the first pixel electrode 158 can be formed in a shape having a portion where a slit 161 formed by the first conductive layer 250 is formed and a portion where the second conductive layer 252 remains at a substantially central portion. FIGS. 44(A) and 44(B) show the first gate electrode 120, the first pixel electrode 158, and

[0198] ​​​​​On the first substrate 100 on which scanning signal lines (116) and the like (not shown) are formed, a first insulating layer 12 2, an oxide conductive layer 124, and a third conductive layer 254 are formed, and a second resist mask 4 52 is formed. This shows the step.

[0199] The first insulating layer 122, the oxide conductive layer 124, and the third conductive layer 254 are formed in the same manner as in the first embodiment. A second resist mask 552 is formed on the upper surface of the third conductive layer 254. The second resist mask 552 is formed using a second photomask 502. The second photo mask 502 has a second mask pattern 512 including a light-shielding portion 524 and a semi-transmissive portion 522 that reduces the amount of transmitted light in the transmissive portion 520. Different from a bar inari mask (a photomask formed by a transmissive portion and a light-shielding portion), the second photomask 502 is a halftone mask having a light-shielding portion 424 for forming data signal lines 118a, 118b, a first oxide conductive layer 124a, and a semi-transmissive portion 422 for forming a second oxide conductive layer 124b. By exposing a photoresist film using the second photomask 502, the second resist mask 552 is formed. Note that the circled number "2" shown in FIGS. 44(A) and 44(B) indicates that the second resist mask 552 is formed using the second photomask 502. indicates.

[0200] As shown in FIGS. 44(A) and 44(B), the second resist mask 452 has a pattern corresponding to the first oxide conductive layer 124a and the second oxide conductive layer 124b, and a pattern corresponding to the data signal line 118a is thickened and included in this pattern in a superposed state. .

[0201] ​With the second resist mask 452 formed, in the same manner as in the first embodiment, the third conductive layer 254 and the oxide conductive layer 124 are etched. By this etching, data signal lines 118a, 118b, and wiring 164 are formed.

[0202] Figures 45(A) and 45(B) show the stage where the oxide semiconductor layer 1 28 is formed on the upper layer side of the first oxide conductive layer 124a, the second oxide conductive layer 12 4b, the data signal lines 118a, 118b, and the wiring 164, and the third resist mask 553 is formed on the oxide semiconductor layer 128. The oxide semiconductor layer 128 is formed in the same manner as in the first embodiment. Similarly, for the formation of the third resist mask 553, the third photomask 503 having the third mask pattern 513 is used. Note that the circled number "3" shown in Figures 45(A) and 45(B) indicates that the third resist mask 553 is formed by the third photomask 503. By etching the oxide semiconductor layer 128 using the third resist mask 553, a pattern corresponding to the arrangement of the transistors, pixel electrodes, and data signal lines is formed.

[0203] Figures 46(A) and 46(B) show the stage where the second insulating layer 130 is formed on the upper layer side of the oxide semiconductor layer 128 and the fourth resist mask 554 for forming the contact holes is formed.

[0204] The second insulating layer 130 is formed in the same manner as in the first embodiment. The fourth resist mask 554 is formed on the second insulating layer 130 by the fourth photomask 504. The fourth photomask 504 has a first contact hole (134) not shown and a fifth contact hole It is a binary mask in which a fourth mask pattern 514 corresponding to 166 is formed. FIG. 46 (A) and FIG. 46(B) show a form in which the fourth mask pattern 514 is formed as a light-shielding portion. Note that the circled number "4" shown in FIG. 46(A) indicates that the fourth resist mask 554 is formed by the fourth photomask 504. By etching the second insulating layer 130, the oxide semiconductor layer 128, the second oxide conductive layer 124b, and the first insulating layer 122 using the fourth resist mask 554, a sixth contact hole 168 is formed. Note that the sixth contact hole 168 is preferably formed by tapered etching so that the second oxide conductive layer 124b is exposed on the inner wall surface.

[0205] FIG. 47(A) and FIG. 47(B) show the stage in which, after the fifth contact hole 166 is formed, a fourth conductive layer 256 and a fifth conductive layer 258 are formed, and a fifth resist mask 555 is formed thereon.

[0206] The fourth conductive layer 256 and the fifth conductive layer 258 are formed in the same manner as in the first embodiment. The fifth resist mask 555 is formed using the fifth photomask 505. The fifth photomask 505 is a halftone mask in which a fifth mask pattern 515 including a light-shielding portion 524 and a semi-transmissive portion 522 that reduces and transmits the amount of transmitted light is formed in the transmissive portion 520. By using the fifth photomask 505, a fifth resist mask 555 in which a portion corresponding to the pattern of the second gate electrode 132 and the second pixel electrode 160 is thickened is formed. Note that the circled number "5" shown in FIG. 47(A) and FIG. 47(B) indicates the fifth resist ​​​It shows that the mask 555 is formed by the fifth photomask 505.

[0207] As shown in FIGS. 47(A) and 47(B), the fifth resist mask 555 corresponds to the second gate electrode 132 and the second pixel electrode 160, and has a shape in which the portion leaving the fifth conductive layer 258 is thickened. With the fifth resist mask 555 formed, the fifth conductive layer 258 and the fourth conductive layer 256 are etched in the same manner as in the first embodiment. By this etching the second gate electrode 132 and the second pixel electrode 160 are formed. The second pixel electrode 160 is connected to the wiring 164 at the portion of the fifth contact hole 166, and is also connected to the first pixel electrode 158 . Although not shown, the second gate electrode 132 is connected to the first gate electrode 120 by the first contact hole (134).

[0208] By using a halftone mask in this process, the second pixel electrode 160 can be formed into a shape having a portion where the slit 161 formed by the fourth conductive layer 256 is formed and a portion where the fifth conductive layer 258 remains in the region overlapping the fifth contact hole 166.

[0209] Through the above steps, the element substrate 210 of the liquid crystal display device 200b having the structure shown in FIGS. 40(A) and 40(B) can be manufactured using five photomasks. In this manufacturing process, by using a halftone mask, the first pixel electrode 158 and the second pixel electrode 160 can be manufactured with one photomask each, and the number of photomasks can be reduced.

[0210] 3-3-2. The Eleventh Embodiment ​​​​​This embodiment shows a different pixel structure in the liquid crystal display device 200b using the PSVA method from that of the tenth embodiment. In the following, the description will focus on the differences from the tenth embodiment. The structures of different pixels are shown. In the following, the description will focus on the parts different from the tenth embodiment. explain.

[0211] FIG. 48 is a schematic plan view of a pixel 106m in the liquid crystal display device 200b according to this embodiment. Also, the cross-sectional structure along the C21-C22 line shown in FIG. 39 is shown in FIG. 40.

[0212] In FIG. 48, the second pixel electrode 160 is electrically connected to the wiring 164 extending from the transistor 202 at the sixth contact hole 168. On the other hand, the first pixel electrode 158 is electrically connected to the second pixel electrode 160 at the seventh contact holes 170a and 170b. The sixth contact hole 168 is provided at a substantially central portion of the pixel 106m, while the seventh contact holes 170a and 170b are provided in a region outside (periphery) of the sixth contact hole 168. FIG. 48 shows an aspect in which the seventh contact holes 170a and 170b are provided at two locations outside the sixth contact hole 168. However, this aspect is an example, and the contact holes connecting the first pixel electrode 158 and the second pixel electrode 160 may be provided at least at one location, or may be provided at two or more locations. For example, the contact holes corresponding to the seventh contact holes may be provided at four locations so as to surround the sixth contact hole 168. FIG. 48 shows an aspect in which the seventh contact holes 170a and 170b are provided at two locations outside the sixth contact hole 168. However, this aspect is an example, and the contact holes connecting the first pixel electrode 158 and the second pixel electrode 160 may be provided at least at one location, or may be provided at two or more locations. For example, the contact holes corresponding to the seventh contact holes may be provided at four locations so as to surround the sixth contact hole 168. an example, and the contact holes connecting the first pixel electrode 158 and the second pixel electrode 160 may be provided at least at one location, or may be provided at two or more locations. For example, the contact holes corresponding to the seventh contact holes may be provided at four locations so as to surround the sixth contact hole 168. at least one location is sufficient, or two or more locations may be provided. For example, the contact holes corresponding to the seventh contact holes may be provided at four locations so as to surround the sixth contact hole 168. As shown in FIG. 49, the second pixel electrode 160 is electrically connected to the wiring 164 by the sixth contact hole 168. Also, the second pixel electrode 160 is connected to the seventh contact hole 1 at least one location is sufficient, or two or more locations may be provided. For example, the contact holes corresponding to the seventh contact holes may be provided at four locations so as to surround the sixth contact hole 168.

[0213] As shown in FIG. 49, the second pixel electrode 160 is electrically connected to the wiring 164 by the sixth contact hole 168. Also, the second pixel electrode 160 is connected to the seventh contact hole 1 at least one location is sufficient, or two or more locations may be provided. For example, the contact holes corresponding to the seventh contact holes may be provided at four locations so as to surround the sixth contact hole 168. It is electrically connected to the first pixel electrode 158 by 70a and 170b. The first pixel electrode 15 8 is provided with a metal layer formed of the second conductive layer 252 in a region overlapping with the sixth contact holes 168a and 168b, and by contacting the second pixel electrode 160 at this portion, it can be surely electrically connected. The first pixel electrode 158 is electrically connected to the wiring 164 via the second pixel electrode 160.

[0214] According to the connection structure between the pixel electrode and the wiring in this embodiment, by providing two types of contact holes, the sixth contact hole 16 8 and the seventh contact holes 170a and 170b, the depth of each contact hole can be made shallow. For example, in the configuration according to the tenth embodiment, the sixth contact hole 168 penetrates the second insulating layer 130, the oxide semiconductor layer 128, the second oxide conductive layer 124b, and the first insulating layer 122. On the other hand, in this embodiment, the sixth contact hole 168 penetrates the second insulating layer 130 and the oxide semiconductor layer 128, and the seventh contact holes 170a and 170b only penetrate the first insulating layer 122 and the second insulating layer 130. Thus, since the contact holes connecting the pixel electrode and the wiring in the pixel 106m are shallow, disconnection at the contact hole portion can be prevented.

[0215] The pixel 106m has the same configuration as the tenth embodiment except that the forms of the contact holes connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring are different, and exhibits the same operational effects.

[0216] 3-3-3. Twelfth Embodiment This embodiment shows a different pixel structure in the liquid crystal display device 200b using the PSVA method from that of the tenth embodiment. In the following, the description will focus on the parts that are different from the tenth embodiment. The structure of different pixels is shown. In the following, the description will focus on the parts that are different from the tenth embodiment. will be described.

[0217] FIG. 50 is a schematic plan view of a pixel 106n in the liquid crystal display device 200b according to this embodiment. Also, the cross-sectional structure along the line A19 - A20 shown in FIG. 50 is shown in FIG. 51(A), and the cross-sectional structure along the line C19 - C20 is shown in FIG. 51(B).

[0218] As shown in FIG. 50, the pixel 106n has a structure in which the first pixel electrode 158 and the second pixel electrode 160 are electrically connected to the wiring 164 extending from the transistor 202 at the eighth contact hole 172 and the ninth contact hole 174. The eighth contact hole 1 72 and the ninth contact hole 174 are provided in the approximate center of the pixel 106n and are provided so as to overlap. The eighth contact hole 1 72 and the ninth contact hole 174 are provided in the approximate center of the pixel 106n and are provided so as to overlap.

[0219] As shown in FIGS. 51(A) and 51(B), the eighth contact hole 172 penetrates the first insulating layer 122, and the ninth contact hole 174 penetrates the second insulating layer 130 and the oxide semiconductor layer 128. On the first insulating layer 122, the wiring 1 64 (the second oxide conductive layer 124b) extending from the transistor 202 is provided, and is electrically connected to the first pixel electrode 158 at the position of the eighth contact hole 172. The first pixel electrode 158 is provided with a metal layer formed of the second conductive layer 252 in a region overlapping the eighth contact hole 172, and the wiring 164 is provided so as to contact this metal layer. Also, a metal layer 126c is provided on the wiring 164 (the second oxide conductive layer 124b) so as to overlap the eighth contact hole 172. 64 (the second oxide conductive layer 124b) extending from the transistor 202 is provided, and is electrically connected to the first pixel electrode 158 at the position of the eighth contact hole 172. The first pixel electrode 158 is provided with a metal layer formed of the second conductive layer 252 in a region overlapping the eighth contact hole 172, and the wiring 164 is provided so as to contact this metal layer. Also, a metal layer 126c is provided on the wiring 164 (the second oxide conductive layer 124b) so as to overlap the eighth contact hole 172. metal layer. Also, a metal layer 126c is provided on the wiring 164 (the second oxide conductive layer 124b) so as to overlap the eighth contact hole 172. metal layer. Also, a metal layer 126c is provided on the wiring 164 (the second oxide conductive layer 124b) so as to overlap the eighth contact hole 172. metal layer. Also, a metal layer 126c is provided on the wiring 164 (the second oxide conductive layer 124b) so as to overlap the eighth contact hole 172. With such a structure, the electrical connection between the first pixel electrode 158 and the wiring 164 can be ensured. It can be achieved.

[0220] The second pixel electrode 160 is electrically connected to the wiring 164 through the ninth contact hole 174. The ninth contact hole 174 is provided at a position overlapping the wiring 164. In this configuration, the ninth contact hole 174 is preferably provided at a position overlapping the metal layer 126c. When forming the ninth contact hole 174, since the metal layer 126c functions as an etching stopper, it becomes easy to control the depth of the contact hole. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed. structure, the depth of the contact hole can be easily controlled. Also, due to the ninth contact hole 174, the upper surface of the metal layer 126c is exposed, enabling a good electrical connection to be formed with the fourth conductive layer 256 that forms the second pixel electrode 160. Thus, in the structure connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring 164, by providing two contact holes in an overlapping manner, the depth of each individual contact hole can be made shallower, and a reliable electrical connection can be achieved. In the pixels of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole causes disorder in the liquid crystal alignment, so it is necessary to block light. As shown in this embodiment, by providing the contact holes connecting the two pixel electrodes in an overlapping manner, a decrease in the aperture ratio can be suppressed.

[0221] The pixel 106n has the same configuration as that of the tenth embodiment except that the form of the contact hole for electrically connecting the first pixel electrode 158 and the second pixel electrode 160 to the wiring is different, and exhibits the same operational effects. operational effects.

Explanation of Reference Numerals

[0222] 100... the first substrate, 101... FPC substrate, 102... the second substrate, 104... display unit, 106... pixel, 108... scanning signal line driving circuit, 109... common signal line driving circuit, 110... data signal line driving circuit, 111... driver IC, 112... ... input terminal section, 114... terminal electrode, 115... output signal line, 116... scanning signal line, 117... common signal line, 118... data signal line, 120... the first gate electrode, 122... the first insulating layer, 124... oxide conductive layer, 126... metal layer, 12 ... low resistance region, 128... oxide semiconductor layer, 129... region, 130... the second insulating layer, 132... the second gate electrode, 134... the first contact hole, 136... ... pixel electrode, 137... the second slit, 138... common electrode, 139... the first slit, 144... common wiring, 146... the second contact hole, 148... the third contact hole, 150... pixel electrode, 152... common electrode, 154... gap, 156... the fourth contact hole, 158... the first pixel electrode, 160... the second pixel electrode, 161... slit, 162... counter electrode, 164... wiring, 166... the fifth contact hole, 168... the sixth contact hole, 170... the seventh contact hole, 172... the eighth contact hole, 174... the ninth contact hole, 1 78... light-shielding layer, 180... color filter layer, 182... overcoat layer, 1 84... the third insulating layer, 200... liquid crystal display device, 202... transistor, 203 ... transistor, 204... liquid crystal element, 206... holding capacitance element, 208... Transistor, 209... Demultiplexer, 210... Element substrate, 212... Pair Substrate, 220... Alignment film, 222... Liquid crystal layer, 224... Light-shielding layer, 226... Color filter layer, 228... Overcoat layer, 230... Wiring, 232... Open ing portion, 234... Metal oxide conductive layer, 236... Sealing material, 250... First conductive layer , 252... Second conductive layer, 254... Third conductive layer, 256... Fourth conductive layer, 258 ... Fifth conductive layer, 301... Pixel first region, 302... Pixel second region, 401... First photomask, 402... Second photomask, 403... Third photomask, 404... Fourth photomask, 405... Fifth photomask, 411... First mask pattern, 412... Second mask pattern, 413... Third mask pattern, 41 4... Fourth mask pattern, 415... Fifth mask pattern, 420... Transmission portion, 422... Semi-transmission portion, 424... Light-shielding portion, 451... First resist mask, 452 ... Second resist mask, 453... Third resist mask, 454... Fourth resist mask, 455... Fifth resist mask, 501... First photomask, 502... Second photomask, 503... Third photomask, 504... Fourth photomask , 505... Fifth photomask, 511... First mask pattern, 512... Second mask pattern, 513... Third mask pattern, 514... Fourth mask pattern, 515... Fifth mask pattern, 520... Transmission portion, 522... Semi-transmission portion, 524 ... Light-shielding portion, 551... First resist mask, 552... Second resist mask, 5 53... the third resist mask, 554... the fourth resist mask, 555... the fifth res ist mask

Claims

1. A plurality of pixels arranged on a substrate in n rows and m columns; A plurality of scanning signal lines and a plurality of common signal lines arranged in accordance with the array, a display unit including a plurality of data signal lines arranged in accordance with the arrangement in the column direction of the pixel electrodes; a scanning signal line that is disposed outside the display unit and outputs a scanning signal to the plurality of scanning signal lines; A drive circuit; A common signal line is disposed outside the display unit and outputs a common signal to the common signal lines. A signal line driver circuit; A data signal line is disposed outside the display unit and outputs a video signal to the data signal lines. A signal line driver circuit, Each of the plurality of pixels is A pixel electrode, a common electrode, and a transistor, The transistor is connected to one of the plurality of data signal lines and the pixel a gate connected to one of the plurality of scanning signal lines; R, the common electrode is connected to one common signal line among the plurality of common signal lines; The pixel electrode is flat, and the common electrode is provided with a slit. The common signal line driving circuit drives each of the plurality of common signal lines for each frame. It outputs a common voltage of the same polarity whose voltage level changes, The data signal line driving circuit is configured to drive a common voltage Vcc, the common voltage Vcc being a common voltage Vcc.

4. A liquid crystal display device of an in-plane switching mode, characterized in that it outputs a video signal of a polarity.

2. A plurality of pixels arranged on a substrate in n rows and m columns; A plurality of scanning signal lines and a plurality of common signal lines arranged in accordance with the array, a display unit including a plurality of data signal lines arranged in accordance with the arrangement in the column direction of the pixel electrodes; a scanning signal line that is disposed outside the display unit and outputs a scanning signal to the plurality of scanning signal lines; A drive circuit; A common signal line is disposed outside the display unit and outputs a common signal to the common signal lines. A signal line driver circuit; A data signal line is disposed outside the display unit and outputs a video signal to the data signal lines. A signal line driver circuit, Each of the plurality of pixels is A pixel electrode, a common electrode, and a transistor, The transistor is connected to one of the plurality of data signal lines and the pixel a gate connected to one of the plurality of scanning signal lines; R, the common electrode is connected to one common signal line among the plurality of common signal lines; A first slit is provided in the pixel electrode, and a second slit is provided in the common electrode; The first slit overlaps the conductive pattern of the common electrode, and the second slit It overlaps with the conductive pattern of the element electrode, The common signal line driving circuit drives each of the plurality of common signal lines for each frame. It outputs a common voltage of the same polarity whose voltage level changes, The data signal line driving circuit is configured to drive a common voltage Vcc, the common voltage Vcc being a common voltage Vcc.

4. A liquid crystal display device of an in-plane switching mode, characterized in that it outputs a video signal of a polarity.

3. The plurality of pixels include a first pixel, a second pixel, and a third pixel arranged in the row direction. Including, The plurality of scanning signal lines are a first scanning signal line connected to the first pixel and the third pixel; a second scanning signal line connected to the transistor of the second pixel; Including, The plurality of common signal lines are connected to the first pixel, the second pixel, and the third pixel. a first common signal line connected to the correspondingly arranged common electrode; The plurality of data signal lines include a first data signal line connected to the first pixel and the second pixel. a second data signal line connected to the third pixel, and a third data signal line connected to the third pixel.

3. The in-plane switching liquid crystal display device according to claim 2.

4. The data signal line driving circuit has a first terminal to which a data signal is input from a driver IC; A data signal input from the first terminal is transmitted to two selected data signal lines from the plurality of data signal lines. and a demultiplexer for distributing the data signal to one or more data signal lines. An in-plane switching liquid crystal display device.

5. The demultiplexer is a dual gate electrode having gate electrodes arranged above and below an oxide semiconductor.

5. The in-plane switching liquid crystal display according to claim 4, which is formed of transistors having a gate structure. Device.

6. The scanning signal line driving circuit is disposed adjacent to the display unit, and the common signal line driving circuit 3. The horizontal electrode according to claim 1, wherein the wiring is disposed outside the scanning signal line driving circuit. A liquid crystal display device using the field method.

7. A first insulating layer between the substrate and the pixel electrode, and a second insulating layer between the pixel electrode and the common electrode 3. The IPS LCD according to claim 1, further comprising a second insulating layer.

8. a color filter layer overlapping the pixel electrode; and a light-shielding layer surrounding the color filter layer. and The color filter layer and the light-shielding layer are provided between the substrate and the first insulating layer.

8. The in-plane switching liquid crystal display device according to claim 7,

9. The transistor is an oxide semiconductor layer between the first insulating layer and the second insulating layer; 8. The in-plane switching liquid crystal display device according to claim 7, further comprising:

10. 10. The in-plane switching mode liquid crystal display device according to claim 9, wherein the plurality of data signal lines are provided between the first insulating layer and the second insulating layer, and the plurality of common signal lines are provided between the substrate and the first insulating layer.

11. The transistor is a first gate electrode overlapping the oxide semiconductor layer; a second gate electrode overlapping the semiconductor layer; The first gate electrode and the front gate electrode are disposed between the first insulating layer and the oxide semiconductor layer. a first oxide conductive layer and a second oxide conductive layer disposed so as to sandwich the second gate electrode from both sides; and 11. The pixel electrode according to claim 10, wherein the pixel electrode is formed in the same layer as the second oxide conductive layer.

2. The in-plane switching liquid crystal display device according to claim 1 .

12. The first oxide conductive layer and the second oxide conductive layer are the first gate of the oxide semiconductor layer.

12. The in-plane switching liquid crystal display device according to claim 11, wherein the first insulating film is in contact with a surface of the first insulating film on the side of the gate electrode.

13. the gate electrode and the common electrode are formed in the same layer on the second insulating layer; 10. The in-plane switching liquid crystal display device according to claim 9.

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