Semiconductor device

Abstract

To provide a highly reliable semiconductor device.SOLUTION: Semiconductor devices (1A, 1B, 1C, 1D) according to one aspect each include: a semiconductor substrate (11) of a first conductivity type, having a main surface (3); a plurality of device regions (10) disposed being separated from each other on the semiconductor substrate (11), each device region including a semiconductor region (12) of a second conductivity type; and an external sub-contact (20) with conductivity, provided on the main surface (3) of the semiconductor substrate (11) and fixing the semiconductor substrate (11) to a referential potential. In plan view, the external sub-contact (20) is disposed along an outer edge of the main surface (3) of the semiconductor substrate (11) so as to partially surround the plurality of device regions (10).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 describes a semiconductor device including an external connection circuit section, an internal circuit section, and a guard ring for preventing latch-up disposed between the external connection circuit section and the internal circuit section.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] An object of the present disclosure is to provide a semiconductor device having high reliability.

[0005] The present disclosure provides a semiconductor device including a semiconductor substrate of a first conductivity type having a main surface, a plurality of device regions spaced apart from each other on the semiconductor substrate and each including a semiconductor region of a second conductivity type, and a conductive external sub-contact provided on the main surface of the semiconductor substrate and fixing the semiconductor substrate to a reference potential. In a plan view, the external sub-contact is disposed along an outer edge of the main surface of the semiconductor substrate so as to at least partially surround the plurality of device regions.

Brief Description of the Drawings

[0006]

Figure 1

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[0007] [Detailed Description] Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted. The drawings may be drawn with some parts simplified or exaggerated for ease of understanding, and the dimensional ratios and the like are not limited to those described in the drawings.

[0008] First, the basic structure of the semiconductor device will be described.

[0009] FIG. 1 is a plan view of a semiconductor device 1A according to an embodiment. The semiconductor device 1A is an LSI (Large Scale Integration) on which a plurality of devices are mounted.

[0010] The semiconductor device 1A includes a rectangular parallelepiped chip 2 (semiconductor chip). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side (see FIG. 2). The chip 2 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. In the following description, the thickness direction of the chip 2 is defined as the Z-axis direction, the direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0011] The first main surface 3 and the second main surface 4 are each a plane perpendicular to the Z-axis direction. The planar shape of the first main surface 3 as viewed from the normal direction (Z-axis direction) of the first main surface 3 is a rectangle (quadrilateral). Similarly, the planar shape of the second main surface 4 is a rectangle (quadrilateral).

[0012] The first main surface 3 includes a first side 6A, a second side 6B, a third side 6C, and a fourth side 6D. The first side 6A extends in the Y direction along the boundary line between the first main surface 3 and the first side surface 5A. The second side 6B extends in the X direction along the boundary line between the first main surface 3 and the second side surface 5B. The third side 6C extends in the Y direction along the boundary line between the first main surface 3 and the third side surface 5C. The fourth side 6D extends in the X direction along the boundary line between the first main surface 3 and the fourth side surface 5D. One end of the first side 6A is connected to one end of the second side 6B. The other end of the second side 6B is connected to one end of the third side 6C. The other end of the third side 6C is connected to one end of the fourth side 6D. The other end of the fourth side 6D is connected to the other end of the first side 6A.

[0013] The semiconductor material constituting the chip 2 is silicon (Si). A compound semiconductor can also be used as the semiconductor material constituting the chip 2. Examples of the compound semiconductor include III-V compound semiconductors, IV-IV compound semiconductors, and mixed crystal semiconductors using these semiconductors. As the III-V compound semiconductor, Ga-containing semiconductors such as GaAs and GaN can be used. As the IV-IV compound semiconductor, Si-containing semiconductors such as SiC and SiGe can be used.

[0014] The semiconductor device 1A includes a plurality of device regions 10. The plurality of device regions 10 are formed on the first main surface 3 and are arranged to be spaced apart from each other when viewed from the Z-axis direction. Each device region 10 is arranged to be spaced apart from the side surfaces (the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D) of the chip 2. The number, arrangement, and shape of the device regions 10 formed in the semiconductor device 1A are arbitrary and are not limited to specific numbers, arrangements, and shapes.

[0015] In a plurality of device regions 10, a plurality of devices are respectively formed. The plurality of devices include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0016] As the MISFET, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used. Each device may be a power transistor. As the power MOSFET, a DMOS (Double-diffused MOSFET) can be used, and types such as vertical type (VDMOS) and lateral type (LDMOS) can be used. As the drain-source voltage of the MISFET, those of high voltage HV (high voltage: for example, 100V or more and 1000V or less), middle voltage MV (middle voltage: for example, 30V or more and 100V or less), and low voltage LV (low voltage: for example, 1V or more and 30V or less) are also known.

[0017] The plurality of devices formed within the plurality of device regions 10 may include a driver for controlling a high-voltage withstand switching device. Examples of the driver for controlling a high-voltage withstand switching device include a high-side driver for controlling the operation of a high-side switch, a gate driver for controlling the operation of a power transistor, and a half-bridge driver for controlling the operation of a half-bridge circuit. These drivers are composed of transistors, inverters, operational amplifiers, etc., and are used as drive devices for power supplies or motors that require high voltage withstand, high output, etc. Note that the devices formed within the device region 10 may be optical devices such as light-emitting elements and light-receiving elements.

[0018] FIG. 2 is a schematic cross-sectional view of the semiconductor device 1A taken along line II-II in FIG. 1.

[0019] The semiconductor device 1A includes a semiconductor substrate 11. The semiconductor substrate 11 is made of a p-type (first conductivity type) semiconductor. The upper surface of the semiconductor substrate 11 constitutes the first main surface 3, and the bottom surface of the semiconductor substrate 11 constitutes the second main surface 4. As described above, a plurality of device regions 10 are formed on the first main surface 3 of the semiconductor substrate 11.

[0020] As shown in FIGS. 1 and 2, each of the plurality of device regions 10 includes a well region 12. The well region 12 is an n-type (second conductivity type) semiconductor region. The well region 12 has, for example, a rectangular planar shape. By forming a circuit including a p-type or n-type semiconductor region within the well region 12, a device is formed within the device region 10.

[0021] As shown in FIGS. 1 and 2, a plurality of well regions 12 are arranged spaced apart from each other when viewed from the Z-axis direction. In FIG. 2, among the plurality of well regions 12, two well regions 12A and 12B are illustrated. The well regions 12A and 12B are spaced apart from each other in the X direction, and form a pn junction with a part of the semiconductor substrate 11 disposed between the well regions 12A and 12B. That is, in the semiconductor device 1A, a region in which the well region 12A, the semiconductor substrate 11, and the well region 12B are arranged in this order is formed. This region functions as a parasitic element having an npn junction.

[0022] A well contact region 13 is formed in the well region 12. The well contact region 13 is an n-type diffusion layer. As shown in FIG. 2, each well region 12 is electrically connected to a well contact 14 via the well contact region 13 exposed from the first main surface 3. The well contact 14 is composed of a conductive material such as tungsten, and supplies a well potential V W to the well region 12. The well contact 14 is connected to a pad 17 via a metal layer 15 and a through-hole conductor 16. The pad 17 is connected to a power supply wiring or another device, and supplies a well potential V W to the well region 12 through the well contact 14.

[0023] The semiconductor device 1A further includes a sub-contact (external sub-contact) 20. The sub-contact 20 is composed of a conductive material containing, for example, tungsten, and is disposed on the first main surface 3 of the semiconductor substrate 11. As shown in FIG. 1, the sub-contact 20 has an annular planar shape when viewed from the Z-axis direction, and is disposed along the outer edge of the first main surface 3 of the semiconductor substrate 11 so as to at least partially surround the plurality of device regions 10.

[0024] In one embodiment, the sub-contact 20 is continuously formed along the entire circumference of the outer edge of the first main surface 3 of the semiconductor substrate 11 in a plan view. That is, the sub-contact 20 includes a first portion 20A extending along the first side 6A of the first main surface 3, a second portion 20B extending along the second side 6B of the first main surface 3, a third portion 20C extending along the third side 6C of the first main surface 3, and a fourth portion 20D extending along the fourth side 6D of the first main surface 3. One end of the first portion 20A is connected to one end of the second portion 20B. The other end of the second portion 20B is connected to one end of the third portion 20C. The other end of the third portion 20C is connected to one end of the fourth portion 20D. The other end of the fourth portion 20D is connected to the other end of the first portion 20A.

[0025] When viewed from the Z-axis direction, the width of the sub-contact 20 in the direction perpendicular to the extending direction of the sub-contact 20 is constant throughout the entire area of the sub-contact 20. That is, the widths of the first portion 20A and the third portion 20C in the X-axis direction, and the widths of the second portion 20B and the fourth portion 20D in the Y-axis direction are equal to each other.

[0026] As shown in FIG. 2, a sub-contact region 21 is formed in the semiconductor substrate 11. The sub-contact region 21 is a p-type diffusion layer. The sub-contact region 21 is exposed from the first main surface 3 and is formed at a position corresponding to the sub-contact 20. That is, the sub-contact region 21 has an annular planar shape and surrounds a plurality of well regions 12 when viewed from the Z-axis direction. The semiconductor substrate 11 is electrically connected to the sub-contact 20 through the sub-contact region 21.

[0027] The sub-contact 20 is connected to the pad 24 through the metal layer 22 and the through-hole conductor 23. The pad 24 is connected to the ground terminal and is a ground pad that connects the sub-contact 30 to the reference potential V GND through the metal layer 22. The reference potential V GND is a constant potential or a ground potential. The sub-contact 20 has a function of fixing the potential of the semiconductor substrate 11 to the reference potential V GND .

[0028] As shown in FIG. 1, the semiconductor device 1A does not include other sub-contacts inside the sub-contact 20. That is, among the plurality of device regions 10, no sub-contact is provided between two adjacent device regions 10. As will be described later, not providing a sub-contact between two adjacent device regions 10 contributes to the inactivation of parasitic elements between the two device regions 10. A parasitic element is an electronic element unintentionally formed in the semiconductor device 1A, and is typically a parasitic transistor. Parasitic elements may have an unexpected effect on the operation of the semiconductor device 1A.

[0029] As shown in FIG. 2, the semiconductor device 1A may be disposed on the first main surface 3 of the semiconductor substrate 11 and may further include an insulating layer 18 covering the first main surface 3. The insulating layer 18 includes at least one of a silicon oxide film and a silicon nitride film, and is formed on the first main surface 3 of the semiconductor substrate 11 by a sputtering method, a CVD method, or the like. Note that the insulating layer 18 may have a stacked structure. The well contact 14, the metal layer 15, the through-hole conductor 16, the sub-contact 20, the metal layer 22, and the through-hole conductor 23 of the semiconductor device 1A are embedded in the insulating layer 18.

[0030] As described above, during the operation of the semiconductor device 1A, a well potential V W is supplied to the well region 12. Here, when the device disposed in the device region 10 is a driver for a high-voltage switching device such as a high-side driver, a gate driver, or a half-bridge driver, a high-voltage AC voltage may be applied to the well region 12 as the well potential V W . For example, a pulse voltage with H level / L level being 100V / 0V respectively is supplied to the well region 12.

[0031] When a pulse voltage of this kind is applied to the well region 12, the well region 12 is charged with electric charges. The electric charges charged in the well region 12 move to the semiconductor substrate 11 through the junction capacitance of the pn junction between the semiconductor substrate 11 and the well region 12 during the transition period of the pulse voltage. As a result, a pulse current flows from the well region 12 to the semiconductor substrate 11.

[0032] With reference to FIGS. 3, 4, and 5, the influence of the pulse current flowing from the well region 12 to the semiconductor substrate 11 will be described. FIG. 3 is a plan view of a conventional semiconductor device 100, and FIG. 4 is a diagram showing a longitudinal sectional configuration of the semiconductor device 100. The semiconductor device 100 includes a sub-contact 120 that fixes the potential of the semiconductor substrate 11 to the reference potential V GND As shown in FIG. 3, in the semiconductor device 100, the sub-contact 120 is arranged so as to be interposed between two adjacent device regions 10 among the plurality of device regions 10.

[0033] As shown in FIG. 4, in the semiconductor device 100, among the plurality of well regions 12, the well regions 12A and 12B adjacent to each other form a pn junction with a part 11a of the semiconductor substrate 11 arranged between the well regions 12A and 12B. The region in which these well regions 12A, a part 11a of the semiconductor substrate 11, and the well region 12B are arranged in this order functions as a parasitic element 50 having an npn junction.

[0034] Here, as shown in FIGS. 3 and 4, when the sub-contact 120 is arranged between the adjacent well regions 12A and 12B when viewed from the Z-axis direction, the parasitic element 50 is activated and becomes easy to operate. That is, the current amplification factor (h fe ) of the parasitic element 50 is increased by the sub-contact 120 arranged on a part 11a of the semiconductor substrate 11. For example, when a current flows through the sub-contact 120 due to a surge caused by an external disturbance, the parasitic element 50 is turned on, and as shown in FIG. 4, the pulse current I PUL flows between the well region 12A and the well region 12B through the semiconductor substrate 11.

[0035] When an unintended pulsed current I flows into the well region 12 from the outside, PUL it may cause malfunction or deterioration of characteristics of the devices formed in the well regions 12A and 12B. In some cases, latch-up may occur between adjacent well regions 12, inhibiting the normal operation of the device or even risking damage to the device.

[0036] On the other hand, as shown in FIG. 1, the sub-contact 20 of the semiconductor device 1A is arranged along the outer edge (the first side 6A, the second side 6B, the third side 6C, and the fourth side 6D) of the first main surface 3 so as to surround the plurality of device regions 10. Therefore, in the semiconductor device 1A, even when a large pulsed current I flows from the well region 12 to the semiconductor substrate 11, PUL as shown in FIG. 5, the pulsed current I PUL flows outwardly of the semiconductor substrate 11 and is output to the outside of the semiconductor device 1A through the sub-contact 20 connected to the reference potential V. GND Thus, the flow of the pulsed current I between adjacent well regions 12 is prevented. PUL

[0037] In particular, in the semiconductor device 1A, since no sub-contact is provided between two adjacent device regions 10 among the plurality of device regions 10, the activation of parasitic elements between the two device regions 10 can be suppressed. Therefore, the flow of an unintended pulsed current I into the well region 12 from the outside is prevented, and malfunction or deterioration of characteristics of the device can be suppressed. As a result, the reliability of the semiconductor device 1A can be improved. PUL

[0038] Next, a semiconductor device 1B according to another embodiment will be described. FIG. 6 is a plan view schematically showing the semiconductor device 1B. Hereinafter, differences from the semiconductor device 1A shown in FIG. 1 will be mainly described, and redundant descriptions will be omitted.

[0039] In addition to the sub-contact 20 provided along the outer edge of the first main surface 3, the semiconductor device 1B further includes another sub-contact (internal sub-contact) 30 disposed inside the sub-contact 20. The sub-contact 30 is a conductor made of, for example, tungsten and is disposed on the main surface 3 of the semiconductor substrate 11. The sub-contact 30 is connected to the pad 24 via the metal layer 22 and the through-hole conductor 23. The sub-contact 30 has a function of fixing the potential of the semiconductor substrate 11 to the reference potential V GND .

[0040] When viewed from the Z-axis direction, the sub-contact 30 is disposed so as to be interposed between two adjacent device regions 10 among the plurality of device regions 10. In the embodiment shown in FIG. 6, the sub-contact 30 is disposed between the device region 10 including the well region 12A and the device region 10 including the well region 12B when viewed from the Z-axis direction.

[0041] The sub-contact 30 may be connected to the sub-contact 20 disposed along the outer edge of the first main surface 3 and may surround one or more device regions 10 together with the sub-contact 20. Note that the sub-contact 30 may be integrally formed with the sub-contact 20. In the embodiment shown in FIG. 6, the sub-contact 20 and the sub-contact 30 cooperate to surround the device region 10 including the well region 12A. Note that the sub-contact 30 may be connected to the pad 24 via the sub-contact 20.

[0042] As described above, when the sub-contact 20 and the sub-contact 30 are disposed so as to surround the device region 10, the potential of the semiconductor substrate 11 is fixed to the reference potential V GND around the device region 10. Therefore, noise from peripheral noise sources can be reduced, and the stability of the device can be improved.

[0043] The above-described configuration is particularly effective when protecting a device that is susceptible to noise from noise. Examples of devices that are susceptible to noise include a reference current source circuit, an AD converter, a high-precision analog circuit, and the like. Further, it is also possible to reduce the influence of noise on surrounding devices by arranging the sub-contact 30 so as to surround the device that becomes a noise source. Examples of devices that become noise sources include circuits having a level shift function such as a power transistor, a gate driver for a power transistor, and a half-bridge driver.

[0044] Note that the sub-contact 30 does not necessarily need to be connected to the sub-contact 20. For example, the sub-contact 30 may have an annular planar shape and surround one or more device regions 10. Even in this case, the stability of the devices within the device region 10 surrounded by the sub-contact 30 can be improved.

[0045] FIG. 7 is a plan view schematically showing a semiconductor device 1C according to still another embodiment. Hereinafter, differences from the semiconductor device 1A shown in FIG. 1 will be mainly described, and overlapping descriptions will be omitted.

[0046] As shown in FIG. 7, the sub-contact 20 of the semiconductor device 1C is different from the semiconductor device 1A in that it is not continuously formed along the entire circumference of the outer edge of the first main surface 3 of the semiconductor substrate 11 and partially surrounds a plurality of device regions 10. Partially surrounding a plurality of device regions 10 means that the sub-contact 20 does not surround the entire circumference of the outer edge of the first main surface 3 of the semiconductor substrate 11, but a part of the sub-contact 20 is cut out, and when viewed from the Z-axis direction, the planar shape of the sub-contact 20 is an open loop. More specifically, if the sub-contact 20 is formed along at least three of the first side 6A, the second side 6B, the third side 6C, and the fourth side 6D of the first main surface 3, it can be said that a plurality of device regions 10 are partially surrounded.

[0047] As shown in FIG. 7, the sub-contact 20 of the semiconductor device 1C is provided along the second side 6B, the third side 6C, and the fourth side 6D of the first main surface 3, and partially surrounds the plurality of device regions 10. Also in this semiconductor device 1C, the pulsed current I flowing from the well region 12 to the semiconductor substrate 11 PUL flows toward the outside of the semiconductor substrate 11 and is output to the outside of the semiconductor device 1A through the sub-contact 20 connected to the reference potential V GND . Therefore, the pulsed current I PUL is prevented from flowing between adjacent well regions 12. Therefore, according to the semiconductor device 1C, the stability of the devices formed in the plurality of device regions 10 can be improved.

[0048] FIG. 8 is a plan view schematically showing a semiconductor device 1D according to still another embodiment. Hereinafter, the differences from the semiconductor device 1A shown in FIG. 1 will be mainly described, and overlapping descriptions will be omitted.

[0049] The semiconductor device 1D is different from the semiconductor device 1A in that the width of the sub-contact 20 is partially different. In the embodiment shown in FIG. 8, the widths w1 of the first portion 20A and the third portion 20C of the sub-contact 20 in the X-axis direction (in-plane direction of the first main surface 3) are larger than the widths w2 of the second portion 20B and the fourth portion 20D of the sub-contact 20 in the Y-axis direction (in-plane direction of the first main surface 3). Here, it is assumed that the contacts between the sub-contact 20 and the metal layer 22 are arranged on the first portion 20A and the third portion 20C.

[0050] When the contacts between the sub-contact 20 and the metal layer 22 are disposed on the first portion 20A and the third portion 20C, the current flowing into the second portion 20B and the fourth portion 20D is collected in the first portion 20A and the third portion 20C and flows to the pad 24 through the metal layer 22. By making the widths w1 of the first portion 20A and the third portion 20C, which are closer to the contacts between the sub-contact 20 and the metal layer 22, larger than the widths w2 of the second portion 20B and the fourth portion 20D, which are farther from the contacts, the electrical resistance of the first portion 20A and the third portion 20C decreases, so that fluctuations in the potential of the sub-contact 20 can be reduced. As a result, the operation of the parasitic element 50 can be suppressed.

[0051] In the embodiment shown in FIG. 8, the widths of the first portion 20A and the third portion 20C in the X-axis direction are constant throughout the Y-axis direction, but the widths of a part of the first portion 20A and the third portion 20C may be partially increased.

[0052] Although various exemplary embodiments have been described above, the present disclosure is not limited to the above-described exemplary embodiments, and various omissions, substitutions, and changes may be made. Also, elements in different embodiments can be combined to form other embodiments. Further, from the above description, it will be understood that various embodiments of the present disclosure are described herein for purposes of illustration, and various changes can be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

[0053] In the above-described embodiment, the first conductivity type is described as p-type and the second conductivity type is described as n-type, but these conductivity types can be substituted for each other.

[0054] The present disclosure includes the following content.

[0055] [A1] A semiconductor substrate 11 of a first conductivity type having a main surface 3, A plurality of device regions 10 that are arranged on the semiconductor substrate 11 so as to be spaced apart from each other and each include a semiconductor region 12 of a second conductivity type; A conductive external sub-contact 20 that is provided on the main surface 3 of the semiconductor substrate 11 and fixes the semiconductor substrate 11 to a reference potential V GND ; and A semiconductor device, wherein, in a plan view, the external sub-contact 20 is arranged along an outer edge of the main surface 3 of the semiconductor substrate 11 so as to at least partially surround the plurality of device regions 10.

[0056] [A2] The semiconductor device according to A1, wherein the external sub-contact 20 is continuously formed over the entire circumference of the outer edge of the main surface 3 of the semiconductor substrate 11.

[0057] [A3] The semiconductor device according to A1 or A2, further comprising a conductive internal sub-contact 30 that is arranged inside the external sub-contact 20 and intervenes between at least two of the plurality of device regions 10 in a plan view.

[0058] [A4] The semiconductor device according to A3, wherein the internal sub-contact 30 is connected to the external sub-contact 20.

[0059] [A5] The semiconductor device according to any one of A1 to A4, further comprising a metal layer 22 connected to the external sub-contact 20 and a ground pad 24 that connects the external sub-contact 20 to the reference potential V through the metal layer 22. GND ; and

[0060] [A6] The external sub-contact 20 includes a first portion 20A and a second portion 20B that is arranged farther from a contact point between the external sub-contact 20 and the metal layer 22 than the first portion 20A. The semiconductor device according to A5, wherein a width w1 of the first portion 20A in the in-plane direction of the main surface 3 is larger than a width w2 of the second portion in the in-plane direction.

[0061] [A7] Another sub-contact for fixing the semiconductor substrate 11 to the reference potential V GND is not included inside the external sub-contact 20, the semiconductor device according to any one of A1 to A6.

[0062] [A8] The semiconductor device according to any one of A1 to A6, wherein the external sub-contact 20 is made of a conductive material containing tungsten.

Explanation of reference numerals

[0063] 1A, 1B, 1C, 1D... semiconductor device, 2... chip, 3... first main surface, 4... second main surface, 5A... first side surface, 5B... second side surface, 5C... third side surface, 5D... fourth side surface, 6A... first side, 6B... second side, 6C... third side, 6D... fourth side, 10... device region, 11... semiconductor substrate, 12, 12A, 12B... well region, 13... well contact region, 14... well contact, 15... metal layer, 16... through hole conductor, 17... pad, 18... insulating layer, 20... sub-contact (external sub-contact), 20A... first portion, 20B... second portion, 20C... third portion, 20D... fourth portion, 21... sub-contact region, 22... metal layer, 23... through hole conductor, 24... pad (ground pad), 30... sub-contact (internal sub-contact), 50... parasitic element, I PUL ... pulse current, V GND ... reference potential, V W ... well potential.

Claims

1. A first-conductivity-type semiconductor substrate having a main surface, a plurality of device regions that are spaced apart from each other on the semiconductor substrate and each include a second-conductivity-type semiconductor region, a conductive external sub-contact provided on the main surface of the semiconductor substrate and fixing the semiconductor substrate to a reference potential, comprising: A semiconductor device, wherein in a plan view, the external sub-contact is arranged along an outer edge of the main surface of the semiconductor substrate so as to at least partially surround the plurality of device regions.

2. The semiconductor device according to claim 1, wherein the external sub-contact is continuously formed over the entire circumference of the outer edge of the main surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, further comprising a conductive internal sub-contact that is arranged inside the external sub-contact and intervenes between at least two of the plurality of device regions in a plan view.

4. The semiconductor device according to claim 3, wherein the internal sub-contact is connected to the external sub-contact.

5. a metal layer connected to the external sub-contact, a ground pad connecting the external sub-contact to the reference potential via the metal layer, The semiconductor device according to claim 1, further comprising:

6. The external sub-contact includes a first portion and a second portion that is spaced apart from the first portion with respect to a contact point between the external sub-contact and the metal layer, The semiconductor device according to claim 5, wherein a width of the first portion in the in-plane direction of the main surface is larger than a width of the second portion in the in-plane direction.

7. The semiconductor device according to claim 1, wherein the external sub-contact does not include other sub-contacts that fix the semiconductor substrate to the reference potential inside.

8. The semiconductor device according to claim 1, wherein the external sub-contact is formed of a conductive material containing tungsten.

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