Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing a decrease in a withstand voltage.SOLUTION: A semiconductor device 100 includes a support having a first surface, and an element portion including a first conductive portion 51 to a fourth conductive portion 54 on the first surface, and a semiconductor layer 30. The direction from the first surface to the first conductive portion 51 is along the Z direction. The second conductive portion 52 is separated from the first conductive portion in the Y direction. The semiconductor layer is located between the first conductive portion and the second conductive portion. The semiconductor layer includes a facing region 38 and a first semiconductor region 31. The third conductive portion 53 is separated from a part of the second conductive portion and the facing region in the X direction. The fourth conductive portion 54 is separated from the first semiconductor region in the X direction. The first semiconductor region includes a first upper end region, a first lower end region, and a first intermediate region in the Z direction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device.

Background Art

[0002] In a semiconductor device, it is desired to suppress a decrease in breakdown voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of suppressing a decrease in breakdown voltage.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a semiconductor device includes a support having a first surface, a first conductive portion, a second conductive portion, a semiconductor layer, a third conductive portion, and a fourth conductive portion. The direction from the first surface toward the first conductive portion is along a first direction perpendicular to the first surface. The second conductive portion is separated from the first conductive portion in a second direction along the first surface. The semiconductor layer is located between the first conductive portion and the second conductive portion. The semiconductor layer has a first end face and a second end face located between the first end face and the support. The semiconductor layer includes a facing region and a first semiconductor region of a first conductivity type. The facing region is located between the second conductive portion and the first semiconductor region and faces a part of the second conductive portion. The third conductive portion is separated from a part of the second conductive portion and the facing region in a third direction that intersects the second direction and is along the first surface. The fourth conductive portion is separated from the first semiconductor region in the third direction. The first semiconductor region includes a first upper region including a part of the first end face, a first lower region including a part of the second end face, and a first intermediate region located between the first upper region and the first lower region. The concentration of impurities of the first conductivity type in the first upper region is higher than the concentration of impurities of the first conductivity type in the first intermediate region. The concentration of impurities of the first conductivity type in the first lower region is higher than the concentration of impurities of the first conductivity type in the first intermediate region.

Brief Description of the Drawings

[0006]

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same elements as those described above with respect to the previously shown figures are denoted by the same reference numerals, and the detailed description will be omitted as appropriate.

[0008] FIG. 1 is a schematic perspective view illustrating the semiconductor device according to the embodiment. FIG. 2 is a schematic plan view illustrating the semiconductor device according to the embodiment. FIG. 2 shows the state of FIG. 1 as viewed from above. FIGS. 3 and 4 are schematic cross-sectional views illustrating the semiconductor device according to the embodiment. FIG. 3 represents the cross-section along the line A1 - A2 shown in FIG. 2. FIG. 4 represents the cross-section along the line A3 - A4 shown in FIG. 2.

[0009] As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a support 10, a semiconductor layer 30, a first conductive portion 51, a second conductive portion 52, a third conductive portion 53, and a fourth conductive portion 54. The semiconductor device 100 further includes an insulating portion 70, a first conductive layer 61, a first insulating layer 21 (see FIG. 3), and a second insulating layer 22. In FIGS. 1 and 2, for convenience, the illustration of the first insulating layer 21 is omitted.

[0010] As shown in FIG. 1, the support 10 has a first surface 10a. An element portion including the semiconductor layer 30, the first to fourth conductive portions (51 to 54), the first conductive layer 61, the first insulating layer 21, and the second insulating layer 22 is provided on the first surface 10a and supported by the support 10. The support 10 is, for example, a substrate.

[0011] In the description of the embodiment, the direction perpendicular to the first surface 10a is defined as the Z direction (first direction). One direction along the first surface 10a is defined as the X direction. A direction along the first surface 10a and intersecting the X direction is defined as the Y direction. The X direction (third direction) and the Y direction (second direction) may each be a direction perpendicular to the Z direction. The X direction (third direction) and the Y direction (second direction) may be perpendicular to each other. The direction perpendicular to the first surface 10a and from the support 10 toward the semiconductor layer 30 may be referred to as "up", and the opposite direction may be referred to as "down". "Up" and "down" are independent of the direction of gravity based on the relative positional relationship between the support 10 and the semiconductor layer 30.

[0012] The first conductive portion 51, the second conductive portion 52, and the semiconductor layer 30 are provided above the first surface 10a. That is, the directions from the first surface 10a toward the first conductive portion 51, from the first surface 10a toward the second conductive portion 52, and from the first surface 10a toward the semiconductor layer 30 each follow the Z direction.

[0013] The second conductive portion 52 is separated from the first conductive portion 51 in the Y direction. That is, the direction from the first conductive portion 51 toward the second conductive portion 52 follows the Y direction.

[0014] The semiconductor layer 30 is positioned between the first conductive portion 51 and the second conductive portion 52. That is, the first conductive portion 51, the semiconductor layer 30, and the second conductive portion 52 are arranged in the Y direction. The semiconductor layer 30 is in contact with each of the first conductive portion 51 and the second conductive portion 52 and is electrically connected to each of the first conductive portion 51 and the second conductive portion 52. The semiconductor layer 30 has a first end face 30t (upper face) and a second end face 30u (lower face). The second end face 30u is positioned between the first end face 30t and the support 10.

[0015] For example, as shown in FIG. 2, the semiconductor layer 30 includes a facing region 38 that faces a part 52a of the second conductive portion 52. The facing region 38 includes a facing surface F1 that faces a part 52a of the second conductive portion 52. In this example, the facing region 38 has a first conductivity type (n-type), and the facing region 38 and the second conductive portion 52 (part 52a) are in Schottky contact. For example, the facing surface F1 and a part 52a of the second conductive portion 52 form a Schottky junction.

[0016] Furthermore, as shown in FIG. 2, the semiconductor layer 30 includes a first semiconductor region 31, a second semiconductor region 32, and a third semiconductor region 33. The first semiconductor region 31, the second semiconductor region 32, and the third semiconductor region 33 each have a first conductivity type.

[0017] The first semiconductor region 31 is positioned between the first conductive portion 51 and the second conductive portion 52. The facing region 38 is positioned between the first semiconductor region 31 and the second conductive portion 52 (part 52a). The direction from the first semiconductor region 31 to the facing region 38 is along the Y direction. The first semiconductor region 31 is continuous with the facing region 38.

[0018] The second semiconductor region 32 is positioned between the first conductive portion 51 and the fourth conductive portion 54 in the Y direction. The second semiconductor region 32 is electrically connected to the first conductive portion 51. A part of the insulating portion 70 (insulating region 73) is provided between the second semiconductor region 32 and the fourth conductive portion 54. The second semiconductor region 32 is separated from the third conductive portion 53 and the fourth conductive portion 54 in the Y direction. The direction from the second semiconductor region 32 to the fourth conductive portion 54 (or the insulating region 73) is along the Y direction.

[0019] The third semiconductor region 33 is located between the first conductive portion 51 and the first semiconductor region 31 in the Y direction. The third semiconductor region 33 is electrically connected to the first conductive portion 51. The third semiconductor region 33 is aligned with the first semiconductor region 31 in the Y direction and is aligned with the second semiconductor region 32 in the X direction. That is, the direction from the third semiconductor region 33 to the first semiconductor region 31 is along the Y direction, and the direction from the third semiconductor region 33 to the second semiconductor region 32 is along the X direction. The third semiconductor region 33 is continuous from the first semiconductor region 31 and the second semiconductor region 32.

[0020] The third conductive portion 53 is separated from a part 52a of the second conductive portion 52 and the opposing region 38 in the X direction. The direction from the opposing region 38 (opposing surface F1) to the third conductive portion 53 is along the X direction.

[0021] The fourth conductive portion 54 is separated from the first semiconductor region 31 in the X direction. That is, the direction from the first semiconductor region 31 to the fourth conductive portion 54 is along the X direction. For example, the fourth conductive portion 54 is located between the third conductive portion 53 and the first conductive portion 51 in the Y direction.

[0022] For example, an insulating portion 70 is provided in a trench formed in the semiconductor layer 30, and a third conductive portion 53 and a fourth conductive portion 54 are provided in the insulating portion 70. The insulating portion 70 insulates between the third conductive portion 53 and the semiconductor layer 30, between the fourth conductive portion 54 and the semiconductor layer 30, and between the third conductive portion 53 and the fourth conductive portion 54. More specifically, the insulating portion 70 includes a first insulating region 71 provided between the third conductive portion 53 and the opposing region 38, and a second insulating region 72 provided between the fourth conductive portion 54 and the first semiconductor region 31. Further, the insulating portion 70 includes an insulating region 73 provided between the fourth conductive portion 54 and the second semiconductor region 32, and an insulating region 74 provided between the third conductive portion 53 and the fourth conductive portion 54. The first insulating region 71 is in contact with each of the third conductive portion 53 and the opposing region 38. The second insulating region 72 is in contact with each of the fourth conductive portion 54 and the first semiconductor region 31. The insulating region 73 is in contact with each of the fourth conductive portion 54 and the second semiconductor region 32. The insulating region 74 is in contact with each of the third conductive portion 53 and the fourth conductive portion 54.

[0023] For the support 10, for example, a silicon substrate can be used. The semiconductor layer 30 includes, for example, at least one selected from the group consisting of silicon (Si), nitride semiconductors (e.g., GaN, etc.), silicon carbide (SiC), and oxide semiconductors (e.g., GaO). When the first semiconductor region 11 contains silicon, the impurity of the first conductivity type includes, for example, at least one selected from the group consisting of phosphorus, arsenic, and antimony. The first conductive portion 51 includes, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt. The second conductive portion 52 includes, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt. When the opposing region 38 contains silicon, a part 52a of the second conductive portion 52 may include at least one selected from the group consisting of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf. The first conductive layer 61 contains, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt. The third conductive portion 53 and the fourth conductive portion 54 contain, for example, at least one of polysilicon and metal. The first insulating layer 21 and the second insulating layer 22 are, for example, silicon oxide layers (e.g., thermal oxide films). The insulating portion 70 contains, for example, silicon oxide.

[0024] For example, by controlling the potential of the third conductive portion 53, the current flowing between the first conductive portion 51 and the second conductive portion 52 is controlled. The first conductive portion 51 functions as, for example, a drain electrode. The second conductive portion 52 functions as, for example, a source electrode. The third conductive portion 53 functions as, for example, a gate electrode. The first insulating region 71 functions as, for example, a gate insulating film. The semiconductor device 100 is, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0025] In the semiconductor device 100, a Schottky barrier is formed at the interface between the opposing region 38 and the second conductive portion 52. The thickness of the Schottky barrier (e.g., the distance in the Y-axis direction) can be controlled by the potential of the third conductive portion 53. When the Schottky barrier is thick, current does not substantially flow. Thereby, an off state is obtained. By controlling the potential of the third conductive portion 53, the Schottky barrier becomes thinner and current (e.g., tunneling current) flows. When current flows, an on state is obtained.

[0026] For example, in the on state of the transistor, a positive voltage is applied to the first conductive portion 51 with respect to the second conductive portion 52, and carriers (electrons) flow from the second conductive portion 52 to the first conductive portion 51 through the opposing region 38, the first semiconductor region 31, the third semiconductor region 33 (and the second semiconductor region 32).

[0027] In this example, the third conductive portion 53 may face the interface (for example, the facing surface F1) between the facing region 38 and the second conductive portion 52. For this reason, for example, compared with a transistor in a reference example in which a gate electrode faces an npn structure, the gate length is short. As a result, the total gate charge amount (Qg) is small. The gate capacitance is small. As a result, high-speed switching can be obtained. The loss is small. For example, the gate capacitance (Cg) and the gate-drain capacitance (Cgd) become small. As a result, the total gate charge amount (Qg) and the gate-drain charge amount (Qgd) are reduced. As a result, the loss of the gate driver can be reduced. For example, the switching speed can be increased. For example, the turn-on loss and the turn-off loss can be suppressed.

[0028] Also, for example, the region including the facing region 38 and the second conductive portion 52 (the region including the Schottky contact) becomes a body diode. Since the body diode is a Schottky barrier diode, the recovery can be accelerated.

[0029] For example, the fourth conductive portion 54 is electrically connected to the second conductive portion 52. Alternatively, the fourth conductive portion 54 may be capable of being electrically connected to the second conductive portion 52. For example, the semiconductor device 100 may have a wiring 54L that electrically connects the fourth conductive portion 54 and the second conductive portion 52. The fourth conductive portion 54 and the second conductive portion 52 may be electrically connected via an external wiring or terminal of the semiconductor device 100.

[0030] The potential of the fourth conductive portion 54 is set to the potential of the second conductive portion 52 (for example, the source potential). By providing the fourth conductive portion 54, the electric field in the semiconductor layer 30 can be controlled. For example, the concentration of the local electric field can be suppressed. For example, high reliability can be easily obtained. The fourth conductive portion 54 functions as, for example, a field plate.

[0031] In one example, the semiconductor device 100 can be formed by bonding two substrates (substrate S1 and substrate S2) shown in FIG. 1. Substrate S1 is a substrate having a first conductive layer 61 and a second insulating layer 22 laminated on a support 10. Substrate S2 is a substrate having an insulating portion 70 and first to fourth conductive portions (51 to 54) formed in a semiconductor layer 30. Substrate S1 and substrate S2 are laminated such that the upper surface of substrate S1 (upper surface 22a of the second insulating layer 22) and the lower surface of substrate S2 (second end surface 30u) face each other. The Z direction may be a direction perpendicular to the upper surface of substrate S1.

[0032] As shown in FIG. 3, a first conductive portion 51 extends along the Z direction on the first conductive layer 61. A second conductive portion 52 extends along the Z direction on the upper surface 22a of the second insulating layer 22. Also, as shown in FIG. 4, a third conductive portion 53 extends along the Z direction on the upper surface 22a of the second insulating layer 22. With such a configuration, transistors can be provided at a high density on the support 10 (for example, a substrate). The channel area per unit area can be increased. Thereby, for example, the on-resistance can be reduced. A large current can be switched.

[0033] In the embodiment, a high-concentration impurity layer (a high-concentration n-type layer in this example) having a high concentration of first-conductive-type impurities is provided on the upper surface side and the lower surface side of the semiconductor layer 30. More specifically, it is as follows.

[0034] As shown in FIG. 3, the first semiconductor region 31 includes a first lower end region 31u, a first intermediate region 31c, and a first upper end region 31t. The upper surface of the first upper end region 31t is a part of the first end surface 30t (upper surface) of the semiconductor layer 30. The lower surface of the first lower end region 31u is a part of the second end surface 30u (lower surface) of the semiconductor layer 30. The first intermediate region 31c is a region between the first upper end region 31t and the first lower end region 31u. The first intermediate region 31c is a region from the first upper end region 31t to the first lower end region 31u in the Z direction. The concentration of the first-conductive-type impurities (atoms / cm 3 ) in the first upper end region 31t is the concentration of the first-conductive-type impurities (atoms / cm3 ) is higher. The concentration of the impurity of the first conductivity type in the first lower end region 31u (atoms / cm 3 ) is higher than the concentration of the impurity of the first conductivity type in the first intermediate region 31c.

[0035] As shown in FIG. 3, the third semiconductor region 33 includes a third lower end region 33u, a third intermediate region 33c, and a third upper end region 33t. The upper surface of the third upper end region 33t is a part of the first end surface 30t (upper surface) of the semiconductor layer 30. The lower surface of the third lower end region 33u is a part of the second end surface 30u (lower surface) of the semiconductor layer 30. The third intermediate region 33c is a region between the third upper end region 33t and the third lower end region 33u. The third intermediate region 33c is a region from the third upper end region 33t to the third lower end region 33u in the Z direction. The concentration of the impurity of the first conductivity type in the third upper end region 33t (atoms / cm 3 ) is higher than the concentration of the impurity of the first conductivity type in the third intermediate region 33c (atoms / cm 3 ). The concentration of the impurity of the first conductivity type in the third lower end region 33u (atoms / cm 3 ) is higher than the concentration of the impurity of the first conductivity type in the third intermediate region 33c.

[0036] As shown in FIG. 4, the second semiconductor region 32 includes a second lower end region 32u, a second intermediate region 32c, and a second upper end region 32t. The upper surface of the second upper end region 32t is a part of the first end surface 30t (upper surface) of the semiconductor layer 30. The lower surface of the second lower end region 32u is a part of the second end surface 30u (lower surface) of the semiconductor layer 30. The second intermediate region 32c is a region between the second upper end region 32t and the second lower end region 32u. The second intermediate region 32c is a region from the second upper end region 32t to the second lower end region 32u in the Z direction. The concentration of the impurity of the first conductivity type in the second upper end region 32t (atoms / cm 3 ) is higher than the concentration of the impurity of the first conductivity type in the second intermediate region 32c (atoms / cm 3 ). The concentration of the impurity of the first conductivity type in the second lower end region 32u (atoms / cm 3 ) is higher than the concentration of the impurity of the first conductivity type in the second intermediate region 32c.

[0037] The first upper region 31t, the second upper region 32t, and the third upper region 33t are continuous and are provided as one high-concentration impurity layer. The impurity concentration of the first conductivity type in the high-concentration impurity layer is higher than the impurity concentration of the first conductivity type in the first intermediate region 31c. The concentration of the impurity of the first conductivity type in the first upper region 31t may be substantially the same as the concentration of the impurity of the first conductivity type in the second upper region 32t, and may also be substantially the same as the concentration of the impurity of the first conductivity type in the third upper region 33t. The thickness (length along the Z direction) of the first upper region 31t may be substantially the same as the thickness of the second upper region 32t, and may also be substantially the same as the thickness of the third upper region 33t.

[0038] Similarly, the first lower region 31u, the second lower region 32u, and the third lower region 33u are continuous and are provided as one high-concentration impurity layer. The concentration of the impurity of the first conductivity type in the first lower region 31u may be substantially the same as the concentration of the impurity of the first conductivity type in the second lower region 32u, and may also be substantially the same as the concentration of the impurity of the first conductivity type in the third lower region 33u. The thickness of the first lower region 31u may be substantially the same as the thickness of the second lower region 32u, and may also be substantially the same as the thickness of the third lower region 33u.

[0039] The first intermediate region 31c, the second intermediate region 32c, and the third intermediate region 33c are continuous and are provided as one low-concentration impurity layer. The concentration of the impurity of the first conductivity type in the first intermediate region 31c may be substantially the same as the concentration of the impurity of the first conductivity type in the second intermediate region 32c, and may also be substantially the same as the concentration of the impurity of the first conductivity type in the third intermediate region 33c. The thickness of the first intermediate region 31c may be substantially the same as the thickness of the second intermediate region 32c, and may also be substantially the same as the thickness of the third intermediate region 33c.

[0040] As described above, in this example, the opposing region 38 is of the first conductivity type. As shown in FIG. 3, the opposing region 38 includes, for example, a lower opposing region 38u, an intermediate opposing region 38c, and an upper opposing region 38t. The upper opposing region 38t includes a part of the first end face 30t (upper face) of the semiconductor layer 30. The first end face 30t is formed by the upper opposing region 38t, the first upper end region 31t, the second upper end region 32t, and the third upper end region 33t. The lower opposing region 38u includes a part of the second end face 30u (lower face) of the semiconductor layer 30. The second end face 30u is formed by the lower opposing region 38u, the first lower end region 31u, the second lower end region 32u, and the third lower end region 33u. The intermediate opposing region 38c is between the upper opposing region 38t and the lower opposing region 38u.

[0041] For example, the concentration of the impurity of the first conductivity type in the upper opposing region 38t (atoms / cm 3 ) may be higher than the concentration of the impurity of the first conductivity type in the intermediate opposing region 38c (atoms / cm 3 ). The upper opposing region 38t may be a part of a high-concentration impurity layer including the first upper end region 31t. That is, a high-concentration impurity layer may be formed over the entire upper end side of the semiconductor layer 30. Not limited to this, the concentration of the impurity of the first conductivity type in the upper opposing region 38t may be equal to the concentration of the impurity of the first conductivity type in the intermediate opposing region 38c. That is, on the upper end side of the semiconductor layer 30, the high-concentration impurity layer may be formed over the entire semiconductor layer 30 excluding the opposing region 38.

[0042] The concentration of the impurity of the first conductivity type in the lower opposing region 38u (atoms / cm 3 ) may be higher than the concentration of the impurity of the first conductivity type in the intermediate opposing region 38c (atoms / cm 3 ). The lower opposing region 38u may be a part of a high-concentration impurity layer including the first lower end region 31u. That is, a high-concentration impurity layer may be formed over the entire lower end side of the semiconductor layer 30. Not limited to this, the concentration of the impurity of the first conductivity type in the lower facing region 38u may be equal to the concentration of the impurity of the first conductivity type in the intermediate facing region 38c. That is, on the lower end side of the semiconductor layer 30, the high-concentration impurity layer may be formed over the entire semiconductor layer 30 excluding the facing region 38. When the high-concentration impurity layer is formed excluding the facing region 38, for example, the influence on the threshold voltage of the transistor due to the high-concentration impurity layer can be suppressed.

[0043] FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. FIG. 5 corresponds to a part of the cross-section along the line A5 - A6 shown in FIG. 2. For example, when the impurity concentration of the first conductivity type of the entire semiconductor layer 30 is increased, the on-resistance is reduced, but the breakdown voltage may decrease. Here, in a structure having a field plate, for example, charge balance in the semiconductor layer 30 is achieved so that concentration of the electric field is easily suppressed. The spread of the depletion layer changes according to the impurity concentration of the semiconductor layer 30 (for example, the first semiconductor region 31), and the electric field distribution is adjusted. For example, concentration of the electric field is suppressed by the balance between the impurity concentration and the electric field.

[0044] On the other hand, for example, as shown in FIG. 5, a capacitor C1 is formed between the upper end 54f (upper surface) of the fourth conductive portion 54 and the upper surface 31f of the first semiconductor region 31 (a part of the first end face 30t). Therefore, the upper end side of the first semiconductor region 31 is likely to be depleted, and the charge balance may be disrupted. There is a risk that the electric field is concentrated and the breakdown voltage decreases. Similarly, a capacitor C2 is formed between the lower end 54g (lower surface) of the fourth conductive portion 54 and the lower surface 31g of the first semiconductor region 31 (a part of the second end face 30u). Therefore, the lower end side of the first semiconductor region 31 is likely to be depleted, and the charge balance may be disrupted. There is a risk that the electric field is concentrated and the breakdown voltage decreases.

[0045] In contrast, in the embodiment, as described above, the concentration of the impurity of the first conductivity type in the first upper end region 31t is higher than the concentration of the impurity of the first conductivity type in the first intermediate region 31c. The concentration of the impurity of the first conductivity type in the first lower end region 31u is higher than the concentration of the impurity of the first conductivity type in the first intermediate region 31c. Thereby, depletion in the first upper end region 31t and the first lower end region 31u can be suppressed. A decrease in breakdown voltage can be suppressed. Further, for example, since the concentration of the impurity of the first conductivity type is high, the on-resistance can be reduced. According to the embodiment, for example, the on-resistance can be reduced without impairing the breakdown voltage.

[0046] Also, for example, as already described, the concentration of the impurity of the first conductivity type in the second upper end region 32t may be higher than the concentration of the impurity of the first conductivity type in the second intermediate region 32c, and the concentration of the impurity of the first conductivity type in the second lower end region 32u may be higher than the concentration of the impurity of the first conductivity type in the second intermediate region 32c. The concentration of the impurity of the first conductivity type in the third upper end region 33t may be higher than the concentration of the impurity of the first conductivity type in the third intermediate region 33c, and the concentration of the impurity of the first conductivity type in the third lower end region 33u may be higher than the concentration of the impurity of the first conductivity type in the third intermediate region 33c. Thereby, a decrease in breakdown voltage can be further suppressed.

[0047] As shown in FIG. 5, a semiconductor layer 30 (the first upper end region 31t and the first lower end region 31u) is located between the first insulating layer 21 and the second insulating layer 22. The first upper end region 31t is between the first lower end region 31u and the first insulating layer 21.

[0048] For example, the first insulating layer 21 is in contact with the first end face 30t of the semiconductor layer 30. The first insulating layer 21 is in contact with the upper surface 31f of the first semiconductor region 31 (and the upper surfaces of the second semiconductor region 32 and the third semiconductor region 33). Also, the first insulating layer 21 is in contact with the upper end 54f of the fourth conductive portion 54 (one end of the fourth conductive portion 54 in the Z direction). Further, as shown in FIG. 4, the first insulating layer 21 is in contact with the upper end 53f (upper surface) of the third conductive portion 53 and the upper end 70f (upper surface) of the insulating portion 70. The first end face 30t, the upper end 54f, the upper end 53f, and the upper end 70f may be on the same plane.

[0049] As shown in FIG. 5, the second insulating layer 22 is in contact with the second end face 30u of the semiconductor layer 30. The second insulating layer 22 is in contact with the lower surface 31g of the first semiconductor region 31 (and the lower surfaces of the second semiconductor region 32 and the third semiconductor region 33). The second insulating layer 22 is in contact with the lower end 54g of the fourth conductive portion 54 (the other end of the fourth conductive portion 54 in the Z direction). Also, as shown in FIG. 4, the second insulating layer 22 is in contact with the lower end 53g (lower surface) of the third conductive portion 53 and the lower end 70g (lower surface) of the insulating portion 70. The second end face 30u, the lower end 54g, the lower end 53g, and the lower end 70g may be on the same plane.

[0050] For example, the thickness (length along the Z direction) of the first insulating layer 21 is 250 nanometers (nm) or more and 1250 nm or less. For example, the thickness (length along the Z direction) of the second insulating layer 22 is 250 nm or more and 1250 nm or less.

[0051] The upper end side of the semiconductor layer 30 may be easily depleted by the first insulating layer 21. The lower end side of the semiconductor layer 30 may be easily depleted by the second insulating layer 22. Even in such cases, by providing high-concentration impurity layers on the upper end side and the lower end side of the semiconductor layer 30, it is easy to suppress the depletion of the upper end side and the lower end side of the semiconductor layer 30. Thereby, for example, a decrease in breakdown voltage can be suppressed.

[0052] The first conductive layer 61 is electrically connected to the first conductive portion 51 (see FIG. 3). For example, in the on state of the transistor, carriers flow from the second conductive portion 52 to the first conductive layer 61 through the semiconductor layer 30 and the first conductive portion 51.

[0053] In this example, the first conductive layer 61 is connected below the first conductive portion 51. The first conductive layer 61 extends along the X-Y plane below the semiconductor layer 30 (and the third conductive portion 53, the fourth conductive portion 54, and the insulating portion 70). A second insulating layer 22 is disposed between the first conductive layer 61 and the semiconductor layer 30 (and the third conductive portion 53, the fourth conductive portion 54, and the insulating portion 70). The first conductive layer 61 is in contact with the second insulating layer 22.

[0054] Thus, the first conductive layer 61 is below the semiconductor layer 30 and the second insulating layer 22. That is, the first lower end region 31u is between the first upper end region 31t and the first conductive layer 61. In other words, the second end face 30u is between the first end face 30t and the first conductive layer 61. Not limited to this, in the embodiment, the first conductive layer 61 (drain) may be provided above the semiconductor layer 30 and the first insulating layer 21. That is, the first upper end region 31t may be between the first lower end region 31u and the first conductive layer 61.

[0055] The concentration of the impurity of the first conductivity type in one of the first upper region 31t and the first lower region 31u may be higher than the concentration of the impurity of the first conductivity type in the other of the first upper region 31t and the first lower region 31u. Thereby, depletion in the said one of the first upper region 31t and the first lower region 31u can be further suppressed. For example, the first conductive layer 61 (drain) is disposed on the other side of the first upper region 31t and the first lower region 31u. In other words, the said other of the first upper region 31t and the first lower region 31u is between the said one of the first upper region 31t and the first lower region 31u and the first conductive layer 61. Here, when the semiconductor device 100 operates, voltages different from that of the second conductive portion 52 are applied to the first conductive portion 51 and the first conductive layer 61. Therefore, the end portion on the side opposite to the first conductive layer 61 of the semiconductor layer 30 (the said one of the first upper region 31t and the first lower region 31u) may be more likely to be depleted than the end portion on the first conductive layer 61 side of the semiconductor layer 30 (the said other of the first upper region 31t and the first lower region 31u).

[0056] On the contrary, for example, the concentration of the impurity of the first conductivity type in the end portion on the side opposite to the first conductive layer 61 of the semiconductor layer 30 (the said one of the first upper region 31t and the first lower region 31u) is higher than the concentration of the impurity of the first conductivity type in the end portion on the first conductive layer 61 side of the semiconductor layer 30 (the said other of the first upper region 31t and the first lower region 31u). Thereby, for example, depletion in the end portion on the side opposite to the first conductive layer 61 of the semiconductor layer 30 can be further suppressed. However, in the embodiment, the concentration of the impurity of the first conductivity type in the end portion on the first conductive layer 61 side of the semiconductor layer 30 may be higher than the concentration of the impurity of the first conductivity type in the end portion on the side opposite to the first conductive layer 61 of the semiconductor layer 30.

[0057] For example, when the first insulating layer 21 is thick, the upper end side (the first upper region 31t) of the semiconductor layer 30 may be likely to be depleted. For example, when the second insulating layer 22 is thick, the lower end side (the first lower region 31u) of the semiconductor layer 30 may be likely to be depleted.

[0058] The thickness of one of the first insulating layer 21 and the second insulating layer 22 may be thinner than that of the other of the first insulating layer 21 and the second insulating layer 22. Thereby, for example, on the side of the one of the first insulating layer 21 and the second insulating layer 22, depletion of the semiconductor layer 30 can be more suppressed. For example, the first conductive layer 61 (drain) is disposed on the other side of the first insulating layer and the second insulating layer. In other words, the other of the first insulating layer 21 and the second insulating layer 22 is located between the one of the first insulating layer 21 and the second insulating layer 22 and the first conductive layer 61. Here, as described above, the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61 may be relatively easily depleted.

[0059] Therefore, for example, the insulating layer on the side opposite to the first conductive layer 61 (the one of the first insulating layer 21 and the second insulating layer 22) may be thinner than the insulating layer on the first conductive layer 61 side (the other of the first insulating layer 21 and the second insulating layer 22). That is, in the example of FIG. 5, the thickness of the first insulating layer 21 may be thinner than the thickness of the second insulating layer 22. Thereby, for example, depletion at the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61 can be more suppressed. However, in the embodiment, the insulating layer on the first conductive layer 61 side may be thinner than the insulating layer on the side opposite to the first conductive layer 61.

[0060] FIG. 6 is a schematic diagram showing the impurity concentration in the semiconductor device according to the embodiment. FIG. 6 is a schematic graph showing an example of the distribution of the concentration of the first conductive type impurities along the Z direction of the semiconductor layer 30. The vertical axis represents the concentration Cn1 of the first conductive type impurities in the first semiconductor region 31. The horizontal axis represents the position pZ in the Z direction.

[0061] The thickness T1 (length along the Z direction) of the first upper region 31t is, for example, 100 nm or more and 1000 nm or less, and is, for example, 500 nm. The thickness T2 (length along the Z direction) of the first lower region 31u is, for example, 100 nm or more and 1000 nm or less, and is, for example, 500 nm. The thickness T3 of the first intermediate region 31c (that is, the distance along the Z direction between the first upper region 31t and the first lower region 31u) is, for example, 3000 nm or more and 60000 nm or less. The thickness T1 is thinner than the thickness T3. The thickness T2 is thinner than the thickness T3. Thereby, for example, the on-resistance can be reduced without impairing the withstand voltage.

[0062] The impurity concentration of the first conductivity type in the first upper region 31t may be different from the impurity concentration of the first conductivity type in the first lower region 31u. The concentration distribution of the impurity of the first conductivity type along the Z direction in the first upper region 31t has a maximum concentration C31t (for example, peak concentration). The concentration distribution of the impurity of the first conductivity type along the Z direction in the first lower region 31u has a maximum concentration C31u (for example, peak concentration). The maximum concentration C31t may be different from the maximum concentration C31u.

[0063] As described above, in this example, the first conductive layer 61 is disposed below the first lower region 31u. And the impurity concentration of the first conductivity type is higher in the first upper region 31t than in the first lower region 31u. For example, in the concentration distribution of the impurity of the first conductivity type along the Z direction, the maximum concentration C31t in the first upper region 31t is higher than the maximum concentration C31u in the first lower region 31u.

[0064] Not limited to this, the impurity concentration of the first conductivity type in the first upper region 31t may be equal to the impurity concentration of the first conductivity type in the first lower region 31u, or may be lower than the impurity concentration of the first conductivity type in the first lower region 31u. For example, the maximum concentration C31t may be lower than the maximum concentration C31u.

[0065] For example, the amount of impurities of the first conductivity type contained in the first upper region 31t (total amount of impurities (number of atoms)) is larger than the amount of impurities of the first conductivity type contained in the first intermediate region 31c. For example, the amount of impurities of the first conductivity type per unit area (atoms / cm 2 ) in the first upper region 31t is larger than the amount of impurities of the first conductivity type per unit area in the first intermediate region 31c. Here, "per unit area" refers to per unit area in a plane perpendicular to the Z direction. For example, the difference between the amount of impurities of the first conductivity type contained in the first upper region 31t and the amount of impurities of the first conductivity type contained in the first intermediate region 31c is 5×10 10 atoms / cm 2 or more and 1.5×10 11 atoms / cm 2 or less per unit area in a plane perpendicular to the Z direction. Since the amount of impurities of the first conductivity type in the first upper region 31t is large, depletion can be suppressed and a decrease in breakdown voltage can be suppressed. The same applies to the second semiconductor region 32 and the third semiconductor region 33. That is, for example, the amount of impurities of the first conductivity type contained in the second upper region 32t is larger than the amount of impurities of the first conductivity type contained in the second intermediate region 32c. For example, the amount of impurities of the first conductivity type contained in the third upper region 33t is larger than the amount of impurities of the first conductivity type contained in the third intermediate region 33c.

[0066] Also, for example, the amount of impurities of the first conductivity type contained in the first lower region 31u is larger than the amount of impurities of the first conductivity type contained in the first intermediate region 31c. For example, the amount of impurities of the first conductivity type per unit area (atoms / cm 2 ) in the first lower region 31u is larger than the amount of impurities of the first conductivity type per unit area in the first intermediate region 31c. For example, the difference between the amount of impurities of the first conductivity type contained in the first lower region 31u and the amount of impurities of the first conductivity type contained in the first intermediate region 31c is 5×10 10 atoms / cm 2 or more and 1.5×10 11 atoms / cm 2The following holds. Since the amount of impurities of the first conductivity type in the first lower end region 31u is large, depletion can be suppressed and a decrease in breakdown voltage can be suppressed. The same applies to the second semiconductor region 32 and the third semiconductor region 33. That is, for example, the amount of impurities of the first conductivity type contained in the second lower end region 32u is larger than the amount of impurities of the first conductivity type contained in the second intermediate region 32c. For example, the amount of impurities of the first conductivity type contained in the third lower end region 33u is larger than the amount of impurities of the first conductivity type contained in the third intermediate region 33c.

[0067] The concentration of impurities of the first conductivity type in the first upper end region 31t is, for example, 1.3×10 16 atoms / cm 3 or more and 6.5×10 16 atoms / cm 3 or less. The concentration of impurities of the first conductivity type in the first lower end region 31u is, for example, 1.3×10 16 atoms / cm 3 or more and 6.5×10 16 atoms / cm 3 or less. The concentration of impurities of the first conductivity type in the first intermediate region 31c is, for example, 1×10 16 atoms / cm 3 or more and 5×10 16 atoms / cm 3 or less.

[0068] FIG. 7 is a schematic perspective view illustrating a semiconductor device according to an embodiment. FIG. 8 is a schematic plan view illustrating a semiconductor device according to an embodiment. FIG. 8 shows a view of FIG. 7 as seen from above. FIGS. 9 and 10 are schematic cross-sectional views illustrating a semiconductor device according to an embodiment. FIG. 9 shows a cross-section along the line B1 - B2 shown in FIG. 8. FIG. 10 shows a cross-section along the line B3 - B4 shown in FIG. 8.

[0069] In the semiconductor device 101 shown in FIGS. 7 to 10, the opposing region 38 of the semiconductor layer 30 is of the second conductivity type (p-type). As shown in FIG. 8, a part 52a of the second conductive portion 52 has a shape protruding from a part 52b of the second conductive portion 52 toward the first conductive portion 51.

[0070] The opposing region 38 includes a first portion 38a and a second portion 38b. The first portion 38a is located between a part 52a of the second conductive portion 52 and the third conductive portion 53 in the X direction. The second portion 38b is located between the first portion 38a and the first semiconductor region 31 and between a part 52a of the second conductive portion 52 and the first semiconductor region 31 in the Y direction. The first portion 38a and the second portion 38b are in contact with a part 52a of the second conductive portion 52. A first insulating region 71 is disposed between the first portion 38a and the third conductive portion 53 and between the second portion 38b and the third conductive portion 53.

[0071] A pn junction is formed between the second portion 38b of the opposing region 38 and the first semiconductor region 31. The direction from the pn junction to the third conductive portion 53 is along the Y direction. As the impurity of the second conductivity type, for example, boron can be used. For the rest, the same description as that of the configuration of the semiconductor device 100 can be applied to the configuration of the semiconductor device 101.

[0072] The semiconductor device 101 is, for example, a pn-type transistor. The height of the barrier formed between the opposing region 38 and the first semiconductor region 31 can be controlled by the potential of the third conductive portion 53. By controlling the potential of the third conductive portion 53, an off state in which substantially no current flows between the first conductive portion 51 and the second conductive portion 52 can be obtained. By controlling the potential of the third conductive portion 53, an on state in which carriers flow from the second conductive portion 52 through the semiconductor layer 30 to the first conductive portion 51 can be obtained. When the opposing region 38 is of the second conductivity type, for example, the influence on the threshold voltage of the transistor by the high-concentration impurity layers (the first upper end region 31t, the first lower end region 31u) can be suppressed.

[0073] Also in the semiconductor device 101, similar to the semiconductor device 100, it is possible to suppress a decrease in breakdown voltage. For example, the on-resistance can be reduced without impairing the breakdown voltage.

[0074] FIG. 11 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. The semiconductor device 102 according to the embodiment shown in FIG. 11 has a second conductive layer 62. Otherwise, the same description as that of the configuration of the semiconductor device 100 can be applied to the configuration of the semiconductor device 102. Note that FIG. 11 shows a cross-section of the semiconductor device 102, similar to the cross-section of the semiconductor device 100 shown in FIG. 3.

[0075] The second conductive layer 62 is electrically connected to the second conductive portion 52. For example, in the on-state of the transistor, carriers flow from the second conductive layer 62, through the second conductive portion 52, the semiconductor layer 30, and the first conductive portion 51, to the first conductive layer 61.

[0076] The second conductive layer 62 is disposed on the side opposite to the first conductive layer 61 of the semiconductor layer 30. That is, the semiconductor layer 30 is located between the first conductive layer 61 and the second conductive layer 62. In this example, the second conductive layer 62 is located above the semiconductor layer 30, and the first conductive layer 61 is located below the semiconductor layer 30. That is, the first upper end region 31t is between the second conductive layer 62 and the first lower end region 31u. Similarly, the second upper end region 32t is between the second conductive layer 62 and the second lower end region 32u, and the third upper end region 33t is between the second conductive layer 62 and the third lower end region 33u. The second conductive layer 62 may be located above the first insulating layer 21 and in contact with the first insulating layer 21.

[0077] Also in the semiconductor device 102, similar to the semiconductor device 100, it is possible to suppress a decrease in breakdown voltage. For example, the on-resistance can be reduced without impairing the breakdown voltage.

[0078] For example, in the semiconductor device 102, the impurity concentration of the first conductivity type in the first upper end region 31t may be higher than the impurity concentration of the first conductivity type in the first lower end region 31u. For example, in the semiconductor device 102, the first insulating layer 21 may be thinner than the second insulating layer 22. Thereby, for example, depletion on the source side (opposite side to the drain) of the semiconductor layer 30 can be suppressed.

[0079] FIGS. 12(a) and 12(b) are schematic plan views illustrating a semiconductor device according to an embodiment. In the semiconductor device 103 according to the embodiment shown in FIG. 12(a), a source region 36 and a drain region 37 are provided in the semiconductor layer 30. A part 52a of the second conductive part 52 has a shape protruding from a part 52b of the second conductive part 52 toward the first conductive part 51. Otherwise, the same description as that of the configuration of the semiconductor device 100 can be applied to the configuration of the semiconductor device 103. Note that FIG. 12(a) shows a plan view of the semiconductor device 103, similar to the plan view of the semiconductor device 100 shown in FIG. 2.

[0080] In the semiconductor device 103, the opposing region 38 has the first conductivity type and includes a first part 38a and a second part 38b. The first part 38a and the second part 38b are in Schottky contact with a part 52a of the second conductive part 52.

[0081] The source region 36 is located between the second conductive part 52 (part 52b) and the opposing region 38 in the Y direction. The source region 36 is located between the second conductive part 52 (part 52a) and the third conductive part 53 in the X direction. The source region 36 has the first conductivity type. In the semiconductor device 103, the impurity concentration of the first conductivity type in the source region 36 is higher than the impurity concentration of the first conductivity type in the opposing region 38. By providing the source region 36, a good electrical connection can be obtained between the second conductive part 52 and the semiconductor layer 30. For example, the on-resistance can be reduced.

[0082] The drain region 37 is provided between the second semiconductor region 32 and the first conductive portion 51, and between the third semiconductor region 33 and the first conductive portion 51. The drain region 37 has a first conductivity type. The impurity concentration of the first conductivity type in the drain region 37 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 31 (for example, the first intermediate region 31c or the first upper end region 31t). By providing the drain region 37, a good electrical connection can be obtained between the first conductive portion 51 and the semiconductor layer 30.

[0083] Also in the semiconductor device 104 according to the embodiment shown in FIG. 12(b), a source region 36 and a drain region 37 are provided in the semiconductor layer 30. Otherwise, the same description as the configuration of the semiconductor device 101 can be applied to the configuration of the semiconductor device 104. Note that FIG. 12(b) shows a plan view of the semiconductor device 104, similar to the plan view of the semiconductor device 101 shown in FIG. 8. The semiconductor device 104 is, for example, an npn-type transistor.

[0084] Thus, in each semiconductor device according to the embodiment, at least one of the source region 36 and the drain region 37 may be provided as appropriate.

[0085] The embodiment may include the following configuration (for example, technical solution). (Configuration 1) A support having a first surface, A first conductive portion, wherein the direction from the first surface to the first conductive portion is along a first direction perpendicular to the first surface, A second conductive portion separated from the first conductive portion in a second direction along the first surface, A semiconductor layer located between the first conductive portion and the second conductive portion, having a first end surface and a second end surface located between the first end surface and the support, wherein the semiconductor layer includes an opposing region and a first semiconductor region of a first conductivity type, and the opposing region is located between the second conductive portion and the first semiconductor region and opposes a part of the second conductive portion, In a third direction that intersects the second direction and extends along the first surface, a part of the second conductive portion and a third conductive portion separated from the opposing region, a fourth conductive portion separated from the first semiconductor region in the third direction, are provided, The first semiconductor region includes a first upper region including a part of the first end face, a first lower region including a part of the second end face, and a first intermediate region located between the first upper region and the first lower region, The concentration of impurities of the first conductivity type in the first upper region is higher than the concentration of impurities of the first conductivity type in the first intermediate region, The concentration of impurities of the first conductivity type in the first lower region is higher than the concentration of impurities of the first conductivity type in the first intermediate region, a semiconductor device. (Configuration 2) The semiconductor device according to Configuration 1, wherein the opposing region has a first conductivity type and is in Schottky contact with a part of the second conductive portion. (Configuration 3) The semiconductor device according to Configuration 1, wherein the opposing region has a second conductivity type. (Configuration 4) a first insulating layer in contact with the first end face, a second insulating layer in contact with the second end face, The semiconductor device according to any one of Configurations 1 to 3, further comprising. (Configuration 5) The first insulating layer is in contact with one end of the fourth conductive portion in the first direction, The semiconductor device according to Configuration 4, wherein the second insulating layer is in contact with the other end of the fourth conductive portion in the first direction. (Configuration 6) The thickness of the first insulating layer is 250 nm or more and 1250 nm or less, The semiconductor device according to Configuration 4 or 5, wherein the thickness of the second insulating layer is 250 nm or more and 1250 nm or less. (Configuration 7) The semiconductor device further comprises a first conductive layer electrically connected to the first conductive portion, One of the first upper region and the first lower region is located between the other of the first upper region and the first lower region and the first conductive layer. The semiconductor device according to any one of Configurations 1 to 6, wherein the concentration of the impurity of the first conductivity type in the other of the first upper region and the first lower region is higher than the concentration of the impurity of the first conductivity type in the one of the first upper region and the first lower region. (Configuration 8) Further comprising a first conductive layer electrically connected to the first conductive portion. The semiconductor device according to Configuration 7, wherein the other of the first upper region and the first lower region is located between the one of the first upper region and the first lower region and the first conductive layer. (Configuration 9) Further comprising a first conductive layer electrically connected to the first conductive portion. The first lower region is located between the first insulating layer and the second insulating layer. The first upper region is located between the first lower region and the first insulating layer. One of the first insulating layer and the second insulating layer is located between the other of the first insulating layer and the second insulating layer and the first conductive layer. The semiconductor device according to any one of Configurations 4 to 6, wherein the thickness of the other of the first insulating layer and the second insulating layer is thinner than the thickness of the one of the first insulating layer and the second insulating layer. (Configuration 10) Further comprising a first conductive layer electrically connected to the first conductive portion. The semiconductor device according to Configuration 9, wherein the other of the first insulating layer and the second insulating layer is located between the one of the first insulating layer and the second insulating layer and the first conductive layer. (Configuration 11) The semiconductor device according to Configuration 8 or 10, wherein the second end face is located between the first end face and the first conductive layer. (Configuration 12) Further comprising a second conductive layer electrically connected to the second conductive portion. The semiconductor layer is a semiconductor device according to Configuration 8, 10, or 11, which is located between the first conductive layer and the second conductive layer. (Configuration 13) The semiconductor layer includes a second semiconductor region of a first conductivity type that is separated from the fourth conductive portion in the second direction and is located between the fourth conductive portion and the first conductive portion. The second semiconductor region includes a second upper region including a part of the first end face, a second lower region including a part of the second end face, and a second intermediate region located between the second upper region and the second lower region. The concentration of impurities of the first conductivity type in the second upper region is higher than the concentration of impurities of the first conductivity type in the second intermediate region. The semiconductor device according to any one of Configurations 1 to 12, wherein the concentration of impurities of the first conductivity type in the second upper region is higher than the concentration of impurities of the first conductivity type in the second intermediate region. (Configuration 14) The semiconductor layer includes a third semiconductor region of a first conductivity type that is located between the first semiconductor region and the first conductive portion in the second direction. The direction from the second semiconductor region to the third semiconductor region is along the third direction. The third semiconductor region includes a third upper region including a part of the first end face, a third lower region including a part of the second end face, and a third intermediate region located between the third upper region and the third lower region. The concentration of impurities of the first conductivity type in the third upper region is higher than the concentration of impurities of the first conductivity type in the third intermediate region. The semiconductor device according to Configuration 13, wherein the concentration of impurities of the first conductivity type in the third upper region is higher than the concentration of impurities of the first conductivity type in the third intermediate region. (Configuration 15) The semiconductor device according to any one of Configurations 1 to 14, wherein the fourth conductive portion is electrically connected to the second conductive portion. (Configuration 16) The thickness of the first upper region is 100 nm or more and 1000 nm or less. The thickness of the first lower end region is 100 nm or more and 1000 nm or less, the thickness of the first upper end region is thinner than the thickness of the first intermediate region, The semiconductor device according to any one of Configurations 1 to 15, wherein the thickness of the first lower end region is thinner than the thickness of the first intermediate region. (Configuration 17) The semiconductor device according to Configuration 16, wherein the amount of impurities of the first conductivity type contained in the first upper end region is larger than the amount of impurities of the first conductivity type contained in the first intermediate region. (Configuration 18) The difference between the amount of impurities of the first conductivity type contained in the first upper end region and the amount of impurities of the first conductivity type contained in the first intermediate region is 5×10 10 atoms / cm 2 or more and 1.5×10 11 atoms / cm 2 or less in a plane perpendicular to the first direction. The semiconductor device according to Configuration 17. (Configuration 19) The concentration of impurities of the first conductivity type in the first intermediate region is 1×10 16 atoms / cm 3 or more and 5×10 16 atoms / cm 3 or less, and the concentration of impurities of the first conductivity type in the first upper end region is 1.3×10 16 atoms / cm 3 or more and 6.5×10 16 atoms / cm 3 or less. The semiconductor device according to any one of Configurations 1 to 18. (Configuration 20) The semiconductor device according to any one of Configurations 1 to 19, further comprising an insulating portion including a first insulating region provided between the third conductive portion and the opposing region and a second insulating region provided between the fourth conductive portion and the first semiconductor region.

[0086] In an embodiment, information regarding the shape of a semiconductor region, etc. is obtained, for example, by electron microscope observation or the like. Information regarding a material and an impurity concentration in a semiconductor region is obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy), or SIMS (Secondary Ion Mass Spectrometry) or the like. Information regarding a carrier concentration in a semiconductor region is obtained, for example, by SCM (Scanning Capacitance Microscopy) or the like.

[0087] According to an embodiment, a semiconductor device capable of suppressing a decrease in breakdown voltage can be provided.

[0088] In this specification, the "nitride semiconductor" includes all compositions in which the composition ratios x, y, and z are changed within their respective ranges in the chemical formula B x In y Al z Ga 1-x-y-z N(0≦x≦1, 0≦y≦1, 0≦z≦1, x + y + z≦1). Further, in the above chemical formula, those further including group V elements other than N (nitrogen), those further including various elements added to control various physical properties such as conductivity type, and those further including various elements contained unintentionally are also included in the "nitride semiconductor".

[0089] In this specification, "electrically connected" includes not only the case of being connected in direct contact but also the case of being connected via other conductive members or the like. In this specification, "vertical" and "parallel" include not only strict vertical and strict parallel but also, for example, variations in the manufacturing process, and it is sufficient that they are substantially vertical and substantially parallel.

[0090] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element, the present invention can be similarly implemented by appropriately selecting from the range known to those skilled in the art, and as long as the same effects can be obtained, it is included in the scope of the present invention.

[0091] As long as it includes the gist of the present invention, a combination of any two or more elements of each specific example within a technically possible range is also included in the scope of the present invention.

[0092] In addition, based on the semiconductor device described above as an embodiment of the present invention, all semiconductor devices that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0093] In addition, within the scope of the idea of the present invention, those skilled in the art can conceive of various modification examples and correction examples, and it is understood that these modification examples and correction examples also belong to the scope of the present invention.

[0094] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and its equivalents.

Explanation of Reference Numerals

[0095] 10: Support 10a: First surface 11: First semiconductor region 21: First insulating layer 22: Second insulating layer 22a: Upper surface 30: Semiconductor layer 30t: First end face 30u: Second end face 31: First semiconductor region 31c: First intermediate region 31f: Upper surface 31g: Lower surface 31t: First upper end region 31u: First lower end region 32: Second semiconductor region 32c: Second intermediate region 32t: Second upper end region 32u: Second lower end region 33: Third semiconductor region 33c: Third intermediate region 33t: Third upper end region 33u: Third lower end region 36: Source region 37: Drain region 38: Opposing region 38a: First part 38b: Second part 38c: Intermediate opposing region 38t: Upper opposing region 38u: Lower opposing region 51: First conductive part 52: Second conductive part 52a, 52b: Part 53: Third conductive part 53f: Upper end 53g: Lower end 54: Fourth conductive part 54L: Wiring 54f: Upper end 54g: Lower end 61: First conductive layer 62: Second conductive layer 70: Insulating part 70f: Upper end 70g: Lower end 71: First insulating region 72: Second insulating region 73, 74: Insulating region 100~104: Semiconductor device C1, C2: Capacitor C31t, C31u: Maximum concentration Cn1: Concentration F1: Opposing surface S1, S2: Substrate T1, T2, T3: Thickness pZ: Position

Claims

1. A support having a first surface, A first conductive portion, wherein the direction from the first surface to the first conductive portion is along a first direction perpendicular to the first surface, A second conductive portion separated from the first conductive portion in a second direction along the first surface, A semiconductor layer positioned between the first conductive portion and the second conductive portion, having a first end face and a second end face positioned between the first end face and the support, wherein the semiconductor layer includes an opposing region and a first semiconductor region of a first conductivity type, and the opposing region is positioned between the second conductive portion and the first semiconductor region and opposes a part of the second conductive portion, In a third direction intersecting the second direction and along the first surface, a third conductive portion separated from a part of the second conductive portion and the opposing region, In the third direction, a fourth conductive portion separated from the first semiconductor region, Comprising, The first semiconductor region includes a first upper end region including a part of the first end face, a first lower end region including a part of the second end face, and a first intermediate region positioned between the first upper end region and the first lower end region, The concentration of impurities of the first conductivity type in the first upper end region is higher than the concentration of impurities of the first conductivity type in the first intermediate region, The concentration of impurities of the first conductivity type in the first lower end region is higher than the concentration of impurities of the first conductivity type in the first intermediate region, a semiconductor device.

2. The opposing region is of a first conductivity type and makes a Schottky contact with a part of the second conductive portion, the semiconductor device according to claim 1.

3. The opposing region is of a second conductivity type, the semiconductor device according to claim 1.

4. A first insulating layer in contact with the first end face, A second insulating layer in contact with the second end face, Further comprising, the semiconductor device according to any one of claims 1 to 3.

5. The first insulating layer is in contact with one end of the fourth conductive portion in the first direction, The second insulating layer is in contact with the other end of the fourth conductive portion in the first direction, the semiconductor device according to claim 4.

6. The thickness of the first insulating layer is 250 nm or more and 1250 nm or less, The thickness of the second insulating layer is 250 nm or more and 1250 nm or less, the semiconductor device according to claim 4.

7. In the semiconductor device according to any one of claims 1 to 3, the concentration of the impurity of the first conductivity type in one of the first upper end region and the first lower end region is higher than the concentration of the impurity of the first conductivity type in the other of the first upper end region and the first lower end region.

8. Further comprising a first conductive layer electrically connected to the first conductive portion, In the semiconductor device according to claim 7, the other of the first upper end region and the first lower end region is located between the one of the first upper end region and the first lower end region and the first conductive layer.

9. The first lower end region is located between the first insulating layer and the second insulating layer, The first upper end region is located between the first lower end region and the first insulating layer, In the semiconductor device according to claim 4, the thickness of one of the first insulating layer and the second insulating layer is thinner than the thickness of the other of the first insulating layer and the second insulating layer.

10. Further comprising a first conductive layer electrically connected to the first conductive portion, In the semiconductor device according to claim 9, the other of the first insulating layer and the second insulating layer is located between the one of the first insulating layer and the second insulating layer and the first conductive layer.

11. In the semiconductor device according to claim 8, the second end face is located between the first end face and the first conductive layer.

12. Further comprising a second conductive layer electrically connected to the second conductive portion, In the semiconductor device according to claim 8, the semiconductor layer is located between the first conductive layer and the second conductive layer.

13. The semiconductor layer includes a second semiconductor region of the first conductivity type that is separated from the fourth conductive portion in the second direction and is located between the fourth conductive portion and the first conductive portion, The second semiconductor region includes a second upper end region including a part of the first end face, a second lower end region including a part of the second end face, and a second intermediate region located between the second upper end region and the second lower end region, The concentration of the impurity of the first conductivity type in the second upper end region is higher than the concentration of the impurity of the first conductivity type in the second intermediate region, In the semiconductor device according to any one of claims 1 to 3, the concentration of the impurity of the first conductivity type in the second upper end region is higher than the concentration of the impurity of the first conductivity type in the second intermediate region.

14. The semiconductor layer includes a third semiconductor region of the first conductivity type that is located between the first semiconductor region and the first conductive portion in the second direction, The direction from the second semiconductor region toward the third semiconductor region is along the third direction. The third semiconductor region includes a third upper region including a part of the first end face, a third lower region including a part of the second end face, and a third intermediate region located between the third upper region and the third lower region. The concentration of the impurity of the first conductivity type in the third upper region is higher than the concentration of the impurity of the first conductivity type in the third intermediate region. The semiconductor device according to claim 13, wherein the concentration of the impurity of the first conductivity type in the third upper region is higher than the concentration of the impurity of the first conductivity type in the third intermediate region.

15. The semiconductor device according to any one of claims 1 to 3, wherein the fourth conductive portion is electrically connected to the second conductive portion.

16. The thickness of the first upper region is 100 nm or more and 1000 nm or less. The thickness of the first lower region is 100 nm or more and 1000 nm or less. The thickness of the first upper region is thinner than the thickness of the first intermediate region. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the first lower region is thinner than the thickness of the first intermediate region.

17. The semiconductor device according to claim 16, wherein the amount of the impurity of the first conductivity type included in the first upper region is larger than the amount of the impurity of the first conductivity type included in the first intermediate region.

18. The difference between the amount of impurities of the first conductivity type contained in the first upper end region and the amount of impurities of the first conductivity type contained in the first intermediate region is 5×10 １０ atoms / cm 2 or more and 1.5×10 １１ atoms / cm 2 or less per unit area in a plane perpendicular to the first direction. The semiconductor device according to claim 17.

19. The concentration of the impurity of the first conductivity type in the first intermediate region is 1×10 １６ atoms / cm 3 or more and 5×10 １６ atoms / cm 3 or less, and The concentration of the impurity of the first conductivity type in the first upper end region is 1.3×10 １６ atoms / cm 3 or more and 6.5×10 １６ atoms / cm 3 or less. The semiconductor device according to any one of claims 1 to 3.

20. The semiconductor device according to any one of claims 1 to 3, further comprising an insulating portion including a first insulating region provided between the third conductive portion and the opposing region, and a second insulating region provided between the fourth conductive portion and the first semiconductor region.

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