Semiconductor device

Abstract

To provide a semiconductor device capable of preventing a short circuit between an upper electrode and a lower electrode while securing a bonding margin between the lower electrode and a contact via.SOLUTION: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on an inner wall of a groove that reaches a drift layer from a surface of the semiconductor substrate, a gate trench and a raised electrode that are formed inside the groove on the gate insulating film, an interlayer insulating film, and an emitter electrode. The gate trench includes a lower electrode and an upper electrode formed above the lower electrode via an intermediate insulating film. The raised electrode includes a first raised electrode connected to the emitter electrode via a contact via that penetrates the interlayer insulating film, and a second raised electrode positioned between the first raised electrode and the gate trench in a direction in which the groove extends in plan view. The second raised electrode includes a narrow width portion having a width narrower than a width of the first raised electrode in plan view.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having a two-layer trench gate structure. Therein, at both longitudinal ends of the gate trench, a lower electrode as a shield electrode extends outward beyond an upper electrode as a gate electrode and is pulled up to the surface of an n - -type drift layer. In Patent Document 1, at the boundary between the lower electrode and the upper electrode pulled up to the n - -type drift layer, the gate trench is widened. Thereby, the thickness of the intermediate insulating film existing at this boundary can be formed thick enough not only on the entrance side but also on the bottom side of the gate trench. Thereby, it becomes possible to secure the breakdown voltage of the intermediate insulating film that insulates the lower electrode and the upper electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] n - The lower electrode pulled up to the surface of the -type drift layer is used as a pull-up electrode for the emitter potential by being brought into contact with a contact via. In order to secure a bonding margin between the lower electrode and the contact via, it is desirable that the width of the pull-up electrode is wide.

[0005] However, in the above method, the width of the pull-up electrode is narrow.

[0006] It is also possible to secure the above-described bonding margin by simply widening the width of the pull-up electrode. However, in that case, the embedding property of the material when forming the lower electrode on the pull-up electrode becomes a problem. This is a problem caused by the fact that the film formation state deteriorates as the width of the groove for embedding the material increases. If the width of the pull-up electrode is widened and the film formation state of the lower electrode deteriorates, there is a concern that the upper electrode, which should originally be removed by etching, may remain in the pull-up electrode unintentionally. If the upper electrode remaining in the pull-up electrode is charged to the emitter potential and contacts the upper electrode in the gate trench in that state, the upper electrode and the lower electrode are short-circuited.

[0007] An object of the present disclosure is to provide a semiconductor device capable of preventing a short circuit between an upper electrode and a lower electrode while securing a bonding margin between the lower electrode and a contact via, in order to solve the above-described problems.

Means for Solving the Problems

[0008] Aspects of the present disclosure include a semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, and an emitter region of the first conductivity type formed in an upper layer portion of the base layer; a gate insulating film formed on an inner wall of a groove penetrating from a surface of the semiconductor substrate through the emitter region and the base layer to reach the drift layer; a gate trench and a pull-up electrode formed on the gate insulating film inside the groove; an interlayer insulating film formed on the gate trench and the pull-up electrode; an emitter electrode formed on the semiconductor substrate and the interlayer insulating film and connected to the emitter region and the base layer; and comprising the gate trench having a lower electrode formed inside the groove and an upper electrode formed on the lower electrode inside the groove with an intermediate insulating film therebetween; the pull-up electrode connecting the lower electrode to the emitter electrode and being insulated from the upper electrode by the intermediate insulating film The lifting electrode includes a first lifting electrode connected to the emitter electrode through a contact via penetrating the interlayer insulating film, and a second lifting electrode disposed between the first lifting electrode and the gate trench in a direction in which the groove extends in a plan view. In a plan view, it is preferable that the semiconductor device has a narrow-width portion where the width of the second lifting electrode is narrower than that of the first lifting electrode. [Effect of the Invention]

[0009] According to an aspect of the present disclosure, a lower electrode is connected to a contact via in a wide first lifting electrode. Further, by disposing a narrow second lifting electrode between the first lifting electrode and the gate trench, it is possible to avoid poor embedding of the lower electrode at both ends of the lifting electrode. Thereby, it is possible to provide a semiconductor device capable of preventing a short circuit between the upper electrode and the lower electrode while securing a bonding margin between the lower electrode and the contact via. [Brief Description of the Drawings]

[0010]

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Embodiments for Carrying Out the Invention

[0011] Embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and repeated description may be omitted.

[0012] Embodiment 1 FIG. 1 is a plan view of a semiconductor device 101 according to Embodiment 1 of the present disclosure. The semiconductor device 101 includes a gate trench 111 formed to extend in one direction, and a pull-up electrode 123 (not shown) connected to the gate trench 111. The semiconductor device 101 is an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure.

[0013] In FIG. 1, the semiconductor device 101 includes a plurality of gate trenches 111, and the plurality of gate trenches 111 are arranged at equal intervals in a direction perpendicular to the extending direction. However, the number of gate trenches 111 does not necessarily have to be plural, and one or more are sufficient.

[0014] The active region 102 includes the gate trench 111 and the pull-up electrode 123, and is a region where the semiconductor device 101 functions as an IGBT.

[0015] FIG. 2 is an enlarged view of FIG. 1. The pull-up electrode 123 includes a first pull-up electrode 112 and a second pull-up electrode 113 disposed between the first pull-up electrode 112 and the gate trench 111. The second pull-up electrode 113 and the gate trench 111 have the same width. On the other hand, the first pull-up electrode 112 has a width wider than that of the second pull-up electrode 113 and the gate trench 111. Note that the width of the gate trench 111 or the pull-up electrode 123 refers to the width when the semiconductor device 101 is viewed in plan.

[0016] An upper electrode 21, a lower electrode 22, and an intermediate insulating film 32 for insulating between them are formed in the gate trench 111. In FIG. 2, the surface where the upper electrode 21 exists is shown.

[0017] In the pull-up electrode 123, the lower electrode 22 is pulled up to the surface of the semiconductor substrate 10 and exposed. The pulled-up lower electrode 22 is surrounded by the insulating film 31 and the intermediate insulating film 32. The lower electrode 22 and the upper electrode 21 are insulated from each other by the intermediate insulating film 32.

[0018] The lower electrode 22 pulled up to the surface of the semiconductor substrate 10 is connected to the contact via 42 at the first pull-up electrode 112. The contact via 42 electrically connects the lower electrode 22 to an emitter electrode 51 (not shown) and is for setting the lower electrode 22 to the emitter potential.

[0019] By connecting the lower electrode 22 to the contact via 42 at the wide first pull-up electrode 112 as in the present disclosure, a bonding margin between the lower electrode 22 and the contact via 42 can be ensured. Thereby, the bonding can be facilitated.

[0020] Also, the area of the contact via 42 can be increased by the amount that the lower electrode 22 is widened, and the contact resistance can be reduced.

[0021] Here, even if all the pull-up electrodes 123 are the first pull-up electrodes 112, it is possible to secure the above-described bonding margin. However, in that case, poor embedding of the material occurs when forming the lower electrode 22 on the first pull-up electrode 112. This has already been described in the problems to be solved by the invention, but will be described in detail below with reference to FIGS. 20 and 21.

[0022] FIG. 20 is a diagram showing the lower electrode 22 formed on the first pull-up electrode 112 according to a comparative example of the present disclosure. Here, a cross section in the short side direction of the first pull-up electrode 112 is shown, and only the upper layer portion of the semiconductor substrate 10 is shown. It is known that the film formation state of the lower electrode 22 deteriorates more when embedding the material in the wider first pull-up electrode 112 than when embedding it in the narrower second pull-up electrode 113. That is, since it is difficult to embed the material in the center of the first pull-up electrode 112, the formed lower electrode 22 is not flat and has a V shape as shown in FIG. 20.

[0023] The formed lower electrode 22 is etched, and the portion exposed on the semiconductor substrate 10 is removed. Further, the intermediate insulating film 32 and the upper electrode 21 are laminated. Here, the upper electrode 21 to be laminated should originally remain only in the gate trench 111 and be removed by etching in the first pull-up electrode 112. However, as a result of the V-shaped lower electrode 22 being reflected, the upper electrode 21 that should not originally remain remains in the first pull-up electrode 112.

[0024] FIG. 21 is a diagram showing the upper electrode 21 remaining in the first pull-up electrode 112 according to the comparative example of the present disclosure. Here, a cross-section in the short side direction of the first pull-up electrode 112 is shown, and only the upper layer portion of the semiconductor substrate 10 is shown. As shown in FIG. 21, the upper electrode 21 that could not be completely removed by etching remains at the central position of the first pull-up electrode 112.

[0025] Since this upper electrode 21 that could not be completely removed exists in the upper layer of the semiconductor substrate 10, it can come into contact with the contact via 42 having the emitter potential. Here, the first pull-up electrode 112 is adjacent to the gate trench 111 with the upper electrode 21 that could not be completely removed remaining in the upper layer portion. In other words, the upper electrode 21 remaining in the first pull-up electrode 112 and the upper electrode 21 of the gate trench 111 are in a state where they are likely to come into contact. If they come into contact, the upper electrode 21 and the lower electrode 22 will short-circuit.

[0026] On the other hand, in the pull-up electrode 123 of the present disclosure, by disposing the second pull-up electrode 113 between the first pull-up electrode 112 and the gate trench 111, it is possible to avoid poor embedding of the lower electrode 22 at both ends of the pull-up electrode 123. As a result, it becomes possible to prevent the upper electrode 21 and the lower electrode 22 from short-circuiting.

[0027] FIG. 3 is a cross-sectional view of the gate trench 111 according to Embodiment 1 of the present disclosure, which is a cross-sectional view taken along line a-a of FIG. 2. The gate trench 111 is embedded in a groove 114 formed on the surface of the semiconductor substrate 10. The semiconductor substrate 10 has a collector electrode 52 disposed on the bottom surface, and on top of it, a p-type collector layer 16, an n-type buffer layer 15, an n-type drift layer 11, an n-type carrier accumulation layer 12, a p-type base layer 13, and an n + -type emitter region 24 are stacked in this order. Note that n + indicates that the impurity concentration is higher than that of the n-type. Here, in this figure, a cross-sectional view of the gate trench 111 in the portion where the upper layer of the p-type base layer 13 is the n + -type emitter region 24 is shown. However, it should be noted that the gate trench 111 is also embedded in the portion where the upper layer of the p-type base layer 13 is the p + -type layer region 23. Note that p + indicates that the impurity concentration is higher than that of the p-type.

[0028] The insulating films 31 and 33 are formed on the inner wall of the groove 114 that penetrates from the n + -type emitter region 24, which is the upper layer of the semiconductor substrate 10, to the n-type carrier accumulation layer 12 and reaches the n-type drift layer 11. The insulating film 31 insulates the lower electrode 22 and the semiconductor substrate 10. The insulating film 33 insulates the upper electrode 21 and the semiconductor substrate 10. Hereinafter, the insulating films 31 and 33 are collectively referred to as the gate insulating film.

[0029] The gate trench 111 is formed on the gate insulating film inside the groove 114. The gate trench 111 has a lower electrode 22 formed inside the groove 114 and an upper electrode 21 formed on the lower electrode 22 inside the groove 114 via an intermediate insulating film 32. The upper electrode 21 performs a switching operation as an IGBT. The lower electrode 22 is formed to reduce the feedback capacitance by being fixed to the emitter potential and improve the electrical characteristics as an IGBT. The lower electrode 22 is composed of, for example, doped Poly-Si.

[0030] The intermediate insulating film 32 is formed between the lower electrode 22 and the upper electrode 21 to insulate between the two.

[0031] An interlayer insulating film 30 is formed via an insulating film 34 on the upper part of the gate trench 111. The interlayer insulating film 30 is covered by an emitter electrode 51. The emitter electrode 51 is connected to an n + -type emitter region 24 which is the upper layer of the semiconductor substrate 10 and a p + -type layer region 23 via a contact via 41. Thereby, the n + -type emitter region 24 and the p + -type layer region 23 can be set to the emitter potential.

[0032] FIG. 4 is a cross-sectional view taken along line b-b of FIG. 2 and is a longitudinal cross-sectional view of the pull-up electrode 123. Further, FIG. 5 is a cross-sectional view taken along line c-c of FIG. 2 and is a cross-sectional view of the first pull-up electrode 112 in the short direction. As shown in FIG. 4, the lower electrode 22 is formed on the insulating film 31. The lower electrode 22 passes through the gate trench 111 and extends to the pull-up electrode 123. Further, the lower electrode 22 is pulled up to the surface of the semiconductor substrate 10 at the pull-up electrode 123. Specifically, as shown in FIG. 5, the lower electrode 22 is pulled up to the surface of the p + -type layer region 23. An interlayer insulating film 30 is formed on the pulled-up lower electrode 22. The lower electrode 22 is connected to the emitter electrode 51 via a contact via 42 at the first pull-up electrode 112. The contact via 42 penetrates the interlayer insulating film 30.

[0033] As described above, according to the present disclosure, the lower electrode 22 is connected to the contact via 42 at the wide first pull-up electrode 112. Further, by disposing the narrow second pull-up electrode 113 between the first pull-up electrode 112 and the gate trench 111, it is possible to avoid the embedding failure of the lower electrode 22 at both ends of the pull-up electrode 123. Thereby, it is possible to provide a semiconductor device capable of preventing a short circuit between the upper electrode 21 and the lower electrode 22 while securing a bonding margin between the lower electrode 22 and the contact via 42.

[0034] Note that the same effects as those in Embodiment 1 can also be obtained in the following modification examples.

[0035] <Modification Example 1 of Embodiment 1> FIG. 6 is a plan view of a semiconductor device 101 according to a modification example of Embodiment 1 of the present disclosure. Here, the gate trench 111 has the same width as the first pull-up electrode 112. Thus, the gate trench 111 may be wide.

[0036] <Modification Example 2 of Embodiment 1> FIG. 7 is a plan view of a semiconductor device 101 according to a modification example of Embodiment 1 of the present disclosure. Here, the second pull-up electrode 113 includes a narrow-width portion 115 connected to the first pull-up electrode 112 and a wide-width portion 116 connected to the gate trench 111 via the intermediate insulating film 32 and wider than the narrow-width portion 115. Note that the wide-width portion 116 desirably has the same width as the first pull-up electrode 112, but may have a width wider than that of the narrow-width portion 115.

[0037] <Modification Example 3 of Embodiment 1> FIG. 8 is a plan view of a semiconductor device 101 according to a modification example of Embodiment 1 of the present disclosure. Here, the second pull-up electrode 113 includes a narrow-width portion 115 narrower than the first pull-up electrode 112 and a connection portion 117 that connects the narrow-width portion 115 and the first pull-up electrode 112 in an inclined manner in a plan view. The narrow-width portion 115 is connected to the gate trench 111 via the intermediate insulating film 32. By connecting portions with different widths in an inclined manner, the electric field concentration at the corner of the pull-up electrode 123 can be alleviated. Note that in the example of FIG. 8, the case where the connection portion 117 connects the narrow-width portion 115 and the first pull-up electrode 112 in an inclined manner has been described, but the same effect can be obtained even if they are connected by a curve. This point is common to all the following embodiments.

[0038] Note that the semiconductor substrate 10 is not limited to being formed of silicon, and may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. The wide bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. The semiconductor substrate 10 formed of such a wide bandgap semiconductor has high breakdown voltage and allowable current density, so that the semiconductor device 101 can be miniaturized. By using this miniaturized semiconductor device 101, a semiconductor module incorporating this semiconductor device 101 can also be miniaturized and highly integrated. Further, since the semiconductor device 101 has high heat resistance, the heat dissipation fins of the heat sink can be miniaturized and the water cooling part can be air-cooled, so that the semiconductor module can be further miniaturized. Further, since the power loss of the semiconductor device 101 is low and it is highly efficient, the semiconductor module can be made highly efficient. Note that this point is common to all the following embodiments.

[0039] Embodiment 2 Here, the points of change from Embodiment 1 will be described. FIG. 9 is a plan view of the semiconductor device 101 according to Embodiment 2 of the present disclosure. FIG. 10 is a cross-sectional view taken along line d-d of FIG. 9. In the present embodiment, a pull-up electrode 123 is formed at the terminal end portion 103 of the gate trench 111. Thereby, the configuration of the gate trench 111 in the active region 102 can be made uniform, and in addition to the effects described in Embodiment 1, an effect of making the heat generation of the semiconductor device 101 uniform in the plane of the active region 102 can also be obtained.

[0040] Note that the same effects as those of Embodiment 2 can be obtained in the following modification examples.

[0041] <Modification Example 1 of Embodiment 2> FIG. 11 is a plan view of the semiconductor device 101 according to the modification example of Embodiment 2 of the present disclosure. Here, the gate trench 111 has the same width as the first pull-up electrode 112. Thus, the gate trench 111 may be wide.

[0042] <Modification Example 2 of Embodiment 2> FIG. 12 is a plan view of a semiconductor device 101 according to a modified example of Embodiment 2 of the present disclosure. Here, the second pull-up electrode 113 includes a narrow portion 115 connected to the first pull-up electrode 112 and a wide portion 116 connected to the gate trench 111 via the intermediate insulating film 32 and wider than the narrow portion 115. Note that the wide portion 116 preferably has the same width as the first pull-up electrode 112, but may have a width wider than the narrow portion 115.

[0043] Embodiment 3 Here, the points of change from Embodiment 1 will be described. FIG. 13 is a plan view of a semiconductor device 101 according to Embodiment 3 of the present disclosure. Here, an example in which the second pull-up electrode 113 and the gate trench 111 have the same width is shown, but the widths may be different.

[0044] In this embodiment, a plurality of gate trenches 111 are connected to the first pull-up electrode 112 via the second pull-up electrode 113. The lower electrode 22 is connected to the contact via 42 at the first pull-up electrode 112.

[0045] Thereby, the area of the first pull-up electrode 112 can be increased as compared with Embodiment 1. Therefore, the bonding margin between the lower electrode 22 and the contact via 42 can be further increased.

[0046] In addition, the area of the contact via 42 can be widened by widening the lower electrode 22, and the contact resistance can be reduced as compared with Embodiment 1.

[0047] <Modification Example 1 of Embodiment 3> FIG. 14 is a plan view of a semiconductor device 101 according to a modified example of Embodiment 3 of the present disclosure. Here, the second pull-up electrode 113 includes a narrow portion 115 connected to the first pull-up electrode 112 and a wide portion 116 connected to the gate trench 111 via the intermediate insulating film 32 and wider than the narrow portion 115. Note that the wide portion 116 desirably has the same width as the first pull-up electrode 112, but may have a width wider than the narrow portion 115. Even in such a modified example, the same effects as those of Embodiment 3 can be obtained.

[0048] Embodiment 4 Here, the points of change from Embodiment 3 will be described. FIG. 15 is a plan view of a semiconductor device 101 according to Embodiment 4 of the present disclosure. In the present embodiment, the pull-up electrode 123 of Embodiment 3 is formed at the end portion 103 of the gate trench 111.

[0049] Thereby, the effects of combining Embodiment 2 and Embodiment 3 can be obtained.

[0050] <Modified Example 1 of Embodiment 4> FIG. 16 is a plan view of a semiconductor device 101 according to a modified example of Embodiment 4 of the present disclosure. Here, the second pull-up electrode 113 includes a narrow portion 115 connected to the first pull-up electrode 112 and a wide portion 116 wider than the narrow portion 115 connected to the gate trench 111 via the intermediate insulating film 32. Note that the wide portion 116 desirably has the same width as the first pull-up electrode 112, but may have a width wider than the narrow portion 115. Even in such a modified example, the same effects as those of Embodiment 4 can be obtained.

[0051] Embodiment 5 Here, the changes from Embodiment 1 will be described. FIG. 17 is a plan view of a semiconductor device 101 according to Embodiment 5 of the present disclosure. FIG. 18 is an enlarged view of FIG. 17. The gate trench 111 of the present embodiment includes a plurality of parallel gate trenches 211 arranged in parallel in a plan view. The plurality of parallel gate trenches 211 are each connected by a gate trench 221 extending in a direction perpendicular to the extending direction of the parallel gate trench 211. Thereby, the lower electrodes 22 of the parallel gate trenches 211 connected by the gate trench 221 can be collectively set to the emitter potential.

[0052] Also, two of the plurality of parallel gate trenches 211 are connected to a pull-up electrode 123 formed therebetween via a gate trench 223. Thereby, a large first pull-up electrode 112 using the space between them can be provided, and the bonding margin between the lower electrode 22 and the contact via 42 can be increased. Furthermore, the layout of the pull-up electrode 123 can be adjusted more freely. In the example of FIG. 17, the parallel gate trenches 211 at both ends of the plurality of parallel gate trenches 211 connected by the gate trench 221 are connected to the pull-up electrode 123 via the gate trench 223. By connecting the parallel gate trenches 211 at both ends, a large first pull-up electrode 112 can be provided.

[0053] <Modification Example 1 of Embodiment 5> FIG. 19 is a plan view of a semiconductor device 101 according to a modification of Embodiment 5 of the present disclosure. Here, a plurality of gate trenches 223 parallel to each other in a plan view are connected to the pull-up electrode 123. Even in such a modification, the same effects as those of Embodiment 5 can be obtained.

[0054] Note that the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof at the implementation stage. Also, the respective embodiments may be implemented in appropriate combination, and in that case, the combined effects can be obtained.

[0055] <Correspondence with Terms Used in Claims> In the claims, the n-type semiconductor conductivity type is referred to as the first conductivity type. Similarly, the p-type semiconductor conductivity type is referred to as the second conductivity type in the claims. Accordingly, in the claims, the n-type drift layer 11 is the drift layer of the first conductivity type, the p-type base layer 13 is the base layer of the second conductivity type, and the n + type emitter region 24 is referred to as the emitter region of the first conductivity type.

[0056] Hereinafter, various aspects of the present disclosure will be collectively described as appendices. (Appendix 1) A semiconductor substrate having a drift layer of the first conductivity type, a base layer of the second conductivity type formed on the drift layer, and an emitter region of the first conductivity type formed in an upper portion of the base layer, A gate insulating film formed on an inner wall of a groove that penetrates the emitter region and the base layer from a surface of the semiconductor substrate to reach the drift layer, A gate trench and a pull-up electrode formed on the gate insulating film inside the groove, An interlayer insulating film formed on the gate trench and the pull-up electrode, An emitter electrode formed on the semiconductor substrate and the interlayer insulating film and connected to the emitter region and the base layer, comprising The gate trench has a lower electrode formed inside the groove and an upper electrode formed on the lower electrode via an intermediate insulating film inside the groove, The pull-up electrode connects the lower electrode to the emitter electrode and is insulated from the upper electrode by the intermediate insulating film, The pull-up electrode has a first pull-up electrode connected to the emitter electrode via a contact via penetrating the interlayer insulating film, and a second pull-up electrode disposed between the first pull-up electrode and the gate trench in a direction in which the groove extends in a plan view, A semiconductor device in which the second pull-up electrode has a narrow-width portion narrower in width than the first pull-up electrode in a plan view. (Appendix 2) Comprising a plurality of the gate trenches, The semiconductor device according to appended claim 1, wherein the gate trench is connected to the first pull-up electrode via the second pull-up electrode. (Appended claim 3) The semiconductor device according to appended claim 1 or 2, wherein the pull-up electrode is formed at a terminal end of the groove. (Appended claim 4) The semiconductor device according to any one of appended claims 1 to 3, wherein the second pull-up electrode includes a narrow-width portion connected to the first pull-up electrode and a wide-width portion connected to the gate trench via the intermediate insulating film and wider than the narrow-width portion in plan view. (Appended claim 5) The semiconductor device according to any one of appended claims 1 to 3, wherein the second pull-up electrode includes the narrow-width portion and a connection portion that connects the narrow-width portion and the first pull-up electrode in an inclined or curved manner in plan view. (Appended claim 6) The semiconductor device according to appended claim 1 or 3, wherein the gate trench has a width equal to that of the narrow-width portion of the first pull-up electrode or the second pull-up electrode in plan view. (Appended claim 7) The gate trench includes two parallel gate trenches arranged in parallel in plan view, The semiconductor device according to appended claim 1, wherein the parallel gate trenches are connected to the pull-up electrode formed between the parallel gate trenches via the gate trench. (Appended claim 8) The semiconductor device according to appended claim 7, wherein a plurality of the gate trenches parallel to each other in plan view are connected to the pull-up electrode. (Appended claim 9) The semiconductor device according to any one of appended claims 1 to 8, wherein the semiconductor substrate is formed of a wide-bandgap semiconductor.

Explanation of reference numerals

[0057] 10 Semiconductor substrate 11 n-type drift layer 12 n-type carrier accumulation layer 13 p-type base layer 15 n-type buffer layer 16 p-type collector layer 21 upper electrode 22 lower electrode 23 p + -type layer region 24 n + -type emitter region 30 interlayer insulating film 31 insulating film 32 intermediate insulating film 33 insulating film 34 insulating film 41 contact via 42 contact via 51 emitter electrode 52 collector electrode 101 semiconductor device 102 active region 103 termination part 111 gate trench 112 first lifting electrode 113 second lifting electrode 114 groove 115 narrow part 116 wide part 117 connection part 123 lifting electrode 211 parallel gate trench 221 gate trench 223 gate trench

Claims

1. A semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, and an emitter region of the first conductivity type formed in an upper portion of the base layer; A gate insulating film formed on an inner wall of a groove that penetrates the emitter region and the base layer from a surface of the semiconductor substrate to reach the drift layer; A gate trench and a pull-up electrode formed on the gate insulating film inside the groove; An interlayer insulating film formed on the gate trench and the pull-up electrode; An emitter electrode formed on the semiconductor substrate and the interlayer insulating film and connected to the emitter region and the base layer; Comprising; The gate trench has a lower electrode formed inside the groove and an upper electrode formed on the lower electrode inside the groove with an intermediate insulating film therebetween; The pull-up electrode connects the lower electrode to the emitter electrode and is insulated from the upper electrode by the intermediate insulating film; The pull-up electrode has a first pull-up electrode connected to the emitter electrode through a contact via penetrating the interlayer insulating film, and a second pull-up electrode disposed between the first pull-up electrode and the gate trench in a direction in which the groove extends in a plan view; A semiconductor device in which the second pull-up electrode has a narrow-width portion narrower than the first pull-up electrode in a plan view.

2. Comprising a plurality of the gate trenches; The semiconductor device according to claim 1, wherein the gate trench is connected to the first pull-up electrode via the second pull-up electrode.

3. The semiconductor device according to claim 1 or 2, wherein the pull-up electrode is formed at a terminal end of the groove.

4. The semiconductor device according to claim 1 or 2, wherein the second pull-up electrode includes the narrow-width portion connected to the first pull-up electrode and a wide-width portion connected to the gate trench via the intermediate insulating film and wider than the narrow-width portion in a plan view.

5. The semiconductor device according to claim 1 or 2, wherein the second pull-up electrode includes the narrow-width portion and a connection portion connecting between the narrow-width portion and the first pull-up electrode in a plan view with an inclination or a curve.

6. The semiconductor device according to claim 1, wherein the gate trench has a width equal to the narrow-width portion of the first pull-up electrode or the second pull-up electrode in a plan view.

7. The gate trenches include two parallel gate trenches arranged in parallel in a plan view, The semiconductor device according to claim 1, wherein the parallel gate trenches are connected to the pull-up electrode formed between the parallel gate trenches via the gate trenches.

8. The semiconductor device according to claim 7, wherein a plurality of the gate trenches parallel to each other in a plan view are connected to the pull-up electrode.

9. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is formed of a wide bandgap semiconductor.

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