Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device capable of suppressing peeling of a sealant.SOLUTION: A semiconductor device 100 comprises: a base substrate 11; a wiring board 14 disposed on the base substrate 11; a copper wire 15 disposed on at least any one of a top face and a bottom face of the wiring board 14; a semiconductor chip 16 which is loaded on the wiring board 14; and a sealant 20 covering the base substrate 11, the wiring board 14, the copper wire 15 and the semiconductor chip 16. An anchor part 12 consisting of a recess directed from the top face toward the bottom face of the wiring board 14 outside of an end portion thereof is formed at a top face side of the base substrate 11, and the anchor part 12 is filled with the sealant 20.SELECTED DRAWING: Figure 1C

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In a semiconductor device, a semiconductor chip is encapsulated with resin to ensure heat resistance, pressure resistance, etc. In the semiconductor device of Patent Document 1, a structure capable of preventing peeling of the encapsulant is adopted in a termination region (a region for relaxing an electric field formed on the outer periphery of the semiconductor chip) on the end face side of the semiconductor chip. Specifically, the semiconductor device of Patent Document 1 includes an insulating resin layer, a stress relaxation resin layer, an adhesive resin layer, and an encapsulant. The insulating resin layer covers the termination region of the semiconductor chip. The stress relaxation resin layer covers from the surface of the semiconductor chip to the surface of the insulating resin layer and the end face of the semiconductor chip. The adhesive resin layer covers the entire surface of the stress relaxation resin layer from the surface of the semiconductor chip. The encapsulant encapsulates the semiconductor chip and the insulating resin layer. Further, the stress relaxation resin layer and the adhesive resin layer are provided between the insulating resin layer and the encapsulant. With such a configuration, the stress in the outer peripheral portion of the semiconductor chip is relaxed by the stress relaxation resin layer, and peeling between the encapsulant and the stress relaxation resin layer can be prevented by the adhesive resin layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the configuration of Patent Document 1, in order to prevent the peeling of the encapsulant, it is necessary to arrange a plurality of types of resin layers such as a stress relaxation resin layer and an adhesive resin layer at specific locations as described above. Therefore, it is complicated to select which resin to use for the encapsulant, the insulating resin layer, the stress relaxation resin layer, the adhesive resin layer, etc., and the manufacturing method for arranging each layer at a specific location is also complicated. Therefore, a separate configuration for preventing the peeling of the encapsulant is required. Therefore, the main object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of suppressing the peeling of the encapsulant.

Means for Solving the Problems

[0005] The semiconductor device according to the present invention includes a base substrate, a wiring substrate disposed on the base substrate, a copper wiring disposed on at least one of the upper and lower surfaces of the wiring substrate, a semiconductor chip mounted on the wiring substrate, and an encapsulant covering the base substrate, the wiring substrate, the copper wiring, and the semiconductor chip. On the upper surface side of the base substrate, an anchor portion formed of a recess extending from the upper surface to the lower surface outside the end portion of the wiring substrate is formed, and the anchor portion is filled with the encapsulant.

[0006] According to the above configuration, the anchor portion is formed on the base substrate, and the encapsulant is filled in the anchor portion. Then, the encapsulant (anchor encapsulant) in the portion filled in the anchor portion becomes a portion that locks the encapsulant (coating encapsulant) covering the base substrate, the wiring substrate, the copper wiring, and the semiconductor chip to the base substrate. Therefore, the adhesion (bonding strength) between the encapsulant and the base substrate can be improved, and the peeling of the encapsulant from the base substrate can be suppressed.

[0007] In the method for manufacturing the semiconductor device according to the present invention, a step of forming a concave first recess that forms part of the anchor portion by pressing the surface of the base substrate with a first mold, and a second mold that is slightly larger than the first recess is used to press the edge portion of the base substrate that is continuous with the outside of the first recess, thereby forming a concave second recess that is continuously formed above the first recess, is larger than the first recess in plan view, and forms part of the anchor portion.

[0008] According to the method for manufacturing the semiconductor device, by pressing with the second mold, the first recess is formed to be inclined toward the wiring substrate side from the upper surface to the lower surface of the base substrate. Therefore, the sealing material (anchor sealing material) in the portion filled in the anchor portion has a greater force to lock the sealing material (coating sealing material) covering the base substrate, the wiring substrate, the copper wiring, and the semiconductor chip to the base substrate. Therefore, the adhesion between the sealing material and the base substrate can be further improved, and the peeling of the sealing material from the base substrate can be further suppressed.

Effect of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress the peeling of the sealing material.

[0010] The above object, other objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments for carrying out the invention with reference to the drawings.

Brief Description of the Drawings

[0011]

Figure 1A

Figure 1B

Figure 1C

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Figure 21

Mode for Carrying Out the Invention

[0012] 1. Embodiment (1) Outline The outline of a first semiconductor device (an example of a semiconductor device) 100 according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a schematic plan view showing the first semiconductor device according to the embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line IB-IB of FIG. 1A. FIG. 1C is a cross-sectional view showing another aspect of FIG. 1B.

[0013] As shown in FIGS. 1A and 1B, the first semiconductor device 100 includes a first semiconductor unit 10 and a sealing material 20.

[0014] The first semiconductor unit 10 includes a base substrate 11, a copper wiring substrate 13, a semiconductor chip 16, and terminals 17.

[0015] The base substrate 11 is a plate-shaped substrate at the bottom of the first semiconductor unit 10, and the copper wiring substrate 13, the semiconductor chip 16, etc. are mounted thereon.

[0016] The copper wiring substrate 13 includes a wiring substrate 14 and copper wirings 15. The wiring substrate 14 is disposed on the base substrate 11 and is a substrate on which wirings such as the copper wirings 15 are arranged. The copper wiring substrate 13 is configured by forming the copper wirings 15 on at least one of the upper surface and the lower surface of the wiring substrate 14. In the present embodiment, a first copper wiring 15a is formed on the upper surface of the wiring substrate 14, and a second copper wiring 15b is formed on the lower surface of the wiring substrate 14. In the examples of FIGS. 1A and 1B, the first copper wiring 15a and the second copper wiring 15b are arranged on the wiring substrate 14 such that the ends of these copper wirings 15a and 15b are recessed inward from the ends of the wiring substrate 14. In other words, the ends of the wiring substrate 14 protrude outward from the ends of the copper wirings 15a and 15b.

[0017] Further, the semiconductor chip 16 is mounted on the copper wiring substrate 13 and is a functional part for causing the first semiconductor device 100 to perform a predetermined function. Various semiconductor elements such as MOS transistors, bipolar transistors, resistors, and capacitors are formed in the semiconductor chip 16.

[0018] The terminal 17 includes a wiring terminal 17a and a chip terminal 17b. One end of the wiring terminal 17a is electrically connected to the first copper wiring 15a. One end of the chip terminal 17b is electrically connected to the semiconductor chip 16. The other ends of the wiring terminal 17a and the chip terminal 17b are connected to an external device, and power and various control signals and the like are supplied from the external device to the semiconductor chip 16 and the copper wiring 15 through these terminals 17a and 17b.

[0019] The upper surface of the base substrate 11 and the lower surface of the copper wiring substrate 13 are joined via a first solder 31. The upper surface of the copper wiring substrate 13 and the wiring terminal 17a are joined via a second solder 32. The upper surface of the copper wiring substrate 13 and the lower surface of the semiconductor chip 16 are joined via a third solder 33. The upper surface of the semiconductor chip 16 and the chip terminal 17b are joined via a fourth solder 34.

[0020] A sealing material 20 is disposed so as to cover the first semiconductor unit 10. That is, the base substrate 11, the copper wiring substrate 13, the semiconductor chip 16, one end portion of the wiring terminal 17a, and one end portion of the chip terminal 17b are covered with the sealing material 20. The other end portions of the wiring terminal 17a and the chip terminal 17b are drawn out to the outside of the sealing material 20 so as to be connectable to an external device that supplies power and various control signals and the like.

[0021] In the present embodiment, on the upper surface side of the base substrate 11, a first anchor portion 12 (an example of an anchor portion), which is a recess extending from the upper surface side to the lower surface side outside the end portion of the wiring substrate 14 in a plan view, is formed. The first anchor portion 12 extends along the vertical direction from the upper surface to the lower surface of the base substrate 11 in a cross-sectional view. The inner surface in the first anchor portion 12 is substantially orthogonal to the surface of the base substrate 11. The sealing material 20 is filled in the first anchor portion 12 and extends upward from the portion filled in the first anchor portion 12 to cover a part of the base substrate 11, the wiring substrate 14, the copper wiring 15, the semiconductor chip 16, and the terminal 17. Hereinafter, the sealing material 20 in the portion filled in the first anchor portion 12 may be referred to as an anchor sealing material, and the sealing material 20 in the portion covering a part of the base substrate 11, the wiring substrate 14, the copper wiring 15, the semiconductor chip 16, and the terminal 17 may be referred to as a covering sealing material. The first anchor portion 12 may be partially formed at the outer peripheral portion of the copper wiring substrate 13 in a plan view, or may be formed so as to surround the entire outer peripheral portion of the copper wiring substrate 13.

[0022] According to the above configuration, the first anchor portion 12 is formed on the base substrate 11, and the sealing material 20 is filled in the first anchor portion 12. Then, the sealing material (anchor sealing material) in the portion filled in the first anchor portion 12 serves as a portion for locking the sealing material (coating sealing material) that covers the base substrate 11, the wiring substrate 14, the copper wiring 15, and the semiconductor chip 16 to the base substrate 11. Therefore, the adhesion (bonding strength) between the sealing material 20 and the base substrate 11 can be improved, and the peeling of the sealing material 20 from the base substrate 11 can be suppressed. As a result, since the sealing material 20 wraps the wiring substrate 14, the copper wiring 15, the semiconductor chip 16, etc. together with the base substrate 11, the adhesion between the wiring substrate 14, the copper wiring 15, etc. and the sealing material 20 can be improved. Therefore, the stress on the wiring substrate 14 due to the peeling of the sealing material 20 can be suppressed. In particular, as shown in FIGS. 1A and 1B, even when the end portion of the copper wiring 15 retreats inward from the end portion of the wiring substrate 14, that is, even when the end portion of the wiring substrate 14 protrudes from the end portion of the copper wiring 15, the breakage of the end portion of the wiring substrate 14 can be further suppressed. In other words, although stress is likely to be applied to the end portion of the wiring substrate 14 that protrudes from the end portion of the copper wiring 15, the breakage of the end portion can be further suppressed by suppressing the stress on the wiring substrate 14. Furthermore, peeling of the sealing material 20 from the wiring substrate 14, the semiconductor chip 16, the wiring terminal 17a, the chip terminal 17b, etc., breakage of the first solder 31 at the interface between the base substrate 11 and the copper wiring substrate 13, breakage of the second solder 32 at the interface between the copper wiring substrate 13 and the wiring terminal 17a, breakage of the third solder 33 at the interface between the semiconductor chip 16 and the copper wiring substrate 13, breakage of the fourth solder 34 at the interface between the semiconductor chip 16 and the chip terminal 17b, deterioration of the first semiconductor device 100 such as insulation failure can be suppressed.

[0023] Note that in the above, an example in which the ends of the first and second copper wirings 15a and 15b are recessed inward from the end of the wiring substrate 14 in FIGS. 1A and 1B has been described. However, any configuration that can suppress the peeling of the sealing material 20 from the base substrate 11 is acceptable. As shown in FIG. 1C, in the first semiconductor device (an example of a semiconductor device) 100 according to the embodiment of the present invention, the ends of the first copper wiring 15a, the ends of the second copper wiring 15b, and the end of the wiring substrate 14 may coincide in a cross-sectional view. Even in this case, the sealing material (anchor sealing material) in the portion filled with the first anchor portion 12 serves as a portion that locks the sealing material (coating sealing material) covering the base substrate 11, the wiring substrate 14, the copper wiring 15, and the semiconductor chip 16 to the base substrate 11. Therefore, the adhesion (bonding strength) between the sealing material 20 and the base substrate 11 can be improved, and the peeling of the sealing material 20 from the base substrate 11 can be suppressed.

[0024] (2) Specific embodiments (2-1) Configuration Hereinafter, the configuration of an example of a specific embodiment of a second semiconductor device (an example of a semiconductor device) 100a according to the embodiment of the present invention will be described. FIG. 2 is a perspective view showing an example of a specific embodiment of the second semiconductor device according to the embodiment of the present invention. FIG. 3 is a perspective view of the second semiconductor device in FIG. 2 with the top plate removed. FIG. 4 is a side view of the second semiconductor unit and the sealing material in a state where the terminals in FIG. 3 are omitted. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 3. FIG. 6 is a top view of the second semiconductor unit. In the description of the second semiconductor device 100a, the description of the same configuration as that of the first semiconductor device 100 above will be omitted or simplified.

[0025] In FIGS. 2 and the like, the side where the terminal 17 is exposed in the second semiconductor device 100a is set as the top, the back surface of the second semiconductor device 100a is set as the bottom, and the vertical direction is the x direction. Also, the short side direction of the second semiconductor device 100a is the width direction y, and the direction orthogonal to the vertical direction x and the width direction y is the length direction z.

[0026] The second semiconductor device 100a includes a main body case 101, a top plate 102, a second semiconductor unit 10a, and a sealing material 20. The main body case 101 has a cavity inside and is open downward. By covering the second semiconductor unit 10a and the sealing material 20 from above with the main body case 101, the second semiconductor unit 10a and the sealing material 20 are stored in the cavity inside the main body case 101. And the opening below the main body case 101 is sealed by the second semiconductor unit 10a. Further, on the upper part of the main body case 101, a top plate opening 101a that opens upward and a terminal opening 101b that opens upward are formed. The top plate opening 101a is sealed by the top plate 102. Terminals 17 (chip terminals 17b connected to the semiconductor chip 16, wiring terminals, etc.) protrude upward from the sealing material 20, and the upper ends of the terminals 17 are exposed in the terminal opening 101b as shown in FIG. 2.

[0027] The second semiconductor unit 10a includes a base substrate 11, a DBC (Direct Bonding Copper) substrate 13a, a semiconductor chip 16, and terminals 17.

[0028] The base substrate 11 is a plate-shaped substrate at the bottom of the second semiconductor unit 10a, and the DBC substrate 13a, the semiconductor chip 16, etc. are mounted thereon. Examples of the constituent material of the base substrate 11 include copper (Cu), iron (Fe), etc.

[0029] The DBC substrate 13a includes a ceramic substrate (an example of a wiring substrate) 14a and copper wirings 15. The ceramic substrate 14a is disposed on the base substrate 11 and is a substrate on which wirings such as the copper wirings 15 are disposed. Examples of the material of the ceramic substrate 14a include silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), alumina (Al 2 O 3) etc. can be adopted. By forming the first copper wiring 15a on the upper surface of the ceramic substrate 14a and the second copper wiring 15b on the lower surface, the DBC substrate 13a is configured. In the example of FIG. 5 etc., the first copper wiring 15a and the second copper wiring 15b are arranged on the ceramic substrate 14a such that the ends of these copper wirings 15a, 15b are positioned retreating inward from the ends of the ceramic substrate 14a. In other words, the ends of the ceramic substrate 14a protrude outward from the ends of the copper wirings 15a, 15b. Note that it is sufficient if the copper wiring 15 is formed on at least either the upper surface or the lower surface of the ceramic substrate 14a. Also, in the example of FIG. 5 etc., the ends of the first copper wiring 15a and the ends of the second copper wiring 15b coincide in a cross-sectional view.

[0030] On the upper surface side of the base substrate 11, a second anchor portion 12a (an example of an anchor portion), which is a recess extending from the upper surface side to the lower surface side outside the end of the ceramic substrate 14a in a plan view, is formed. Different from the first anchor portion 12, the second anchor portion 12a is inclined toward the inner side of the base substrate 11 as it goes from the upper surface to the lower surface of the base substrate 11. This second anchor portion 12a has a first recess 121a and a second recess 121b. The first recess 121a is the recess located below in the second anchor portion 12a. The first recess 121a is inclined toward the ceramic substrate 14a side as it goes from the upper surface to the lower surface of the base substrate 11 in a cross-sectional view. That is, the first recess 121a is inclined toward the inner side of the base substrate 11 as it goes from the upper surface to the lower surface of the base substrate 11. In this case, at least in the first recess 121a, the inner inclined surface IS on the ceramic substrate 14a side is inclined toward the inner side of the base substrate 11 as it goes from the upper surface to the lower surface of the base substrate 11. It is preferable that the inner angle θa formed by the inner inclined surface IS on the ceramic substrate 14a side and the bottom surface BS is less than 90°. More preferably, the inner angle θa is 75° or more and less than 90°. The second recess 121b is formed continuously above the first recess 121a and is a recess larger than the first recess 121a in a plan view.

[0031] As shown in FIG. 6, the second anchor portion 12a is formed so as to surround the entire circumference of the outer peripheral portion of the DBC substrate 13a in plan view.

[0032] The sealing material 20 is disposed on the base substrate 11. The sealing material 20 has a portion filled in the second anchor portion 12a (anchor sealing material) and a portion extending upward from the anchor sealing material to cover a part of the base substrate 11, the DBC substrate 13a, the semiconductor chip 16, and the terminal 17 (coating sealing material). As the sealing material 20, an epoxy resin is used. Here, it is preferable that the relationship is such that the coefficient of linear expansion of the base substrate 11 > the coefficient of linear expansion of the epoxy resin of the sealing material 20 > the coefficient of linear expansion of the ceramic substrate 14a.

[0033] The second anchor portion 12a having the first recess 121a and the second recess 121b is manufactured as follows. In FIG. 7, (a) to (c) are schematic cross-sectional views sequentially showing an example of a manufacturing method of the second anchor portion having the first recess and the second recess.

[0034] As shown in FIG. 7(a), a first mold 51 for forming the first recess 121a is disposed at a position for forming the first recess 121a of the second anchor portion 12a outside the DBC substrate 13a on the base substrate 11. The first mold 51 is advanced toward the base substrate 11, and the base substrate 11 is pressed by the first mold 51. As a result, as shown in FIG. 7(b), the first recess 121a is formed in the base substrate 11. The first recess 121a is formed such that the depth h1 of the first stage is, for example, about half (h1 = t / 2) with respect to the thickness t of the base substrate 11. When the first recess 121a is formed, it is preferable that the thickness t of the base substrate 11 does not change due to the pressing by the first mold 51.

[0035] Next, as shown in FIG. 7(c), a second mold 52 for forming the second recess 121b is disposed at a position on the second anchor portion 12a where the second recess 121b is formed. The width 52w of the second mold 52 is larger than the width 51w of the first mold 51. The second mold 52 is disposed on the first recess 121a so as to cover the first recess 121a in a top view. The second mold 52 is advanced toward the base substrate 11, and the base substrate 11 on the edge of the first recess 121a is pressed by the second mold 52. As a result, a second recess 121b continuous above the first recess 121a is formed. The second recess 121b is formed such that the depth h2 of its second stage is part of the depth h1 of the first stage of the first recess 121a. The second recess 121b formed in this way has an inner collapsed surface 121b1 exposed on the upper surface on the DBC substrate 13a side with respect to the first recess 121a, and an outer collapsed surface 121b2 exposed on the upper surface on the side away from the DBC substrate 13a with respect to the first recess 121a. Further, due to the pressing by the second mold 52, the first recess 121a is formed to be inclined toward the DBC substrate 13a as it goes from the upper surface to the lower surface of the base substrate 11. In this way, the first recess 121a and the second recess 121b continuous above the first recess 121a are formed. Even when the second recess 121b is formed, it is preferable that the thickness t of the base substrate 11 does not change due to the pressing by the second mold 52.

[0036] (2-2) Function and effect According to the above configuration, the second anchor portion 12a is formed on the base substrate 11, and the epoxy resin is filled in the second anchor portion 12a as the sealing material 20. Then, the epoxy resin (anchor sealing material) in the portion filled in the second anchor portion 12a becomes a portion that locks the epoxy resin (coating sealing material) covering the base substrate 11, the DBC substrate 13a, the semiconductor chip 16, etc. to the base substrate 11. Therefore, the adhesion between the epoxy resin and the base substrate 11 can be improved, and the epoxy resin can be prevented from peeling off from the base substrate 11. As a result, since the epoxy resin wraps the ceramic substrate 14a, the copper wiring 15, the semiconductor chip 16, etc. together with the base substrate 11, the adhesion between the ceramic substrate 14a, the copper wiring 15, etc. and the epoxy resin can be improved. Therefore, the stress on the ceramic substrate 14a due to the peeling of the epoxy resin can be suppressed, and the breakage of the ceramic substrate 14a, etc., particularly the breakage of the end portion protruding from the end portion of the copper wiring 15 in the ceramic substrate 14a, can be further suppressed. Furthermore, the peeling of the epoxy resin from the DBC substrate 13a, the semiconductor chip 16, the wiring terminal, the chip terminal 17b, etc., the breakage of the first solder 31 at the interface between the base substrate 11 and the DBC substrate 13a, the breakage of the solder at the interface between the DBC substrate 13a and the wiring terminal, the breakage of the third solder 33 at the interface between the DBC substrate 13a and the semiconductor chip 16, the breakage of the fourth solder 34 at the interface between the semiconductor chip 16 and the chip terminal 17b, and the deterioration of the second semiconductor device 100a such as insulation failure can be suppressed. This will be described in more detail below.

[0037] (Effect from the perspective of the epoxy direct structure) In Fig. 8, (a) is a schematic plan view schematically showing a third semiconductor device having a two-layer sealing material, and (b) is a cross-sectional view taken along line VIIIb-VIIIb of (a). In recent years, the adoption of a DBC substrate 13a in which a copper wiring 15 is formed on a ceramic substrate 14a made of ceramic has been spreading. By using the copper wiring 15, the electrical resistance can be lowered and the wiring delay can be suppressed. A sealing material 2 for sealing the DBC substrate 13a in the third semiconductor device 1 is formed of two layers, a silicone gel excellent in adhesion, heat resistance, insulation properties, etc., and an epoxy resin with little deterioration in H / C test (temperature cycle test), P / C test (power cycle test), etc., and this configuration is being studied.

[0038] Specifically, referring to Figs. 8(a) and 8(b), the third semiconductor device 1 includes a third semiconductor unit 1a and a sealing material 2. The third semiconductor unit 1a includes a base substrate 11, a DBC substrate 13a, a semiconductor chip 16, and terminals 17.

[0039] The base substrate 11 is a plate-shaped substrate at the bottom of the third semiconductor unit 1a, and the DBC substrate 13a, the semiconductor chip 16, etc. are mounted thereon. An anchor portion (including a first anchor portion 12 and a second anchor portion 12a) is not formed on the base substrate 11 of the third semiconductor device 1. The DBC substrate 13a includes a ceramic substrate 14a and a copper wiring 15. The copper wiring 15 includes a first copper wiring 15a formed on the upper surface of the ceramic substrate 14a and a second copper wiring 15b formed on the lower surface of the ceramic substrate 14a. The first copper wiring 15a and the second copper wiring 15b are arranged on the ceramic substrate 14a such that the ends of these copper wirings 15a and 15b are recessed inward from the ends of the ceramic substrate 14a.

[0040] The sealing material 2 includes a first sealing material 2a of the first layer which is a silicone gel, and a second sealing material 2b of the second layer which is an epoxy resin formed on the upper part of the first sealing material 2a. The first sealing material 2a which is a silicone gel seals the DBC substrate 13a, the semiconductor chip 16, etc., and the second sealing material 2b which is an epoxy resin of the second layer seals a part of the wiring terminal 17a, the chip terminal 17b (terminal 17), etc.

[0041] However, when the sealing material 2 has a two-layer structure, it is necessary to cover the DBC substrate 13a, the semiconductor chip 16, the terminal 17, etc. with the first-layer silicone gel and form the second-layer epoxy resin so as to cover the first-layer silicone gel. Therefore, the sealing process is complicated.

[0042] Furthermore, according to the present inventors, even when an epoxy resin with less deterioration in temperature cycle tests, power cycle tests, etc. is added to the silicone gel and used as a sealing material, it has been found that it is difficult to suppress the deterioration of the silicone gel in temperature cycle tests, power cycle tests, etc. That is, when the sealing material 20 contains a silicone gel, deterioration such as peeling of the silicone gel, destruction of the solder, and destruction of the ceramic substrate 14a has occurred due to the generation of cracks in the silicone gel. As a result, there was a possibility that the third semiconductor device 1 would have an insulation breakdown.

[0043] Therefore, the present inventors considered using a single-layer epoxy resin with less deterioration in temperature cycle tests, power cycle tests, etc. as the sealing material in order to simplify the sealing process and suppress the insulation breakdown of the semiconductor device. The configuration in which this single-layer epoxy resin is used as the sealing material of the semiconductor device is called an epoxy direct structure.

[0044] However, the inventors have found that even in this epoxy direct structure, especially when a temperature cycle test is performed, the epoxy resin peels off from the base substrate 11 or the like, and as a result, the ceramic substrate 14a is broken. In particular, in the case of the DBC substrate 13a on which the copper wiring 15 is formed, when the DBC substrate 13a is cut and the cut copper wiring 15 adheres to the ceramic substrate 14a, insulation failure may occur in the DBC substrate 13a. Therefore, in the DBC substrate 13a, the copper wiring 15 is formed at a position recessed from the end of the ceramic substrate 14a. Thereby, when cutting the semiconductor device, by cutting the DBC substrate 13a at a position where the copper wiring 15 is not formed, it is possible to suppress the copper wiring 15 from being cut and to suppress the cut copper wiring 15 from adhering to the ceramic substrate 14a. However, since it is formed at a position where the copper wiring 15 is recessed from the end of the ceramic substrate 14a in this way, especially the strength of the end of the ceramic substrate 14a where the copper wiring 15 is not formed becomes small, and thus the ceramic substrate 14a is easily broken when the epoxy resin peels off from the base substrate 11 or the like. Also, the amount of deformation of the copper wiring 15 with respect to temperature changes in the manufacturing process of the semiconductor device is larger than the amount of deformation of the epoxy resin and the ceramic substrate 14a or the like. Therefore, when the epoxy resin peels off from the base substrate 11 or the like, the copper wiring 15, which is easily deformed, and the ceramic substrate 14a cannot be held in a state of being adhered by the epoxy resin, and the adhesion between the copper wiring 15 and the ceramic substrate 14a decreases. Therefore, deterioration such as the copper wiring 15 peeling off from the ceramic substrate 14a occurs. An example of the copper wiring 15 peeling off from the ceramic substrate 14a will be further described below.

[0045] In the third semiconductor device 1 shown in FIGS. 8(a) and 8(b), for example, assume that the constituent material of the base substrate 11 is Cu. When a temperature cycle test is performed on this third semiconductor device 1, the base substrate 11 made of Cu is likely to be deformed into a warped state including concave warping and convex warping in the horizontal direction due to thermal contraction. The concave warping is the warping of the base substrate 11 in a direction where the side on which the DBC substrate 13a is disposed is concave. The convex warping is the warping of the base substrate 11 in the direction opposite to the concave warping. On the other hand, the epoxy resin is less likely to be deformed than the base substrate 11. Therefore, the stress due to the warping of the base substrate 11 is likely to concentrate, for example, on the solder 31. And, for example, when the joining at the interface between the solder 31 and the base substrate 11 or the joining at the interface between the solder 31 and the second copper wiring 15b becomes larger than the joining at the interface between the ceramic substrate 14a and the second copper wiring 15b, the second copper wiring 15b and the ceramic substrate 14a are peeled off from each other. In this case, the support of the ceramic substrate 14a by the second copper wiring 15b becomes small, and as described above, the strength of the end portion of the ceramic substrate 14a where the copper wiring 15 is not formed becomes particularly small. Therefore, when the epoxy resin peels off from the base substrate 11 or the like, the ceramic substrate 14a is likely to be broken.

[0046] In the second semiconductor device 100a in the above-described embodiment, the second anchor portion 12a is provided on the base substrate 11 in the epoxy direct structure. Then, since the epoxy resin is filled in the second anchor portion 12a, the epoxy resin (anchor sealing material) in the portion filled in the second anchor portion 12a serves as a portion for locking the epoxy resin (coating sealing material) covering the base substrate 11, the DBC substrate 13a, the copper wiring 15, the semiconductor chip 16, etc. to the base substrate 11. Therefore, the adhesion between the epoxy resin and the base substrate 11 can be improved, so that the epoxy resin can be prevented from peeling off from the base substrate 11, and the breakage of the ceramic substrate 14a and solder can also be suppressed. In this case, it is considered that the deformation of the epoxy resin can follow the deformation of the base substrate 11 by locking the epoxy resin to the second anchor portion 12a. And it is considered that the epoxy resin holds the ceramic substrate 14a etc. together with the base substrate 11, and the epoxy resin peeled off from the base substrate 11 can reduce stress applied to the ceramic substrate 14a and solder etc. Thereby, it is considered that the breakage of the ceramic substrate 14a and solder etc. can also be suppressed as described above. From the above, the deterioration of the second semiconductor device 100a adopting the epoxy direct structure can be suppressed. Also, in the epoxy direct structure, since the sealing material 20 can be formed of the epoxy resin, the manufacturing process can be simplified compared with the case where a plurality of layers of resin are used as the sealing material. Also, as described above, since the stress on the ceramic substrate 14a can be suppressed, even when the ends of the copper wirings 15a and 15b are located retracted inward from the ends of the ceramic substrate 14a, the breakage of the ends of the ceramic substrate 14a can be more suppressed.

[0047] Also, the epoxy resin tends to deteriorate less in terms of the occurrence of cracks in temperature cycle tests, power cycle tests, etc. than resins such as silicone gel. Therefore, the deterioration of the second semiconductor device 100a can also be suppressed by using the epoxy resin as the sealing material 20.

[0048] (Effect from the point that the second anchor portion is inclined) In the second semiconductor device 100a, as described above, the first recess 121a is inclined toward the ceramic substrate 14a side from the upper surface to the lower surface of the base substrate 11 in a cross-sectional view. Therefore, the anchor sealing material in the portion filled with the second anchor portion 12a is in a state of holding the base substrate 11. Thus, the force for locking the coating sealing material continuous with the upper portion of the anchor sealing material to the base substrate 11 can be increased. Thus, the adhesion between the sealing material 20 and the base substrate 11 can be further improved, and the peeling of the sealing material 20 from the base substrate 11 can be further suppressed. As a result, the adhesion between the ceramic substrate 14a, the copper wiring 15, etc. and the sealing material 20 can also be further improved.

[0049] Also, in the second semiconductor device 100a, as described above, the inner angle θa of the first recess 121a is less than 90°, and more preferably, the inner angle θa can be formed to be 75° or more and less than 90°. In this case, the force for the anchor sealing material to hold the base substrate 11 can be increased. Thus, the adhesion between the sealing material 20 and the base substrate 11 can be further improved.

[0050] (Effect from the point that the second anchor portion is formed on the entire circumference of the DBC substrate) Also, in the second semiconductor device 100a, the second anchor portion 12a is formed so as to surround the entire outer peripheral portion of the DBC substrate 13a. Since the DBC substrate 13a etc. are covered while the sealing material 20 is filled in the second anchor portion 12a, it is possible to suppress moisture from entering from the outside of the sealing material 20 to the inside of the sealing material 20 at the entire circumference of the DBC substrate 13a. Thus, the moisture resistance reliability of the second semiconductor device 100a can be improved.

[0051] (Effect from the relationship between the linear expansion coefficients of the base substrate, the epoxy resin, and the ceramic substrate) Also, in the second semiconductor device 100a, it can be set such that the linear expansion coefficient of the base substrate 11 > the linear expansion coefficient of the epoxy resin of the sealing material 20 > the linear expansion coefficient of the ceramic substrate 14a. In this relationship, the linear expansion coefficients of the base substrate 11, the epoxy resin as the sealing material 20, and the ceramic substrate 14a can be balanced. Therefore, the occurrence of cracks in the ceramic substrate 14a, the epoxy resin as the sealing material 20, and solder or the like can be suppressed.

[0052] For example, when in the relationship where the linear expansion coefficient of the epoxy resin > the linear expansion coefficient of the base substrate 11 > the linear expansion coefficient of the ceramic substrate 14a, the difference between the linear expansion coefficient of the epoxy resin and the linear expansion coefficient of the ceramic substrate 14a tends to be large. Therefore, in temperature cycle tests, power cycle tests, etc., the amount of deformation of the epoxy resin becomes larger than the amount of deformation of the ceramic substrate 14a. Thus, the deformation of the ceramic substrate 14a cannot follow the deformation of the epoxy resin, and cracks may occur in the ceramic substrate 14a.

[0053] On one hand, by setting the linear expansion coefficient relationship as the linear expansion coefficient of the base substrate 11 > the linear expansion coefficient of the epoxy resin of the sealing material 20 > the linear expansion coefficient of the ceramic substrate 14a, it is possible to make the difference between at least the linear expansion coefficient of the epoxy resin and the linear expansion coefficient of the ceramic substrate 14a smaller. As a result, the difference between the deformation amount of the epoxy resin and the deformation amount of the ceramic substrate 14a in temperature cycle tests, power cycle tests, etc. can be made smaller, and at least either the occurrence of cracks in the ceramic substrate 14a or the occurrence of cracks in the epoxy resin can be suppressed. Here, in the second semiconductor device 100a, a second anchor portion 12a is provided on the base substrate 11, and the anchor sealing material filled in the second anchor portion 12a firmly adheres the coating sealing material of other portions to the base substrate 11. Therefore, although the deformation amount of the base substrate 11 is larger than the deformation amount of the epoxy resin in the above linear expansion coefficient relationship, the deformation of the epoxy resin can follow the deformation of the base substrate 11. Therefore, it is possible to suppress the epoxy resin from peeling off from the base substrate 11, and thus it is possible to suppress the stress on the ceramic substrate 14a and solder, etc. caused by the peeling of the epoxy resin. As a result, at least either the occurrence of cracks in the ceramic substrate 14a or the occurrence of cracks in the solder can be suppressed.

[0054] In particular, since the end portion of the ceramic substrate 14a protrudes outside the copper wiring 15, it is likely to be stressed in temperature cycle tests, power cycle tests, etc. However, by setting the linear expansion coefficient to the above relationship, the stress related to the end portion of the ceramic substrate 14a can be suppressed, and the occurrence of cracks, etc. at the end portion of the ceramic substrate 14a can be suppressed.

[0055] From the above, according to the above linear expansion coefficient relationship, the deterioration of the semiconductor device can be further suppressed, and the long life of the semiconductor device can be achieved.

[0056] Incidentally, as an example, the linear expansion coefficient of the epoxy resin can be about 12, the linear expansion coefficient of the base substrate 11 can be greater than that of the epoxy resin and about 18, and the linear expansion coefficient of the ceramic substrate 14a can be smaller than that of the epoxy resin and about 7.

[0057] (Effect from the point of adopting a ceramic substrate) In addition, in the second semiconductor device 100a, a ceramic substrate 14a is adopted. The ceramic substrate 14a is superior in substrate strength, insulation property, etc. at high temperatures and the like compared with a conventional organic printed circuit board. Further, the ceramic substrate 14a can be formed from an inorganic material which is a decarbonized material, and the environmental load can be suppressed.

[0058] (Effect in the manufacturing method of the second anchor portion) In addition, in the second semiconductor device 100a, after forming the first recess 121a, the second recess 121b is formed by pressing an edge continuous with the outside of the first recess 121a by the second mold 52. In the process of forming this second recess 121b, the first recess 121a can be formed so as to incline toward the ceramic substrate 14a as it goes from the upper surface to the lower surface of the base substrate 11. Thereby, the force by which the anchor sealing material in the portion filled in the second anchor portion 12a locks the coating sealing material in other portions to the base substrate 11 can be made larger. Therefore, the adhesion between the sealing material 20 and the base substrate 11 can be further improved, and the peeling of the sealing material 20 from the base substrate 11 can be further suppressed.

[0059] Incidentally, the above-described second semiconductor device (an example of a semiconductor device) 100a adopts an epoxy direct structure, and mainly described that an epoxy resin is used as the sealing material 20. However, the sealing material 20 is not limited to an epoxy resin, and for example, a thermosetting resin such as a phenol resin or a melamine resin can be used. Here, it is preferable that the linear expansion coefficient of the base substrate 11 > the linear expansion coefficient of various sealing materials 20 including the epoxy resin > the linear expansion coefficient of the ceramic substrate 14a.

[0060] (2-3) Other configurations The second semiconductor device 100a further includes a snap fit 60 for suppressing the lifting of the terminal 17, and a case locking portion 110 for fixing the base substrate 11 and the main body case 101. Each will be described below.

[0061] (2-3-1) Snap fit FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 2. The terminal 17 electrically connects the DBC substrate 13a, the semiconductor chip 16, etc. to an external device. In the case of FIG. 9, the terminal 17 is connected to the DBC substrate 13a. In the process of connecting the terminal 17 to the DBC substrate 13a, first, the terminal 17 is inserted into the main body case 101 from the upper part of the main body case 101 through the terminal opening 101b. In this case, the terminal 17 falls downward due to free fall by its own weight. Then, the terminal connection portion 173, which is the tip of the terminal 17, comes into contact with the DBC substrate 13a. When the connection between the terminal connection portion 173 and the DBC substrate 13a by solder 35 is performed later, since the terminal 17 is not fixed, the terminal 17 may lift upward from the main body case 101. The snap fit 60 suppresses this lifting of the terminal 17 from the main body case 101. The snap fit 60 is formed by being connected to the main body case 101. Then, by locking a part of the snap fit 60 to the terminal locking opening 174 of the terminal 17, the lifting of the terminal 17 from the main body case 101 is suppressed. This will be further specifically described below.

[0062] In the present embodiment, the snap fit 60 has a main body portion 60b, a head portion 60a continuous with the upper part of the main body portion 60b, and a foot portion 60c continuous with the lower part of the main body portion 60b.

[0063] Here, the terminal 17 has a horizontal terminal upper surface 171 exposed from the terminal opening 101b, a terminal vertical portion 172 extending downward in the vertical direction from the end of the terminal upper surface 171, and a terminal connection portion 173 connected from the terminal vertical portion 172 to a connection target, here the DBC substrate 13a. A terminal fixing opening 174 that penetrates the terminal vertical portion 172 in the horizontal direction, that is, from the inner surface 172a to the outer surface 172b, is formed in the terminal vertical portion 172.

[0064] The main body portion 60b of the snap fit 60 extends in the vertical direction along the inner surface 172a of the terminal vertical portion 172, and the snap fit 60 is arranged such that the outer surface of the main body portion 60b contacts the inner surface 172a of the terminal vertical portion 172. The head portion 60a is connected to the upper end of the main body portion 60b and extends in a direction away from the inner surface 172a, and is connected to the main body case 101. That is, the snap fit 60 is fixed to the main body case 101 via the head portion 60a. Further, the main body portion 60b is formed to have elasticity in the horizontal direction (the y direction in FIG. 9) with respect to the head portion 60a. The foot portion 60c is connected to the lower end of the main body portion 60b and extends toward the side approaching the inner surface 172a. When the snap fit 60 is arranged at a predetermined position, the foot portion 60c is inserted into the terminal fixing opening 174. In this way, with the head portion 60a of the snap fit 60 fixed to the main body case 101, the foot portion 60c is inserted into the terminal fixing opening 174 of the terminal 17. Therefore, the vertical movement of the terminal 17 is restricted by the foot portion 60c, and the lifting of the terminal 17 from the main body case 101 is suppressed. Thereafter, as shown in FIG. 9, the terminal connection portion 173 can be connected to the DBC substrate 13a via the solder 35.

[0065] Note that the terminal fixing opening 174 is formed larger than the foot portion 60c. The terminal fixing opening 174 is designed such that the foot portion 60c can move slightly within the terminal fixing opening 174 when the snap fit 60 is arranged at a predetermined position. Further, since the main body portion 60b has elasticity in the horizontal direction, the foot portion 60c can be inserted into the terminal fixing opening 174 while positioning the main body portion 60b in a horizontal state.

[0066] (2-3-2) Case locking part FIG. 10 is a rear view of the second semiconductor device in FIG. 2. FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 10. As shown in FIGS. 10 and 11, the end of the base substrate 11 in the longitudinal direction z faces the main body case 101. The base substrate 11 has a base substrate corner 11a extending along the width direction y at the end facing the main body case 101. The base substrate corner 11a is formed so as to notch the corner of the base substrate 11.

[0067] Further, on the back surface of the main body case 101, in a part of the portion facing the base substrate corner 11a, in the central portion in the width direction y in the present embodiment, a concave locking recess 111 is formed. A case locking portion 110 rising from the locking recess 111 is formed in the locking recess 111. In a state where the main body case 101 and the base substrate 11 on which the DBC substrate 13a and the like are mounted are combined, the case locking portion 110 is melted by, for example, ultrasonic welding. The melted case locking portion 110 flows into the base substrate corner 11a. Thereafter, by being cooled, the case locking portion 110 locks to the base substrate corner 11a in a state of being connected to the main body case 101. Thereby, the base substrate 11 and the main body case 101 are fixed. Note that the locking recess 111 may be formed in the main body case 101 over the entire portion facing the base substrate corner 11a. And the case locking portion 110 may be formed over the entire y direction in the locking recess 111.

[0068] 2. Experimental examples The experimental examples of the present invention will be described. As experimental examples, Experimental examples 1 and 2 were conducted. In Experimental example 1, an H / C test was performed using a first semiconductor device having a first anchor portion, a second semiconductor device having a second anchor portion, and a semiconductor device having a base substrate with a roughened surface. In Experimental example 2, a test was performed to confirm the state of solder deterioration in a second semiconductor device having second anchor portions of various shapes.

[0069] (1) Experimental example 1 A. Preparation of Samples In Experimental Example 1, three types of samples, namely Example 1-1, Example 1-2, and Comparative Example 1-1, were prepared. In FIG. 12, (a) is a schematic plan view of the base substrate of the first semiconductor device according to Example 1-1, and (b) is a cross-sectional view taken along line XIIb-XIIb of the first semiconductor device in which a copper wiring substrate or the like is mounted on the base substrate of (a). In FIG. 13, (a) is a schematic plan view of the base substrate of the second semiconductor device according to Example 1-2, and (b) is a cross-sectional view taken along line XIIIb-XIIIb of the second semiconductor device in which a DBC substrate or the like is mounted on the base substrate of (a). FIG. 14 is a photograph showing the surface state of the base substrate of the semiconductor device according to Comparative Example 1-1.

[0070] In the sample of Example 1-1, a first semiconductor device having a first semiconductor unit 10 shown in FIG. 12(b) was prepared. A plurality of first anchor portions 12 were formed on the base substrate 11 of the first semiconductor unit 10. In Example 1-1, the first anchor portions 12 extend in the vertical direction and are formed in a hole shape, and are not inclined in the vertical direction. Further, the plurality of first anchor portions 12 having a hole shape are arranged in the longitudinal direction at both longitudinal ends of the base substrate 11. The sealing material 20 is filled in the plurality of first anchor portions 12 and covers the base substrate 11, the wiring substrate 14, the copper wirings 15a, 15b, etc.

[0071] In the sample of Example 1-2, a second semiconductor device having a second semiconductor unit 10a shown in FIG. 13(b) was prepared. A second anchor portion 12a was formed on the base substrate 11 of the second semiconductor unit 10a. In the sample of Example 1-2, the second anchor portion 12a extends in the longitudinal direction along both longitudinal edges of the base substrate 11. The second anchor portion 12a has a first recess 121a and a second recess 121b. The first recess 121a is inclined toward the ceramic substrate 14a side from the upper surface to the lower surface of the base substrate 11. The sealing material 20 is filled in the second anchor portion 12a and covers the base substrate 11, the ceramic substrate 14a, the copper wirings 15a, 15b, etc.

[0072] For the sample of Comparative Example 1-1, a semiconductor device having a base substrate with the surface state shown in FIG. 14 was prepared. The photograph in FIG. 14 shows the surface of the base substrate 11 photographed at a magnification of 5000 times. As shown in FIG. 14, the surface of the base substrate 11 has been subjected to a plating process so as to have uneven protrusions. No anchor portion is formed on the base substrate 11. Although not shown, a ceramic substrate, copper wiring, etc. are formed on the base substrate 11, and a sealing material covers the base substrate, the ceramic substrate, the copper wiring, etc.

[0073] B. Evaluation of Samples For each of the samples of Example 1-1, Example 1-2, and Comparative Example 1-1, an H / C test was performed at -40° for 1 hour and at 125° for 1 hour as one cycle, and the number of cycles until defects such as peeling of the sealing material and breakage of the wiring substrate occurred was counted. When a defect occurred, it was judged as "NG", and when no defect occurred, it was judged as "OK". The H / C test was performed on 36 samples in Example 1-1, 3 samples in Example 1-2, and 6 samples in Comparative Example 1, respectively.

[0074] Table 1 shows the results of the H / C test in Example 1-1, Example 1-2, and Comparative Example 1-1.

[0075]

Table 1

[0076] In Comparative Example 1-1, a defect occurred at 50 cyc, in Example 1-1, a defect occurred at 100 cyc, and in Example 1-2, a defect occurred at 350 cyc.

[0077] From this result, in the semiconductor device of Comparative Example 1-1 in which the surface of the base substrate 11 was subjected to an uneven plating process, defects such as breakage of the ceramic substrate occurred, and it is considered that the adhesion between the base substrate 11 and the sealing material 20 was weak.

[0078] Also, in the first semiconductor device of Example 1-1 having the first anchor portion 12 with a hole shape, it is considered that the adhesion between the base substrate 11 and the sealing material 20 is improved compared to the semiconductor device of Comparative Example 1-1. Therefore, by forming the first anchor portion 12 on the base substrate 11, it was found that the adhesion between the base substrate 11 and the sealing material 20 can be improved compared to the case where no anchor portion is provided on the base substrate 11.

[0079] Also, in the second semiconductor device of Example 1-2 having the second anchor portion 12a, it is considered that the adhesion between the base substrate 11 and the sealing material 20 is improved compared to the semiconductor devices of Comparative Example 1-1 and Example 1-1. In particular, the second semiconductor device (Example 1-2) having the inclined second anchor portion 12a had the number of cycles until failure increased by about three times compared to the first semiconductor device (Example 1-1) having the non-inclined first anchor portion 12. Therefore, by forming the inclined second anchor portion 12a on the base substrate 11, it was found that the adhesion between the base substrate 11 and the sealing material 20 can be significantly improved compared to the case where the non-inclined first anchor portion 12 is provided on the base substrate 11.

[0080] (2) Experimental Example 2 A. Preparation of Samples In Experimental Example 2, seven types of samples of Examples 2-1 to 2-6 and Comparative Example 2-1 were prepared. FIG. 15 is a cross-sectional view of the base substrate in Example 2-1. FIG. 16 is a cross-sectional view of the base substrate in Example 2-2. FIG. 17 is a cross-sectional view of the base substrate in Example 2-3. FIG. 18 is a cross-sectional view of the base substrate in Example 2-4. FIG. 19 is a cross-sectional view of the base substrate in Example 2-5. FIG. 20 is a cross-sectional view of the base substrate in Example 2-6. FIG. 21 is a cross-sectional view of the base substrate in Comparative Example 2-1.

[0081] In each of the samples of Example 2-1 and 2-2, a second semiconductor device was prepared using a base substrate 11 having a second anchor portion 12a shown in FIGS. 15 and 16. The second anchor portion 12a shown in FIGS. 15 and 16 has a first recess 121a and a second recess 121b, and the inner angle θa on the ceramic substrate side of the first recess 121a is less than 90°. In the sample of Example 2-3, a first semiconductor device was prepared using a base substrate 11 having a first anchor portion 12 shown in FIG. 17. The first anchor portion 12 in FIG. 17 does not have two recesses, the inner angle θa is about 90°, and the side surface on the ceramic substrate side is not inclined toward the ceramic substrate side and is along the vertical direction. In each of the samples of Example 2-4 to 2-6, in order to examine the optimal mode of the second anchor portion 12a, the modes of the first recess 121a and the second recess 121b and the mode of the inner angle θa were changed as shown in FIGS. 18 to 20. In the sample of Comparative Example 2-1, a semiconductor device was prepared using a base substrate 11 not having the anchor portion shown in FIG. 21.

[0082] For each sample, the thickness t (μm) of the base substrate, the first-stage depth h1 which is the depth to the first recess 121a, the first-stage width w1 which is the width of the bottom of the first recess 121a, the second-stage depth h2 which is the depth of the second recess 121b, the second-stage width w2 which is the width of the second recess 121b, the inner angle θa on the ceramic substrate side in the first recess 121a, the outer angle θb on the side away from the ceramic substrate in the first recess 121a, the inner collapse width La facing the upper surface on the ceramic substrate side of the second recess 121b, and the outer collapse width Lb facing the upper surface on the side away from the ceramic substrate of the second recess 121b are as shown in Table 2.

[0083] B. Evaluation of Samples For each of the samples of Examples 2-1 to 2-6 and Comparative Example 2-1, the state of solder deterioration after 600 H / C tests, with one cycle being 1 hour at -40°C and 1 hour at 125°C, was confirmed. The state of solder deterioration was judged based on the presence or absence of solder peeling. When solder deterioration occurred over almost the entire surface of the semiconductor device, it was indicated as "×" representing a failure. When solder deterioration occurred only in a part of the semiconductor device, it was indicated as "△", showing that the degree of failure was better than "×". When no solder deterioration occurred, it was judged as a good product and indicated as "〇".

[0084] Table 2 shows the results of the H / C tests in Examples 2-1 to 2-6 and Comparative Example 2-1.

[0085]

Table 2

[0086] In Examples 2-1 and 2-2, no solder deterioration occurred. On the other hand, in Comparative Example 2-1, solder deterioration occurred over almost the entire surface of the semiconductor device. Also, in Examples 2-3 to 2-6, solder deterioration occurred only in a part of the semiconductor device.

[0087] From these results, it is considered that in the semiconductor device of Comparative Example 2-1 where the anchor part was not formed, the adhesion between the base substrate 11 and the sealing material 20 was weak, so the sealing material 20 peeled off from the base substrate 11 and solder deterioration occurred.

[0088] Also, in the first semiconductor device of Example 2-3 using the base substrate 11 having the first anchor part 12, although the adhesion between the base substrate and the sealing material was stronger than that of the semiconductor device of Comparative Example 2-1, it is considered that a part of the sealing material peeled off from the base substrate and solder deterioration occurred in part.

[0089] Among Examples 2-1, 2-2, 2-4 to 2-6, it was found that when the second anchor part 12a was formed in the manner of Examples 2-1 and 2-2, the adhesion between the base substrate 11 and the sealing material 20 was strong and solder deterioration could be suppressed.

[0090] According to the results of Experimental Example 2, in Examples 2-1 and 2-2 where no solder degradation occurred, θa was 82.4° and 84.8°, respectively. On the other hand, in Examples 2-3 to 2-5 where solder degradation occurred in a part of the semiconductor device, θa exceeded 90°. From this, it was found that θa < 90° is preferable. Furthermore, it was found that 75° ≤ θa < 90° is more preferable. In Example 2-6, although θa was less than 90°, solder degradation occurred. This is presumably because the depth h1 of the first stage was shallow and the adhesion between the base substrate 11 and the sealing material 20 was weak.

[0091] Also, according to the results of Experimental Example 2, in Examples 2-1 and 2-2 where no solder degradation occurred, h2 / (h1 - h2) was 0.27 and 0.52, respectively. On the other hand, in Examples 2-4 and 2-6 where solder degradation occurred in a part of the semiconductor device, h2 / (h1 - h2) was 0.08 and 0.78, respectively. Therefore, it was found that 0.2 ≤ h2 / (h1 - h2) ≤ 0.6 is preferable. In Example 2-5 where solder degradation occurred in a part of the semiconductor device, h2 / (h1 - h2) was 0.29 and was within the above range. However, while h1 was 1.44 in each of Examples 2-1 and 2-2, h1 was 1.02 in Example 2-5, which was considerably smaller compared to Examples 2-1 and 2-2. Therefore, in Example 2-5, since the adhesion between the base substrate 11 and the sealing material 20 was weak, although h2 / (h1 - h2) was within the range of 0.2 or more and 0.6 or less, solder degradation occurred in a part of the semiconductor device.

[0092] Also, in Experimental Example 2, when the second anchor portion 12a was formed by pressing the base substrate 11 with a mold, h1 / t ≤ 0.5 was set in consideration of the deformation of the base substrate 11.

[0093] Also, in Experimental Example 2, when forming an anchor portion having a two-stage shape by pressing the base substrate 11 with the first mold 51 and the second mold 52 (Examples 2-1, 2-2, 2-4 to 2-6), the anchor portion was formed such that W2 > W1.

[0094] Note that, as described above, the embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. That is, various changes can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position, or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and they are included in the present invention.

[0095] <Modification Example> In the above-described embodiment, as shown in FIG. 6, the second anchor portion 12a is formed so as to surround the entire circumference of the DBC substrate 13a in a plan view. However, the second anchor portion 12a can also be formed so as to surround a part of the DBC substrate 13a in a plan view. For example, the second anchor portion 12a may be a set of a plurality of recesses formed at intervals in the outer peripheral portion of the DBC substrate 13a.

[0096] In the above-described embodiment, the second anchor portion 12a has a two-stage recess including a first recess 121a and a second recess 121b. However, the anchor portion may be formed of a single-stage recess consisting only of the first recess 121a. And, similar to the above, in a cross-sectional view, the inner inclined surface IS of the first recess 121a is inclined toward the ceramic substrate 14a as it goes from the upper surface to the lower surface of the base substrate 11. Also, the second anchor portion 12a may be formed of a plurality of recesses having three or more stages.

Explanation of Signs

[0097] 1: Third semiconductor device 1a: Third semiconductor unit 2: Sealing material 2a, 2b: First and second sealing materials 10, 10a: First and second semiconductor units 11: Base substrate 11a: Base substrate corner 12, 12a: First and second anchor portions 13: Copper wiring substrate 13a: DBC substrate 14: Wiring substrate 14a: Ceramic substrate 15: Copper wiring 15a, 15b: First and first copper wirings 16: Semiconductor chip 17: Terminal 17a: Wiring terminal 17b: Chip terminal 20: Sealing material 31 to 34: First to fourth solders 51, 52: First and second molds 60: Snap fit 60a: Head 60b: Body portion 60c: Foot portion 100, 100a: First and second semiconductor devices 101: Body case 101a: Top plate opening 101b: Opening for terminal 102: Top plate 110: Case locking part 111: Locking recess 121a, 121b: First and second recesses 121b1: Inner crushed surface 121b2: Outer crushed surface 171: Top surface of terminal 172: Vertical part of terminal 172a: Inner surface 172b: Outer surface 173: Terminal connection part 174: Opening for fixing terminal BS: Bottom surface IS: Inner inclined surface La: Inner crushing width Lb: Outer crushing width OS: Outer inclined surface t: Thickness θa: Inner angle θb: Outer angle x: Vertical direction y: Width direction z: Length direction

Claims

1. A base substrate, A wiring substrate disposed on the base substrate, Copper wiring disposed on at least one of the upper and lower surfaces of the wiring substrate, A semiconductor chip mounted on the wiring substrate, A sealing material covering the base substrate, the wiring substrate, the copper wiring, and the semiconductor chip, and A semiconductor device, wherein an anchor portion formed of a recess extending from the upper surface to the lower surface outside the end of the wiring substrate is formed on the upper surface side of the base substrate, and the anchor portion is filled with the sealing material.

2. The semiconductor device according to claim 1, wherein an end of the copper wiring is located inside, retreating from an end of the wiring substrate.

3. The semiconductor device according to claim 1 or 2, wherein the anchor portion is inclined toward the wiring substrate side from the upper surface to the lower surface of the base substrate in a cross-sectional view.

4. The semiconductor device according to claim 3, wherein an angle between an inner inclined surface close to the wiring substrate side inside the anchor portion and a bottom surface in a cross-sectional view of the anchor portion is 75° or more and less than 90°.

5. The anchor portion has a concave first recess and a concave second recess that is continuously formed above the first recess and is larger than the first recess in a plan view, The semiconductor device according to claim 1 or 2, wherein the first recess is inclined toward the wiring substrate side from the upper surface to the lower surface of the base substrate in a cross-sectional view.

6. The semiconductor device according to claim 1 or 2, wherein the anchor portion is formed so as to surround the entire circumference of the wiring substrate in a plan view.

7. The semiconductor device according to claim 1 or 2, having a relationship of linear expansion coefficient of the base substrate > linear expansion coefficient of the sealing material > linear expansion coefficient of the wiring substrate.

8. The semiconductor device according to claim 1 or 2, wherein the sealing material is an epoxy resin.

9. The semiconductor device according to claim 1 or 2, wherein the wiring substrate is a ceramic substrate.

10. A method of manufacturing the semiconductor device according to claim 1 or 2, comprising: Forming a concave first recess constituting a part of the anchor portion by pressing a surface of the base substrate with a first mold. A method of manufacturing a semiconductor device, comprising: pressing, by a second mold that is slightly larger than the first recess, an edge portion of the base substrate that is continuous outside the first recess, to form a concave second recess that is continuous above the first recess, is larger than the first recess in plan view, and constitutes a part of the anchor portion.

Images