Pad-out structure for xtacking architecture

Abstract

To provide a method for manufacturing a semiconductor device.SOLUTION: The method according to the present invention can include a step of bonding a first die and a second die face to face. The first die includes: a substrate; transistors formed on a front surface side of the first die over a semiconductor layer comprising an insulating layer between the substrate and a semiconductor layer; and a first contact structure on the front surface side of the first die extending through the insulating layer. The method can also include the steps of: exposing the first contact structure from a back surface side of the first die; forming, from the back surface side of the first die, a contact hole in the insulating layer so as to expose the semiconductor layer; and forming, on the back surface side of the first die, a first pad-out structure connected with the first contact structure and a second pad-out structure, on the contact hole, conductively connected with the semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments generally related to semiconductor memory devices are described by this application.

Background Art

[0002] To achieve higher data recording density without requiring smaller memory cells, three-dimensional (3D) NAND flash memory technology has been developed. 3D NAND memory typically includes array transistors that form vertical memory cell columns and peripheral transistors that form peripheral circuits. In conventional 3D NAND devices, the array transistors and the peripheral transistors are processed on the same substrate. However, in the Xtacking architecture, an array substrate including array transistors and a peripheral substrate including peripheral transistors are stacked face-to-face via a bonding interface with the transistors sandwiched between the two substrates. Therefore, the Xtacking architecture can achieve higher recording density, a simpler process flow, and a shorter cycle time.

[0003] The Xtacking architecture can also include an electrode output (pad out) structure on the back side of either the array substrate or the peripheral substrate. Therefore, an external circuit can apply a control signal to the transistors sandwiched between the two substrates via the electrode output structure. The electrode output structure can be manufactured in a through-silicon contact (TSC) configuration.

Summary of the Invention

Means for Solving the Problems

[0004] Aspects of the present disclosure provide an electrode output structure for a semiconductor device according to the Xtacking architecture and a method of forming the electrode output structure.

[0005] According to a first aspect, a semiconductor device with an electrode output structure according to an exstacking architecture is disclosed. The semiconductor device can include a first die and a second die that are joined face to face. The first die can include an insulating layer on the back side of the first die, a first contact structure extending from the front side of the first die through a first portion of the insulating layer, a semiconductor layer on the front side of the second portion of the insulating layer, and a first transistor formed on the front side of the semiconductor layer.

[0006] In some embodiments, the first transistor can include a memory cell formed across the semiconductor layer on the front side of the first die. The memory cell can include an alternating stack of a word line layer and an insulating layer, and a plurality of channel structures extending through the stack. In some embodiments, the first die can further include a plurality of contact structures formed in the stepped region of the stack, and the plurality of contact structures are coupled to the word line layer. The stepped region may be on or in the middle of the boundary of the stack. Further, the channel structure can include a channel layer surrounded by one or more insulating layers.

[0007] In some embodiments, the second die can include a substrate and peripheral circuits for memory cells formed on the front side of the substrate.

[0008] The semiconductor device can also include a first electrode output structure disposed on the back side of the first die, and the first electrode output structure is electrically coupled to the first contact structure. The semiconductor device can further include a second electrode output structure disposed on the back side of the first die, and this second electrode output structure is electrically coupled to the semiconductor layer through a contact hole, and the second electrode output structure fills the contact hole.

[0009] The first electrode output structure can include a first portion of the first conductive layer, and the second electrode output structure can include a second portion of the first conductive layer. The first portion of the first conductive layer can be spaced apart from the second portion of the first conductive layer. The first conductive layer can be made of a first metal material. In some embodiments, the first electrode output structure can further include a first portion of a second conductive layer disposed between the first contact structure and the first pad layer. The second electrode output structure can further include a second portion of the second conductive layer disposed between the semiconductor layer and the second pad layer. The first portion of the second conductive layer can be spaced apart from the second portion of the second conductive layer. The second conductive layer can be made of a second metal material. In an example, the first metal material is made of aluminum and the second metal material is made of titanium.

[0010] In some embodiments, the first electrode output structure can be coupled to the input circuit / output circuit of the peripheral circuit through the first contact structure, the bonding interface between the first die and the second die, and the corresponding second contact structure in the second die. The peripheral circuit can be coupled to the memory cell through the corresponding third contact structure in the first die, the bonding interface, and the corresponding fourth contact structure in the second die. The second electrode output structure can be configured to provide an array common source to the memory cell.

[0011] In an alternative embodiment, the second die can further include a memory cell formed on the surface side of the substrate, and the first transistor can include a peripheral circuit for the memory cell formed on the surface side of the substrate. Further, the first electrode output structure can be coupled to the input circuit / output circuit of the peripheral circuit through the first contact structure, and the peripheral circuit can be coupled to the memory cell through the corresponding contact structure in the first die, the bonding interface between the first die and the second die, and the corresponding contact structure in the second die.

[0012] According to a second aspect of the present disclosure, a method for fabricating a semiconductor device with an exstacking architecture having an electrode output structure is provided. This method can include bonding a first die and a second die face to face, where the first die includes a first substrate, an insulating layer on the surface side of the first substrate, a first contact structure on the surface side of the first die extending through a first portion of the insulating layer, and a semiconductor layer on the surface side of a second portion of the insulating layer.

[0013] In some embodiments, the first die can further include a memory cell formed on the surface side of the semiconductor layer, and the second die can include a peripheral circuit for the memory cell on the surface side of the second substrate. In some embodiments, bonding the first die and the second die face to face can further include bonding a first bonding structure connected to the first contact structure in the first die to a second bonding structure connected to an input circuit / output circuit of the peripheral circuit in the second die.

[0014] In an alternative embodiment, the second die can include a memory cell disposed on the surface side of the second die, and the first die can further include a peripheral circuit for the memory cell.

[0015] The method can also include exposing the first contact structure from the back side of the first die by removing the first substrate from the back side of the first die. In some embodiments, the method can include removing an etch stop layer after removing the first substrate, where the etch stop layer is sandwiched between the first substrate and the insulating layer.

[0016] The method may further include forming contact holes in the second portion of the insulating layer from the back side of the first die, the contact holes exposing the semiconductor layer, and forming a first electrode output structure conductively connected to the first contact structure at the back side of the first die and a second electrode output structure conductively connected to the semiconductor layer at the contact holes. In some embodiments, the second electrode output structure can be configured to provide an array common source to the memory cells.

[0017] Further, forming the first electrode output structure and the second electrode output structure may include forming a first conductive layer from the back side of the first die across the first contact structure and the semiconductor layer, filling the contact holes with the first conductive layer, and patterning the first conductive layer from the back side of the first die to form a first electrode output structure conductively connected to the first contact structure and a second electrode output structure conductively connected to the semiconductor layer. In some embodiments, a second conductive layer can be formed on the back side of the insulating layer, the second conductive layer connecting the first conductive layer and the first contact structure and connecting the first conductive layer and the semiconductor layer, and the second conductive layer being patterned using the same photomask as the first conductive layer.

[0018] In some embodiments, the first conductive layer can be made of a first metal material and the second conductive layer can be made of a second metal material. In an example, the first conductive layer includes at least titanium and the second conductive layer includes at least aluminum.

[0019] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that in accordance with the practice in the industry, various features are not drawn to exact scale. In fact, the dimensions of the various features may be enlarged or reduced for clarity of explanation.

Brief Description of the Drawings

[0020]

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DETAILED DESCRIPTION OF THE INVENTION

[0021] To implement the various features of the presented subject matter, many different embodiments or examples are provided by the following disclosure. For simplicity of the present disclosure, specific examples of components and configurations are described below. These are of course merely examples and are not intended to be limiting. For example, in the following description, forming the first feature across the second feature or on the second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features cannot be in direct contact. Further, the present disclosure may, in various examples, repeat reference numerals and / or text. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations described.

[0022] Further, as shown in the figures, in order to facilitate the description of the relationship of one element to another element or of one feature to another feature, spatial relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used in this specification. The spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented (rotated 90 degrees or at other orientations) to other states, and the spatial relative descriptors used herein may likewise be interpreted accordingly.

[0023] The present disclosure provides a method of forming an electrode output structure for a 3D memory device with an exstacking architecture. The method can include bonding a first die and a second die, removing a substrate of the first die, forming contact holes, and forming an electrode output structure. Compared to a through-silicon contact (TSC) electrode for an exstacking architecture, the disclosed method eliminates the additional deposition of a dielectric layer and etching of TSC metal, and thus simplifies the manufacturing process.

[0024] FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an exemplary embodiment of the present disclosure. As shown, the device 100 can include a first die D1 and a second die D2 joined together via a bonding interface 140 in a face-to-face manner (the circuit side is the front and the substrate side is the back). The first die D1 and the second die D2 can each include bonding structures 141 and 142 that are correspondingly aligned with each other. Further, the bonding structure 141 can be electrically coupled to the corresponding bonding structure 142.

[0025] As shown in FIG. 1, the first die D1 can include an insulating layer 103 (e.g., silicon oxide), a semiconductor layer 105 (e.g., doped polysilicon) on the surface side of the insulating layer 103, and a first contact structure 121 (e.g., tungsten) formed on the surface side of the insulating layer 103 and extending through the insulating layer 103.

[0026] The first die D1 can also include 3D NAND memory cells. For example, an alternating stack of an insulating layer 111 and a word line layer 112 (also called a gate layer) can be disposed on the surface side of the semiconductor layer 105. The stack can include an array region 110 in which at least one channel structure 130 is formed and extends into the semiconductor layer 105 through the stack. The stack of the insulating layer 111 and the word line layer 112 and the channel structure 130 can form a stack of transistors such as an array of vertical memory cell strings. In some examples, the stack of transistors can include memory cells and select transistors such as one or more bottom select transistors and one or more top select transistors. In some examples, the stack of transistors can also include one or more dummy select transistors.

[0027] The insulating layer 111 can be made of an insulating material such as silicon nitride or silicon oxide. The word line layer 112 can be made of a gate stack material such as a high-k gate insulator layer or a metal gate electrode. The channel structure 130 can include a channel layer 131 (e.g., polysilicon) surrounded by one or more insulating layers 132 such as a tunneling layer (e.g., silicon oxide), a charge trapping layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide) that together form an oxide-nitride-oxide structure surrounding the channel layer 131.

[0028] Furthermore, the laminate can have a stepped region 120 in which a plurality of second contact structures 122 and third contact structures 123 are formed. The second contact structure 122 is connected to the word line layer 112 that can function as a gate and a dummy gate of a vertical memory cell column. The third contact structure 123 is connected to the semiconductor layer 105. It should be noted that the device 100 can have various stepped configurations such as a central stepped mounting form or a side stepped mounting form.

[0029] Furthermore, in FIG. 1, the first die D1 may further include a first conductive layer 171 (also referred to as a pad layer) on the back side of a second conductive layer 161 (also referred to as a liner layer) having a first portion 161a covering the back side of the first contact structure 121 and a second portion 161b covering the hole in the insulating layer 103. The first portion 171a of the first conductive layer and the second portion 171b of the first conductive layer may be disposed on the back side of the first portion 161a of the second conductive layer and the back side of the second portion 161b of the second conductive layer, respectively, to form a first electrode output structure and a second electrode output structure. The first portion 171a of the first conductive layer can be electrically coupled to the first contact structure 121, and the second portion 171b of the first conductive layer can be electrically coupled to the semiconductor layer 105. In this example, the first conductive layer 171 is aluminum and the semiconductor layer 105 is polysilicon. The second conductive layer 161 can be a bonding layer such as a titanium layer having a thickness in the range of 10 nm to 20 nm disposed between aluminum and polysilicon. According to embodiments, the second conductive layer 161 may be formed from titanium silicide under a relatively high temperature (e.g., above 500°C). In other examples, the first conductive layer 171 can be made of other conductive materials, and the second conductive layer 161 can be a barrier layer, a seed layer, and / or a bonding layer. Also, the second conductive layer 161 can be used to reduce contact resistance. According to embodiments, the second conductive layer 161 may not be necessary in some cases.

[0030] In the example of FIG. 1, the first die D1 can include 3D memory cells, and the second die D2 can include peripheral circuits (e.g., address decoders, drive circuits, sense amplifiers, etc.). Generally, the peripheral circuits of the second die D2 can be connected to the memory cells using external circuits. For example, the peripheral circuits receive commands from the external circuits via the first electrode output structures (171a and 161a), provide control signals to the memory cells, receive data from the memory cells, and output data to the external circuits via the first electrode output structures (171a and 161a). Further, in some embodiments, the semiconductor layer 105 is coupled to an array common source (ACS) for a memory cell array, and as a result, the second electrode output structures (171b and 161b) can provide input / output electrode output structures to the ACS.

[0031] For simplicity of discussion, the substrate 191 and two transistors 180 formed on the substrate are shown in the second die D2. For example, the transistors 180 can form complementary metal-oxide-semiconductor (CMOS). The substrate 191 can be any suitable substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, such as a Group IV semiconductor, a III-V compound semiconductor, or a II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate 191 may be a bulk wafer or an epitaxial layer. Note that the first die D1 initially includes the substrate, on which the semiconductor layer 105 and the insulating layer 103 are disposed. The substrate is removed before forming the electrode output structures (171 and 161).

[0032] In some embodiments, the semiconductor memory device can include a plurality of array dies (e.g., the first die D1) and a CMOS die (e.g., the second die D2). The plurality of array dies and the CMOS die can both be stacked and bonded together. Each array die is coupled to a portion of the CMOS die, and the CMOS die can drive the array dies individually or together in a similar manner. Further, in some examples, the semiconductor device 100 includes at least a first wafer and a second wafer bonded face-to-face. The first die D1 is disposed on the first wafer using other array dies such as D1, and the second die D2 is disposed on the second wafer using other CMOS dies such as D2. Both the first wafer and the second wafer are bonded, and as a result, the array die on the first wafer is bonded to the corresponding CMOS die on the second wafer.

[0033] In an alternative embodiment, the first die D1 can include a peripheral circuit, and the second die D2 can include 3D memory cells (not shown). Still, the electrode output structures (171 and 161) can be disposed on the back side of the first die D1. Since the input signal / output signal does not need to pass through the memory cell array die, the path of the input signal / output signal can be shorter than the signal path in FIG. 1.

[0034] FIGS. 2-9 are cross-sectional views of a semiconductor device such as device 100 in various intermediate manufacturing steps according to an exemplary embodiment of the present disclosure. The device 100 can be any suitable device such as, for example, a memory circuit, a semiconductor chip (or die) in a state where the memory circuit is formed on the semiconductor chip, a semiconductor wafer in a state where a plurality of semiconductor dies are formed on the semiconductor wafer, a stack of semiconductor chips, or a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0035] Figure 2 shows a cross-sectional view of the semiconductor device 200 that will ultimately become the device 100. It should be understood that Figure 2 shows only a portion of the device 200. Similar to the device 100, the device 200 can include a first die D1' corresponding to the first die D1, and a second die (not shown) corresponding to the second die D2, which are joined together via a joining interface (not shown) corresponding to the joining interface 140. For the sake of simplicity, the joining structure 141 and the cap layer 106 of the first die D1 in Figure 1 are omitted in Figure 2.

[0036] As shown in the figure, the device 200 can include a substrate 201 (e.g., silicon) on the back side of the first die D1', and an etching stop layer 202 (e.g., silicon nitride) on the surface side of the substrate 201. The device 200 can also include an insulating layer 203 (e.g., silicon oxide) on the surface side of the etching stop layer 202, which will ultimately become the insulating layer 103 in Figure 1. Depending on the embodiment, the etching stop layer 202 may not be necessary.

[0037] As shown in Figure 2, the device 200 has components configured in the same manner as the corresponding components of the device 100 in Figure 1. For example, the first contact structure 221, the semiconductor layer 205, the alternating stack of the insulating layer 211 and the word line layer 212, the array region 210, the staircase region 220, the channel structure 230, the plurality of second contact structures 222, and the third contact structure 223 are configured in the same manner as the first contact structure 121, the semiconductor layer 105, the alternating stack of the insulating layer 111 and the word line layer 112, the array region 110, the staircase region 120, the channel structure 130, the plurality of second contact structures 122, and the third contact structure 123, respectively. These components have been described so far, but will be omitted here for clarity.

[0038] FIG. 3 shows the device 200 after the substrate 201 has been removed from the back side in FIG. 2. The removal of the substrate 201 can be achieved by chemical mechanical polishing (CMP) and / or wet etching. The etching stop layer 202 can be used to determine when to stop the CMP and / or wet etching process.

[0039] FIG. 4 shows the device 200 after a portion of the etching stop layer 202 and the first contact structure 221 have been removed in FIG. 3. Thus, the remaining first contact structure 221 and the insulating layer 203 are exposed from the back side. Similar to FIG. 3, the removal of a portion of the etching stop layer 202 and the first contact structure 221 can be achieved by a CMP process. Alternatively, the etching stop layer 202 can be removed by a first etching process, and a portion of the first contact structure 221 can be removed by a second etching process. In some embodiments, the removal of a portion of the first contact structure 221 may not be necessary. As a result, a portion of the first contact structure 221 will be exposed (not shown). Further, although the first contact structure 221 is shown as extending into the etching stop layer 202, in some embodiments, it only extends to the back side surface 203' of the insulating layer 203 (not shown). Thus, the removal of any portion of the first contact structure 221 may not be necessary.

[0040] In FIG. 5, the contact hole 251 can be formed in the insulating layer 203 of the device 200, as a result of which a portion of the semiconductor layer 205 is exposed. The contact hole 251 can have a bottom 251' and two sidewalls 251". In the example of FIG. 5, it is shown that two contact holes 251 have a trapezoidal cross-section that extends from the front side to the back side. It will be understood that any number of contact holes 251 can be formed and that the contact holes 251 can have other shapes such as a rectangle. The contact hole 251 can be formed by an etching process using a photoresist as an etching mask defined by a photolithography process.

[0041] In FIG. 6, finally, the second conductive layer 261, which will ultimately be the second conductive layer 161 in FIG. 1, can be formed so as to conformally coat the exposed first contact structure 221, the insulating layer 203, and the exposed portion of the semiconductor layer 205. As a result, the bottom 251' and the sidewalls 251" of the contact hole 251 are covered by the second conductive layer 261. The second conductive layer 261 can be made of titanium and can be formed by chemical vapor deposition. The second conductive layer 261 can have a thickness in the range of 10 nm to 20 nm. Depending on the embodiment, the second conductive layer 261 may not be necessary, and thus this step can be omitted.

[0042] In FIG. 7, finally, the first conductive layer 271, which will ultimately be the first conductive layer 171 in FIG. 1, can be formed from the back side over the second conductive layer 261, as a result of which the contact hole 251 can be filled with the first conductive layer 271. The first conductive layer 271 can be a conductive layer made of aluminum and can be formed by chemical vapor deposition. In an example where the second conductive layer 261 is titanium and the semiconductor layer 205 is polysilicon, titanium can be a bonding layer between aluminum and polysilicon. Further, the recessed structure 272 can be formed on the back side of the first conductive layer 271 as a result of the contact hole 251.

[0043] FIG. 8 shows device 200 after a portion of the first conductive layer 271 and a portion of the second conductive layer 261 have been removed in FIG. 7. Removal of a portion of the first conductive layer 271 and a portion of the second conductive layer 261 can be achieved by etching using a photoresist and / or a hard mask layer. Thus, a first portion 271a of the first conductive layer can be disposed on a first portion 261a of the second conductive layer to form a first electrode output structure, and a second portion 271b of the first conductive layer can be disposed on a second portion 261b of the second conductive layer to form a second electrode output structure. Similar to device 100, an external circuit (not shown) can provide a control signal to a peripheral circuit (not shown) of the second die D2' of device 200 via a first electrode output structure (271a and 261a) coupled to the peripheral circuit via a first contact structure 221, and can receive data from the peripheral circuit (not shown) of the second die D2' of device 200. The peripheral circuit can then interact with the transistors of the first die D1'.

[0044] FIG. 9 is a flowchart of an exemplary process 900 for manufacturing an exemplary semiconductor device such as device 100 in FIG. 1 or device 200 in FIG. 8 according to an embodiment of the present disclosure. Process 900 begins with a step S901 in which a first die and a second die are joined face to face (the circuit side is the front and the substrate side is the back). The first die can include a first substrate, a first transistor formed on the surface side of the first die in a semiconductor layer having an insulating layer between the first substrate and the semiconductor layer, and a first contact structure on the surface side of the first die extending through the insulating layer. The second die can include a second substrate having a structure formed on the surface side of the second die.

[0045] To bond the first die to the second die, a plurality of first bonding structures such as pillars can be formed on the surface side of the first die, and a plurality of second bonding structures can be formed on the surface side of the second die. The bonding structure can include Cu, Ni, and SnAg. The bonding process can be operated at a temperature exceeding 220° C. such that the bonding structure melts, and as a result, the first bonding structure can form a connection with the corresponding second bonding structure. Therefore, the first transistor in the first die can be coupled to the structure in the second die via the corresponding bonding structure at the bonding interface and the corresponding contact structure in the two dies.

[0046] Furthermore, as shown in the example of FIG. 1, the first transistor can form a vertical memory cell column, and the second die can include a peripheral circuit. In an alternative embodiment, the first transistor can include a peripheral circuit, and the second die can include a memory cell.

[0047] In step S902, the first substrate is removed from the back side of the first die, exposing the first contact structure from the back side of the first die. As a result, the insulating layer is also exposed from the back side of the first die. In an example where an etching stop layer is sandwiched between the first substrate and the insulating layer, the etching stop layer can also be removed from the back side of the first die. The removal of the first substrate and the etching stop layer can be achieved by CMP and / or etching.

[0048] In step S903, a contact hole exposing a portion of the semiconductor layer is formed in the insulating layer from the back side of the first die. The contact hole has a bottom and two sidewalls. The contact hole pattern can be defined in the photoresist and / or the hard mask layer using photolithography technology, the pattern can be transferred to the insulating layer using etching technology, and then the photoresist and / or the hard mask layer can be removed.

[0049] In process S904, the first electrode output structure and the second electrode output structure can be formed on the back side of the first die by two deposition processes, a photolithography process, and two etching processes. First, a conformal liner layer can be formed by a first deposition process so as to cover the exposed first contact structure, the insulating layer, and the exposed portions of the semiconductor layer. The liner layer can also cover the bottom and sidewalls of the contact holes. Next, a pad layer can be formed by a second deposition process over the liner layer from the back side. The pad layer can fill the contact holes, and as a result of these contact holes, a recessed structure can be formed on the back side. Thereafter, a photolithography process can be performed to define an electrode output pattern from a photoresist and / or a hard mask layer that functions as an etching mask. Next, two etching processes can be performed to transfer the electrode output pattern to the pad layer and the liner layer, thereby forming the first electrode output structure and the second electrode output structure. In some embodiments, the two etching processes can be replaced by a single etching process. Further, the photoresist and / or the hard mask layer will be removed.

[0050] As a result, the first electrode output structure is conductively connected to the first contact structure with a first portion of the liner layer sandwiched therebetween. The external circuit can be coupled to the peripheral circuits of the device through the first electrode output structure and the first contact structure. Similarly, the second electrode output structure is formed over the contact holes with a second portion of the liner layer sandwiched therebetween and is conductively connected to the semiconductor layer. The second electrode output structure can be configured to provide an array common source to the memory cells.

[0051] Furthermore, in an example where the electrode output structure is aluminum and the semiconductor layer is polysilicon, the liner layer can be made of a bonding material such as titanium. In other examples, the electrode output structure can be made of other conductive materials, and the liner layer can be a barrier layer, a seed layer, and / or a bonding layer. The liner layer can also be used to reduce contact resistance. Depending on the embodiment, the liner layer may not be necessary.

[0052] Note that additional steps can be provided during and before and after step 900, some of the described steps can be replaced, eliminated, or performed in a different order for additional embodiments of step 900. For example, the formation of the liner layer may not be necessary. In particular, in step S904, the pad layer having the concave structure can be planarized by a CMP process before the photolithography process that defines the etching mask. Thus, the electrode output structure will have a flat surface on the back side. Furthermore, the electrode output structure can also be formed using a lift-off method in which a photolithography process is performed before depositing the liner layer and the pad layer.

[0053] According to various embodiments described herein, several advantages are provided. For example, in a related 3D NAND memory device, the electrode output structure is formed in a TSC configuration that requires the deposition and etching of an interlayer dielectric (e.g., silicon oxide, silicon nitride, etc.) and a TSC metal (e.g., tungsten) on the back side of the first substrate. In the method of the present disclosure, the manufacturing process is simplified and a non-TSC electrode output structure can be formed.

[0054] From the foregoing description, an overview of the features of several embodiments has been described, and as a result, those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will understand that the present disclosure can be easily used as a basis for designing or modifying other processes and other structures for achieving the same purpose as the embodiments introduced herein and / or achieving the same advantages of the embodiments. It should also be recognized by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various variations, alternative forms, and modifications herein can be realized without departing from the spirit and scope of the present disclosure.

Description of Reference Numerals

[0055] 100 Semiconductor device 103 Insulating layer 105 Semiconductor layer 106 Cap layer 110 Array region 111 Insulating layer 112 Word line layer 120 Staircase region 121 First contact structure 122 Second contact structure 123 Third contact structure 130 Channel structure 131 Channel layer 132 Insulating layer 140 Junction interface 141 Junction structure 142 Junction structure 161 Second conductive layer, electrode output structure 161a First portion of the second conductive layer, first electrode output structure 161b Second portion of the second conductive layer, second electrode output structure 171 First conductive layer, electrode output structure 171a First portion of the first conductive layer, first electrode output structure 171b Second portion of the first conductive layer, second electrode output structure 180 Transistor 191 Substrate 200 Semiconductor device 201 Substrate 202 Etching stop layer 203 Insulating layer 203’ Back surface side surface of insulating layer 203 205 Semiconductor layer 210 Array region 211 Insulating layer 212 Word line layer 220 Staircase region 221 First contact structure 222 Second contact structure 223 Third contact structure 230 Channel structure 251 Contact hole 251’ Bottom of contact hole 251” Side wall of contact hole 261 Second conductive layer 261a First part of the second conductive layer 261b Second part of the second conductive layer 271 First conductive layer 271a First part of the first conductive layer 271b Second part of the first conductive layer 272 Recess structure D1 First die D1’ First die D2 Second die D2’ Second die

Claims

1. 1. A method of fabricating a semiconductor device, comprising: bonding a first die and a second die in a face-to-face relationship, the first die including a first substrate, an insulating layer on a front side of the first substrate, a first contact structure on a front side of the first die extending through a first portion of the insulating layer, and a semiconductor layer on a front side of a second portion of the insulating layer; removing the first substrate from a backside of the first die to expose the first contact structure from the backside of the first die; forming a contact hole in the second portion of the insulating layer from the back side of the first die, the contact hole exposing the semiconductor layer; forming a first electrode output structure on the back side of the first die, the first electrode output structure being conductively connected to the first contact structure and a second electrode output structure being conductively connected to the semiconductor layer through the contact hole; A method for fabricating a semiconductor device, comprising:

2. forming the first electrode output structure and the second electrode output structure, forming a first conductive layer from the back side of the first die over the first contact structure and the semiconductor layer, the first conductive layer filling the contact hole; patterning the conductive layer from the backside of the first die to form the first electrode output structure conductively connected to the first contact structure and the second electrode output structure conductively connected to the semiconductor layer; The method of claim 1 further comprising:

3. forming the first electrode output structure and the second electrode output structure, forming a second conductive layer on a back side of the insulating layer, the second conductive layer connecting the first conductive layer to the first contact structure and connecting the first conductive layer to the semiconductor layer; patterning the second conductive layer using the same photomask as the first conductive layer; The method of claim 2 , further comprising:

4. the first conductive layer is made of a first metallic material; The method of claim 3 , wherein the second conductive layer is made of a second metallic material.

5. the first conductive layer includes at least aluminum; The method of claim 4 , wherein the second conductive layer comprises at least titanium.

6. exposing the first contact structure from the back side of the first die, removing an etch stop layer after removing the first substrate, the etch stop layer being sandwiched between the first substrate and the insulating layer; The method of claim 1 further comprising:

7. the first die further includes a memory cell formed on a front side of the semiconductor layer; the second die includes peripheral circuits for the memory cells on a front side of a second substrate; The method of claim 1.

8. The step of bonding the first die and the second die in a face-to-face relationship includes:

8. The method of claim 7, further comprising the step of bonding a first bonding structure connected to the first contact structure in the first die to a second bonding structure connected to an input circuit / output circuit in the peripheral circuit in the second die.

9. The method of claim 7 , wherein the second electrode output structure is configured to provide an array common source to the memory cell.

10. the second die includes memory cells disposed on a front side of the second die; The method of claim 1 , wherein the first die further includes peripheral circuitry for the memory cells.

11. a first die and a second die bonded face-to-face, the first die including an insulating layer on a back side of the first die, a first contact structure extending from a front side of the first die through a first portion of the insulating layer, a semiconductor layer on a front side of a second portion of the insulating layer, and a first transistor formed on the front side of the semiconductor layer; a first electrode output structure disposed on the back side of the first die, the first electrode output structure being electrically coupled to the first contact structure; a second electrode output structure disposed on the back side of the first die, the second electrode output structure being electrically coupled to the semiconductor layer through a contact hole, the second electrode output structure filling the contact hole; 13. A semiconductor device comprising:

12. the first transistor includes a memory cell formed across a semiconductor layer on the front side of the first die; The semiconductor device of claim 11 , wherein the second die includes a substrate and peripheral circuitry for the memory cells formed on a front side of the substrate.

13. The memory cell comprises: an alternating laminate of word line layers and insulating layers; a plurality of channel structures extending through the stack, the channel structures including a channel layer surrounded by one or more insulating layers; The semiconductor device of claim 12 , comprising:

14. 14. The semiconductor device of claim 13, wherein the first die further comprises a plurality of contact structures formed in a staircase region of the stack, the plurality of contact structures being coupled to the word line layer, the staircase region being on a boundary or in the middle of the stack.

15. the first electrode output structure is coupled to an input circuit / output circuit of the peripheral circuit via the first contact structure, a bonding interface between the first die and the second die, and a corresponding second contact structure on the second die; 13. The semiconductor device of claim 12, wherein the peripheral circuitry is coupled to the memory cells via corresponding third contact structures in the first die, the bonding interface, and corresponding fourth contact structures in the second die.

16. The semiconductor device of claim 12 , wherein the second electrode output structure is configured to provide an array common source to the memory cell.

17. the second die further includes a memory cell formed on a front side of the substrate; the first transistor includes a peripheral circuit for the memory cell formed on a front surface side of the substrate; the first electrode output structure is coupled to an input circuit / output circuit of the peripheral circuit via the first contact structure; 12. The semiconductor device of claim 11, wherein the peripheral circuits are coupled to the memory cells via corresponding contact structures in the first die, a bonding interface between the first die and the second die, and corresponding contact structures in the second die.

18. the first electrode output structure includes a first portion of a first conductive layer; the second electrode output structure includes a second portion of the first conductive layer; the first portion of the first conductive layer is spaced from the second portion of the first conductive layer; The semiconductor device of claim 11 , wherein the first conductive layer is made of a first metallic material.

19. the first electrode output structure further includes a first portion of a second conductive layer disposed between the first contact structure and the first pad layer; the second electrode output structure further includes a second portion of the second conductive layer disposed between the semiconductor layer and the second pad layer; the first portion of the second conductive layer is spaced from the second portion of the second conductive layer; 20. The semiconductor device of claim 18, wherein the second conductive layer is made of a second metallic material.

20. the first metallic material is made of aluminum; 20. The semiconductor device of claim 19, wherein the second metallic material is made of titanium.

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