Manufacturing method of ceramic circuit board and manufacturing method of semiconductor device

Abstract

To provide a ceramic circuit board having a good adhesion with a mold resin, and provide a manufacturing method for obtaining a semiconductor device.SOLUTION: A manufacturing method of a ceramic circuit board according to an embodiment, comprises: a first step of manufacturing a lamination body to which a plurality of metal parts is bonded to each of a plurality of first regions on a first surface of a ceramic substrate; and a second step of executing an etching step or a chemical polishing step to a second region positioned to between the adjacent first regions on the first surface. In the case where an average length RSm in the second region after the second step is measured under a measurement condition that λs filter is presence, λs cutoff ratio is 300, a cutoff type is Gaussian, and a cutoff wavelength (λc) is 0.8 mm, the average length RSm is 40 μm or larger.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The embodiments described below generally relate to a method for manufacturing a ceramic circuit board and a method for manufacturing a semiconductor device.

Background Art

[0002] In recent years, with the improvement in performance of industrial equipment, the output of power modules mounted thereon has been increasing. Along with this, the output of semiconductor elements has been increasing. The guaranteed operating temperature of semiconductor elements is 125°C to 150°C, but there is a possibility that it will rise to 175°C or higher in the future. As a circuit board for mounting semiconductor elements, a ceramic circuit board is used. The ceramic circuit board includes a ceramic substrate and a metal plate joined thereto. For example, in Japanese Patent No. 6789955 (Patent Document 1), there is an overhanging portion where the bonding layer protrudes from the end of the metal plate. In Patent Document 1, the TCT characteristics (thermal cycle characteristics) are improved by controlling the hardness and size of the overhanging portion of the bonding layer.

[0003] Also, resin molding may be performed to protect the semiconductor element. The molding resin has a role of protecting the semiconductor element and wiring from external stress. The molding resin also has a role of protecting the semiconductor element and the like from outside air such as moisture.

[0004] With the increase in the guaranteed operating temperature of semiconductor elements, the adhesion between the ceramic circuit board and the molding resin has been a problem. Due to the difference in the thermal expansion coefficient between the ceramic circuit board and the molding resin, there has been a problem that the molding resin peels off from the ceramic circuit board. When the molding resin peels off, it has caused conduction failure of semiconductor elements and the like.

[0005] For example, in International Publication No. 2018 / 173921 (Patent Document 2), a recess is provided in the copper plate of the ceramic circuit board. Further, in Japanese Unexamined Patent Application Publication No. 2021-68850 (Patent Document 3), a recess is provided in the ceramic substrate.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the ceramic circuit boards of Patent Document 2 and Patent Document 3, the adhesion to the mold resin is improved by providing recesses in the metal plate or the ceramic substrate. On the other hand, in recent years, the mounting density of semiconductor elements on ceramic circuit boards has been increasing. In order to increase the mounting density, a method of increasing the mounting area of semiconductor elements on the surface of the metal plate can be mentioned. In order to increase the mounting area on the surface of the metal plate, a method of increasing the flat surface of the metal plate can be mentioned. There is also a method of reducing the distance between the metal plates to increase the mounting area of the metal plates. In the method of providing recesses in the metal plate as in Patent Document 2, the mounting area cannot be increased. Regarding conventional ceramic circuit boards, it could not be said that ensuring the mounting area and the adhesion of the mold resin were both sufficient.

[0008] An embodiment is for addressing such problems, and provides a method for manufacturing a ceramic circuit board and a method for manufacturing a semiconductor device that can achieve both ensuring the mounting area and adhesion to the mold resin.

Means for Solving the Problems

[0009] The manufacturing method of the ceramic circuit board according to the embodiment includes a first step of producing a laminate in which a plurality of metal parts are respectively joined to a plurality of first regions on the first surface of the ceramic substrate, and a second step of performing an etching process or a chemical mechanical polishing process on a second region located between the adjacent first regions on the first surface. When the average length RSm in the second region after the second step is measured under the measurement conditions of λs filter: yes, λs cut-off ratio: 300, cut-off type: Gaussian, cut-off wavelength (λc): 0.8 mm, the average length RSm is 40 μm or more.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0011] The manufacturing method of the ceramic circuit board according to the embodiment includes a first step of producing a laminate in which a plurality of metal parts are respectively joined to a plurality of first regions on the first surface of the ceramic substrate, and a second step of subjecting a second region located between adjacent first regions on the first surface to an etching process or a chemical mechanical polishing process. When the average length RSm in the second region after the second step is measured under the measurement conditions of λs filter: yes, λs cut-off ratio: 300, cut-off type: Gaussian, cut-off wavelength (λc): 0.8 mm, the average length RSm is 40 μm or more.

[0012] FIG. 1 is a plan view showing an example of the ceramic circuit board according to the embodiment. FIG. 2 is a side view showing an example of the ceramic circuit board according to the embodiment. In FIGS. 1 and 2, reference numeral 1 denotes a ceramic circuit board. Reference numeral 2 denotes a ceramic substrate. Reference numeral 3 denotes a metal part. In the ceramic circuit board 1, a plurality of metal parts 3 are provided on at least one surface of the ceramic substrate 2 via a plurality of bonding layers 4 respectively.

[0013] FIG. 3 is a plan view showing an example of the ceramic substrate. FIG. 4 is a side view showing an example of the ceramic substrate. In FIGS. 3 and 4, reference numeral 2a denotes the first surface (front surface) of the ceramic substrate 2. Reference numeral 2b denotes the second surface (back surface) of the ceramic substrate 2. The second surface 2b is located on the opposite side of the first surface 2a.

[0014] As shown in FIGS. 3 and 4, the first surface 2a includes two or more first regions r1 and one or more second regions r2. In FIG. 3, the first region r1 is indicated by a two-dot chain line. The second region r2 is indicated with dots. Also, in FIG. 3, the metal part 3 joined to the first surface 2a is indicated by a dashed line. The metal part 3 is joined to the first region r1. The second region r2 is located between the first regions r1. The metal part 3 is not provided on the second region r2. The second region r2 may also be called an inter-pattern region. In the illustrated example, three metal parts 3 are arranged on the ceramic substrate 2. In this case, the first surface 2a of the ceramic substrate 2 includes three first regions r1 and two second regions r2.

[0015] More specifically, the second region r2 is a region located between adjacent first regions r1 in the direction in which the distance between adjacent metal parts 3 is the shortest. Here, the direction parallel to the thickness direction of the ceramic substrate 2 is defined as the "Z direction". Two directions perpendicular to the Z direction and perpendicular to each other are defined as the "X direction" and the "Y direction". For convenience, the X direction is the long side direction of the ceramic substrate 2, and the Y direction is the short side direction. In the example shown in FIG. 3, the plurality of metal parts 3 includes a metal part 3a, a metal part 3b, and a metal part 3c. The distance d1 between the metal part 3a and the metal part 3b is the shortest in the X direction. Therefore, in the X direction, the region located between the first region r1 to which the metal part 3a is joined and the first region r1 to which the metal part 3b is joined becomes the second region r2. Similarly, the distance d2 between the metal part 3b and the metal part 3c is the shortest in the X direction. In the X direction, the region between the first region r1 to which the metal part 3b is joined and the first region r1 to which the metal part 3c is joined becomes the second region r2.

[0016] Figures 5 and 6 are plan views showing another example of the ceramic substrate. In the examples shown in Figures 5 and 6, the size and position of the metal part 3 joined to the ceramic substrate 2 are different from those in the examples shown in Figures 1 to 4. In the examples shown in Figures 1 to 4, the shape of each metal part 3 is rectangular when viewed from the Z direction, and the longitudinal directions of the metal parts 3 are parallel to each other. In the example shown in Figure 5, a plurality of metal parts 3 are arranged in the X direction and the Y direction. In the example shown in Figure 6, a plurality of metal parts 3 are arranged such that the longitudinal directions of the metal parts 3 are oblique to each other.

[0017] Regarding the arrangements shown in Figures 5 and 6 as well, the second region r2 on the first surface 2a is specified in the same manner as the example shown in Figure 3. Specifically, in the example shown in Figure 5, metal parts 3a to 3d are provided. The distance d1 between the metal part 3a and the metal part 3b, and the distance d2 between the metal part 3c and the metal part 3d are the shortest in the X direction. In the X direction, the regions located between the first region r1 to which the metal part 3a is joined and the first region r1 to which the metal part 3b is joined, and the regions located between the first region r1 to which the metal part 3c is joined and the first region r1 to which the metal part 3d is joined respectively become the second region r2. Also, the distance d3 between the metal part 3a and the metal part 3c, and the distance d4 between the metal part 3b and the metal part 3d are the shortest in the Y direction. In the Y direction, the regions located between the first region r1 to which the metal part 3a is joined and the first region r1 to which the metal part 3c is joined, and the regions located between the first region r1 to which the metal part 3b is joined and the first region r1 to which the metal part 3d is joined respectively become the second region r2.

[0018] Also, the distance d5 between the metal part 3a and the metal part 3d, and the distance d6 between the metal part 3b and the metal part 3c are the shortest in a direction inclined with respect to the X direction and the Y direction. Therefore, in the inclined direction, the region located between the first region r1 to which the metal part 3a is joined and the first region r1 to which the metal part 3d is joined, and the region located between the first region r1 to which the metal part 3b is joined and the first region r1 to which the metal part 3c is joined can each be the second region r2. However, for portions where the distance between the metal parts 3 exceeds 3 mm, they are not treated as the second region r2. For example, even if the shortest distance between the metal parts 3 is 3 mm or less, regions where the distance between the metal parts 3 exceeds 3 mm are not included in the second region r2.

[0019] In the example shown in FIG. 6, the distance d1 between the metal part 3a and the metal part 3b, and the distance d2 between the metal part 3b and the metal part 3c are the shortest in the X direction. For this reason, in the X direction, the region located between the first region r1 to which the metal part 3a is joined and the first region r1 to which the metal part 3b is joined becomes the second region r2. In the X direction, the region between the first region r1 to which the metal part 3b is joined and the first region r1 to which the metal part 3c is joined becomes the second region r2. However, the distance between a part of the first region r1 to which the metal part 3a is joined and a part of the first region r1 to which the metal part 3b is joined exceeds 3 mm. For this reason, the region between the said part of the first region r1 to which the metal part 3a is joined and the said part of the first region r1 to which the metal part 3b is joined is not included in the second region r2.

[0020] Also, in FIGS. 1 and 2, reference numeral 4 denotes a bonding layer provided on the first surface 2a. Reference numeral 5 denotes a metal part. The metal part 5 is also called a back metal part. Reference numeral 6 denotes a bonding layer provided on the second surface 2b. The metal part 3 may be directly bonded to the first surface 2a, or may be bonded to the first surface 2a via the bonding layer 4 as shown in FIGS. 1 and 2. As shown in FIG. 2, the metal part 5 may be bonded to the second surface 2b. The metal part 5 may be directly bonded to the second surface 2b, or may be bonded to the second surface 2b via the bonding layer 6 as shown in FIG. 2. The metal part 5 is used as a heat sink. The metal part 5 is used for bonding to a heat sink or a housing (not shown). In the ceramic circuit board 1 according to the embodiment, the metal part 5 may be used as a circuit.

[0021] When the metal part 3 is bonded to the first surface 2a via the bonding layer 4, the bonding layer 4 preferably includes an overhang portion 4a. The overhang portion 4a is a portion of the bonding layer 4 that extends beyond the end of the metal part 3. When the bonding layer 4 includes the overhang portion 4a, the region of the first surface 2a that contacts the overhang portion 4a is also included in the first region r1. The second region r2 is located between the first regions r1 that contact the bonding layer 4 including the overhang portion 4a. That is, the second region r2 is a region that does not overlap with either the metal part 3 or the bonding layer 4 (including the overhang portion 4a) when viewed in the Z direction.

[0022] The ceramic circuit board 1 according to the embodiment is characterized in that the average length RSm of the roughness curve elements in the second region r2 of the first surface 2a is 40 μm or more. The average length RSm of the roughness curve elements is the average value of the lengths Xs of the contour curve elements at the reference length. The average length RSm of the roughness curve elements is defined in JIS-B-0601(2013). As defined in JIS-B-0601(2013), for the measurement of the average length RSm of the roughness curve elements, it is necessary to identify the minimum height and minimum length determined as peaks and valleys. The standard value of the distinguishable minimum height is 10% of the maximum height roughness Rz. The standard value of the distinguishable minimum length is 1% of the reference length. After determining the peaks and valleys so as to satisfy both of these two conditions, the average value of the lengths Xs of the contour curve elements is obtained. Note that JIS-B-0601 corresponds to ISO4287.

[0023] The fact that the average length RSm of the roughness curve elements is 40 μm or more indicates that one cycle of peaks and valleys is 40 μm or more. The fact that RSm in the second region r2 is 40 μm or more indicates that one cycle of peaks and valleys is large. Thereby, when the ceramic circuit board 1 is molded with resin, the adhesion between the ceramic substrate 2 and the molding resin can be improved. In the conventional ceramic substrate, RSm was less than 40 μm and was small. When the cycle of peaks and valleys is small, microscopic gaps are formed between the ceramic substrate 2 and the molding resin. Generally, the thermal expansion coefficient of the molding resin is larger than that of the ceramic substrate 2. When the temperature of the ceramic substrate 2 and the molding resin changes due to the heat of the semiconductor element, stress is generated at the interface between the ceramic substrate 2 and the molding resin due to the difference in thermal conductivity. When microscopic gaps exist between the ceramic substrate 2 and the molding resin, the molding resin is likely to be peeled off from the ceramic substrate 2 due to the stress generated due to the heat of the semiconductor element.

[0024] In addition, the molding resin in the vicinity of the second region r2 is susceptible to the heat of the semiconductor element mounted on the metal part. Generally, the thermal conductivity of the metal part 3 is higher than that of the ceramic substrate 2. The heat of the semiconductor element is released through the metal part 3. By providing the protruding portion 4a, the stress generated at the end of the metal part 3a is relaxed. On the other hand, the heat transmitted to the metal part 3 is also transmitted to the second region r2 where the metal part 3 is not provided. Since the metal part 3 is not provided in the second region r2, the heat transmitted to the second region r2 is difficult to be released. For this reason, the temperature in the vicinity of the second region r2 is likely to rise. Furthermore, stress due to the thermal expansion of the metal part 3 is also applied to the molding resin in contact with the second region r2. For this reason, between the second region r2 and the molding resin, peeling of the molding resin from the ceramic substrate 2 is more likely to occur than in other parts.

[0025] According to the embodiment, by controlling the RSm in the second region r2, the adhesion between the ceramic substrate 2 and the molding resin can be improved. When the adhesion between the ceramic substrate 2 and the molding resin is improved, when stress is applied to the molding resin in the direction parallel to the X-Y plane, the peaks and valleys on the surface of the second region r2 are caught by the molding resin. That is, an anchor effect occurs on the molding resin. Thereby, peeling of the molding resin from the ceramic substrate 2 can be suppressed. The embodiment is particularly effective for a ceramic circuit board where there is a portion where the distance between the metal parts 3 is 3 mm or less.

[0026] The upper limit of the average length RSm of the roughness curve elements is not particularly limited, but is preferably 100 μm or less. If RSm is larger than 100 μm, it may be difficult to control RSm. For this reason, the RSm in the second region r2 is preferably in the range of 40 μm or more and 100 μm or less, more preferably in the range of 50 μm or more and 80 μm or less.

[0027] Further, the maximum peak height Rp of the roughness curve in the second region r2 is preferably 1.0 μm or more. The maximum valley depth Rv of the roughness curve in the second region r2 is preferably 1.0 μm or more. The maximum peak height Rp and the maximum valley depth Rv of the roughness curve are also defined in JIS-B-0601(2013).

[0028] The maximum peak height Rp of the roughness curve is the height of the largest peak in the roughness curve. By setting Rp to 1.0 μm or more, the adhesion between the ceramic substrate 2 and the mold resin can be improved. If Rp is less than 1.0 μm, the adhesion between the ceramic substrate 2 and the mold resin may decrease. The upper limit of Rp is not particularly limited, but is preferably 3.0 μm or less. If Rp is greater than 3.0 μm, there may be a portion where the mold resin does not enter the gaps of the irregularities on the surface of the second region r2. For this reason, Rp is preferably in the range of 1.0 μm or more and 3.0 μm or less, more preferably in the range of 1.2 μm or more and 2.0 μm or less.

[0029] The maximum valley depth Rv of the roughness curve is the depth of the largest valley in the roughness curve. By setting Rv to 1.0 μm or more, the adhesion between the ceramic substrate 2 and the mold resin can be improved. If Rv is less than 1.0 μm, the adhesion between the ceramic substrate 2 and the mold resin may decrease. The upper limit of Rv is not particularly limited, but is preferably 3.0 μm or less. If Rv is greater than 3.0 μm, there may be a portion where the mold resin does not enter the gaps of the irregularities on the surface of the second region r2. For this reason, Rv is preferably in the range of 1.0 μm or more and 3.0 μm or less, more preferably in the range of 1.2 μm or more and 2.0 μm or less. When the valley is deep, Rv becomes large.

[0030] By controlling one or both of Rp and Rv after controlling the aforementioned RSm, the adhesion between the ceramic substrate 2 and the mold resin can be further improved. The mold resin becomes more difficult to peel off from the ceramic substrate 2.

[0031] RSm, Rp, and Rv are measured by a method conforming to JIS-B-0601 (2013). The measurement conditions are set as follows: measurement length: 4.0 mm, measurement speed: 0.6 mm / s, shape removal: least squares straight line, λs filter: yes, λs cut-off ratio: 300, cut-off type: Gaussian, cut-off wavelength (λc): 0.8 mm. When the measurement length of 4.0 mm cannot be ensured in one measurement, the measurement may be carried out in multiple times. Also, the measurement direction of the average length RSm of the roughness curve elements in the second region r2 is arbitrary. The measurement length of 4.0 mm is the reference length.

[0032] In the ceramic circuit board 1 according to the embodiment, the average length RSm of the roughness curve elements in the second region r2 is controlled. For example, when conforming to the above measurement conditions, no matter which part of the second region r2 is measured, RSm is 40 μm or more. Also, no matter which part of the second region r2 is measured, Rp is preferably 1.0 μm or more. No matter which part of the second region r2 is measured, Rv is preferably 1.0 μm or more. Note that in the first region r1 joined to the metal part 3, there may be a portion where RSm is less than 40 μm.

[0033] Also, the total area of each second region r2 with respect to the surface area of the first surface 2a is preferably in the range of 5% or more and 50% or less. That is, it is preferably 5 (%) ≤ [total area of second region r2 / area of first surface 2a] × 100 ≤ 50 (%). For example, in the case of a ceramic substrate with a long side of 50 mm and a short side of 40 mm, the surface area of the first surface 2a is 50 × 40 = 2000 mm 2 is. When only one second region r2 exists on the first surface 2a, the area of that second region r2 corresponds to the above-mentioned "total area of second region r2". When a plurality of second regions r2 exist on the first surface 2a, the total area of the areas of each second region r2 corresponds to the above-mentioned "total area of second region r2". For example, in the examples shown in FIGS. 1 to 4, two second regions r2 exist. The total area of the areas of the two second regions r2 is the "total area of second region r2".

[0034] By setting the total area of the second region r2 within the range of 5% or more and 50% or less of the surface area of the first surface 2a, it is possible to achieve both good adhesion of the mold resin and sufficient mounting area for the semiconductor element. If the total area of the second region r2 is less than 5%, the effect of improving the adhesion between the ceramic substrate 2 and the mold resin may be insufficient. If the total area of the second region r2 exceeds 50% and is too large, there may be insufficient area for mounting semiconductor elements and the like. Therefore, the total area of the second region r2 is preferably within the range of 5% or more and 50% or less of the surface area of the first surface 2a, more preferably within the range of 10% or more and 40% or less.

[0035] Various substrates can be applied to the ceramic substrate 2. Examples of the ceramic substrate include a silicon nitride substrate, an aluminum nitride substrate, an alumina substrate, a zirconia substrate, and an aldyl substrate. The aldyl substrate is a ceramic sintered body obtained by mixing alumina and zirconia. The thickness of the ceramic substrate is preferably 0.2 mm or more and 3 mm or less.

[0036] The three-point bending strength of the silicon nitride substrate is preferably 600 MPa or more. The thermal conductivity of the silicon nitride substrate is preferably 80 W / m·K or more. By increasing the strength of the silicon nitride substrate, the substrate thickness can be reduced. Therefore, the three-point bending strength of the silicon nitride substrate is preferably 600 MPa or more, more preferably 700 MPa or more. By using a silicon nitride substrate, the substrate thickness can be reduced to 2 mm or less, and further to 0.40 mm or less.

[0037] The three-point bending strength of the aluminum nitride substrate is about 300 - 450 MPa. On the other hand, the thermal conductivity of the aluminum nitride substrate is 160 W / m·K or more. Since the strength of the aluminum nitride substrate is low, the substrate thickness is preferably 0.60 mm or more. The three-point bending strength of the aluminum oxide substrate is about 300 - 450 MPa, but the aluminum oxide substrate is inexpensive. The three-point bending strength of the aldyl substrate is as high as about 550 MPa, but the thermal conductivity is about 30 - 50 W / m·K.

[0038] It is preferable that the silicon nitride substrate be used as the ceramic substrate 2. Since the silicon nitride substrate has high strength, it can withstand the thermal shrinkage of the mold resin. Further, by using a silicon nitride substrate having a thermal conductivity of 80 W / m·K or more, the heat dissipation performance can also be improved. In the silicon nitride substrate, silicon nitride crystal particles having an aspect ratio of 1.5 or more are mainly present. By the entanglement of the elongated silicon nitride crystal particles, the strength of the ceramic substrate 2 can be increased. Further, by the random orientation of the elongated silicon nitride crystal particles, it becomes easier to control RSm.

[0039] Examples of the metal part 3 include a metal plate, a thin film, and a metallized film. The thin film refers to a conductive film formed by a sputtering method or a plating method or the like. The metallized film refers to a conductive film formed by applying a metal powder paste and baking it.

[0040] The metal part 3 is preferably a member obtained by processing a metal plate. The thickness of the metal plate (metal part 3) is preferably 0.3 mm or more. By increasing the thickness of the metal plate, the heat dissipation performance can be improved. The capacitance can also be improved. For this reason, the thickness of the metal plate is preferably 0.3 mm or more, more preferably 0.6 mm or more. The upper limit of the thickness of the metal plate is not particularly limited, but is preferably 5 mm or less. If the thickness exceeds 5 mm, it may be difficult to control the inclined shape of the side surface of the metal part 3. Further, from the viewpoint of heat dissipation performance, it is preferable to use a copper plate having a thickness of 0.3 mm or more for the metal part 3. Further, it is preferable that both the thickness of the metal part 3 and the thickness of the metal part 5 are 0.3 mm or more. By using a metal plate for the metal part 3, the adhesion between the metal part 3 and the mold resin can be improved, and the capacitance and heat dissipation performance of the metal part 3 can be improved.

[0041] Examples of the metal plate include one or more selected from a copper plate, a copper alloy plate, an aluminum plate, and an aluminum alloy plate. A copper plate is preferred as the metal plate. Further, an oxygen-free copper plate is preferred. Oxygen-free copper has a copper purity of 99.96 wt% or more as shown in JIS-H-3100. The thermal conductivity of copper is about 400 W / m·K, and the thermal conductivity of aluminum is about 240 W / m·K. Copper has a higher thermal conductivity than aluminum. By using a copper plate for the metal part 3, the heat dissipation of the metal part 3 is improved. Also, the aluminum plate is preferably pure aluminum. Pure aluminum is shown in JIS-H-4000. Note that JIS-H-4000 corresponds to ISO6361. JIS-H-3100 corresponds to ISO197 etc.

[0042] The ceramic substrate 2 and the metal part 3 are preferably joined via a joining layer 4. The joining layer 4 is preferably a member formed using an active metal joining method. The active metal joining method is a joining method using one or more active metals selected from Ti (titanium), Zr (zirconium), and Hf (hafnium). An active metal solder containing copper (Cu) or silver (Ag) as a main component and containing an active metal is used. Here, the main component refers to the component most contained among the metal components of the solder.

[0043] The active metal solder preferably contains 0 mass% or more and 60 mass% or less of Ag (silver), 15 mass% or more and 70 mass% or less of Cu (copper), and 1 mass% or more and 15 mass% or less of Ti (titanium) or TiH 2 (titanium hydride). When both Ti and TiH 2 are used, the total of these is in the range of 1 mass% or more and 15 mass% or less. When both Ag and Cu are used, it is preferable that Ag is in the range of 20 mass% or more and 60 mass% or less, and Cu is in the range of 15 mass% or more and 40 mass% or less. If necessary, one or both of Sn (tin) or In (indium) may be contained in the active metal solder in the range of 1 mass% or more and 50 mass% or less. Also, if necessary, C (carbon) may be contained in the active metal solder in the range of 0.1 mass% or more and 2 wt% or less.

[0044] The ratio of the composition of the active metal brazing filler metal is calculated with the total of the raw materials to be mixed being 100% by mass. For example, when the active metal brazing filler metal is composed of three types of Ag, Cu, and Ti, Ag + Cu + Ti = 100% by mass. Ag, Cu, TiH 2 When the active metal brazing filler metal is composed of four types of In, Ag + Cu + TiH 2 + In = 100% by mass. When the active metal brazing filler metal is composed of five types of Ag, Cu, Ti, Sn, and C, Ag + Cu + Ti + Sn + C = 100% by mass.

[0045] Ag or Cu is a component that becomes the base material of the brazing filler metal. Sn or In has the effect of lowering the melting point of the brazing filler metal. C (carbon) has the effect of controlling the fluidity of the brazing filler metal or reacting with other components to control the structure of the bonding layer. Therefore, examples of the components of the brazing filler metal include Ag-Cu-Ti, Ag-Cu-Sn-Ti, Ag-Cu-Ti-C, Ag-Cu-Sn-Ti-C, Ag-Ti, Cu-Ti, Ag-Sn-Ti, Cu-Sn-Ti, Ag-Ti-C, Cu-Ti-C, Ag-Sn-Ti-C, Cu-Sn-Ti-C. In may be used instead of Sn. Both Sn and In may be used.

[0046] One or more selected from tungsten (W), molybdenum (Mo), and rhenium (Re) may be added to the active metal brazing filler metal in the range of 0.1% by mass or more and 10% by mass or less. By adding tungsten, molybdenum, or rhenium, the fluidity of the active metal brazing filler metal can be controlled. Magnesium (Mg) may be added to the active metal brazing filler metal.

[0047] The above-mentioned active metal solder material is effective for joining copper plates. The metal part 3 is a copper member, and it is preferable that the ceramic substrate and the copper member are joined via a Ag-free joining layer. The Ag-free joining layer refers to a member formed using an active metal solder material without adding Ag. It may contain Ag as an unavoidable impurity in an amount of 0.01 mass% or less (including zero as the detection limit). By using a Ag-free joining layer, the occurrence of Ag ion migration can be suppressed. Ag ion migration is a phenomenon in which Ag in the joining layer ionizes and moves when a voltage is applied in a humid environment. When Ag ions move, Ag is deposited at another location. This causes insulation failure. Among active metal solder materials, Ag is most likely to cause ion migration. By not using Ag in the joining layer, Ag ion migration can be suppressed.

[0048] When the metal plate is an aluminum plate, it is preferable to use an Al-Si-based or Al-Mg-based solder material for the active metal solder material. The content of one or both of Si and Mg in the active metal solder material is preferably in the range of 0.1 mass% or more and 20 mass% or less.

[0049] The ceramic circuit board according to the embodiment can be used for a semiconductor device in which a semiconductor element is mounted on the metal part 3. The ceramic circuit board preferably includes a mold resin.

[0050] FIG. 7 is a side view showing an example of a semiconductor device according to the embodiment. In FIG. 7, reference numeral 1 indicates a ceramic circuit board. Reference numeral 6 indicates a semiconductor element. Reference numeral 7 indicates a mold resin. Reference numeral 10 indicates a semiconductor device. The semiconductor element 7 is mounted on the metal part 3. FIG. 7 illustrates a semiconductor device 10 on which two semiconductor elements 7 are mounted. The semiconductor device 10 according to the embodiment is not limited to this form. The number of semiconductor elements 7 is arbitrary. The semiconductor device 10 may include wire bonding or a lead frame (not shown).

[0051] In the form shown in FIG. 7, the first surface 2a on which the semiconductor element 7 is mounted is covered with a mold resin 8. The mold resin 8 is not limited to such a form, and the metal part 5 of the semiconductor device 10 may also be covered with the mold resin 8.

[0052] The mold resin 8 serves to protect the semiconductor element 7, wiring, etc. from external stress. The mold resin also serves to protect the semiconductor element 7, etc. from outside air such as moisture. Mainly thermosetting resins are used for the mold resin. Examples of thermosetting resins include epoxy resins and silicone resins.

[0053] Examples of the molding method include the transfer method and the compression method. The transfer method is a sealing method in which molten resin is injected into a mold and cured. A mold formed by the transfer method is called a transfer mold. The compression method is a sealing method in which resin is previously put into a mold, melted, and cured. A mold formed by the compression method is called a compression mold. The transfer mold is excellent in mass productivity because it is a method of injecting resin. Since the transfer mold involves resin flow, there is a possibility of displacement of the semiconductor element, wire bonding, etc. In the compression method, since the resin is previously put into the mold and melted, the influence on the displacement of the semiconductor element, etc. is small. On the other hand, the resin must be put into the mold in advance. Therefore, the mass productivity by the compression method is lower than that of the transfer mold.

[0054] In the ceramic circuit board according to the embodiment, the surface of the ceramic substrate in the gap between the metal parts has an average length RSm of the roughness curve element of 40 μm or more. The cycle of peaks and valleys is enlarged. Thereby, the adhesion to the mold resin is improved. The adhesion can be improved by either the transfer molding method or the compression molding method. For example, transfer molding involves resin flow. Even if the resin flows, by enlarging the cycle of peaks and valleys, the flowing resin can enter the surface irregularities. Thereby, the adhesion can be improved. In other words, it is suitable for the semiconductor device 10 including the mold resin 8.

[0055] In a semiconductor device including a mold resin, when measuring the average length RSm of the roughness curve element in the gap (region between metal parts), the mold resin is removed and then the average length RSm is measured. Examples of the method for removing the mold resin include chemical treatment for dissolving only the resin.

[0056] Next, a method for manufacturing the ceramic circuit board 1 according to the embodiment will be described. The manufacturing method of the ceramic circuit board 1 according to the embodiment is not limited as long as it has the above configuration. Here, a method for manufacturing the ceramic circuit board 1 with good yield will be described.

[0057] First, a bonded body of a ceramic substrate 2 and a metal plate is prepared. The metal plate is provided on one or both sides of the ceramic substrate 2. The ceramic substrate 2 is preferably one selected from a silicon nitride substrate, an aluminum nitride substrate, an alumina substrate, a zirconia substrate, and an aldyl substrate. The metal plate is preferably one or more selected from a copper plate, a copper alloy plate, an aluminum plate, and an aluminum alloy plate. For bonding the ceramic substrate 2 and the metal plate, a method using an active metal bonding method is preferable.

[0058] When the metal plate is a copper plate (including copper alloy plates), the active metal brazing filler metal has Cu or Ag as the main component and further contains one or more selected from Ti, Zr, and Hf. If necessary, one or more selected from Sn, In, or C (carbon) may be added. When the metal plate is an aluminum plate, it is preferable to use an Al-Si-based or Al-Mg-based brazing filler metal for the active metal brazing filler metal. The preferable composition range of the active metal brazing filler metal is as described above.

[0059] Examples of the bonding step include a step of heating a laminate of a ceramic substrate and a metal plate at 600 to 980 °C in a vacuum or an inert atmosphere. Regarding the vacuum, the pressure is preferably 10 -2 Pa or less. As the inert atmosphere, a nitrogen atmosphere is preferable. In the bonding step in a vacuum, it is preferable to use a batch furnace. In the bonding step in an inert atmosphere, it is preferable to use a continuous furnace. By the bonding step, a bonded body in which the ceramic substrate 2 and the metal plate are bonded via the bonding layer 4 is prepared.

[0060] Next, an etching step is performed. The etching step is carried out to impart a circuit shape to the metal plate. By imparting a circuit shape to the metal plate, the above-described metal part 3 is obtained. Further, by imparting a circuit shape to the metal plate, a ceramic circuit board 1 is manufactured. Note that a metal plate that has been processed into a circuit shape in advance may be bonded to the ceramic substrate 2. In this case, there is no need to perform the etching step, and the metal plate with the circuit shape corresponds to the above-described metal part 3.

[0061] It is effective to utilize the etching step for the control of RSm, Rp, and Rv. In the bonding layer using the active metal brazing filler metal, a layer mainly composed of Ag or Cu and a layer mainly composed of an active metal are formed. International Publication No. WO2019 / 054294 (Patent Document 4) mentions a method using a brazing filler metal etching step and a chemical polishing step as the etching step of the bonding layer using the active metal brazing filler metal.

[0062] When a part of the copper plate is etched, a part of the bonding layer is exposed. In the brazing material etching process, the exposed part of the bonding layer is removed. Also, when a part of the brazing material is exposed, the surface of the exposed brazing material may be oxidized. Depending on the etching process of the copper plate, reaction products may also be formed on the surface of the brazing material. The chemical polishing process is performed to remove oxides or reaction products formed on the surface of the brazing material. By performing the chemical polishing process, the bonding layer can be efficiently removed in the subsequent brazing material etching process.

[0063] For the control of RSm etc., it is effective to increase the etching amount of the brazing material etching solution. As a method of increasing the etching amount of the brazing material etching solution, one or more selected from increasing the etching rate of the brazing material etching solution, suppressing the decrease in the etching rate of the brazing material etching solution, and lengthening the etching time are effective.

[0064] Examples of the brazing material etching solution include a solution with a pH of 6 or less containing hydrogen peroxide. To increase the etching rate of the brazing material etching solution, it is effective to increase the concentration of the hydrogen peroxide solution. The etching solution may contain ammonium fluoride and a pH stabilizer in addition to hydrogen peroxide. As the pH stabilizer, one or more selected from HBF 4 , EDTA, NTA, CyDTA, DTPA, TTHA, GEDTA, glycine, dicarboxylic acid, tricarboxylic acid, oxycarboxylic acid and their salts can be mentioned.

[0065] To suppress the decrease in the etching rate of the brazing material etching solution, a method of introducing a new etching solution when the concentration of the hydrogen peroxide solution changes by 5 mass% is effective. Thereby, the decrease in the etching rate of the brazing material etching solution can be suppressed. Lengthening the etching time of the brazing material etching is also effective for the control of RSm. As a guide, the time for one brazing material etching process is set to 15 minutes or more.

[0066] Also, for the control of RSm and the like, it is effective to increase the amount of the bonding layer removed by the chemical mechanical polishing process. Examples of methods for increasing the amount removed by the chemical mechanical polishing process include increasing the concentration of hydrochloric acid or sulfuric acid and increasing the time for performing the chemical mechanical polishing process. For example, when a combination of hydrogen peroxide and sulfuric acid is used as the brazing material etching solution, the sulfuric acid content should be 5% by mass or more. When hydrochloric acid is used as the brazing material etching solution, a method of making the hydrochloric acid content 7% by mass or more can be mentioned. It is also effective to set the time for performing the chemical mechanical polishing process to 5 minutes or more.

[0067] The above brazing material etching process and chemical mechanical polishing process may be executed in combination. That is, the above methods may be applied to each of the chemical mechanical polishing process and the brazing material etching process. Also, the chemical mechanical polishing process and the brazing material etching process may be executed alternately. In this case, it is effective to apply the above method to the last chemical mechanical polishing process among the plurality of chemical mechanical polishing processes and to apply the above method to the last brazing material etching process among the plurality of brazing material etching processes.

[0068] The last brazing material etching process is a process of completely removing the bonding layer. When the ceramic substrate 2 and the metal plate are joined by the active metal bonding method, a layer mainly composed of the active metal is formed. When Ti is used as the active metal and a silicon nitride substrate is used as the ceramic substrate, the layer mainly composed of the active metal becomes a titanium nitride (TiN) layer. The formation of the layer mainly composed of the active metal in the bonding layer improves the bonding strength. On the other hand, since the layer mainly composed of the active metal has conductivity, if it remains on the ceramic circuit board 1, it may cause poor conduction between the metal parts 3. Therefore, it is necessary to remove the layer mainly composed of the active metal. By increasing the amount removed in the etching process or the chemical mechanical polishing process, the layer mainly composed of the active metal and a part of the surface of the ceramic substrate below it can be removed. Thereby, control of RSm and the like can be performed.

[0069] When a metal plate with a circuit shape is pre-bonded to the ceramic substrate 2 and no etching process is performed, it is effective to perform a chemical polishing process on the gap between the metal plates. Also, if necessary, a method of controlling RSm etc. by performing a blasting process or a polishing process on the second region is also effective.

[0070] Through the above processes, the ceramic circuit board 1 according to the embodiment can be manufactured. Furthermore, by mounting a semiconductor element 7 etc. on the ceramic circuit board 1, the semiconductor device 10 can be manufactured. If necessary, a mold resin 8 is provided in the semiconductor device 10.

[0071] (Examples 1 - 7, Comparative Examples 1 - 2) As the ceramic substrates according to Examples 1 - 6, silicon nitride substrates were prepared. The thermal conductivity of the silicon nitride substrate is 90 W / m·K, and the three-point bending strength is 700 MPa. The longitudinal dimension of the silicon nitride substrate is 50 mm, the transverse dimension is 40 mm, and the thickness is 0.32 mm. As the metal plate, a copper plate with a thickness of 0.8 mm was prepared.

[0072] Next, a bonded body (silicon nitride circuit board) of the silicon nitride substrate and the copper plate was manufactured using the active metal bonding method. Copper plates with a thickness of 0.8 mm were bonded to both sides of the silicon nitride substrate respectively. The composition of the active metal solder is as shown in Table 1.

[0073] As the ceramic substrate according to Example 7, an aluminum nitride substrate was prepared. The thermal conductivity of the aluminum nitride substrate is 170 W / m·K, and the three-point bending strength is 400 MPa. As the metal plate, a copper plate with a thickness of 0.4 mm was prepared. Using the active metal bonding method, copper plates with a thickness of 0.4 mm were bonded to both sides of the aluminum nitride substrate respectively, and a bonded body (aluminum nitride circuit board) was manufactured. Also, as Comparative Example 1, a silicon nitride circuit board was manufactured. As Comparative Example 2, an aluminum nitride circuit board was manufactured.

[0074]

Table 1

[0075] Next, an etching process was used to impart a circuit shape to the copper plate and form the metal part 3. For the ceramic circuit board according to the example, a method of increasing the etching amount of the brazing material etching solution or a method of increasing the amount removed by the chemical polishing process was used.

[0076] In the manufactured ceramic circuit board, the total area (%) of the second region r2 is as shown in Table 2. The total area (%) of the second region r2 was calculated by (total of the areas of each second region r2 / surface area of the first surface 2a) × 100 (%). The surface area of the first surface 2a is 50 mm in length × 40 mm in width = 2000 mm 2 is. Also, RSm, Rp, and Rv in the second region r2 were measured. The measuring methods of RSm, Rp, and Rv are as described above.

[0077] [Table 2]

[0078] In the ceramic circuit board according to the example, RSm was set to 40 μm or more. Also, Rp was set to 1.0 μm or more and Rv was set to 1.0 μm or more. In Comparative Example 1 and Comparative Example 2, RSm was less than 40 μm.

[0079] Next, a semiconductor element was mounted on the ceramic circuit boards according to the examples and comparative examples to manufacture a semiconductor device. A mold resin was provided for the semiconductor device. The Ag migration characteristics and resin adhesion of the semiconductor device provided with the mold resin were measured.

[0080] In the evaluation of the Ag migration characteristics, a voltage was applied to the semiconductor device in an atmosphere of high temperature and high humidity, and the occurrence rate of Ag migration marks was measured. As the measuring device, an electrochemical migration evaluation system manufactured by Espec Corporation was used. In an environment of a temperature of 85°C and a humidity of 85%, an applied voltage of AC2000 V (peak voltage 2820 V) was continuously applied to the semiconductor device for 40 hours. The presence or absence of Ag migration marks on the surface of the ceramic circuit board was examined.

[0081] In each example and each comparative example, 100 semiconductor devices were evaluated. In each example, the number of semiconductor devices in which at least one Ag migration mark was present was counted. An example in which the counted number was 0 was regarded as "best". An example in which the counted number was 1 or more and 10 or less was regarded as "good". An example in which the counted number was 11 or more was regarded as "bad".

[0082] Regarding the resin adhesion, the presence or absence of peeling of the mold resin after the TCT test (thermal cycle test) was measured. In the TCT test, one cycle was defined as -40°C × 30 minutes → room temperature (25°C) × 10 minutes → 175°C × 30 minutes → room temperature (25°C) × 10 minutes, and the presence or absence of peeling of the mold resin after 300 cycles was measured. The presence or absence of resin peeling on the surface of the second region r2 was measured by ultrasonic flaw detection method (SAT). The peeling rate (%) of the mold resin was calculated by (total area where the resin has peeled in the second region r2 / total area of the second region r2) × 100. The results are shown in Table 3.

[0083] [Table 3]

[0084] As can be seen from Table 3, in the semiconductor device according to the example, the adhesion between the ceramic substrate and the resin was good. Even without providing a recess in the copper plate as in Patent Document 2, the adhesion was improved. Therefore, according to the embodiment, it is possible to suppress a decrease in the area for mounting the semiconductor element.

[0085] As in Example 6 and Example 7, when RSm was outside the range of 40 μm or more and 100 μm or less, resin peeling occurred. Therefore, it can be seen that RSm preferably falls within the range of 40 μm or more and 100 μm or less. Further, in Examples 4 to 7 using an Ag-free solder material, Ag ion migration did not occur. From this point of view, it is preferable to use an Ag-free solder material. In other words, by using an Ag-free solder material, it is possible to achieve both suppression of Ag ion migration and improvement in the adhesion of the mold resin. On the other hand, in Comparative Example 1 and Comparative Example 2, since RSm was small, the adhesion of the mold resin decreased.

[0086] Embodiments of the present invention may include the following configurations. (Configuration 1) A ceramic substrate having a first surface, and a plurality of metal parts respectively provided in a plurality of first regions on the first surface, the first surface has a second region located between adjacent first regions, a ceramic circuit board, wherein an average length RSm of roughness curve elements in the second region is 40 μm or more. (Configuration 2) The ceramic circuit board according to Configuration 1, wherein the average length RSm in the second region is 100 μm or less. (Configuration 3) The ceramic circuit board according to any one of Configurations 1 to 2, wherein a maximum peak height Rp of a surface roughness curve in the second region is 1.0 μm or more. (Configuration 4) The ceramic circuit board according to any one of Configurations 1 to 3, wherein a maximum valley depth Rv of a surface roughness curve in the second region is 1.0 μm or more. (Configuration 5) The ceramic circuit board according to any one of Configurations 1 to 4, wherein a sum of areas of one or more second regions with respect to a surface area of the first surface is within a range of 5% or more and 50% or less. (Configuration 6) The ceramic substrate is a silicon nitride substrate, and the ceramic circuit board according to any one of Configurations 1 to 5. (Configuration 7) Each of the plurality of metal parts is a copper member, The plurality of copper members are each joined to the plurality of first regions via a plurality of bonding layers that do not contain Ag, and the ceramic circuit board according to any one of Configurations 1 to 6. (Configuration 8) In the second region, the maximum peak height Rp of the roughness curve is 1.0 μm or more, and the maximum valley depth Rv of the roughness curve is 1.0 μm or more, and the ceramic circuit board according to Configuration 7. (Configuration 9) The sum of the areas of the one or more second regions with respect to the surface area of the first surface is within a range of 5% or more and 50% or less, and the ceramic circuit board according to Configuration 8. (Configuration 10) The ceramic circuit board according to any one of Configurations 1 to 9, A semiconductor element mounted on any one of the plurality of metal parts, A semiconductor device comprising. (Configuration 11) The semiconductor device according to Configuration 10, further comprising a mold resin that covers the second region.

[0087] As described above, some embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof. Also, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0088] 1... Ceramic circuit board 2... Ceramic substrate 2a…First surface 2b…Second surface (back surface) 3, 3a~3d…Metal part 4…Bonding layer 5…Metal part (inner metal part) 6…Bonding layer 7…Semiconductor element 8…Molding resin 10…Semiconductor device r1…First region r2…Second region

Claims

1. A first step of producing a laminate in which a plurality of metal parts are respectively joined to a plurality of first regions on a first surface of a ceramic substrate; a second step of subjecting a second region located between adjacent first regions on the first surface to an etching step or a chemical polishing step, A method for manufacturing a ceramic circuit board, wherein an average length RSm in the second region after the second step is 40 μm or more when measured under measurement conditions of: λs filter: present; λs cutoff ratio: 300; cutoff type: Gaussian; and cutoff wavelength (λc): 0.8 mm.

2. the laminate includes a bonding layer formed on the plurality of first regions and on the second region, the plurality of metal portions are bonded to the plurality of first regions via the bonding layer, In the second step, the etching step is performed at least once on the bonding layer formed on the second region; The method for producing a ceramic circuit board according to claim 1 , wherein the time for performing the etching process once on the bonding layer is 15 minutes or more.

3. the laminate includes a bonding layer formed on the plurality of first regions and on the second region, the plurality of metal portions are bonded to the plurality of first regions via the bonding layer, In the second step, the chemical polishing step is performed on the bonding layer formed on the second region using a brazing material etching solution containing hydrogen peroxide and hydrochloric acid. The method for producing a ceramic circuit board according to any one of claims 1 and 2.

4. 3. The method for producing a ceramic circuit board according to claim 1, wherein the second step includes a chemical polishing step for 5 minutes or more.

5. The method for producing a ceramic circuit board according to claim 3 , wherein the second step includes a chemical polishing step for 5 minutes or more.

6. The second step includes the etching step, 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein hydrogen peroxide is used in the etching step, and new etching solution is added when the concentration of the hydrogen peroxide changes by 5 mass %.

7. The second step includes the etching step, 6. The method for producing a ceramic circuit board according to claim 5, wherein hydrogen peroxide is used in the etching step, and new etching solution is added when the concentration of the hydrogen peroxide changes by 5 mass %.

8. 2. The method for manufacturing a ceramic circuit board according to claim 1, wherein in the second step, a part of the ceramic substrate is removed in the second region while the plurality of metal portions are provided on the plurality of first regions, respectively.

9. 9. The method for producing a ceramic circuit board according to claim 8, wherein the average length RSm in the second region after the second step is 153 μm or less.

10. 3. The method for producing a ceramic circuit board according to claim 1, wherein a maximum peak height Rp of a surface roughness curve in said second region after said second step is 1.0 μm or more.

11. 3. The method for producing a ceramic circuit board according to claim 1, wherein a maximum valley depth Rv of a surface roughness curve in said second region after said second step is 1.0 μm or more.

12. 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein in the laminate, a sum of an area of ​​the one or more second regions with respect to a surface area of ​​the first surface is within a range of 5% to 50%.

13. 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein the ceramic board is a silicon nitride board.

14. Each of the plurality of metal parts is a copper member, 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein the copper members are bonded to the first regions via a bonding layer that does not contain Ag.

15. 9. The method for producing a ceramic circuit board according to claim 8, wherein the maximum peak height Rp of the roughness curve in the second region after the second step is 1.0 μm or more, and the maximum valley depth Rv of the roughness curve is 1.0 μm or more.

16. The method for producing a ceramic circuit board according to claim 15 , wherein a sum of an area of ​​the one or more second regions with respect to a surface area of ​​the first surface is within a range of 5% to 50%.

17. The method for producing a ceramic circuit board according to claim 16, wherein the ceramic board is a silicon nitride board.

18. Implementing the method for manufacturing a ceramic circuit board according to any one of claims 1 and 2, A method for manufacturing a semiconductor device, comprising mounting a semiconductor element on any one of the plurality of metal portions of the ceramic circuit board.

19. The method for manufacturing a semiconductor device according to claim 18 , further comprising the step of covering the second region with a molding resin after the semiconductor element is mounted.

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