Image sensor and manufacturing method therefor

Abstract

To provide an image sensor having more improved electric and optical characteristics.SOLUTION: The present invention provides an image sensor. The image sensor of the present invention comprises a first surface and a second surface that are opposite each other, and comprises a semiconductor substrate having a first conductive type, a photoelectric conversion that is positioned in the semiconductor substrate and has a second conductive type, and a first pixel separation construction body between the photoelectric conversion regions adjacent to each other in a first direction. The first pixel separation construction body is adjacent to the semiconductor substrate, and can comprises: a first conductive pattern having a shape where it is extended to the second surface from the second surface, an internal insulation pattern onto an inside surface of the first conductive pattern, an embedded insulation pattern onto the internal insulation pattern, and an etching stop film between the internal insulation pattern and the embedded insulation pattern.SELECTED DRAWING: Figure 4A

Description

Technical Field

[0001] The present invention relates to an image sensor and a method for manufacturing the same, and more particularly, to an image sensor having improved electrical and optical characteristics and a method for manufacturing the same.

Background Art

[0002] An image sensor converts an optical image into an electrical signal. With the development of the computer and communication industries, the demand for image sensors with improved performance in various fields such as digital cameras, video cameras, PCS (Personal Communication System), game devices, security cameras, and medical micro cameras is increasing. Image sensors include charge-coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate a signal processing circuit on a single chip, so the product can be miniaturized. CMOS image sensors also have very low power consumption, so they are easily applicable to products with limited battery capacity. In addition, since CMOS image sensors can use CMOS process technology compatibly, the manufacturing cost can be reduced. Therefore, as high resolution becomes achievable with the development of CMOS image sensor technology, their use is increasing rapidly.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide an image sensor having further improved electrical and optical characteristics.

[0005] The problem to be solved by the present invention is to provide a method for manufacturing an image sensor having more improved electrical and optical characteristics.

[0006] The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned should be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0007] In order to achieve the problem to be solved, an image sensor according to an embodiment of the present invention includes a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing each other; a photoelectric conversion region located in the semiconductor substrate and having a second conductivity type; and a first pixel separation structure between the photoelectric conversion regions adjacent to each other in a first direction. The first pixel separation structure includes a first conductive pattern adjacent to the semiconductor substrate and having a shape extending from the first surface to the second surface; an internal insulating pattern on an inner surface of the first conductive pattern; an embedded insulating pattern on the internal insulating pattern; and an etching stop film between the internal insulating pattern and the embedded insulating pattern.

[0008] In order to achieve the problem to be solved, an image sensor according to an embodiment of the present invention includes a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing each other; a photoelectric conversion region located in the semiconductor substrate and having a second conductivity type; an element isolation film located in the semiconductor substrate and adjacent to the first surface; a first pixel separation structure located between two adjacent ones of the photoelectric conversion regions and including a first etching stop film; and a second pixel separation structure located between four adjacent ones of the photoelectric conversion regions and including a second etching stop film. The first etching stop film and the second etching stop film can be located between a lower surface of the element isolation film and the second surface.

[0009] In order to achieve the problem to be solved, an image sensor according to an embodiment of the present invention includes a light-receiving region, a light-shielding region, and a pad region, and a semiconductor substrate having a first surface and a second surface facing each other; a pixel separation structure disposed in the semiconductor substrate in the light-receiving region and the light-shielding region, defining a plurality of pixel regions, and including a first conductive pattern; a transfer gate electrode on the first surface of the semiconductor substrate; a plurality of photoelectric conversion regions in the semiconductor substrate in the light-receiving region and the light-shielding region; a pixel circuit layer on the first surface of the semiconductor substrate; and a light-transmitting layer on the second surface of the semiconductor substrate. The pixel separation structure includes a first pixel separation structure between the pixel regions adjacent to each other in a first direction or a second direction intersecting the first direction, and a second pixel separation structure between the pixel regions adjacent to each other in a third direction obliquely to the first and second directions. The first pixel separation structure further includes an internal insulating pattern on an inner surface of the first conductive pattern, and the second pixel separation structure can further include a second conductive pattern on the inner surface of the first conductive pattern.

[0010] In order to achieve the problem to be solved, a method of manufacturing an image sensor according to an embodiment of the present invention includes providing a semiconductor substrate including a first surface and a second surface facing each other; removing a part of the semiconductor substrate to form a first trench and a second trench; forming a first pixel separation structure including an etch stop film in the first trench; and forming a second pixel separation structure in the second trench. Forming the first pixel separation structure can include forming the etch stop film using a first ion implantation process.

Effects of the Invention

[0011] An image sensor according to an embodiment of the present invention can include a pixel separation structure including an etch stop film. The etch stop film can determine the level (or height) of the upper surface of the first conductive pattern in the manufacturing method of the image sensor. Thereby, the area where the semiconductor substrate and the first conductive pattern are horizontally overlapped with each other can be increased. Therefore, since the dark current of the image sensor can be sufficiently reduced by the negative bias applied to the first conductive pattern, the electrical and optical characteristics of the image sensor can be improved.

Brief Description of the Drawings

[0012]

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The same reference numerals can refer to the same components throughout the entire text of this specification.

[0014] FIG. 1 is a block diagram of an image sensor according to an embodiment of the present invention.

[0015] Referring to FIG. 1, the image sensor includes an Active Pixel Sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a Correlated Double Sampler (CDS) 6, an Analog to Digital Converter (ADC) 7, and an Input / Output (I / O) buffer 8.

[0016] The Active Pixel Sensor array 1 includes a plurality of unit pixels arranged two-dimensionally and converts an optical signal into an electrical signal. The Active Pixel Sensor array 1 can be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal from the row driver 3. Also, the converted electrical signal is provided to the Correlated Double Sampler 6.

[0017] The row driver 3 provides a plurality of driving signals for driving a number of unit pixels to the Active Pixel Sensor array 1 according to the result decoded by the row decoder 2. When the unit pixels are arranged in a matrix shape, the driving signals can be provided for each row.

[0018] The timing generator 5 provides timing signals and control signals to the row decoder 2 and the column decoder 4.

[0019] The Correlated Double Sampler 6 receives, holds, and samples the electrical signal generated by the Active Pixel Sensor array 1. The Correlated Double Sampler 6 double-samples a specific noise level and a signal level by the electrical signal and outputs a level corresponding to the difference between the noise level and the signal level.

[0020] The analog-digital converter 7 converts an analog signal corresponding to the level output by the correlation double sampler 6 into a digital signal and outputs it.

[0021] The input / output buffer 8 latches a digital signal, and the latched signal sequentially outputs the digital signal to a video signal processing unit (not shown) according to the decoding result in the column decoder 4.

[0022] FIG. 2A and FIG. 2B are circuit diagrams of unit pixels of an image sensor according to an embodiment of the present invention.

[0023] Referring to FIG. 2A, the unit pixel P can include first and second photoelectric conversion elements PD1, PD2, first and second transfer transistors TX1, TX2, and four pixel transistors. For example, each of the four pixel transistors can correspond to a reset transistor (RX), a source follower transistor (SF), a selection transistor (SEL), and a dual conversion gain transistor (DCX), but is not limited thereto. That is, pixel transistors can be provided in various ways in each unit pixel P.

[0024] The first and second photoelectric conversion elements PD1, PD2 can generate and accumulate charges corresponding to incident light. For example, the first and second photoelectric conversion elements PD1, PD2 can be a photo diode, a photo transistor, a photo gate, a Pinned Photo Diode (PPD), and combinations thereof.

[0025] The first and second transfer transistors TX1 and TX2 transfer the charges accumulated in the first and second photoelectric conversion elements PD1 and PD2 to the floating diffusion region FD. The first and second transfer transistors TX1 and TX2 can be controlled by signals applied to the first and second transfer gate electrodes TG1 and TG2. The first and second transfer transistors TX1 and TX2 can share the floating diffusion region FD, but are not limited thereto. That is, each of the first and second transfer transistors TX1 and TX2 can be connected to different floating diffusion regions FD from each other.

[0026] The floating diffusion region FD accumulatively stores the charges generated in the first or second photoelectric conversion element PD1 or PD2. The source follower transistor SF can be controlled according to the amount of the photoelectric charges accumulated in the floating diffusion region FD.

[0027] The reset transistor RX can periodically initialize the charges accumulated in the floating diffusion region FD according to a reset signal applied to the reset gate electrode RG. Specifically, the drain terminal of the reset transistor RX can be connected to the double conversion gain transistor DCX, and the source terminal can be connected to the pixel power supply voltage VDD. When the reset transistor RX and the double conversion gain transistor DCX are turned on, the pixel power supply voltage VDD is transmitted to the floating diffusion region FD. Thereby, the charges accumulated in the floating diffusion region FD are discharged, and the floating diffusion region FD can be initialized.

[0028] The dual conversion gain transistor DCX can be connected between the floating diffusion region FD and the reset transistor RX. The dual conversion gain transistor DCX can control the conversion gain by changing the capacitance of the floating diffusion region FD in response to a dual conversion gain control signal. That is, different conversion gains can be provided according to the operation of the dual conversion gain transistor DCX. Therefore, in the high illuminance mode, the dual conversion gain transistor DCX can be turned on, and in the low illuminance mode, the dual conversion gain transistor DCX can be turned off.

[0029] The source follower transistor SF can be a source follower buffer amplifier that generates a source-drain current proportional to the charge amount of the floating diffusion region FD input to the source follower gate electrode. The source follower transistor SF amplifies the potential change in the floating diffusion region FD and outputs the amplified signal to the output line Vout through the selection transistor SEL. The source follower transistor SF can be connected to the pixel power supply voltage VDD and the selection transistor SEL. That is, the source follower transistor SF can be located between the pixel power supply voltage VDD and the selection transistor SEL.

[0030] The selection transistor SEL can select the unit pixel P to be read out in row units. When the selection transistor SEL is turned on by a selection signal applied to the selection gate electrode SG, the electrical signal output to the drain electrode of the source follower transistor SF can be output to the output line Vout.

[0031] Referring to FIG. 2B, the unit pixel P can include first to fourth photoelectric conversion elements PD1, PD2, PD3, PD4, first to fourth transfer transistors TX1, TX2, TX3, TX4, and four pixel transistors.

[0032] The first to fourth transfer transistors TX1, TX2, TX3, and TX4 can share a floating diffusion region FD. The first to fourth transfer transistors TX1, TX2, TX3, and TX4 can be controlled by signals applied to the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4.

[0033] For example, the four pixel transistors can correspond to the reset transistor RX, the source follower transistor SF, the selection transistor SEL, and the double conversion gain transistor DCX described in FIG. 2A.

[0034] FIG. 3 is a plan view showing an image sensor according to an embodiment of the present invention. FIGS. 4A and 4B are cross-sectional views of the image sensor according to an embodiment of the present invention, and are views cut along the lines A-A' and B-B' of FIG. 3.

[0035] Referring to FIGS. 3, 4A, and 4B, the image sensor according to an embodiment of the present invention can include a photoelectric conversion layer 10, a pixel circuit layer 20, and a light transmission layer 30 from a vertical perspective.

[0036] From a vertical perspective, the photoelectric conversion layer 10 can be located between the pixel circuit layer 20 and the light transmission layer 30. Light incident from the outside can be converted into an electrical signal by the photoelectric conversion layer 10. The photoelectric conversion layer 10 can include a semiconductor substrate 100, a pixel isolation structure PIS located inside the semiconductor substrate 100, a barrier region 103, an element isolation film 105, and a photoelectric conversion region PD.

[0037] Specifically, the semiconductor substrate 100 can have a first surface 100a and a second surface 100b facing each other. The semiconductor substrate 100 can be a substrate in which an epitaxial layer having a first conductivity type (for example, p-type) is formed on a bulk silicon substrate having the first conductivity type. During the manufacturing process of the image sensor, the bulk silicon substrate may be removed and only the epitaxial layer having the first conductivity type remains. Alternatively, the semiconductor substrate 100 may be a bulk silicon substrate including a well of the first conductivity type. That is, the semiconductor substrate 100 can be a substrate having the first conductivity type.

[0038] The element isolation film 105 can be adjacent to the first surface 100a of the semiconductor substrate 100 while being located within the semiconductor substrate 100. The element isolation film 105 can be located within an element isolation trench formed by recessing the first surface 100a of the semiconductor substrate 100. The upper surface of the element isolation film 105 can be coplanar with the first surface 100a of the semiconductor substrate 100. The element isolation film 105 can include an insulating material. The element isolation film 105 can define active portions on the first surface 100a of the semiconductor substrate 100. For example, the element isolation film 105 can define a first active portion ACT1 and a second active portion ACT2. Each of the first active portion ACT1 and the second active portion ACT2 can be located separately from each other and can have different sizes.

[0039] The pixel separation structure PIS is located within the semiconductor substrate 100 and can define a plurality of pixel regions PR. In plan view, the pixel separation structure PIS can surround the plurality of pixel regions PR or the photoelectric conversion region PD. Specifically, the pixel separation structure PIS can include a first pixel separation structure PIS1 located within a first trench T1 and a second pixel separation structure PIS2 located within a second trench T2.

[0040] Each of the first trenches T1 can be provided between pixel regions PR or photoelectric conversion regions PD adjacent to each other in the first direction D1 or the second direction D2. Each of the second trenches T2 can be provided between pixel regions PR or photoelectric conversion regions PD adjacent to each other in the third direction D3. In plan view, the first trench T1 can be adjacent to one side surface of the pixel region PR or the photoelectric conversion region PD. In plan view, the second trench T2 can be adjacent to the vertex of the pixel region PR or the photoelectric conversion region PD. For example, each of the first trenches T1 can be located between two of the pixel regions PR or the photoelectric conversion regions PD adjacent to each other. Each of the second trenches T2 can be located between four of the pixel regions PR or the photoelectric conversion regions PD adjacent to each other.

[0041] The pixel isolation structure PIS can penetrate the semiconductor substrate 100 from the first surface 100a to the second surface 100b of the semiconductor substrate 100. From a vertical perspective, the pixel isolation structure PIS can have a shape extending in the fourth direction D4. The pixel isolation structure PIS can have a length in the fourth direction D4. The length of the pixel isolation structure PIS can be substantially the same as the vertical thickness of the semiconductor substrate 100. The pixel isolation structure PIS can penetrate a part of the element isolation film 105.

[0042] In this specification, the first direction D1, the second direction D2, and the third direction D3 can be parallel to the first surface 100a and the second surface 100b of the semiconductor substrate 100. The first direction D1, the second direction D2, and the third direction D3 can intersect each other. The first direction D1 and the second direction D2 can be orthogonal to each other. That is, the third direction D3 can be oblique to the first direction D1 or the second direction D2. The fourth direction D4 can intersect the first direction D1, the second direction D2, and the third direction D3. For example, the fourth direction D4 can be a direction perpendicular to the first surface 100a and the second surface 100b of the semiconductor substrate 100.

[0043] The pixel isolation structure PIS can have an upper width on the first surface 100a of the semiconductor substrate 100 and can have a lower width on the second surface 100b of the semiconductor substrate 100. The lower width of the pixel isolation structure PIS can be smaller than the upper width of the pixel isolation structure PIS. The width of the pixel isolation structure PIS becomes narrower as it goes from the first surface 100a to the second surface 100b of the semiconductor substrate 100, but is not limited thereto. For example, the pixel isolation structure PIS can have a constant width or a widening width as it goes from the first surface 100a to the second surface 100b of the semiconductor substrate 100.

[0044] The structures of the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 will be described in more detail with reference to FIGS. 5A to 7B.

[0045] The barrier region 103 can be provided in the semiconductor substrate 100 adjacent to the sidewall of the pixel isolation structure PIS. The barrier region 103 can contain impurities of the first conductivity type (e.g., p-type) same as the semiconductor substrate 100. The barrier region 103 can reduce the generation of dark current by charge-hole pairs (EHP: Electron-Hole Pair) generated by surface defects of the first trench T1 and the second trench T2 when forming the first trench T1 and the second trench T2.

[0046] The photoelectric conversion region PD can be provided within the semiconductor substrate 100 of each pixel region PR. The photoelectric conversion region PD can generate photo charges in proportion to the intensity of incident light. The photoelectric conversion region PD can have a second conductivity type opposite to the first conductivity type of the semiconductor substrate 100. A photodiode can be formed by the junction of the photoelectric conversion region PD having the second conductivity type and the semiconductor substrate 100 having the first conductivity type. For example, the photoelectric conversion region PD may have a concentration difference of impurities between the region adjacent to the first surface 100a and the region adjacent to the second surface 100b so as to have a potential gradient between the first surface 100a and the second surface 100b of the semiconductor substrate 100. For example, the photoelectric conversion region PD may include a plurality of vertically stacked doping regions.

[0047] The pixel circuit layer 20 can be located on the first surface 100a of the semiconductor substrate 100. The pixel circuit layer 20 can include a pixel circuit (e.g., MOS transistor) electrically connected to the photoelectric conversion region PD. That is, the pixel circuit layer 20 can include a reset transistor RX, a selection transistor SEL, a double conversion gain transistor DCX, and a source follower transistor SF, which are the pixel transistors described in FIG. 2A.

[0048] In each pixel region PR, a transfer gate electrode TG can be disposed above the first active portion ACT1 of the semiconductor substrate 100. The transfer gate electrode TG can be located on the first surface 100a of the semiconductor substrate 100. The transfer gate electrode TG can penetrate a part of the semiconductor substrate 100. From a vertical perspective, the transfer gate electrode TG can be T-shaped. A gate insulating film GIL can be provided between the transfer gate electrode TG and the semiconductor substrate 100.

[0049] The floating diffusion region FD can be provided within the first active portion ACT1 on one side of the transfer gate electrode TG. The floating diffusion region FD can be formed by ion implanting impurities of a second conductivity type opposite to the first conductivity type of the semiconductor substrate 100. For example, the floating diffusion region FD can have the second conductivity type.

[0050] In each pixel region PR, at least one pixel transistor can be provided in the second active portion ACT2. The pixel transistor can be one of the reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and selection transistor SEL described with reference to FIGS. 2A and 2B. The pixel transistor can include a pixel gate electrode PG that crosses the second active portion ACT2 and source / drain regions provided within the second active portion ACT2 on both sides of the pixel gate electrode PG. The pixel gate electrode PG can have a bottom surface parallel to the upper surface of the second active portion ACT2. For example, the pixel gate electrode PG can include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0051] The interlayer insulating film 210 is located on the first surface 100a of the semiconductor substrate 100 and can be composed of multiple layers. The interlayer insulating film 210 can cover the transfer gate electrode TG and the wiring structure connected to the pixel circuit. The wiring structure can include metal wiring 223 and contact plugs 221 that connect them.

[0052] The light transmissive layer 30 can be located on the second surface 100b of the semiconductor substrate 100. The light transmissive layer 30 can include a planar insulating film 310, a grating structure 320, a protective film 330, a color filter 340, a microlens 350, and a passivation film 360. The light transmissive layer 30 can collect and filter light incident from the outside and provide it to the photoelectric conversion layer 10.

[0053] Specifically, the planar insulating film 310 can cover the second surface 100b of the semiconductor substrate 100. The planar insulating film 310 can be made of a transparent insulating material and can include a plurality of layers. The planar insulating film 310 can be made of an insulating material having different refractive indices from those of the semiconductor substrate 100. The planar insulating film 310 can include a metal oxide and / or a silicon oxide. For example, the planar insulating film 310 is Al 2 O 3 , CeF 3 , HfO 2 , ITO, MgO, Ta 2 O 5 , TiO 2 , ZrO 2 , Si, Ge, ZnSe, ZnS, or PbF2, etc. can be included. Differently, the planar insulating film 310 may be formed of an organic substance having a high refractive index and can include a siloxane resin, BCB (Benzocyclobutene), polyimide series, acryl series, Parylene C, PMMA (Poly(methyl methacrylate)), PET (Polyethylene terephthalate), etc. Further, the planar insulating film 310 can include strontium titanate (SrTiO 3 ), polycarbonate, glass, bromine, sapphire, cubic zirconia, potassium niobate (KNbO 3 ), moissanite (SiC), gallium(III) phosphide (GaP), gallium(III) arsenide (GaAs), etc.

[0054] The lattice structure 320 can be disposed on the flat insulating film 310. The lattice structure 320 can have a planar lattice shape similar to the pixel isolation structure PIS. In a plan view, the lattice structure 320 can be superimposed on the pixel isolation structure PIS. That is, the lattice structure 320 can be superimposed on the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. The width of the lattice structure 320 can be substantially the same as or smaller than the minimum width of the pixel isolation structure PIS.

[0055] The lattice structure 320 can include a light-shielding pattern and / or a low-refractive-index pattern. The light-shielding pattern can include a metallic substance such as, for example, titanium, tantalum, or tungsten. The low-refractive-index pattern can be made of a substance having a refractive index lower than that of the light-shielding pattern. The low-refractive-index pattern can be made of an organic substance and can have a refractive index of about 1.1 to 1.3. For example, the lattice structure 320 can be a polymer layer containing silica nanoparticles.

[0056] The protective film 330 can cover the surfaces of the flat insulating film 310 and the lattice structure 320. The protective film 330 can have a substantially uniform thickness. For example, the protective film 330 can include at least one single film or multiple films of aluminum oxide film and silicon carbon oxide film.

[0057] The color filter 340 can be formed on the protective film 330 corresponding to each of the pixel regions PR. The color filter 340 can fill the space defined by the lattice structure 320. For example, the color filter 340 can include a red, green, or blue color filter according to a unit pixel, or can include a magenta, cyan, or yellow color filter.

[0058] The microlens 350 can be disposed on the color filter 340. The microlens 350 can have a bulging shape and can have a predetermined radius of curvature. For example, the microlens 350 can include a light-transmissive resin.

[0059] The passivation film 360 can be located on the microlens 350 and can cover the surface of the microlens 350 with a uniform thickness. For example, the passivation film 360 can include an inorganic oxide.

[0060] FIGS. 5A to 7B are enlarged views for explaining an image sensor according to an embodiment of the present invention. FIGS. 5A, 6A, and 7A are enlarged views of a P1 portion of FIG. 4A, and FIGS. 5B, 6B, and 7B are enlarged views of a P2 portion of FIG. 4B.

[0061] Referring to FIGS. 5A and 5B, the first pixel isolation structure PIS1 can be located in a first trench T1 formed by recessing a first surface 100a of the semiconductor substrate 100. The second pixel isolation structure PIS2 can be located in a second trench T2 formed by recessing the first surface 100a of the semiconductor substrate 100. The first trench T1 can have a first width W1 in a first direction D1 on the first surface 100a of the semiconductor substrate 100. The second trench T2 can have a second width W2 in a third direction D3 on the first surface 100a of the semiconductor substrate 100. The first width W1 can be smaller than the second width W2. Thereby, the width of the first pixel isolation structure PIS1 in the first direction D1 can be smaller than the width of the second pixel isolation structure PIS2 in the third direction D3.

[0062] The first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 can include a liner insulating pattern 111, a first conductive pattern 113, and an embedded insulating pattern 119. The first pixel isolation structure PIS1 can further include an internal insulating pattern 115 and an etch stop film 117. The second pixel isolation structure PIS2 can further include a second conductive pattern 118.

[0063] The liner insulating pattern 111 can be located on the inner walls of the first trench T1 and the second trench T2. The liner insulating pattern 111 can cover the inner walls of the first trench T1 and the second trench T2 with a uniform thickness. The liner insulating pattern 111 can be in direct contact with the semiconductor substrate 100. Since the liner insulating pattern 111 contains a material having a refractive index lower than that of the semiconductor substrate 100, the refractive index of the liner insulating pattern 111 can be made smaller than the refractive index of the semiconductor substrate 100. For example, the liner insulating pattern 111 can include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride), a high-k material (e.g., hafnium oxide and / or aluminum oxide), and / or a metal oxide. Also, the liner insulating pattern 111 can include impurities having a first conductivity type. For example, the impurities having a first conductivity type can include at least any one of boron (B), phosphorus (P), arsenic (As), gallium (Ga), indium (In), antimony (Sb), and aluminum (Al).

[0064] The first conductive pattern 113 can be located on the inner surface of the liner insulating pattern 111 within the first trench T1 and the second trench T2. The first conductive pattern 113 can cover a part of the inner surface of the liner insulating pattern 111. The first conductive pattern 113 can be made not to cover the remaining part of the inner surface of the liner insulating pattern 111 adjacent to the first surface 100a of the semiconductor substrate 100. For example, the first conductive pattern 113 can include doped polysilicon or undoped polysilicon.

[0065] The first conductive pattern 113 in the first trench T1 can have an upper surface parallel to the first direction D1. In contrast, the first conductive pattern 113 in the second trench T2 can include an upper portion having a curved surface. For example, the first conductive pattern 113 in the second trench T2 can have a thickness that decreases in the third direction D3 so as to be adjacent to the lower surface 119b of the embedded insulating pattern 119 and the first surface 100a of the semiconductor substrate 100 described later.

[0066] The upper surface of the first conductive pattern 113 in the first trench T1 can have a first height H1 in the fourth direction D4 from the lower surface 105b of the element isolation film 105. The upper surface of the first conductive pattern 113 in the second trench T2 can have a second height H2 in the fourth direction D4 from the lower surface 105b of the element isolation film 105. The first height H1 is smaller than the second height H2, but is not limited thereto. That is, the first height H1 can be substantially the same as the second height H2. For example, the first height H1 and the second height H2 can be about 5 nm to 1000 nm.

[0067] The internal insulating pattern 115 can be located on the inner side surface of the first conductive pattern 113. The internal insulating pattern 115 can be located at the center of the first trench T1 along the first direction D1. That is, since the internal insulating pattern 115 is located at the center of the first pixel isolation structure PIS1, the first conductive pattern 113 can be located between the internal insulating pattern 115 and the liner insulating pattern 111. The internal insulating pattern 115 does not necessarily have to be provided in the second trench T2. Since the internal insulating pattern 115 includes a material having a refractive index lower than that of the first conductive pattern 113, the refractive index of the internal insulating pattern 115 can be made smaller than the refractive index of the first conductive pattern 113. For example, the internal insulating pattern 115 includes a material substantially the same as that of the liner insulating pattern 111, but is not limited thereto.

[0068] The etching stop film 117 can be positioned on the internal insulation pattern 115. The etching stop film 117 can be positioned between the internal insulation pattern 115 and an embedded insulation pattern 119, which will be described later, within the first trench T1. The etching stop film 117 does not necessarily have to be provided within the second trench T2. The upper surface of the etching stop film 117 can be coplanar with the upper surface of the first conductive pattern 113. That is, the etching stop film 117 can be positioned between the lower surface 105b of the element isolation film 105 and the second surface 100b of the semiconductor substrate 100 in FIG. 4A. For example, the upper surface of the etching stop film 117 can have a first height H1 in the fourth direction D4 from the lower surface 105b of the element isolation film 105.

[0069] The etching stop film 117 can contain a material having an etching selectivity ratio with respect to the etching process. For example, the etching stop film 117 can contain a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) doped with impurities, and / or a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide). The impurities doped in the etching stop film 117 can contain at least any one of boron (B), carbon (C), silicon (Si), and argon (Ar). For example, the etching stop film 117 can be formed by doping impurities into a part of the internal insulation pattern 115.

[0070] The second conductive pattern 118 can be located on the inner surface of the first conductive pattern 113 within the second trench T2. The second conductive pattern 118 can be located at the center of the second trench T2 along the third direction D3. That is, since the second conductive pattern 118 is located at the center of the second pixel isolation structure PIS2, the first conductive pattern 113 can be located between the second conductive pattern 118 and the liner insulating pattern 111. The upper surface of the second conductive pattern 118 can be coplanar with the upper surface of the first conductive pattern 113. In other words, the upper surface of the second conductive pattern 118 can have a second height H2 in the fourth direction D4 from the lower surface 105b of the element isolation film 105. For example, the second conductive pattern 118 includes substantially the same material as the first conductive pattern 113, but is not limited thereto.

[0071] The embedded insulating pattern 119 can be located at the upper part of the first trench T1 and the upper part of the second trench T2. Specifically, the embedded insulating pattern 119 can be located on the etching stop film 117 within the first trench T1. The embedded insulating pattern 119 can be located on the second conductive pattern 118 within the second trench T2. The embedded insulating pattern 119 can have an upper surface and a lower surface 119b facing the upper surface. The upper surface of the embedded insulating pattern 119 can be coplanar with the first surface 100a of the semiconductor substrate 100. The lower surface 119b of the embedded insulating pattern 119 can be located at a level lower than the lower surface 105b of the element isolation film 105. That is, the thickness of the embedded insulating pattern 119 in the fourth direction D4 can be made larger than the thickness of the element isolation film 105 in the fourth direction D4.

[0072] Again, since the lower surface 119b of the embedded insulating pattern 119 is in contact with the etching stop film 117 within the first trench T1, the lower surface 119b of the embedded insulating pattern 119 can have a first height H1 in the fourth direction D4 with respect to the lower surface 105b of the element isolation film 105. Since the lower surface 119b of the embedded insulating pattern 119 is in contact with the second conductive pattern 118 within the second trench T2, the lower surface 119b of the embedded insulating pattern 119 can have a second height H2 in the fourth direction D4 with respect to the lower surface 105b of the element isolation film 105. For example, the embedded insulating pattern 119 includes, but is not limited to, substantially the same material as the liner insulating pattern 111 and / or the internal insulating pattern 115.

[0073] Referring to FIGS. 6A and 6B, the first pixel isolation structure PIS1 can further include the second conductive pattern 118. A part of the second conductive pattern 118 can be located between the etching stop film 117 and the embedded insulating pattern 119 within the first trench T1. That is, the lower surface of the second conductive pattern 118 within the first trench T1 can be in contact with the etching stop film 117 and the first conductive pattern 113, and the upper surface of the second conductive pattern 118 can be in contact with the embedded insulating pattern 119. Thereby, the upper surface of the first conductive pattern 113 and the upper surface of the etching stop film 117 can have a third height H3 in the fourth direction D4 with respect to the lower surface 105b of the element isolation film 105 within the first trench T1. The second conductive pattern 118 can have a first height H1 in the fourth direction D4 with respect to the lower surface 105b of the element isolation film 105 within the first trench T1. The first height H1 can be substantially the same as that described in FIGS. 5A and 5B, and the third height H3 can be greater than the first height H1.

[0074] Within the second trench T2, the upper surfaces of the first conductive pattern 113 and the second conductive pattern 118 may not be coplanar. The upper surface of the second conductive pattern 118 can be located at a higher level than the upper surface of the first conductive pattern 113. For example, the second conductive pattern 118 can be T-shaped. The upper surface of the second conductive pattern 118 can have a second height H2 in the fourth direction D4 from the lower surface 105b of the element isolation film 105 within the second trench T2. The second height H2 can be substantially the same as that described in FIGS. 5A and 5B.

[0075] Referring to FIGS. 7A and 7B, the first pixel isolation structure PIS1 can include a first etch stop film 117a, and the second pixel isolation structure PIS2 can include a second etch stop film 117b.

[0076] The first etch stop film 117a can be located between the internal insulation pattern 115 and the embedded insulation pattern 119 and between the first conductive pattern 113 and the embedded insulation pattern 119 within the first trench T1. The first etch stop film 117a can be located between the lower surface 105b of the element isolation film 105 and the second surface 100b of the semiconductor substrate 100 in FIG. 4A. The upper surface of the first conductive pattern 113 can be coplanar with the upper surface of the internal insulation pattern 115.

[0077] For example, the first etch stop film 117a can include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) doped with impurities containing at least one of boron (B), carbon (C), silicon (Si), and argon (Ar), and / or a high dielectric constant material (e.g., hafnium oxide and / or aluminum oxide). According to one embodiment, the first etch stop film 117a can be substantially the same as the etch stop film 117 described in FIGS. 5A and 6A.

[0078] The second etching stop film 117b can be positioned between the second conductive pattern 118 and the embedded insulating pattern 119 and between the first conductive pattern 113 and the embedded insulating pattern 119 within the second trench T2. Similar to the first etching stop film 117b, the second etching stop film 117b can be positioned between the lower surface 105b of the element isolation film 105 and the second surface 100b of the semiconductor substrate 100 in FIG. 4B. The upper surfaces of the first conductive pattern 113 and the second conductive pattern 118 can be coplanar, and the upper surface of the second conductive pattern 118 can be parallel to the third direction D3. Different from FIGS. 5B and 6B, the second conductive pattern 118 can have a certain thickness so as to be adjacent to the lower surface 119b of the embedded insulating pattern 119 and the first surface 100a of the semiconductor substrate 100. For example, the second etching stop film 117b can include polysilicon doped with impurities containing at least one of boron (B), carbon (C), silicon (Si), and argon (Ar).

[0079] Referring again to FIGS. 5A to 7B, an image sensor according to an embodiment of the present invention can include a first pixel isolation structure PIS1 including an internal insulating pattern 115. The internal insulating pattern 115 is located at the center of the first pixel isolation structure PIS1 from the first conductive pattern 113 and can have a refractive index lower than that of the first conductive pattern 113. Thereby, light incident on the image sensor can be totally reflected between the first conductive pattern 113 and the internal insulating pattern 115, preventing the incident light from being absorbed by the first pixel isolation structure PIS1. Therefore, the electrical and optical characteristics of the image sensor can be improved.

[0080] Also, the image sensor according to an embodiment of the present invention can include a first pixel isolation structure PIS1 including an etch stop film 117. The etch stop film 117 can determine the level (or height) of the upper surface of the first conductive pattern 113 in the manufacturing process of the image sensor. For example, the upper surface of the first conductive pattern 113 can be formed at substantially the same level as the lower surface 105b of the element isolation film 105. The vertical length of the first conductive pattern 113 can be substantially the same as the vertical length of the semiconductor substrate 100 adjacent to the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. From a horizontal perspective, the semiconductor substrate 100 can be completely overlapped with the first conductive pattern 113. Thereby, the negative bias applied to the first conductive pattern 113 can sufficiently reduce the dark current generated between the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 and the semiconductor substrate 100. Therefore, the electrical and optical characteristics of the image sensor can be improved.

[0081] FIG. 8 is a schematic plan view of an image sensor including a semiconductor device according to an embodiment of the present invention. FIGS. 9A and 9B are cross-sectional views of the image sensor according to an embodiment of the present invention, which are views cut along the line C-C' of FIG. 8.

[0082] Referring to FIGS. 8 and 9A, the image sensor can include a sensor chip S1 and a logic chip S2. The sensor chip S1 can include a pixel array region R1 and a pad region R2.

[0083] The pixel array region R1 can include a plurality of pixels P two-dimensionally arranged along a first direction D1 and a second direction D2 intersecting each other. Each of the pixels P can include a photoelectric conversion element and a readout element. An electrical signal generated by incident light from each of the pixels P in the pixel array region R1 can be output.

[0084] The pixel array region R1 can include a light-receiving region AR and a light-shielding region OB. In plan view, the light-shielding region OB can surround the light-receiving region AR. That is, in plan view, the light-shielding region OB can be disposed above, below, to the left, and to the right of the light-receiving region AR. A reference pixel Pa where no light is incident is provided in the light-shielding region OB, and by comparing the amount of charge sensed by the unit pixel Pb in the light-receiving region AR with the amount of reference charge generated in the reference pixel Pa, the size of the electrical signal sensed by the unit pixel Pb can be calculated.

[0085] A plurality of conductive pads CP used for inputting and outputting control signals, optoelectronic signals, etc. can be arranged in the pad region R2. In plan view, the pad region R2 can surround the pixel array region R1. Therefore, the pad region R2 can facilitate electrical connection with external elements. The conductive pad CP can input and output the electrical signal generated in the unit pixel P to an external device.

[0086] In the light-receiving region AR, the sensor chip S1 can include the same technical features as the image sensor described above. That is, the sensor chip S1 can include a photoelectric conversion layer 10 between the pixel circuit layer 20 and the light-transmitting layer 30.

[0087] A first pixel separation structure PIS1 can be provided between pixels P adjacent to each other in the first direction D1 or the second direction D2. A second pixel separation structure PIS2 can be provided between pixels P adjacent to each other in the diagonal direction (for example, the third direction D3). For example, each of the first pixel separation structures PIS1 can be located between two adjacent pixels P, and each of the second pixel separation structures PIS2 can be located between four adjacent pixels P. The first pixel separation structure PIS1 can be substantially the same as that described in FIGS. 5A, 6A, and 7A, and the second pixel separation structure PIS2 can be substantially the same as that described in FIGS. 5B, 6B, and 7B.

[0088] The light transmission layer 30 can include a light-shielding pattern OBP, a back contact plug PLG, a contact pattern CT, an organic film 355, and a passivation film 360 in the light-shielding region OB.

[0089] The contact pattern CT can be embedded in a contact hole in which the back contact plug PLG is formed. The contact pattern CT can include a substance different from that of the back contact plug PLG. For example, the back contact plug PLG can include titanium and / or titanium nitride, and the contact pattern CT can include aluminum (Al).

[0090] In the light-shielding region OB, a part of the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 can be electrically connected to the back contact plug PLG and the contact pattern CT. A negative bias can be applied to the first pixel isolation structure PIS1 and the second pixel isolation structure through the contact pattern CT and the back contact plug PLG. The negative bias can be transmitted to the light-receiving region AR in the light-shielding region OB through the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. Thereby, the dark current generated between the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 and the semiconductor substrate 100 can be reduced.

[0091] In the light-shielding region OB, the light-shielding pattern OBP can be continuously extended from the back contact plug PLG and disposed on the upper surface of the planar insulating film 310. That is, the light-shielding pattern OBP can include the same substance as the back contact plug PLG. The light-shielding pattern OBP can include a metal and / or a metal nitride. For example, the light-shielding pattern OBP can include titanium and / or titanium nitride. The light-shielding pattern OBP does not have to extend to the light-receiving region AR of the pixel array.

[0092] The light-shielding pattern OBP can block light from entering the photoelectric conversion region PD provided in the light-shielding region OB. In the reference pixel Pa of the light-shielding region OB, the photoelectric conversion region PD can output a noise signal instead of a photoelectric signal. The noise signal can be generated by electrons generated by heat generation, dark current, or the like.

[0093] In the light-shielding region OB, the organic film 355 and the passivation film 360 can be provided on the light-shielding pattern OBP. The organic film 355 can contain the same substance as the microlens 350.

[0094] In the light-shielding region OB, the first through-conductive pattern 511 can penetrate the semiconductor substrate 100 and be electrically connected to the metal wiring 223 of the pixel circuit layer 20 and the wiring structure 1111 of the logic chip S2. The first through-conductive pattern 511 can have bottom surfaces located at different levels from each other. The first embedded pattern 521 can be provided inside the first through-conductive pattern 511. The first embedded pattern 521 can contain a low-refractive-index substance and have insulating properties.

[0095] In the pad region R2, a conductive pad CP can be provided on the second surface 100b of the semiconductor substrate 100. The conductive pad CP can be embedded in the second surface 100b of the semiconductor substrate 100. For example, the conductive pad CP can be provided in a pad trench formed on the second surface 100b of the semiconductor substrate 100 in the pad region R2. The conductive pad CP can contain a metal such as aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof. In the mounting process of the image sensor, a bonding wire can be bonded to the conductive pad CP. The conductive pad CP can be electrically connected to an external device through the bonding wire.

[0096] In the pad region R2, the second through-conductive pattern 513 can penetrate the semiconductor substrate 100 and be electrically connected to the wiring structure 1111 of the logic chip S2. The second through-conductive pattern 513 can be extended on the second surface 100b of the semiconductor substrate 100 and be electrically connected to the conductive pad CP. A part of the second through-conductive pattern 513 can cover the bottom surface and the side wall of the conductive pad CP. The second embedded pattern 523 can be provided inside the second through-conductive pattern 513. The second embedded pattern 523 can contain a low refractive index material and have insulating properties. In the pad region R2, the second pixel isolation structure PIS2 can be provided around the second through-conductive pattern 513.

[0097] The logic chip S2 can include a logic semiconductor substrate 1000, a logic circuit TR, a wiring structure 1111 connected to the logic circuit TR, and a logic interlayer insulating film 1100. The uppermost layer in the logic interlayer insulating film 1100 can be joined to the pixel circuit layer 20 of the sensor chip S1. The logic chip S2 can be electrically connected to the sensor chip S1 through the first through-conductive pattern 511 and the second through-conductive pattern 513.

[0098] Referring to FIGS. 8 and 9B, the first and second through-conductive patterns 511 and 513 and the first and second embedded patterns 521 and 523 in FIG. 9A can be omitted. By directly joining the bonding pads of the sensor chip S1 and the logic chip S2 to each other, the sensor chip S1 and the logic chip S2 can be electrically connected.

[0099] Specifically, the sensor chip S1 of the image sensor can include a first bonding pad BP1 located at the uppermost part of the pixel circuit layer 20. The logic chip S2 can include a second bonding pad BP2 located at the uppermost layer within the logic interlayer insulating film 1100. That is, the first bonding pad BP1 is located on the lower surface of the sensor chip S1, and the second bonding pad BP2 is located on the upper surface of the logic chip S2 and can be in contact with each other. The first and second bonding pads BP1 and BP2 can include at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0100] The first bonding pad BP1 of the sensor chip S1 and the second bonding pad BP2 of the logic chip S2 can be directly electrically connected to each other in a hybrid bonding manner. Hybrid bonding means a bonding in which two components containing the same substance fuse at their interface. For example, when the first and second bonding pads BP1 and BP2 are made of copper (Cu), they can be physically and electrically connected by copper (Cu)-copper (Cu) bonding.

[0101] FIGS. 10A to 17B are cross-sectional views for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. FIGS. 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A are views cut along the line A-A' of FIG. 3, and FIGS. 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B are views cut along the line B-B' of FIG. 3.

[0102] Referring to FIGS. 10A and 10B, a semiconductor substrate 100 having a first conductivity type (e.g., p-type) can be provided. The first semiconductor substrate 100 can have a first surface 100a and a second surface 100b facing each other. The semiconductor substrate 100 can include an epitaxial layer having a first conductivity type formed on a bulk silicon substrate having a first conductivity type. For example, the epitaxial layer can be formed by performing selective epitaxial growth (SEG) using the bulk silicon substrate as a seed, and impurities of the first conductivity type can be doped during the epitaxial growth process.

[0103] According to one embodiment, the semiconductor substrate 100 can be a bulk silicon substrate including a well of a first conductivity type, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, or a silicon-germanium substrate.

[0104] The first surface 100a of the semiconductor substrate 100 can be patterned to form an element isolation trench. The element isolation trench can define the first and second active portions ACT1 and ACT2 in FIG. 3. The element isolation trench can be formed by forming a buffer film BFL and a mask pattern MP on the first surface 100a of the semiconductor substrate 100 and performing an anisotropic etching process using the mask pattern MP as an etching mask.

[0105] The buffer film BFL can be formed by performing a deposition process or a thermal oxidation process on the first surface 100a of the semiconductor substrate 100. For example, the buffer film BFL can include a silicon oxide film, and the mask pattern MP can include silicon nitride or silicon oxynitride.

[0106] Thereafter, an element isolation insulating film 105a filling the element isolation trench can be formed. The element isolation insulating film 105a can be formed by thickly depositing an insulating material on a semiconductor substrate 100 in which the element isolation trench is formed. The element isolation insulating film 105a can cover the mask pattern MP while filling the element isolation trench.

[0107] Referring to FIGS. 11A and 11B, a first trench T1 and a second trench T2 defining the pixel region PR of FIG. 3 can be formed in the semiconductor substrate 100. The first trench T1 and the second trench T2 can be formed by patterning the element isolation insulating film 105a and the first surface 100a of the semiconductor substrate 100. That is, the first trench T1 and the second trench T2 can be formed by forming a second mask pattern (not shown) on the element isolation insulating film 105a and removing a part of the semiconductor substrate 100 in an anisotropic etching process using the second mask pattern as an etching mask.

[0108] The first trench T1 and the second trench T2 can extend perpendicularly to the second surface 100b at the first surface 100a of the semiconductor substrate 100 to expose a part of the side wall of the semiconductor substrate 100. The first trench T1 and the second trench T2 can be formed deeper than the element isolation trench and can penetrate a part of the element isolation trench. For example, each of the first trench T1 and the second trench T2 is a deep trench having an aspect ratio of about 10:1 to about 15:1, but is not limited thereto.

[0109] The width of each of the first trench T1 and the second trench T2 can gradually decrease from the first surface 100a to the second surface 100b of the semiconductor substrate 100. That is, each of the first trench T1 and the second trench T2 can have an inclined side wall. The bottom surface of the first trench T1 and the second trench T2 can be separated from the second surface 100b of the semiconductor substrate 100 in the fourth direction D4. However, the present invention is not limited thereto, and the width of each of the first trench T1 and the second trench T2 can be constant along the fourth direction D4.

[0110] Each of the first trench T1 and the second trench T2 can have a length perpendicular to the fourth direction D4. The vertical length of the first trench T1 can be substantially the same as the vertical length of the second trench T2. The first trench T1 can have a horizontal width in the first direction D1. The second trench T2 can have a horizontal width in the third direction D3. The horizontal width of the first trench T1 can be smaller than the horizontal width of the second trench T2. Thereby, the same components formed in the first trench T1 and the second trench T2 can have different shapes from each other.

[0111] According to an embodiment, a doping process can be performed on the semiconductor substrate 100. The doping process can include doping the sidewalls of the semiconductor substrate 100 exposed by the first trench T1 and the second trench T2 with impurities of the first conductivity type. For example, the doping process can include a beam lined ion implantation process, a gas phase doping process, and a plasma doping process (PLAD). In the case of the plasma doping process, the source material can be supplied into the process chamber in a gaseous state. After the source material is plasma-ionized, a high voltage bias is applied to an electrostatic chuck (not shown) on which the semiconductor substrate 100 is loaded, so that the ionized source material can be implanted into the sidewalls of the semiconductor substrate. Therefore, the sidewalls of the semiconductor substrate 100 can have a uniform impurity concentration regardless of the position (or height).

[0112] Thereafter, a liner insulating film 111a, a first conductive film 113a, and an internal insulating film 115a can be sequentially formed on the inner walls of the first trench T1 and the second trench T2. The liner insulating film 111a can cover the inner walls of the first trench T1 and the second trench T2 and the element isolation insulating film 105a with a uniform thickness. The liner insulating film 111a can be deposited using a deposition method with excellent step coverage characteristics. For example, the liner insulating film 111a can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Alternatively, the liner insulating film 111a can include a multi-layer formed of at least two of silicon oxide, silicon nitride, and silicon oxynitride.

[0113] The first conductive film 113a can cover the liner insulating film 111a with a uniform thickness. The first conductive film 113a can be formed by a deposition method using a precursor. For example, the first conductive film 113a can include polysilicon doped with impurities. In this case, at least one of DIPAS (Di-isopropylamino Silane) and HCDS (Hexachoro Disilane) can be used as the precursor. The thickness of the first conductive film 113a is smaller than the thickness of the liner insulating film 111a, but is not limited thereto. For example, a doping process can be performed on the first conductive film 113a. The doping process can include doping impurities of the first conductivity type or the second conductivity type. For example, the doping process can be performed simultaneously with the formation of the first conductive film 113a, or can be performed after the formation of the first conductive film 113a.

[0114] The internal insulating film 115a can cover the first conductive film 113a with a uniform thickness. Similar to the liner insulating film 111a, the internal insulating film 115a can be deposited using a deposition method with excellent step coverage characteristics. The internal insulating film 115a can be formed at a low level within the first trench T1 and the second trench T2. For example, the internal insulating film 115a can completely fill the lower part of the first trench T1. In contrast, the internal insulating film 115a can only fill a part of the lower part of the second trench T2. That is, since the horizontal width of the first trench T1 is smaller than the horizontal width of the second trench T2, the form of the internal insulating film 115a within the first trench T1 and the second trench T2 can be different from each other.

[0115] Referring to FIGS. 12A and 12B, a first impurity film I1 can be formed on the semiconductor substrate 100. The first impurity film I1 can be formed by a first ion implantation process (IMP1) for doping the first impurity. The first impurity can be implanted into the internal insulating film 115a and located between the atoms constituting the internal insulating film 115a. Thereby, in the etching process of removing the internal insulating film 115a described later, the first impurity film I1 can have a relatively lower etching rate than the internal insulating film 115a that is not doped with the first impurity. That is, the first impurity film I1 can function as an etch stop film in the etching process. For example, the first impurity used in the first ion implantation process (IMP1) can include at least any one of boron (B), carbon (C), silicon (Si), and argon (Ar). For example, the concentration of the first impurity in the first impurity film I1 can be about 1x10 14 ions / cm 2 or more.

[0116] According to an embodiment, the first ion implantation process (IMP1) can be performed with the semiconductor substrate 100 tilted. In this case, the tilted angle of the semiconductor substrate 100 can be about 1° to about 4°.

[0117] Since the first trench T1 and the second trench T2 correspond to deep trenches with a large aspect ratio, the level of the first impurity film I1 formed in the first ion implantation step (IMP1) can be different inside and outside the first trench T1 and the second trench T2. For example, the first impurity film I1 can be formed at a level higher than the first surface 100a of the semiconductor substrate 100 outside the first trench T1 and the second trench T2. The first impurity film I1 can be formed at a level lower than the first surface 100a of the semiconductor substrate 100 inside the first trench T1 and the second trench T2.

[0118] More specifically, the first impurity film I1 can be formed to be adjacent to the first surface 100a of the semiconductor substrate 100 inside the first trench T1, and can be formed to be adjacent to the second surface 100b of the semiconductor substrate 100 inside the second trench T2. The first impurity film I1 can be formed within the internal insulating film 115a. The first impurity film I1 within the first trench T1 can be formed at a level lower than the lower surface 105b of the element isolation insulating film 105a. The upper surface of the first impurity film I1 within the first trench T1 can have a first height H1 in the fourth direction D4 from the lower surface 105b of the element isolation insulating film 105a. The position where the first impurity film I1 is formed can be provided in various ways according to the depth of the first impurity implanted in the first ion implantation step (IMP1). For example, the first height H1 can be from about 5 nm to about 1000 nm.

[0119] Referring to FIGS. 13A and 13B, a second impurity film I2 can be formed on the semiconductor substrate 100. The second impurity film I2 can be formed by a second ion implantation process (IMP2) for doping a second impurity. The second impurity can be implanted into the internal insulating film 115a to break the bonds of the atoms constituting the internal insulating film 115a. Thereby, in an etching process for removing the internal insulating film 115a described later, the second impurity film I2 can have a relatively higher etching rate than the internal insulating film 115a that is not doped with the second impurity. That is, the second impurity film I2 can function as an etching acceleration film in the etching process. Thereby, the difference between the etching rate of the first impurity film I1 and the etching rate of the second impurity film I2 can be further increased. For example, the second impurity used in the second ion implantation process (IMP2) can include at least any one of BF3, arsenic (As), and phosphorus (P).

[0120] The depth of the second impurity implanted in the second ion implantation process (IMP2) can be made smaller than the depth of the first impurity implanted in the first ion implantation process (IMP1). Thereby, the second impurity film I2 can be located on the first impurity film I1. That is, the second impurity film I2 can be formed on the upper portions of the first and second trenches T1, T2. For example, the second impurity film I2 can be formed at a level higher than the lower surface 105b of the element isolation insulating film 105a. A part of the second impurity film I2 and the first impurity film I1 can be overlapped with each other. However, the present invention is not limited thereto.

[0121] Referring to FIGS. 14A and 14B, the internal insulation pattern 115 can be formed in the first trench T1. The internal insulation pattern 115 can be formed by a wet etching process that utilizes the etching selectivity of the internal insulation film 115a, the first impurity film I1, and the second impurity film I2. The second impurity film I2 can have an etching rate higher than that of the internal insulation film 115a, and the first impurity film I1 can have an etching rate lower than that of the internal insulation film 115a. Again, in the wet etching process, the second impurity film I2 can function as an etching acceleration film, and the first impurity film I1 can function as an etching stop film. Therefore, in the wet etching process, the second impurity film I2 is removed, and the first impurity film I1 may not be removed.

[0122] In the first trench T1, since the first impurity film I1 closes the upper part of the first trench T1, the internal insulation film 115a under the first impurity film I1 may not be removed. As a result, the internal insulation pattern 115 can be formed from a part of the internal insulation film 115a in the first trench T1. In contrast, in the second trench T2, since the first impurity film I1 does not close the upper part of the second trench T2, the internal insulation film 115a can be removed.

[0123] Again, forming the internal insulation pattern 115 can include forming the first impurity film I1 that functions as an etching stop film, forming the second impurity film I2 that functions as an etching acceleration film, and removing a part of the internal insulation film 115a including the second impurity film I2.

[0124] Thereafter, the first conductive pattern 113 can be formed at the lower part of the first trench T1 and the lower part of the second trench T2. The first conductive pattern 113 can be formed by an etching process that removes a part of the first conductive film 113a. For example, the etching process that removes a part of the first conductive film 113a can include an etch-back process.

[0125] For example, the etching process can proceed until the upper surface of the first conductive film 113a is coplanar with the upper surface of the first impurity film I1 in the first trench T1. The upper surface of the first conductive pattern 113 in the first trench T1 can have a first height H1 in the fourth direction D4 from the lower surface 105b of the element isolation insulating film 105a. The upper surface of the first conductive pattern 113 in the second trench T2 can have a second height H2 in the fourth direction D4 from the lower surface 105b of the element isolation insulating film 105a. Since the horizontal width of the second trench T2 is larger than the horizontal width of the first trench T1, the first conductive film 113a in the second trench T2 can be etched more than the first conductive film 113a in the first trench T1. That is, the second height H2 can be larger than or substantially the same as the first height H1.

[0126] Referring to FIGS. 15A and 15B, a second conductive film 118a can be formed on the semiconductor substrate 100. The second conductive film 118a can be located on the first impurity film I1 in the first trench T1. The second conductive film 118a can be located on the first conductive pattern 113 in the second trench T2. That is, the second conductive film 118a can fill the upper part of the first trench T1 and the upper and lower parts of the second trench T2.

[0127] For example, the second conductive film 118a can be deposited using a deposition method with excellent step coverage characteristics, and the deposition method can include LPCVD (Low Pressure Chemical Vapor Deposition). The second conductive film 118a can include polysilicon doped with impurities. That is, the second conductive film 118a includes substantially the same material as the first conductive pattern 113, but is not limited thereto.

[0128] Referring to FIGS. 16A and 16B, a first pixel isolation structure PIS1 can be formed in the first trench T1, and a second pixel isolation structure PIS2 can be formed in the second trench T2. Specifically, the second conductive pattern 118 can be formed by an etching process that removes a part of the second conductive film 118a. The etching process can be advanced until the upper surface of the second conductive film 118a is coplanar with the upper surface of the first conductive pattern 113 in the second trench T2. That is, forming the second conductive pattern 118 can be substantially the same as forming the first conductive pattern 113. Thereby, the second conductive film 118a formed on the upper part of the first trench T1 and the upper part of the second trench T2 can be removed. Therefore, the second conductive pattern 118 can be formed only in the second trench T2.

[0129] According to an embodiment, a part of the second conductive pattern 118 can remain in the first trench T1. As shown in FIGS. 6A and 6B, the second conductive pattern 118 can be formed in the first trench T1 and the second trench T2. In this case, the upper surface of the second conductive pattern 118 can be located at a level higher than the upper surface of the first conductive pattern 113.

[0130] Thereafter, a buried insulating film (not shown) that fills the first trench T1 and the second trench T2 can be formed. The buried insulating film can be formed using a film-forming technique with excellent step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). For example, the buried insulating film can include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0131] Thereafter, a planarization process can be performed to remove the mask pattern MP and expose the first surface 100a of the semiconductor substrate 100. In the planarization process, a part of the first impurity film I1, a part of the element isolation insulating film 105a, a part of the liner insulating film 111a, and a part of the buried insulating film can be removed. As a result, the element isolation film 105 can be formed from the element isolation insulating film 105a, the liner insulating pattern 111 can be formed from the liner insulating film 111a, and the buried insulating pattern 119 can be formed from the buried insulating film. The first impurity film I1 in the first trench T1 can be formed of the etching stop film 117. The upper surface of the element isolation film 105 and the upper surface of the buried insulating pattern 119 can be coplanar with the first surface 100a of the semiconductor substrate 100.

[0132] Again, forming the first pixel isolation structure PIS1 can include forming a liner insulating pattern 111, a first conductive pattern 113, an internal insulating pattern 115, an etching stop film 117, and a buried insulating pattern 119 on the inner sidewall of the first trench T1. Forming the second pixel isolation structure PIS2 can include forming a liner insulating pattern 111, a first conductive pattern 113, a second conductive pattern 118, and a buried insulating pattern 119 on the inner sidewall of the second trench T2.

[0133] Referring to FIGS. 17A and 17B, a photoelectric conversion region PD having a second conductivity type can be formed in the semiconductor substrate 100. The photoelectric conversion region PD can be formed by doping the semiconductor substrate 100 with impurities of the second conductivity type (e.g., n-type). The photoelectric conversion region PD can be separated from the first surface 100a and the second surface 100b of the semiconductor substrate 100. Thus, the photoelectric conversion layer 10 of the image sensor can be formed. According to one embodiment, the photoelectric conversion region PD can be formed before forming the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2.

[0134] The pixel circuit layer 20 can be formed on the first surface 100a of the semiconductor substrate 100. Forming the pixel circuit layer 20 can include forming the transfer gate electrode TG, forming the floating diffusion region FD, and forming the interlayer insulating film 210 and the wiring structure.

[0135] Forming the transfer gate electrode TG can include patterning the semiconductor substrate 100 to form a gate recess region, forming a gate insulating film GIL that conformally covers the inner wall of the gate recess region, forming a gate conductive film that fills the gate recess region, and patterning the gate conductive film. For example, forming the transfer gate electrode TG can include forming the pixel gate electrode PG in FIG. 3.

[0136] Forming the floating diffusion region FD can include ion implanting impurities of the second conductivity type into the semiconductor substrate 100 on one side of the transfer gate electrode TG. When forming the floating diffusion region FD, the source / drain regions of the pixel transistors can be formed simultaneously.

[0137] Forming the interlayer insulating film 210 and the wiring structure can include forming the interlayer insulating film 210 covering the first surface 100a of the semiconductor substrate 100, and forming a floating diffusion region FD and a wiring structure connected to the pixel transistor in the interlayer insulating film 210. The interlayer insulating film 210 can cover the MOS transistors constituting the pixel circuit. The interlayer insulating film 210 can be formed of a material with excellent gap fill characteristics and can be formed such that the upper part is planarized. A contact plug 221 can be formed in the interlayer insulating film 210. A metal wiring 223 can be formed between the interlayer insulating films 210. For example, the contact plug 221 and the metal wiring 223 can be formed of copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), and alloys made of combinations thereof, etc.

[0138] Referring again to FIGS. 4A and 4B, a thinning process of removing a part of the semiconductor substrate 100 can be performed to reduce the vertical thickness of the semiconductor substrate 100. The thinning process can include grinding or polishing the second surface 100b of the semiconductor substrate 100 and anisotropic and isotropic etching. The upper and lower sides of the semiconductor substrate 100 can be inverted to thin the semiconductor substrate 100.

[0139] Thereafter, a planar insulating film 310, a lattice structure 320, a protective film 330, a color filter 340, a microlens 350, and a passivation film 360 can be sequentially formed on the second surface 100b of the semiconductor substrate 100. Thus, the light transmission layer 30 of the image sensor can be formed.

[0140] The planar insulating film 310 can cover the second surface 100b of the semiconductor substrate 100. For example, the planar insulating film 310 can be formed by depositing a metal oxide such as aluminum oxide and / or hafnium oxide.

[0141] The lattice structure 320 can include a light-shielding pattern and / or a low-refractive-index pattern. For example, the light-shielding pattern can include a metal substance such as titanium, tantalum, or tungsten. The low-refractive-index pattern can be made of a substance having a refractive index lower than that of the light-shielding pattern. The low-refractive-index pattern can be made of an organic substance and can have a refractive index of about 1.1 to 1.3. For example, the lattice structure 320 can be a polymer layer containing silica nanoparticles.

[0142] The protective film 330 can be formed to cover the surface of the lattice structure 320 on the planar insulating film 310 with a substantially uniform thickness. For example, the protective film 330 can include at least one single film or multiple films of aluminum oxide film and silicon carbon oxide film.

[0143] Color filters 340 can be formed on the protective film 330 corresponding to each of the pixel regions PR. For example, the color filters 340 can include blue, red, and green color filters.

[0144] Micro-lenses 350 can be respectively formed on the color filters 340. The micro-lenses 350 have a bulging shape and can have a predetermined radius of curvature. The micro-lenses 350 can be formed of a light-transmissive resin.

[0145] The passivation film 360 can conformally cover the upper surface of the micro-lenses 350. For example, the passivation film 360 can be formed of an inorganic oxide.

[0146] Figs. 18A to 21B are cross-sectional views for explaining a method of manufacturing an image sensor according to an embodiment of the present invention. Figs. 18A, 19A, 20A, and 21A are views cut along the line A-A' of Fig. 3, and Figs. 18B, 19B, 20B, and 21B are views cut along the line B-B' of Fig. 3.

[0147] Referring to Figs. 18A and 18B, a buffer film BFL, a mask pattern MP, and an element isolation insulating film 105a can be formed on a semiconductor substrate 100. Forming the buffer film BFL, the mask pattern MP, and the element isolation insulating film 105a can be substantially the same as that described with reference to Figs. 10A and 10B.

[0148] Thereafter, a first trench T1 and a second trench T2 can be formed in the semiconductor substrate 100. A liner insulating film 111a, a first conductive film 113a, and an internal insulating film 115a substantially the same as those described with reference to Figs. 11A and 11B can be formed on the inner sidewalls of the first trench T1 and the second trench T2.

[0149] A preliminary internal insulating pattern 115b can be formed in the first trench T1. The preliminary internal insulating pattern 115b can be formed by a wet etching process for removing a part of the internal insulating film 115a. Since the horizontal width of the second trench T2 is larger than the horizontal width of the first trench T1, the surface area of the internal insulating film 115a exposed to the etching solution can be relatively large. Accordingly, the internal insulating film 115a in the second trench T2 can be removed, but only a part of the internal insulating film 115a in the first trench T1 can be removed. The upper surface of the preliminary internal insulating pattern 115b can be formed to be positioned at a level higher than the lower surface 105b of the element isolation insulating film 105a.

[0150] Thereafter, the preliminary first conductive pattern 113b can be formed in the first trench T1 and the second trench T2. The preliminary first conductive pattern 113b can be formed by an etching process that removes a part of the first conductive film 113a. The etching process that removes a part of the first conductive film 113a can be substantially the same as that described in FIGS. 14A and 14B. Since the upper surface of the preliminary first conductive pattern 113b is coplanar with the upper surface of the preliminary internal insulating pattern 115b, the upper surface of the preliminary first conductive pattern 113b can be positioned at a level higher than the lower surface 105b of the element isolation insulating film 105a.

[0151] The second conductive film 118a can be formed on the preliminary internal insulating pattern 115b and the preliminary first conductive pattern 113b. Forming the second conductive film 118a can be substantially the same as that described in FIGS. 15A and 15B.

[0152] Referring to FIGS. 19A and 19B, the preliminary second conductive pattern 118b can be formed in the second trench T2. The preliminary second conductive pattern 118b can be formed by an etching process that removes a part of the second conductive film 118a. The etching process that removes a part of the second conductive film 118a can be substantially the same as that described in FIGS. 16A and 16B. That is, all of the second conductive film 118a in the first trench T1 can be removed, and the preliminary second conductive pattern 118b can be formed only in the second trench T2. The upper surface of the preliminary second conductive pattern 118b can be formed to be positioned at a level higher than the lower surface 105b of the element isolation insulating film 105a.

[0153] Thereafter, the first impurity film I1 can be formed on the semiconductor substrate 100. The first impurity film I1 can be formed by a first ion implantation process (IMP1) that dopes the first impurity. The first ion implantation process (IMP1) can be substantially the same as that described in FIGS. 12A and 12B.

[0154] Within the first trench T1, the first impurity film I1 can be formed within the preliminary first conductive pattern 113b and the preliminary internal insulating pattern 115b. Within the second trench T2, the first impurity film I1 can be formed within the preliminary first conductive pattern 113b and the preliminary second conductive pattern 118b. That is, the first impurity film I1 that functions as an etch stop film can also be formed within the second trench T2. The first impurity film I1 can be formed at a level lower than the lower surface 105b of the element isolation insulating film 105a within the first trench T1 and the second trench T2.

[0155] Referring to FIGS. 20A and 20B, the second impurity film I2 can be formed on the semiconductor substrate 100. The second impurity film I2 can be formed by a second ion implantation process (IMP2) that dopes the second impurity. The second ion implantation process (IMP2) can be substantially the same as that described in FIGS. 13A and 13B.

[0156] The second impurity film I2 can be formed on the first impurity film I1. Within the first trench T1 and the second trench T2, the second impurity film I2 can be formed within the preliminary internal insulating pattern 115b, the preliminary first conductive pattern 113b, and the preliminary second conductive pattern 118b that are located on the first impurity film I1.

[0157] Referring to FIGS. 21A and 21B, the first pixel isolation structure PIS1 can be formed within the first trench T1. The second pixel isolation structure PIS2 can be formed within the second trench T2. The first pixel isolation structure PIS1 can include the first etch stop film 117a, and the second pixel isolation structure PIS2 can include the second etch stop film 117b. That is, the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 can be substantially the same as that described in FIGS. 7A and 7B.

[0158] Specifically, the second impurity film I2 can be removed in the wet etching process. The wet etching process can be substantially the same as that described with reference to FIGS. 13A and 13B. That is, by utilizing the etching rate difference between the first impurity film I1 and the second impurity film I2, the second impurity film I2 can be removed while the first impurity film I1 remains. As a result, the first impurity film I1 in the first trench T1 can be formed of the first etch stop film 117a, and the first impurity film I1 in the second trench T2 can be formed of the second etch stop film 117b.

[0159] Thereafter, a planarization process can be performed to remove the mask pattern MP and expose the first surface 100a of the semiconductor substrate 100. The planarization process can be substantially the same as that described with reference to FIGS. 16A and 16B.

[0160] Thereafter, the pixel circuit layer 20 and the light transmissive layer 30 of FIGS. 4A and 4B can be formed on each of the first surface 100a and the second surface 100b of the semiconductor substrate 100, which can be substantially the same as that described above.

[0161] As described above, embodiments of the present invention have been described with reference to the accompanying drawings. Those of ordinary skill in the art to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing its technical idea and essential features. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive.

Description of Reference Numerals

[0162] 10 Photoelectric conversion layer 20 Pixel circuit layer 30 Light transmissive layer 100 Semiconductor substrate 103 Barrier region 105 Element isolation film 111 Liner insulation pattern 113 First conductive pattern 115 Internal insulation pattern 117 Etch stop film 118 Second conductive pattern 119 Embedded insulation pattern 210 Interlayer insulation film 221 Contact plug 223 Metal wiring 310 Planar insulation film 320 Lattice structure 330 Protective film 340 Color filter 350 Microlens 360 Passivation film FD Floating diffusion region GIL Gate insulation film PD Photoelectric conversion region PIS Pixel separation structure PR Pixel region TG Transfer gate electrode

Claims

1. a semiconductor substrate having a first conductivity type, the semiconductor substrate including a first surface and a second surface opposed to each other; a photoelectric conversion region located within the semiconductor substrate and having a second conductivity type; a first pixel separating structure between the photoelectric conversion regions adjacent to each other in a first direction; The first pixel separating structure is a first conductive pattern adjacent to the semiconductor substrate and extending from the first surface to the second surface; an inner insulating pattern on an inner surface of the first conductive pattern; a buried insulating pattern on the inner insulating pattern; an etch stop layer between the inner insulating pattern and the buried insulating pattern.

2. a second pixel separating structure between adjacent photoelectric conversion regions in a second direction diagonal to the first direction, the second pixel separating structure The first conductive pattern; a second conductive pattern on the inner surface of the first conductive pattern; the buried insulating pattern on the second conductive pattern.

3. 3. The image sensor of claim 2, wherein the first conductive pattern of the second pixel separating structure has a thickness that narrows adjacent the first surface of the semiconductor substrate.

4. The image sensor of claim 2 , wherein a top surface of the first conductive pattern and a top surface of the second conductive pattern of the second pixel separating structure are coplanar.

5. The image sensor of claim 2 , wherein a top surface of the first conductive pattern of the second pixel separating structure is located at a lower level than a top surface of the second conductive pattern.

6. 3. The image sensor of claim 2, wherein a bottom surface of the buried insulating pattern of the first pixel separating structure is located at a different level than a bottom surface of the buried insulating pattern of the second pixel separating structure.

7. The image sensor of claim 2 , wherein a width of the first pixel separating structure in the first direction is smaller than a width of the second pixel separating structure in the second direction.

8. 3. The image sensor of claim 2, wherein the first pixel isolating structure is a portion of the second conductive pattern located between the etch stop layer and the buried insulating pattern.

9. The image sensor of claim 2 , wherein the first conductive pattern and the second conductive pattern comprise polysilicon.

10. The image sensor of claim 2 , wherein the first direction and the second direction are parallel to the first surface and the second surface of the semiconductor substrate.

11. 2. The image sensor of claim 1, wherein the etch stop layer comprises at least one of carbon, silicon, argon, and boron.

12. an isolation layer adjacent to the first surface in the semiconductor substrate; the first pixel isolation structure penetrates the device isolation film; 2. The image sensor of claim 1, wherein a lower surface of the isolation layer is located at a level higher than the etch stop layer.

13. 13. The image sensor of claim 12, wherein a distance between the bottom surface of the isolation layer and the top surface of the etch stop layer is between 5 nm and 1000 nm.

14. a semiconductor substrate having a first conductivity type, the semiconductor substrate including a first surface and a second surface opposed to each other; a photoelectric conversion region located within the semiconductor substrate and having a second conductivity type; an isolation film located in the semiconductor substrate and adjacent to the first surface; a first pixel isolation structure located between two adjacent ones of the photoelectric conversion regions and including a first etch stop layer; a second pixel isolation structure located between four adjacent ones of the photoelectric conversion regions and including a second etch stop layer; the first etch stop layer and the second etch stop layer are located between a lower surface of the device isolation layer and the second surface.

15. 15. The image sensor of claim 14, wherein the first etch stop layer and the second etch stop layer include at least one of carbon, silicon, argon, and boron.

16. the first pixel isolating structure includes an interior insulating pattern between the first etch stop layer and the second surface, and first conductive patterns on both sides of the interior insulating pattern; 15. The image sensor of claim 14, wherein the second pixel separating structure comprises a second conductive pattern between the second etch stop layer and the second surface, and the first conductive patterns on either side of the second conductive pattern.

17. The image sensor of claim 14 , wherein each of the first pixel separating structure and the second pixel separating structure has a width that narrows from the first surface to the second surface.

18. a semiconductor substrate including a light receiving region, a light shielding region, and a pad region, the semiconductor substrate having a first surface and a second surface opposed to each other; a pixel isolating structure disposed in the semiconductor substrate in the light receiving region and the light blocking region, the pixel isolating structure defining a plurality of pixel regions and including a first conductive pattern; a transfer gate electrode on the first surface of the semiconductor substrate; a plurality of photoelectric conversion regions in the semiconductor substrate in the light receiving region and the light shielding region; a pixel circuit layer on the first surface of the semiconductor substrate; a light transmissive layer on the second surface of the semiconductor substrate; The pixel separating structure comprises: a first pixel separating structure between adjacent pixel regions in a first direction or a second direction intersecting the first direction; a second pixel separating structure between adjacent pixel regions in a third direction that is oblique to the first and second directions; the first pixel isolating structure further includes an inner insulating pattern on an inner surface of the first conductive pattern, the second pixel separating structure further includes a second conductive pattern on the inner surface of the first conductive pattern.

19. The image sensor of claim 18 , wherein the first direction, the second direction, and the third direction are parallel to the first surface and the second surface.

20. the first pixel isolating structure includes a buried insulating pattern adjacent to the first surface, and an etch stop layer between the internal insulating pattern and the buried insulating pattern, 20. The image sensor of claim 18, wherein the etch stop layer comprises at least one of carbon, silicon, argon, and boron.

Images