Circuit board and electronic component package including the same

Abstract

To provide a circuit board capable of efficiently absorbing and dispersing heat generated from an electronic component while ensuring a mounting space for the electronic component, and an electronic component package including the same.SOLUTION: A circuit board disclosed herein includes a first insulating layer having a first surface and a second surface facing each other and having a cavity recessed from the first surface, a first heat dissipation pattern disposed on the second surface of the first insulating layer, and a heat dissipation portion connected to the first heat dissipation pattern and penetrating the first insulating layer and protruding into the cavity.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a circuit board and an electronic component package including the same.

Background Art

[0002] A circuit board is formed by forming a circuit pattern with a conductive material such as copper on an insulating material. As electronic devices in the IT field such as mobile phones are miniaturized, a method has been proposed in which a cavity is formed in the circuit board and electronic components such as ICs, active elements, or passive elements are housed in the cavity.

[0003] As the performance of electronic components such as application processors (APs) and DRAMs housed inside the cavity of the circuit board continues to evolve, a large amount of heat can be generated in the electronic components during the process of rapidly transmitting a larger amount of data.

[0004] Therefore, in a situation where it is necessary to develop a circuit board and an electronic component package having heat dissipation characteristics so that electronic components can exhibit more stable performance.

Summary of the Invention

Problems to be Solved by the Invention

[0005] One aspect of the present disclosure is to provide a circuit board and an electronic component package including the same that can efficiently absorb and disperse heat generated from electronic components while securing a mounting space for the electronic components.

[0006] Another aspect of the present disclosure is to provide a circuit board and an electronic component package including the same that can apply a structure having a heat dissipation effect to electronic components of various thicknesses and can efficiently absorb and disperse heat generated from electronic components even when the design of the circuit pattern layer is complicated.

[0007] However, the problems to be solved by the embodiments of the present invention are not limited to the above problems, and can be variously extended within the scope of the technical idea included in the present invention.

Means for Solving the Problems

[0008] The circuit board according to the embodiment includes a first surface and a second surface facing each other, a first insulating layer having a cavity recessed from the first surface, a first heat dissipation pattern disposed on the second surface of the first insulating layer, and a heat dissipation portion connected to the first heat dissipation pattern and protruding into the cavity through the first insulating layer.

[0009] Further including at least one circuit pattern layer embedded in the first heat dissipation pattern, and a second insulating layer laminated in a first direction on the second surface, the first insulating layer includes an upper surface region overlapping the cavity in the first direction, and a side surface region overlapping the cavity in a second direction perpendicular to the first direction, and the heat dissipation portion can protrude from the upper surface region.

[0010] The heat dissipation portion can include a first portion embedded in the first insulating layer and a second portion extending from the first portion and protruding from the upper surface region.

[0011] The first insulating layer has a groove portion where the second portion is located in the upper surface region, and the width of the groove portion may be larger than the width of the second portion.

[0012] Further including a first pattern layer including a first heat dissipation pattern and a first circuit pattern layer disposed around the first heat dissipation pattern, the first heat dissipation pattern can be connected to at least one other pattern layer. The first insulating layer further includes a second heat dissipation pattern disposed on the first surface, and the first heat dissipation pattern may be connected to the second heat dissipation pattern.

[0013] Embed at least one pattern layer including the first heat dissipation pattern, further include a second insulating layer laminated in a first direction on the second surface, and a third heat dissipation pattern disposed on a third surface of the second insulating layer facing the second surface of the first insulating layer, and the first heat dissipation pattern may be connected to the third heat dissipation pattern.

[0014] The heat dissipation part can extend along one edge of the cavity.

[0015] The heat dissipation parts are provided in plurality, and the plurality of heat dissipation parts can include portions arranged in alignment in one direction.

[0016] The heat dissipation parts are provided in plurality, and the plurality of heat dissipation parts may be arranged separately from each other.

[0017] The heat dissipation part can contain copper.

[0018] The electronic component package according to the embodiment includes a first circuit board having a cavity on one surface, a second circuit board connected to the first circuit board, and an electronic component mounted on one surface of the second circuit board and housed inside the cavity. The first circuit board includes a first surface and a second surface facing each other, a first insulating layer having the cavity recessed from the first surface, a first heat dissipation pattern disposed on the second surface of the first insulating layer, and a heat dissipation part connected to the first heat dissipation pattern and protruding into the cavity through the first insulating layer.

[0019] Embed at least one circuit pattern layer including the first heat dissipation pattern, further include a second insulating layer laminated in a first direction on the second surface. The first insulating layer includes an upper surface region overlapping the cavity in the first direction and a side surface region overlapping the cavity in a second direction perpendicular to the first direction, and the heat dissipation part can protrude from the upper surface region.

[0020] The heat dissipation part may include a first part embedded in the first insulating layer and a second part extending from the first part and protruding from the upper surface region.

[0021] The first insulating layer has a groove portion where the second part is located in the upper surface region, and the width of the groove portion may be larger than the width of the second part.

[0022] It further includes a first pattern layer including the first heat dissipation pattern and a first circuit pattern layer disposed around the first heat dissipation pattern, and the first heat dissipation pattern is connected to at least one other pattern layer.

[0023] It further includes a second heat dissipation pattern disposed on the first surface of the first insulating layer, and the first heat dissipation pattern may be connected to the second heat dissipation pattern.

[0024] At least one pattern layer including the first heat dissipation pattern is embedded, and a second insulating layer laminated in a first direction on the second surface, and a third heat dissipation pattern layer disposed on a third surface of the second insulating layer facing the second surface of the first insulating layer are further included, and the heat dissipation pattern may be connected to the first and third heat dissipation patterns.

[0025] The heat dissipation part can extend along one edge of the cavity.

[0026] The heat dissipation parts are provided in plurality, and the plurality of heat dissipation parts may include parts arranged in alignment in one direction.

Advantages of the Invention

[0027] According to the circuit board according to the embodiment and the electronic component package including the same, while securing the mounting space for the electronic component, the heat generated from the electronic component can be efficiently absorbed and dissipated.

[0028] Also, according to the circuit board and the electronic component package including the same according to the embodiment, a structure having a heat dissipation effect can be applied to electronic components of various thicknesses, and even when the design of the circuit pattern layer is complicated, heat generated from the electronic components can be efficiently absorbed and dispersed.

Brief Description of the Drawings

[0029]

Figure 1

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Figure 10

Figure 11

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Figure 17

Figure 18

Mode for Carrying Out the Invention

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement it. In order to clearly explain the present invention in the drawings, unnecessary parts for the explanation are omitted, and the same reference numerals are given to the same or similar components throughout the specification. Also, in the accompanying drawings, some components are exaggerated, omitted, or shown schematically, and the sizes of the respective components do not fully reflect the actual sizes.

[0031] The accompanying drawings are only for easily understanding the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings, and should be understood to include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0032] Terms including ordinal numbers such as first, second, etc. can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another component.

[0033] Also, when a part such as a layer, film, region, or plate is "on" or "above" another part, this includes not only the case where it is directly above the other part, but also the case where there is another part in between. Conversely, when a part is "directly above" another part, it means that there is no other part in between. Also, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" in the direction opposite to gravity.

[0034] Throughout the specification, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part "comprises" a certain component, this means that, unless otherwise stated to the contrary, it can further include other components rather than excluding other components.

[0035] Also, throughout the specification, when it is said "on a plane", this means when looking at the target part from above, and when it is said "in a cross-section", this means when looking at the cross-section obtained by vertically cutting the target part from the side.

[0036] Throughout the specification, when a part is "coupled" to another part, this includes not only the case where it is "directly or physically coupled", but also the case where it is "indirectly or non-contactingly coupled" with another element sandwiched in between.

[0037] Also, throughout the specification, when "connected" is mentioned, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, are not only physically connected but also electrically connected, or can be meant to be integral although referred to by different names depending on their positions and functions.

[0038] Hereinafter, various embodiments and modifications will be described in detail with reference to the drawings.

[0039] With reference to FIGS. 1 and 2, a circuit board according to an embodiment will be described. FIG. 1 is a cross-sectional view of a circuit board according to an embodiment, and FIG. 2 is a plan view schematically showing one surface of the circuit board of FIG. 1.

[0040] Referring to FIG. 1, the circuit board 10 according to this embodiment includes a first surface and a second surface facing each other, and includes a first insulating layer 110 having a cavity 111 recessed from the first surface, a first heat dissipation pattern 131 disposed on the second surface of the first insulating layer 110, and a heat dissipation portion 200 connected to the first heat dissipation pattern 131. The heat dissipation portion 200 penetrates the first insulating layer 110 and protrudes into the cavity 111.

[0041] The circuit board 10 according to this embodiment can include a plurality of insulating layers 110 and 120. The plurality of insulating layers can include a first insulating layer 110 and a second insulating layer 120 located on the first insulating layer 110. As the material of each of the plurality of insulating layers, an insulating substance is used, and the insulating substance can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material in which inorganic fillers such as silica and reinforcing materials such as glass fibers are included in these resins. For example, as the material of each of the plurality of insulating layers, prepreg, RCC (Resin Coated Copper foil), etc. can be used, but it is not limited thereto, and materials that do not include reinforcing materials such as glass fibers, for example, ABF (Ajinomoto - Build up Film), etc. may be used. If necessary, a photosensitive insulating material such as PID (Photo Image - able Dielectric) may be used as the material of each of the plurality of insulating layers.

[0042] The first insulating layer 110 can have a first surface and a second surface facing each other. A cavity 111 can be located on the first surface of the first insulating layer 110. The first insulating layer 110 can have a cavity 111 recessed from the first surface. The cavity 111 can be in a shape recessed and hollowed out from the first surface of the first insulating layer 110. The cavity 111 can be formed by an etching process. Also, when the circuit board 10 is to be connected to a substrate of an electronic component as an interposer substrate in the future, a sealing material 23 (see FIG. 16) is disposed inside the cavity 111.

[0043] The second insulating layer 120 can be laminated in a first direction on the second surface of the first insulating layer 110. The first direction can mean the direction in which the plurality of insulating layers are laminated. At least one circuit pattern layer can be embedded in the second insulating layer 120.

[0044] Referring to FIG. 1, the second insulating layer 120 is illustrated as one layer that embeds one circuit pattern layer, but is not limited thereto. The second insulating layer 120 can embed more circuit pattern layers than those illustrated, or may not be able to embed circuit pattern layers.

[0045] The circuit board 10 according to one embodiment can further include a plurality of pattern layers. Each of the plurality of pattern layers can be located on one side of the first insulating layer 110 or the second insulating layer 120. Each of the plurality of pattern layers 130, 140, 150 can include a heat dissipation pattern 131, 141, 151. Each of the plurality of pattern layers 130, 140, 150 can further include circuit pattern layers 132, 142, 152. Each circuit pattern layer 132, 142, 152 can be arranged around its respective heat dissipation pattern 131, 141, 151.

[0046] Referring to FIG. 1, the first pattern layer 130 can include a first heat dissipation pattern 131 and a first circuit pattern layer 132 arranged around the first heat dissipation pattern 131. The second pattern layer 140 can include a second heat dissipation pattern 141 and a second circuit pattern layer 142 arranged around the second heat dissipation pattern 141. The third pattern layer 150 can include a third heat dissipation pattern 151 and a third circuit pattern layer 152 arranged around the third heat dissipation pattern 151. However, referring to FIG. 1, although each of the second and third pattern layers 140, 150 is shown as including a heat dissipation pattern and a circuit pattern layer, it is not limited thereto. The second and third pattern layers 140, 150 can include either a heat dissipation pattern or a circuit pattern layer.

[0047] In FIG. 1, only the first to third circuit pattern layers 132, 142, 152 are shown, but it is not limited thereto. More circuit pattern layers than those illustrated may be arranged, or a smaller number of circuit pattern layers may be arranged.

[0048] The circuit board 10 according to this embodiment can include a plurality of circuit pattern layers 132, 142, and 152. Each of the plurality of circuit pattern layers can be located on one side of the insulating layers 110 and 120. The circuit pattern layers 132, 142, and 152 can transmit signals of the circuit board 100. As the material of the circuit pattern layers 132, 142, and 152, a metal material is used. The metal material includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The circuit pattern layers 132, 142, and 152 can perform various functions according to design patterns such as ground patterns, power patterns, and signal patterns. These patterns can each have a line, plane, or pad form. In the case of the circuit pattern layer located in the outermost layer among the plurality of circuit pattern layers 132, 142, and 152, it can function as a pad for connection to other substrates or components.

[0049] The plurality of circuit pattern layers 132, 142, and 152 can include first to third circuit pattern layers 132, 142, and 152.

[0050] The first circuit pattern layer 132 is disposed on the second surface of the first insulating layer 110. The first circuit pattern layer 132 may be embedded in the second insulating layer 120. For example, the first circuit pattern layer 132 can include copper.

[0051] The second pattern layer 140 can be located on the first surface of the first insulating layer 110. The second pattern layer 140 may be embedded in the first insulating layer 110. The second pattern layer 140 can function as a pad for connection to other substrates or components. For example, the second pattern layer 140 can include copper.

[0052] The third circuit pattern layer 152 can be located on one surface of the second insulating layer 120. The third circuit pattern layer 152 may be disposed on the third surface. The third surface may be one surface of the second insulating layer 120 facing the second surface of the first insulating layer 110. The third circuit pattern layer 152 can function as a pad for connection to other substrates or components. For example, the third circuit pattern layer 152 can contain copper.

[0053] Referring to FIG. 1, only the first to third circuit pattern layers 132, 142, 152 are illustrated, but the present invention is not limited thereto, and a larger number of circuit pattern layers than those illustrated may be disposed, or a smaller number of circuit pattern layers may be disposed.

[0054] The circuit board 10 according to the present embodiment can include a plurality of via layers 160, 170. The plurality of via layers 160, 170 can be arranged to electrically connect the first to third circuit pattern layers 132, 142, 152 to each other. Each via electrode of the plurality of via layers 160, 170 can have a tapered shape in which the width of one surface is larger than the width of the other surface. As the material of the plurality of via layers 160, 170, a metallic substance may be used. The metallic substance may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0055] The plurality of via layers 160, 170 can include signal vias, ground vias, power vias, etc. according to the design. The via electrodes of the via layers 160, 170 may each be such that the via holes are completely filled with a metallic substance, or the metallic substance may be formed along the wall surfaces of the via holes. Each of the plurality of via layers 160, 170 can be formed by a plating process, for example, processes such as AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting). Each of the plurality of via layers 160, 170 can include a seed layer of an electroless plating layer and an electroplating layer formed based on such a seed layer.

[0056] The plurality of via layers 160, 170 can include a first via layer 160 located within the first insulating layer 110 and a second via layer 170 located within the second insulating layer 120.

[0057] The first via layer 160 can penetrate the first insulating layer 110 and connect to the first circuit pattern layer 132 and the second pattern layer 140. Therefore, the first circuit pattern layer 132 and the second circuit pattern layer 142 can be electrically connected via the first via layer 160.

[0058] The second via layer 170 can penetrate the second insulating layer 120 and connect to the first circuit pattern layer 132 and the third circuit pattern layer 152. Therefore, the first circuit pattern layer 132 and the third circuit pattern layer 152 can be electrically connected via the second via layer 170.

[0059] Referring to FIG. 1, only the first and second via layers 160, 170 are illustrated, but it is not limited thereto, and more or fewer via layers may be arranged as necessary.

[0060] The circuit board 10 according to this embodiment may include a heat dissipation part 200. The heat dissipation part 200 may be connected to the first heat dissipation pattern 131. The first heat dissipation pattern 131 can be arranged on the first insulating layer 110. The first heat dissipation pattern 131 may be connected to at least one circuit pattern layer. For example, the first heat dissipation pattern 131 can be a dummy electrode or a heat dissipation electrode. Specifically, the first heat dissipation pattern 131 can function to transfer heat generated from the circuit board 10 of the embodiment without a signal transmission function. However, it is not limited thereto, and the first heat dissipation pattern 131 can function to transfer heat generated from the circuit board 10 while having a signal transmission function.

[0061] Referring to FIG. 1, the first heat dissipation pattern 131 can be connected to the second heat dissipation pattern 141 via the first via layer 160. Specifically, the first via layer 160 can include a first heat dissipation via electrode 161 that connects the first heat dissipation pattern 131 to the second pattern layer 141. The first heat dissipation via electrode 161 can function to transfer heat generated from the circuit board 10 of the embodiment. Also, the first heat dissipation pattern 131 can be connected to the third heat dissipation pattern 151 via the second via layer 170. Specifically, the second via layer 170 can include a second heat dissipation via electrode 171 that connects the first heat dissipation pattern 131 to the third heat dissipation pattern 151. The first heat dissipation via electrode 171 can function to transfer heat generated in the circuit board 10 of the embodiment. Through the first heat dissipation via electrode 161 and the first heat dissipation via electrode 171, the heat generated from the electronic component 22 disposed in the cavity 111 can be dispersed above and below the circuit board 10.

[0062] The second heat dissipation pattern 141 can be connected to the first heat dissipation pattern 131 via the first heat dissipation via electrode 161. By this connection, the second heat dissipation pattern 141 can be transferred heat from the first heat dissipation pattern 131 via the first heat dissipation via electrode 161, and the heat generated by the electronic component 22 disposed in the cavity 111 may be transferred to one side of the circuit board 10. Thereby, the heat dissipation characteristics of the circuit board 10 can be improved.

[0063] The third heat dissipation pattern 151 is connected to the first heat dissipation pattern 131 via the second heat dissipation via electrode 171. The third heat dissipation pattern 151 receives heat from the first heat dissipation pattern 131 via the second heat dissipation via electrode 171, and transfers the heat generated by the electronic component 22 disposed in the cavity 111 to the other side of the circuit board (10), thereby improving the heat dissipation characteristics of the circuit board 10.

[0064] The first insulating layer 110 may include an upper surface region 110a overlapping the cavity 111 in the first direction and a side surface region 110b overlapping the cavity 111 in the second direction perpendicular to the first direction. The side surface region 110b may be in a form surrounding the upper surface region 110a. The heat dissipation part 200 penetrates the first insulating layer 110 and protrudes into the cavity 111.

[0065] Referring to FIG. 2, a plurality of heat dissipation parts 200 may be provided. The plurality of heat dissipation parts 200 may include portions arranged in alignment in one direction. Specifically, the plurality of heat dissipation parts 200 may include some heat dissipation parts arranged in alignment in one direction and other some heat dissipation parts arranged in alignment in the other direction perpendicular to the one direction. The plurality of heat dissipation parts 200 are arranged separately from each other.

[0066] As the material of the heat dissipation part 200, a metal substance may be used. The metal substance may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0067] The heat dissipation part 200 may include a first part 201 embedded in the first insulating layer 110 and a second part 202 extending from the first part 201 and protruding from the upper surface region 110a.

[0068] The first part 201 may include a part of the via electrode formed in the first via layer 160. The first part 201 may include a portion where the width decreases as it gets farther from the first heat dissipation pattern 131.

[0069] The second part 202 can protrude into the cavity 111. The second part 202 can be exposed from the upper surface region 110a of the first insulating layer 110, and thus can efficiently absorb and disperse the heat generated from the electronic components to be mounted in the cavity 111 later. The length by which the second part 202 protrudes into the cavity 111 and the planar area of the second part 202 can be variously changed according to the purpose. For example, when the height of the electronic component housed inside the cavity 111 is low, the length of the second part 202 can be formed longer to improve the heat dissipation efficiency. As another example, the planar area of the second part 202 can be formed larger to increase the surface area of the heat dissipation part 200 and improve the heat dissipation efficiency.

[0070] The first insulating layer 110 can have a groove portion 110c in the upper surface region 110a. The groove portion 110c can be shaped to be recessed in the first direction. The second part 202 can be positioned within the groove portion 110c. The second part 202 can protrude from the groove portion 110c. The width of the groove portion 110c along the second direction may be larger than the width of the second part 202 along the second direction. That is, there is a free space between the groove portion 110c and the second part 202, and the inner surface of the groove portion 110c and the second part 202 can be spaced apart.

[0071] The first solder resist layer 180 can be positioned on the first surface of the first insulating layer 110 so as to cover a part of the second pattern layer 140 in order to prevent unnecessary short circuits. The first solder resist layer 180 can be arranged so as to expose at least a part of the second pattern layer 140. The first solder resist layer 180 can contain a photosensitive resin material.

[0072] The second solder resist layer 190 can be positioned on one surface of the second insulating layer 120 so as to cover a part of the third circuit pattern layer 152 in order to prevent unnecessary short circuits. The second solder resist layer 190 can be arranged so as to expose at least a part of the third circuit pattern layer 152. The second solder resist layer 190 can contain a photosensitive resin material.

[0073] According to the circuit board according to this embodiment, since the heat dissipation part with a protruding structure is located inside the cavity in which the electronic component is accommodated, it is possible to efficiently absorb and disperse the heat generated from the electronic component while securing the mounting space for the electronic component. Further, the length of the heat dissipation part can be adjusted and formed, and the heat dissipation part can be applied to electronic components of various thicknesses.

[0074] Hereinafter, with reference to FIGS. 3 to 15, a method for manufacturing a circuit board according to an embodiment will be described. FIGS. 3 to 15 are cross-sectional views showing a method for manufacturing a circuit board according to an embodiment.

[0075] Referring to FIG. 3, a second pattern layer 140 can be formed on a carrier substrate CS including a core portion CO and thin film metal layers MS laminated on both sides of the core portion CO. A second heat dissipation pattern 141 and a second circuit pattern layer 142 can be formed on the carrier substrate CS. Here, a first sacrificial layer 1111 disposed at a position where the cavity 111 is formed can be formed together. The second pattern layer 140 and the first sacrificial layer 1111 can be formed by a plating process. The second pattern layer 140 and the first sacrificial layer 1111 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive (Subtractive) method. It is not limited thereto, and any method capable of forming a pattern on a circuit board can be used without limitation. The second circuit pattern layer 142 and the first sacrificial layer 1111 can each include an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electro copper) as a plating layer, but are not limited thereto. As a method of forming the electroless plating layer, a sputtering layer can be used instead of chemical copper. If necessary, the second pattern layer 140 may or may not include a copper foil.

[0076] The first sacrificial layer 1111 can be formed together with the second pattern layer 140. The first sacrificial layer 1111 can be made of the same material as the second pattern layer 140 and can have the same thickness as the second pattern layer 140. The thickness of the first sacrificial layer 1111 can correspond to the depth of the cavity 111 formed later.

[0077] Referring to FIG. 4, the second sacrificial layer 2021 can be formed on the first sacrificial layer 1111. The second sacrificial layer 2021 can be formed in a form including a plurality of portions that are spaced apart from each other on the first sacrificial layer 1111. The second sacrificial layer 2021 can be formed by a plating process. As an example, the second sacrificial layer 2021 can be formed by forming a photoresist on the first sacrificial layer 1111, patterning the photoresist in an exposure and development process, then plating and filling the patterned region, and peeling off the photoresist. As an example, the second sacrificial layer 2021 can be formed by forming a photoresist on the first sacrificial layer 1111, patterning the photoresist in an exposure and development process, then plating and filling the patterned region, and peeling off the photoresist. However, it is not limited thereto, and any method capable of forming a pattern on a circuit board can be used without limitation. The second sacrificial layer 2021 can contain nickel, but is not limited thereto.

[0078] Referring to FIG. 5, the first insulating layer 110 can be formed so as to embed the second pattern layer 140, the first sacrificial layer 1111, and the second sacrificial layer 2021. The first insulating layer 110 can be formed using materials such as prepreg (PPG), ABF (Ajinomoto build-up film), and RCC (Resin Coated Copper foil).

[0079] Referring to FIG. 6, a first pattern 130 can be formed on the first insulating layer 110, and a first via layer 160 can be formed to penetrate at least a part of the first insulating layer 110. Specifically, a first heat dissipation pattern 131 and a first circuit pattern layer 132 can be formed as the first pattern layer 130 on the first insulating layer 110. A part of the via electrodes of the first via layer 160 can be formed to be in contact with the first circuit pattern layer 132 and the second circuit pattern layer 142. That is, a part of the via electrodes of the first via layer 160 can be formed such that the first circuit pattern 132 and the second circuit pattern layer 142 are connected.

[0080] In addition, a first heat dissipation via electrode 161 can be formed to penetrate another part of the first insulating layer 110. The first heat dissipation via electrode 161, which is another part of the via electrodes of the first via layer 160, can be formed to be in contact with the first heat dissipation pattern 131 and the second sacrificial layer 2021, or in contact with the first heat dissipation pattern 131 and the second heat dissipation pattern 141. That is, the first heat dissipation via electrode 161 can be formed such that the first heat dissipation pattern 131 and the second sacrificial layer 2021 are connected, and the first heat dissipation via electrode 161 can be formed such that the first heat dissipation pattern 131 and the second heat dissipation pattern 141 are connected.

[0081] The first pattern layer 130 may be formed by any one of the SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive process, but is not limited thereto, and can be used without limitation as long as it is a process capable of forming a pattern on a circuit board. As an example, the first pattern layer 130 can be formed by forming a seed layer by electroless plating on a copper foil, forming a photoresist on the seed layer, patterning the photoresist in an exposure and development process, filling the patterned area by electroplating, and then peeling off the photoresist. The first pattern layer 130 can include an electroless plating layer (or electroless copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, respectively, but is not limited thereto. As a method of forming the electroless plating layer, a sputtering layer can be used instead of electroless copper. If necessary, the first pattern layer 130 may or may not include a copper foil. The first via layer 160 can be formed by laser, mechanical drilling, or the like. As an example, a via penetrating at least a part of the first insulating layer 110 can be formed by a laser or the like, and the first via layer 160 can be formed by filling the via with a conductive material.

[0082] Referring to FIG. 7, the second insulating layer 120 can be formed on the first insulating layer 110 such that the first heat dissipation pattern 131 is embedded therein. The second insulating layer 120 can be formed using materials such as prepreg (PPG), ABF (Ajinomoto build-up film), and RCC (Resin Coated Copper foil).

[0083] Referring to FIG. 8, a third pattern layer 150 can be formed on the second insulating layer 120, and a second via layer 170 can be formed to penetrate at least a part of the second insulating layer 120. Specifically, as the third pattern layer 150, a third heat dissipation pattern 151 and a third circuit pattern layer 152 can be formed on the second insulating layer 120. A part of the via electrodes of the second via layer 170 can be formed to be in contact with the first circuit pattern layer 132 and the third circuit pattern layer 152. In other words, a part of the via electrodes of the second via layer 170 can be formed such that the first circuit pattern layer 132 and the third circuit pattern layer 152 are connected.

[0084] In addition, a second heat dissipation via electrode 171 can be formed to penetrate another part of the second insulating layer 120. The second heat dissipation via electrode 171, which is another part of the via electrodes of the second via layer 170, can be formed to be in contact with the first heat dissipation pattern 131 and the third heat dissipation pattern 151. That is, the second heat dissipation via electrode 171 can be formed such that the first heat dissipation pattern 131 and the third heat dissipation pattern 151 are connected.

[0085] The third pattern layer 150 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or Subtractive process, but is not limited thereto, and any process that can form a pattern on a circuit board can be used without limitation. As an example, the third pattern layer 150 can be formed by forming a seed layer by electroless plating on a copper foil, forming a photoresist on the seed layer, patterning the photoresist in an exposure and development process, filling the patterned area by electroplating, and then peeling off the photoresist. The third pattern layer 150 can include an electroless plating layer (or electroless copper) as a seed layer and an electroplating layer (or electroformed copper) as a plating layer, respectively, but is not limited thereto. As a method of forming the electroless plating layer, a sputtering layer can be used instead of electroless copper. Optionally, the third pattern layer 150 may or may not include a copper foil.

[0086] The second via layer 170 can be formed by laser, mechanical drilling, etc. As an example, a via penetrating at least a part of the second insulating layer 120 can be formed by a laser or the like, and the second via layer 170 can be formed by filling the via with a conductive material.

[0087] Referring to FIG. 9, the substrate portion (SUB) can be separated from both sides of the carrier substrate (CS).

[0088] Hereinafter, one substrate portion (SUB) separated from the carrier substrate (CS) will be described.

[0089] Referring to FIG. 10, the first solder resist layer 180 can be formed on the first surface of the first insulating layer 110. The first solder resist layer 180 can be formed so as to expose a part of the first heat dissipation pattern 132. Also, the second solder resist layer 190 can be formed on the third surface of the second insulating layer 120. The second solder resist layer 190 can be formed so as to expose a part of the third circuit pattern layer 152.

[0090] Specifically, the first solder resist layer 180 can be formed through an exposure and development process. The first solder resist layer 180 can include an opening that exposes at least a part of the second circuit pattern layer 142.

[0091] The second solder resist layer 190 can be formed through an exposure and development process. The second solder resist layer 190 can include an opening that exposes at least a part of the third circuit pattern layer 152.

[0092] Referring to FIG. 11, by etching and removing the first sacrificial layer 1111, the cavity 111 can be formed. The etching process can use dry etching or wet etching, but is not limited thereto. As an example, an etching resist can be formed in the remaining region excluding the first sacrificial layer 1111 to be etched, and the first sacrificial layer 1111 can be etched and removed. The etching resist can include a dry film. Referring to FIG. 12, by etching and removing the second sacrificial layer 2021, the groove portion 110c can be formed in the upper surface region 110a of the first insulating layer 110. The etching process can use dry etching or wet etching, but is not limited thereto. For example, the first sacrificial layer 1111 can be etched using an etching solution. And the second sacrificial layer 2021 can be etched using another etching solution. The first sacrificial layer 1111 and the second sacrificial layer 2021 can include metal materials that can be selectively removed by different etching solutions. As described above, for example, the first sacrificial layer 1111 includes copper. And the second sacrificial layer 2021 can include nickel. However, it is not limited thereto. Here, one surface of the first portion 201 of the heat dissipation portion 200 (see FIG. 1) can be exposed to the outside through the groove portion 110c.

[0093] The second pattern layer 140 and the second sacrificial layer 2021 can include different metal materials. Therefore, the second pattern layer 140 and the sacrificial layer 2021 can be selectively removed by different etching solutions. Also, the second sacrificial layer 2021 can be selectively etched without separately masking the exposed second pattern layer 140.

[0094] In the embodiment, with reference to FIGS. 10 to 12, the first solder resist layer 180 and the second solder resist layer 190 are formed, and the first sacrificial layer 1111 and the second sacrificial layer 2021 are etched and removed. However, the present invention is not limited thereto. For example, an etching resist may be formed, the first sacrificial layer 1111 and the second sacrificial layer 2021 may be removed, and then the etching resist may be removed. Thereafter, the first solder resist layer 180 is formed on the first insulating layer 110, and the second solder resist layer 190 is formed on the second insulating layer 120.

[0095] Referring to FIG. 13, a seed layer (SD) can be formed on one surface of the first portion 201. The seed layer (SD) can be formed inside the groove portion 110c. The seed layer (SD) can be formed by a chemical copper plating process. For example, after patterning the region where the seed layer SD is to be formed using a dry film or the like, the chemical copper plating process can be performed to form the seed layer SD.

[0096] Referring to FIG. 14, a mask layer (MSK) can be disposed on the first solder resist layer 180, the upper surface region 110a of the first insulating layer 110, the side surface region 110b of the first insulating layer 110, and the second solder resist layer 190. That is, all portions except the region where the second portion 202 (see FIG. 1) is formed can be covered by the mask layer (MSK). A conductive portion 2022 can be formed on the seed layer (SD). The conductive portions 2022 may be provided in plurality. The conductive portion 2022 can be formed so as to protrude from one surface of the first insulating layer 110. The conductive portion 2022 can be formed by a plating process. The mask layer (MSK) can be formed including a dry film. By forming the conductive portion 2022 on the seed layer SD which is a chemical copper plating layer, even when the area of the one surface region of the first portion 201 where the conductive portion 2022 is formed is small, the necessary adhesion can be ensured, and the conductive portion 2022 can be formed to protrude more stably. However, the present invention is not limited thereto, and it is also possible to directly electroplate one surface of the first portion 201 to form the second portion 202 (see FIG. 1).

[0097] Referring to FIG. 15, the mask layer (MSK) can be removed to form a circuit board as shown in FIG. 1. In the embodiment, referring to FIGS. 13 to 15, it has been shown that the seed layer SD is formed on one surface of the first portion 201, but it is not limited thereto. In the seed layer forming step described with reference to FIG. 13, the seed layer can also be formed on one surface of the first portion 201, the first surface of the second circuit pattern layer 142, and the third surface of the third circuit pattern layer.

[0098] Here, a conductive portion 2022 can be formed on a part of the seed layer disposed on one surface of the first portion 201, and the remaining part of the seed layer can be removed to form a circuit board similar to FIG. 1. The remaining part of the seed layer (SD) can be removed by an etching process. The etching process can use dry etching or wet etching, but is not limited thereto. As an example, an etching resist can be formed in the remaining region except for the remaining part of the seed layer SD to be etched, and the remaining part of the seed layer can be etched and removed. The etching resist can include a dry film. Here, the conductive portion 2022 may have a greater thickness in the stacking direction than a part of the seed layer to be etched. Therefore, even when the conductive portion 2022 is etched together during the process of etching a part of the seed layer (SD), the conductive portion 2022 can be protected.

[0099] According to the method for manufacturing a circuit board according to this embodiment, by forming a heat dissipation portion with a protruding structure inside the cavity in which the electronic component is accommodated, while ensuring the mounting space of the electronic component, the heat generated from the electronic component can be efficiently absorbed and dispersed. In addition, the length of the heat dissipation portion can be adjusted and formed during the manufacturing process, and the heat dissipation portion can be applied to electronic components of various thicknesses.

[0100] Hereinafter, with reference to FIG. 16, an electronic component package according to an embodiment will be described. FIG. 16 is a cross-sectional view schematically showing an electronic component package according to an embodiment.

[0101] Referring to FIG. 16, the electronic component package 20 according to this embodiment can include the circuit board 10 according to the above-described embodiment. Hereinafter, the description regarding the first circuit board 10 can be similarly applied to the description regarding the circuit board 10 according to the above-described embodiment.

[0102] The electronic component package 20 according to one embodiment includes a first circuit board 10, a second circuit board 21 connected to the first circuit board 10, an electronic component 22 mounted on one surface of the second circuit board 21 and housed inside the cavity 111, a sealing material 23 disposed between the first and second circuit boards 10 and 21, filling the cavity 111 and covering at least a part of the electronic component 22, a conductive member 24 electrically connecting the first and second circuit boards 10 and 21, an electrode 25 electrically connecting the second circuit board 21 and the electronic component 22, and an underfill 26.

[0103] The second circuit board 21 is a circuit board on which the electronic component 22 is mounted, and can include an insulating layer, a wiring layer, a via layer, and a solder resist layer.

[0104] The electronic component 22 can be an integrated circuit (IC) die in which hundreds to millions or more of elements are integrated within one chip. For example, the electronic component 22 can be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, specifically an application processor (AP), but is not limited thereto. Additionally, it can also be other volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), memory such as flash memory, or logic such as an analog-to-digital converter or an application-specific IC (ASIC). If necessary, the electronic component 22 can be a chip-shaped passive component, for example, a chip-shaped capacitor such as a multi-layer ceramic capacitor (MLCC), a chip-shaped inductor such as a power inductor (PI). The electronic component 22 is covered by a sealing material 23 and at least one surface can be physically in contact with the sealing material 23.

[0105] The sealing material 23 can cover at least a part of one surface of the first solder resist layer 180, one surface of the second circuit board 21, and the outer surface of the electronic component 22. Also, the sealing material 23 can fill at least a part of the cavity 111, and as a result, can cover at least a part of the upper surface of the electronic component 22. For example, the sealing material 23 can physically contact at least a part of each of the upper surface, lower surface, and side surface of the electronic component 22. Since the sealing material 23 has fluidity in the pre-cured state, it can flow along the outer surface of the electronic component 22 and the surface of the first insulating layer 110 to fill the inside of the cavity 111.

[0106] As the material of the sealing material 23, an insulating substance can be used. As the insulating substance, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide can be used. Further, those containing an inorganic filler such as silica in these resins may be used. For example, ABF (Ajinomoto Build-up Film) can be used as the material of the sealing material 23. ABF is provided in the form of RCC (Resin coated Copper), but is not limited thereto. If necessary, a photosensitive material such as PID (Photo Image-able Dielectric) may be used. Also, the sealing material 23 may be a known EMC (Epoxy Molding Compound), but is not limited thereto.

[0107] The conductive member 24 is disposed at at least a part of the opening of the second circuit board 21. The conductive member 24 can physically and / or electrically connect the second circuit board 21 to the outside. For example, the conductive member 24 can electrically connect the exposed circuit pattern layer of the second circuit board 21 and the second circuit pattern layer 142 of the first circuit board 10. The conductive member 24 is formed of tin (Sn) or an alloy containing tin (Sn), for example, solder, etc., but is not limited thereto. For example, the conductive member 24 may be a ball, a land, a pin, or a column-shaped metal post, or a column shape in which a plurality of balls are combined.

[0108] The underfill 26 is a substance filled between the electronic component 22 mounted in the cavity 111 of the second circuit board 21 and the second circuit board 21, and can fix the electronic component 22 in the cavity 111. In particular, when the electrode 25 is formed to protrude and a gap is generated between one surface of the electronic component 22 and the second circuit board 21, the underfill 26 can be filled in the gap.

[0109] According to the electronic component package according to this embodiment, since the heat radiating part with a protruding structure is located inside the cavity of the first circuit board in which the electronic component is accommodated, it is possible to efficiently absorb and disperse the heat generated from the electronic component while securing the mounting space for the electronic component. Further, the length of the heat radiating part can be adjusted and formed, and the heat radiating part can be applied to electronic components of various thicknesses.

[0110] FIGS. 17 and 18 are drawings for explaining circuit boards according to various embodiments. FIG. 17 is a cross-sectional view of a circuit board according to another embodiment, and FIG. 18 is a plan view schematically showing one surface of a circuit board according to another embodiment.

[0111] Referring to FIG. 17, the circuit board 10A according to another embodiment is similar to the circuit board according to the embodiment described with reference to FIGS. 1 and 2. Specific descriptions of the same components are omitted.

[0112] Referring to FIG. 17, unlike the circuit board according to one embodiment illustrated in FIG. 1, the circuit board 10A according to another embodiment may not include the first heat radiating via electrode 161 in the first via layer 160, and the second via layer 170 may not include the second heat radiating via electrode 171. In other words, the first heat radiating pattern 131 may not be connected to other circuit pattern layers. As described above, by forming the heat radiating pattern and the heat radiating part in a simple structure, even when the design of the circuit pattern layer is complicated and it is difficult to connect the circuit pattern layer and the heat radiating pattern, a heat radiating part can be formed on the circuit board to efficiently absorb and disperse heat.

[0113] Referring to FIG. 18, the circuit board 10B according to another embodiment is similar to the circuit board according to one embodiment described with reference to FIGS. 1 and 2. Specific descriptions of the same components are omitted.

[0114] Referring to FIG. 18, different from the circuit board according to one embodiment illustrated in FIG. 1, the circuit board 10B according to another embodiment can have the heat dissipation part 200B extending along one edge of the cavity 111. The heat dissipation part 200B can extend in a direction perpendicular to the first direction. For example, the heat dissipation part 200B can extend along the second direction. The heat dissipation part 200B has a quadrilateral planar shape but is not limited thereto. For example, the heat dissipation part 200B can be formed by forming vias with a laser or the like in a via overlap method. As described above, by forming the heat dissipation part to have a wider planar area, the surface area of the heat dissipation part exposed inside the cavity in which the electronic components are accommodated can be increased, and the heat dissipation efficiency can be improved.

[0115] As described above, the preferred embodiments of the present invention have been described. However, the present invention is not limited thereto, and various modifications can be made and implemented within the scope of the claims, the description of the invention, and the accompanying drawings, and it is natural that these also belong to the scope of the present invention.

Explanation of Reference Numerals

[0116] 10: (First) Circuit board 20: Electronic component package 21: Second circuit board 22: Electronic component 23: Sealing material 24: Conductive member 25: Electrode 26: Underfill 110: First insulating layer 111: Cavity 120: Second insulating layer 130: First pattern 131: First heat dissipation pattern 132: First circuit pattern layer 140: Second pattern layer 141: Second heat dissipation pattern 142: Second circuit pattern layer 150: Third pattern layer 151: Third heat dissipation pattern 152: Third circuit pattern layer 160: First via layer 170: Second via layer 180: First solder resist layer 190: Second solder resist layer 200: Heat dissipation part 201: First part 202: Second part

Claims

1. a first insulating layer including a first surface and a second surface opposed to each other, the first surface having a cavity recessed therein; a first heat dissipation pattern disposed on the second surface of the first insulating layer; and a heat dissipation portion connected to the first heat dissipation pattern and protruding into the cavity through the first insulating layer;

2. a second insulating layer that embeds the first heat dissipation pattern and the at least one circuit pattern layer and is laminated in a first direction on the second surface; the first insulating layer includes a top surface region overlapping the cavity in the first direction and a side surface region overlapping the cavity in a second direction perpendicular to the first direction; The circuit board according to claim 1 , wherein the heat dissipation portion protrudes from the top surface region.

3. The heat dissipation portion is a first portion embedded in the first insulating layer; 3. The circuit board of claim 2, further comprising a second portion extending from said first portion and projecting from said top surface region.

4. the first insulating layer has a groove in the upper surface region in which the second portion is located; The circuit board according to claim 3 , wherein the width of the groove is greater than the width of the second portion.

5. A first pattern layer including the first heat dissipation pattern and a first circuit pattern layer disposed around the first heat dissipation pattern, The circuit board according to claim 1 , wherein the first heat dissipation pattern is connected to at least one other pattern layer.

6. the first insulating layer further includes a second heat dissipation pattern disposed on the first surface, The circuit board according to claim 5 , wherein the first heat dissipation pattern is connected to the second heat dissipation pattern.

7. a second insulating layer that embeds at least one pattern layer including the first pattern layer and is stacked in a first direction on the second surface; and a third heat dissipation pattern disposed on a third surface of the second insulating layer opposite to the second surface of the first insulating layer; The circuit board according to claim 5 , wherein the first heat dissipation pattern is connected to the third heat dissipation pattern.

8. The circuit board of claim 1 , wherein the heat sink portion extends alongside one edge of the cavity.

9. The heat dissipation portion is provided in plurality, The circuit board according to claim 1 , wherein the plurality of heat dissipation portions include portions arranged in a line in one direction.

10. The heat dissipation portion is provided in plurality, The circuit board according to claim 1 , wherein the heat dissipation portions are spaced apart from one another.

11. The circuit board according to claim 1 , wherein the heat dissipation portion comprises copper.

12. a first circuit board having a cavity on one side; a second circuit board connected to the first circuit board; and an electronic component mounted on one surface of the second circuit board and accommodated within the cavity; The first circuit board is a first insulating layer including a first surface and a second surface opposed to each other, the first surface having the cavity recessed therein; a first heat dissipation pattern disposed on the second surface of the first insulating layer; and an electronic component package comprising a heat dissipation portion connected to the first heat dissipation pattern, penetrating the first insulating layer and protruding into the cavity;

13. a second insulating layer that embeds the first heat dissipation pattern and the at least one circuit pattern layer and is laminated in a first direction on the second surface; the first insulating layer includes a top surface region overlapping the cavity in the first direction and a side surface region overlapping the cavity in a second direction perpendicular to the first direction; The electronic component package of claim 12 , wherein the heat dissipation portion protrudes from the top surface region.

14. The heat dissipation portion is a first portion embedded in the first insulating layer; 14. The electronic component package of claim 13, further comprising a second portion extending from said first portion and projecting from said top surface region.

15. the first insulating layer has a groove in the upper surface region in which the second portion is located; The electronic component package of claim 14 , wherein a width of the groove is greater than a width of the second portion.

16. A first pattern layer including the first heat dissipation pattern and a first circuit pattern layer disposed around the first heat dissipation pattern, The electronic component package of claim 12 , wherein the first heat dissipation pattern is connected with at least one other pattern layer.

17. a second heat dissipation pattern disposed on the first surface of the first insulating layer; The electronic component package according to claim 16 , wherein the first heat dissipation pattern is connected to the second heat dissipation pattern.

18. a second insulating layer that embeds at least one pattern layer including the first pattern layer and is stacked in a first direction on the second surface; and a third heat dissipation pattern disposed on a third surface of the second insulating layer opposite to the second surface of the first insulating layer; The electronic component package according to claim 16 , wherein the first heat dissipation pattern is connected to the third heat dissipation pattern.

19. The electronic component package of claim 12 , wherein the heat spreader extends alongside one edge of the cavity.

20. The heat dissipation portion is provided in plurality, The electronic component package according to claim 12 , wherein the plurality of heat dissipation portions include portions arranged in a line in one direction.

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