Semiconductor element

Abstract

To suppress an expansion of a width in an end part of a stripe-shaped region.SOLUTION: A semiconductor element includes: a p-type resistance region that is extended in an annular shape so as to surround a contact region of an upper electrode and a semiconductor substrate; and a specific semiconductor layer that is arranged to the side lower from the resistance region. The specific semiconductor layer includes: a first conductive type specific region; a plurality of second conductive type stripe regions; and a second conductive type curvature region. In view of them from an upper side, each strip region is extended in a liner shape along a first direction, and is arranged with an interval along a second direction. In view of them from an upper side, an outer peripheral edge of the resistance region includes a curvature-shaped corner part. In view of them from the upper side, a border line obtained by connecting an end part of a long direction of the plurality of strip regions includes the curvature part extended along the corner part. The curvature region is extended along the curvature part at a position to the curvature part in view of them from the upper side.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

[0002] The semiconductor device disclosed in Patent Document 1 has a p-type RESURF layer that extends annularly so as to surround the contact region between the upper electrode and the semiconductor substrate. P-type layers such as the RESURF layer, FLR (Field Limiting Ring), and JTE (Junction Termination Extension) (i.e., p-type layers that extend annularly so as to surround the contact region between the upper electrode and the semiconductor substrate) are called the breakdown voltage region. Further, the semiconductor device disclosed in Patent Document 1 has a superjunction structure below the breakdown voltage region. In the superjunction structure, stripe-shaped p-type regions and n-type regions are alternately arranged when viewed from above. According to the superjunction structure, the breakdown voltage of the semiconductor device can be improved. In Patent Document 1, the superjunction structure is provided in a region extending from below the upper electrode to near the outer peripheral end of the semiconductor substrate. That is, in Patent Document 1, the superjunction structure is provided in a wide range on the outer peripheral side of the breakdown voltage region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The superjunction structure provided on the outer peripheral side rather than the breakdown voltage region does not contribute much to improving the breakdown voltage and also causes leakage current. In order to suppress the leakage current, the superjunction structure on the outer peripheral side rather than the breakdown voltage region can be reduced. On the other hand, when reducing the superjunction structure on the outer peripheral side rather than the breakdown voltage region, if the outer peripheral edge of the superjunction structure extends along the outer peripheral edge of the breakdown voltage structure, the electric field concentration in the semiconductor substrate can be suppressed. Therefore, in the corner portion where the outer peripheral edge of the breakdown voltage structure extends in a curved shape, the contour line (that is, the contour line obtained by connecting the ends of the stripe-shaped regions) constituting the outer peripheral edge of the superjunction structure below it can be formed in a curved shape along the corner portion of the breakdown voltage structure.

[0005] Figs. 5 and 6 illustrate the process of forming each stripe-shaped region 42 by ion implantation. In Fig. 6, the case where each stripe-shaped region 42 is p-type is shown as an example. Each region 42 is formed by ion implantation through a resist mask 90 provided on the semiconductor substrate 12. When forming the contour line of the superjunction structure in a curved shape, there is a wide portion 94a of the resist mask 90 at a position adjacent in the width direction to each opening 92. During ion implantation, the resist mask 90 is heated and solvents and the like volatilize, causing the resist mask 90 to shrink. At this time, the amount of shrinkage becomes large in the wide portion 94a, and the side surface 92a of the opening 92 adjacent to the wide portion 94a inclines. Due to the inclination of the side surface 92a, dopants are implanted in a range wider than the design value. As a result, in the range where the contour line of the superjunction structure is curved, the width of each stripe-shaped region 42 becomes wider. Thus, when the width of each stripe-shaped region expands, the balance of dopants is disrupted and the breakdown voltage of the semiconductor device decreases.

[0006] This specification proposes a technique for suppressing the expansion of the width of the stripe-shaped region when providing the contour line of the superjunction structure in a curved shape.

Means for Solving the Problem

[0007] The semiconductor device of Configuration 1 disclosed in this specification has a semiconductor substrate and an upper electrode provided on the upper surface of the semiconductor substrate. The semiconductor substrate has a breakdown voltage region and a specific semiconductor layer. The breakdown voltage region is provided in a range including the upper surface, and is a p-type region extending annularly so as to surround the contact region between the upper electrode and the semiconductor substrate when viewed from above. The specific semiconductor layer is disposed below the breakdown voltage region. The specific semiconductor layer has a specific region of a first conductivity type which is one of n-type and p-type, a plurality of stripe regions of a second conductivity type which is the other of n-type and p-type, and a curved region of the second conductivity type. When viewed from above, each of the stripe regions extends linearly along a first direction. When viewed from above, the plurality of stripe regions are arranged in the specific region at intervals along a second direction orthogonal to the first direction. When viewed from above, the plurality of stripe regions are distributed in a range straddling the lower part of the contact region and the lower part of the breakdown voltage region. When viewed from above, the outer peripheral edge of the breakdown voltage region has a curved corner portion. When viewed from above, the contour line obtained by connecting the longitudinal ends of the plurality of stripe regions has a curved portion extending along the corner portion. The curved region is separated from the plurality of stripe regions and extends along the curved portion at a position facing the curved portion when viewed from above.

[0008] In this semiconductor device, a curved region of the same second conductivity type as the stripe region is provided at a position facing the curved portion (that is, the curved portion of the contour line obtained by connecting the longitudinal ends of the stripe regions) when viewed from above. Therefore, each stripe region and the curved region can be formed simultaneously by ion implantation. In the resist mask for ion implantation, an opening for the curved region is disposed between the opening for each stripe region and the wide portion of the mask. Therefore, even when the mask portion contracts during ion implantation, deformation of the opening for each stripe region is suppressed. For this reason, an increase in the width at the end of each stripe region can be suppressed.

Brief Description of the Drawings

[0009]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0010] Following the above configuration 1, additional configurations of the vehicle disclosed in this specification will be described below.

[0011] (Configuration 2) When viewed from above, the outer peripheral edge of the region where the plurality of stripe regions are distributed has a first straight portion that extends along the first direction and is connected to one end of the curved portion, and a second straight portion that extends along the second direction and is connected to the other end of the curved portion. When a line obtained by extending the first straight portion toward the curved portion side is defined as a first extension line, and a line obtained by extending the second straight portion toward the curved portion side is defined as a second extension line, the curved region is arranged within a range surrounded by the first extension line, the second extension line, and the curved portion when viewed from above. The semiconductor element according to Configuration 1. (Configuration 3) The semiconductor device according to Configuration 1 or 2, wherein when a rated voltage is applied to the upper electrode, a depletion layer extending from the plurality of stripe regions to the specific region does not reach the curved region. (Configuration 4) The semiconductor device according to any one of Configurations 1 to 3, wherein when viewed from above, the curved portion is disposed on the outer peripheral side of the corner portion. (Configuration 5) A method of manufacturing a semiconductor device according to any one of Configurations 1 to 4, the method comprising: forming a resist mask having openings corresponding to the plurality of stripe regions and the curved region on the upper surface of the semiconductor substrate; and forming the plurality of stripe regions and the curved region by implanting dopants into the semiconductor substrate through the resist mask.

[0012] According to Configuration 2, the space in the semiconductor substrate can be efficiently utilized, and the semiconductor device can be miniaturized.

[0013] According to Configuration 3, the electric field concentration inside the semiconductor substrate can be suppressed.

[0014] The semiconductor device 10 of the embodiment shown in FIGS. 1 and 2 includes a semiconductor substrate 12, an upper electrode 14, a lower electrode 16, and a protective insulating layer 18. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). However, the semiconductor substrate 12 may be made of a semiconductor other than silicon carbide (e.g., silicon, gallium nitride, gallium oxide, etc.). The upper electrode 14 is in contact with the central portion of the upper surface 12a of the semiconductor substrate 12. Hereinafter, the semiconductor region below the contact region 12b between the upper electrode 14 and the semiconductor substrate 12 is referred to as an element region 12c, and the semiconductor region around the element region 12c is referred to as an outer peripheral region 12d. That is, the outer peripheral region 12d is a semiconductor region between the element region 12c and the outer peripheral end surface 12e of the semiconductor substrate 12. The protective insulating layer 18 covers the upper surface 12a of the semiconductor substrate 12 in the outer peripheral region 12d. The lower electrode 16 covers the entire lower surface 12f of the semiconductor substrate 12. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, and a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction.

[0015] The semiconductor substrate 12 has a main p-type region 20, a breakdown voltage region 22, an upper n-type region 24, a specific semiconductor layer 26, a lower n-type region 28, and a contact n-type region 30.

[0016] The main p-type region 20 is provided within the element region 12c. The main p-type region 20 is provided in a range including the upper surface 12a and makes an ohmic contact with the upper electrode 14.

[0017] The breakdown voltage region 22 is a so-called RESURF layer and is a p-type region having a lower p-type impurity concentration than the main p-type region 20. The breakdown voltage region 22 is provided within the outer peripheral region 12d. The breakdown voltage region 22 is provided in a range including the upper surface 12a. As shown in FIG. 1, the breakdown voltage region 22 extends annularly so as to surround the element region 12c. As shown in FIG. 2, the breakdown voltage region 22 is in contact with the main p-type region 20 from the outer peripheral side. As shown in FIG. 1, the breakdown voltage region 22 extends in a curved shape at a position adjacent to the corner of the contact region 12b. Note that, as the breakdown voltage region 22, an FLR or a JTE may be provided instead of the RESURF layer.

[0018] As shown in FIG. 2, the upper n-type region 24 is provided across the element region 12c and the outer peripheral region 12d. The upper n-type region 24 is in contact with the main p-type region 20 and the breakdown voltage region 22 from the lower side. The upper n-type region 24 is distributed up to the upper surface 12a and the outer peripheral end surface 12e on the outer peripheral side of the breakdown voltage region 22.

[0019] The specific semiconductor layer 26 is a layer composed of an n-type specific region 40 and a plurality of p-type regions dispersed and arranged within the specific region 40. The specific semiconductor layer 26 is distributed across the element region 12c and the outer peripheral region 12d. The specific semiconductor layer 26 is in contact with the upper n-type region 24 from the lower side.

[0020] The lower n-type region 28 is provided across the element region 12c and the outer peripheral region 12d. The lower n-type region 28 is in contact with the specific semiconductor layer 26 from the lower side.

[0021] The contact n-type region 30 is an n-type region having an n-type impurity concentration higher than that of the upper n-type region 24, the specific region 40, and the lower n-type region 28. The contact n-type region 30 is provided across the element region 12c and the outer peripheral region 12d. The contact n-type region 30 is provided in a range including the lower surface 12f and makes an ohmic contact with the lower electrode 16.

[0022] Next, the specific semiconductor layer 26 will be described in detail. The specific region 40 has an n-type impurity concentration substantially equal to that of the upper n-type region 24 and the lower n-type region 28. The specific region 40 is connected to the upper n-type region 24 at the upper end of the specific semiconductor layer 26 and is connected to the lower n-type region 28 at the lower end of the specific semiconductor layer 26. That is, the upper n-type region 24, the specific region 40, and the lower n-type region 28 are continuous n-type regions with each other.

[0023] As shown in FIG. 1, the specific semiconductor layer 26 has a plurality of stripe regions 42 and a plurality of curved regions 44. Each stripe region 42 and each curved region 44 are p-type regions. The plurality of stripe regions 42 and the plurality of curved regions 44 are dispersedly arranged in the specific region 40.

[0024] As shown in FIG. 2, each stripe region 42 extends from the upper end to the lower end of the specific semiconductor layer 26. When the semiconductor substrate 12 is viewed from above as shown in FIG. 1, each stripe region 42 extends linearly along the y direction. The plurality of stripe regions 42 are arranged at intervals in the x direction. As shown in FIG. 2, a specific region 40 is provided in the interval between the plurality of stripe regions 42. Hereinafter, the specific region 40 provided in the interval between the plurality of stripe regions 42 may be referred to as the stripe region 40n. The stripe region 40n and the stripe region 42 are alternately arranged along the x direction. The plurality of stripe regions 42 are distributed in a range straddling the element region 12c and the outer peripheral region 12d. More specifically, as shown in FIG. 1, each stripe region 42 is distributed across the lower part of the breakdown voltage region 22 and the lower part of the contact region 12b in the y direction. Each stripe region 42 extends from a position outside the outer peripheral edge 22a of the breakdown voltage region 22 to a position outside the outer peripheral edge 22a on the opposite side in the y direction. As shown in FIG. 2, in the x direction, a plurality of stripe regions 42 are arranged dispersedly in a range straddling the lower part of the contact region 12b to the lower part of the breakdown voltage region 22. The outermost stripe region 42x is arranged on the outer peripheral side of the outer peripheral edge 22a of the breakdown voltage region 22. As shown in FIG. 2, an n-type specific region 40 is distributed between the stripe region 42x and the outer peripheral end face 12e of the semiconductor substrate 12.

[0025] FIG. 3 shows an enlarged view of the corner of the breakdown voltage region 22. As shown in FIG. 3, the outer peripheral edge 22a of the breakdown voltage region 22 has a corner portion 22c that extends in a curved shape. Also, the contour line 42b in FIG. 3 is a contour line obtained by connecting the ends of each stripe region 42 in the y direction. The contour line 42b has a curved portion 42c that extends in a curved shape along the corner portion 22c. Since the ends of each stripe region 42 are arranged on the outer peripheral side of the breakdown voltage region 22, the contour line 42b is arranged on the outer peripheral side of the corner portion 22c.

[0026] As shown in FIG. 4, each curved region 44 is arranged in a depth range overlapping with each stripe region 42. Each curved region 44 extends from the upper end to the lower end of the specific semiconductor layer 26. Each curved region 44 is separated from each stripe region 42 by a specific region 40. As shown in FIG. 3, the curved region 44 extends along the curved portion 42c at a position facing the curved portion 42c when viewed from above. The extension line 46x in FIG. 3 is an extension line obtained by extending the side 45x extending along the x - direction of the outer peripheral edge of the region where the plurality of stripe regions 42 are distributed toward the curved portion 42c side. Also, the extension line 46y is an extension line obtained by extending the side 45y extending along the y - direction of the outer peripheral edge of the region where the plurality of stripe regions 42 are distributed toward the curved portion 42c side. The curved region 44 is arranged within the range surrounded by the extension line 46x, the extension line 46y, and the curved portion 42c. According to this configuration, the curved region 44 can be provided without expanding the chip size.

[0027] Within the element region 12c, a pn diode is formed by the main p - type region 20, the upper n - type region 24, the specific semiconductor layer 26, the lower n - type region 28, and the contact n - type region 30. When a potential higher than that of the lower electrode 16 is applied to the upper electrode 14, holes flow from the main p - type region 20 through the upper n - type region 24, the stripe region 40n, and the lower n - type region 28 to the contact n - type region 30. At the same time, electrons flow from the contact n - type region 30 through the lower n - type region 28, the stripe region 40n, and the upper n - type region 24 to the main p - type region 20. When a potential higher than that of the upper electrode 14 is applied to the lower electrode 16, the diode turns off, and a depletion layer spreads from the main p - type region 20 to the upper n - type region 24. Within the outer peripheral region 12d, a depletion layer spreads from the breakdown voltage region 22 to the upper n - type region 24. Also, within the specific semiconductor layer 26, depletion layers spread from each pn junction constituting the interface between the stripe region 42 and the specific region 40 to the stripe region 42 and the specific region 40. By such spreading depletion layers, a wide range of the upper n - type region 24, the specific semiconductor layer 26, and the lower n - type region 28 is depleted.

[0028] Note that, even when a rated voltage is applied between the upper electrode 14 and the lower electrode 16, the curved region 44 is arranged at a position where the depletion layer extending from the stripe region 42 to the specific region 40 does not reach. Therefore, the curved region 44 does not affect the distribution of the depletion layer inside the semiconductor substrate 12. For this reason, the distribution of the depletion layer does not get disturbed in the vicinity of the curved portion 42c, and the semiconductor element 10 has a high breakdown voltage.

[0029] Next, a method for manufacturing the semiconductor element 10 will be described. First, problems that occur when manufacturing a semiconductor element without the curved region 44 will be described. The p-type stripe region 42 is formed by implanting p-type impurities into the n-type specific region 40 through a resist mask. FIG. 5 shows a resist mask 90 used in the manufacturing process of a semiconductor element without the curved region 44. The resist mask 90 has a plurality of stripe-shaped openings 92 corresponding to the stripe region 42. As shown in FIG. 6, each stripe region 42 is formed by implanting p-type impurities passing through the openings 92 of the resist mask 90 into the specific region 40 of the semiconductor substrate 12. In the ion implantation process, the resist mask 90 is heated. Solvents and the like volatilize from the heated resist mask 90, and the resist mask 90 shrinks. As shown in FIG. 5, at the position corresponding to the curved portion 42c, the end portions of each opening 92 are adjacent to the wide portion 94a of the resist mask 90 in the x direction. Since the width of the wide portion 94a is wide, the amount of shrinkage of the wide portion 94a in the x direction is large. For this reason, as shown in FIG. 6, the side surface 92a of the opening 92 adjacent to the wide portion 94a is inclined, and p-type impurities are implanted into the specific region 40 through the side surface 92a. As a result, as shown in FIGS. 6 and 7, in the curved portion 42c, the width of the surface layer portion of the stripe region 42 becomes locally wide. When the width of the stripe region 42 becomes wide in the curved portion 42c in this way, the amount of p-type impurities in the stripe region 42 and the amount of n-type impurities in the specific region 40 become unbalanced in the vicinity of the curved portion 42c. As a result, in the off state of the diode, electric field concentration is likely to occur around the curved portion 42c.

[0030] Next, a method for manufacturing the semiconductor element 10 of the embodiment will be described. FIG. 8 shows a resist mask 80 used in the manufacturing process of the semiconductor element 10 of the embodiment. The resist mask 80 has a plurality of stripe-shaped openings 82 corresponding to the stripe regions 42 and an opening 84 corresponding to the curved region 44. As shown in FIG. 9, each stripe region 42 is formed by p-type impurities passing through the opening 82, and the curved region 44 is formed by p-type impurities passing through the opening 84. As shown in FIG. 8, since the opening 84 exists at a position in the x direction with respect to the end of each opening 84, each opening 84 is not adjacent to the wide portion 84a in the curved portion 42c. Therefore, as shown in FIG. 9, even if the resist mask 80 shrinks in the ion implantation process, almost no inclination occurs on the side surface of the opening 82. For this reason, as shown in FIGS. 3 and 9, it is possible to prevent the width of the stripe region 42 from becoming wider in the curved portion 42c. Therefore, in the semiconductor element 10 of the embodiment, in the off state of the diode, the electric field concentration around the curved portion 42c can be suppressed.

[0031] As described above, according to the structure and manufacturing method of the semiconductor element 10 of the embodiment, the electric field concentration in the vicinity of the curved portion 42c can be suppressed.

[0032] In the above-described embodiment, the stripe region 42 is separated from the main p-type region 20, but the stripe region 42 may be connected to the main p-type region 20. Also, in the above-described embodiment, the stripe region 42 is separated from the breakdown voltage region 22, but the stripe region 42 may be connected to the breakdown voltage region 22.

[0033] Also, in the above-described embodiment, the curved portion 42c is arranged on the outer peripheral side of the corner portion 22c, but the curved portion 42c may be arranged on the inner peripheral side of the corner portion 22c. That is, the curved portion 42c may be arranged below the breakdown voltage region 22.

[0034] In the above-described embodiment, the stripe region 42 and the curved region 44 are p-type, and the specific region 40 is n-type. However, the stripe region 42 and the curved region 44 may be n-type, and the specific region 40 may be p-type. In this case, by implanting n-type impurities into the p-type specific region 40, the n-type stripe region 42 and the curved region 44 can be formed.

[0035] Also, in the above-described embodiment, the element formed in the element region 12c is a diode, but other elements may be formed in the element region 12c instead of the diode. For example, a field effect transistor or an insulated gate bipolar transistor that uses the main p-type region 20 as a body region (i.e., a region where a channel is formed) may be provided in the element region 12c. In this case, the upper electrode 14 functions as a source electrode or an emitter electrode, and the lower electrode 16 functions as a drain electrode or a collector electrode. Note that, in this case, the gate may have a planar structure or a trench structure. Also, a Schottky barrier diode may be provided in the element region 12c. In this case, the upper n-type region 24 can be brought into Schottky contact with the upper electrode 14 without providing the main p-type region 20 in the element region 12c.

[0036] Also, in the above-described embodiment, one curved region 44 is provided for one curved portion 42c, but multiple curved regions 44 may be provided for one curved portion 42c as shown in FIG. 10.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves a plurality of purposes simultaneously, and has technical utility by achieving one of those purposes itself.

Description of Symbols

[0038] 10: Semiconductor element, 12: Semiconductor substrate, 14: Upper electrode, 20: Main p-type region, 22: Breakdown voltage region, 22c: Corner portion, 42: Strip region, 42c: Curved portion, 44: Curved region

Claims

1. A semiconductor device, comprising: a semiconductor substrate; an upper electrode provided on the upper surface of the semiconductor substrate; and having wherein the semiconductor substrate has a p-type breakdown voltage region provided in a range including the upper surface and extending annularly so as to surround a contact region between the upper electrode and the semiconductor substrate when viewed from above; a specific semiconductor layer disposed below the breakdown voltage region; and having wherein the specific semiconductor layer has a specific region of a first conductivity type which is one of n-type and p-type, a plurality of stripe regions of a second conductivity type which is the other of n-type and p-type, and a curved region of the second conductivity type; when viewed from above, each of the stripe regions extends linearly along a first direction; when viewed from above, the plurality of stripe regions are arranged in the specific region at intervals along a second direction orthogonal to the first direction; when viewed from above, the plurality of stripe regions are distributed in a range straddling a lower portion of the contact region and a lower portion of the breakdown voltage region; when viewed from above, an outer peripheral edge of the breakdown voltage region has a curved corner portion; when viewed from above, a contour line obtained by connecting longitudinal ends of the plurality of stripe regions has a curved portion extending along the corner portion; the curved region is separated from the plurality of stripe regions and extends along the curved portion at a position facing the curved portion when viewed from above; a semiconductor device.

2. When viewed from above, an outer peripheral edge of a region where the plurality of stripe regions are distributed has a first straight line portion extending along the first direction and connected to one end of the curved portion, and a second straight line portion extending along the second direction and connected to the other end of the curved portion; when a line obtained by extending the first straight line portion toward the curved portion side is defined as a first extension line, and a line obtained by extending the second straight line portion toward the curved portion side is defined as a second extension line, the curved region is disposed within a range surrounded by the first extension line, the second extension line, and the curved portion when viewed from above; The semiconductor device according to claim 1.

3. When a rated voltage is applied to the upper electrode, a depletion layer extending from the plurality of stripe regions to the specific region does not reach the curved region. The semiconductor device according to claim 1 or 2.

4. When viewed from above, the curved portion is disposed on an outer peripheral side of the corner portion. The semiconductor device according to claim 1 or 2.

5. A method for manufacturing a semiconductor device according to claim 1 or 2, the method comprising the step of forming a resist mask having openings corresponding to the plurality of stripe regions and the curved region on the upper surface of the semiconductor substrate, and forming the plurality of stripe regions and the curved region by implanting a dopant into the semiconductor substrate through the resist mask.

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