Semiconductor device, semiconductor module and electronic apparatus

Abstract

To provide a semiconductor device, a semiconductor module and an electronic apparatus in which leakage current can be reduced.SOLUTION: A semiconductor device comprises a Schottky gate type transistor. The Schottky gate type transistor comprises: a semiconductor that has first crystal orientation on a surface; and a control electrode that contacts with the surface, is formed by a metal of a face-centered cubic lattice structure having second crystal orientation, and in which the second crystal orientation is matched with the first crystal orientation in at least a portion of a vertical direction or a horizontal direction for the surface.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and an electronic device.

Background Art

[0002] In power amplifiers for communication, high output power and high efficiency at high frequencies are desired. For this reason, high electron mobility transistors (HEMTs) are used as the transistors for constructing power amplifiers. In MIS (Metal Insulator Semiconductor) type HEMTs, the threshold voltage (Vth) fluctuates due to the voltage stress during transistor operation. For this reason, MIS type HEMTs have not reached practical use. Therefore, research and development of Schottky gate type HEMTs are being advanced. The Schottky gate type HEMT is disclosed in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Schottky gate type HEMTs, there is a concern that an off-leakage current is generated. For this reason, development of a semiconductor device, a semiconductor module, and an electronic device including a Schottky gate type HEMT capable of reducing leakage current is desired.

Means for Solving the Problems

[0005] The semiconductor device according to the first embodiment of the present disclosure includes a Schottky gate transistor. The Schottky gate transistor includes a semiconductor having a first crystal orientation on its surface, and a control electrode formed of a face-centered cubic lattice structure metal having a second crystal orientation and in contact with the surface, and the second crystal orientation is aligned with the first crystal orientation in at least a part of the direction perpendicular or horizontal to the surface.

[0006] In the semiconductor device according to the second embodiment of the present disclosure, in the semiconductor device according to the first embodiment, the semiconductor is a barrier layer or a composite layer in which a cap layer is laminated on the barrier layer. The barrier layer or the cap layer is GaN having a <1-210> direction as the first crystal orientation. The control electrode has a <11-2> direction as the second crystal orientation.

[0007] The semiconductor module according to the third embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a Schottky gate transistor. The Schottky gate transistor includes a semiconductor having a first crystal orientation on its surface, and a control electrode formed of a face-centered cubic lattice structure metal having a second crystal orientation and in contact with the surface, and the second crystal orientation is aligned with the first crystal orientation in at least a part of the direction perpendicular or horizontal to the surface.

[0008] The electronic device according to the fourth embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a Schottky gate transistor. The Schottky gate transistor includes a semiconductor having a first crystal orientation on its surface, and a control electrode formed of a face-centered cubic lattice structure metal having a second crystal orientation and in contact with the surface, and the second crystal orientation is aligned with the first crystal orientation in at least a part of the direction perpendicular or horizontal to the surface.

Brief Description of Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment is the first example in which the present technology is applied to a semiconductor device equipped with a Schottky gate transistor. The first embodiment will explain the longitudinal cross-sectional structure and manufacturing method of the Schottky gate transistor. Furthermore, the first embodiment will explain in detail the physical characteristics and electrical characteristics of the Schottky gate transistor as compared with the Schottky gate transistor according to the comparative example. 2. Second Embodiment The second embodiment is the second example for explaining a semiconductor module in which the semiconductor device according to the first embodiment is mounted. 3. Third Embodiment The third embodiment is the third example for explaining an electronic device in which the semiconductor device according to the first embodiment is mounted. 4. Other Embodiments

[0011] <1. First Embodiment> The semiconductor device 1 according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 16. Here, in the drawings, the arrow X direction shown as appropriate represents one planar direction of the semiconductor device 1 placed on the plane for convenience. The arrow Y direction represents another planar direction orthogonal to the arrow X direction. The arrow Z direction represents the upward direction orthogonal to the arrow X direction and the arrow Y direction. That is, the arrow X direction, the arrow Y direction, and the arrow Z direction exactly coincide with the X-axis direction, Y-axis direction, and Z-axis direction of the three-dimensional coordinate system, respectively. Note that these directions are shown for facilitating understanding of the description and do not limit the direction of the present technology.

[0012] [Configuration of Semiconductor Device 1] (1) Schematic Configuration of Schottky Gate Transistor Tr FIG. 1 shows an example of the longitudinal cross-sectional structure of the semiconductor device 1 according to the first embodiment.

[0013] In the first embodiment, the semiconductor device 1 includes, as a main component, a Schottky gate type transistor Tr for constructing, for example, a power device, a high-frequency device, or the like. As the Schottky gate type transistor Tr, for example, a Schottky barrier junction type HEMT is used. Here, the Schottky gate type transistor Tr is formed in an n-channel conductivity type with electrons as majority carriers.

[0014] The Schottky gate type transistor Tr includes, as main components, a semiconductor 12 disposed on the substrate 10 with a buffer layer 11 interposed therebetween, a control electrode 20, and a pair of main electrodes 21.

[0015] (2) Configuration of the substrate 10 The semiconductor device 1 is configured based on the substrate 10. Here, in the first embodiment, the substrate 10 is formed of silicon carbide (SiC). Also, the substrate 10 may be formed of silicon (Si) or sapphire (Al 2 O 3 ).

[0016] (3) Configuration of the buffer layer 11 The buffer layer 11 is laminated on the surface of the substrate 10 in the arrow Z direction. The buffer layer 11 is used to ensure lattice matching between the substrate 10 and the semiconductor 12. In the first embodiment, the buffer layer 11 is formed of aluminum gallium nitride (AlGaN). Also, the buffer layer 11 may be formed of aluminum nitride (AlN) or gallium nitride (GaN).

[0017] (4) Configuration of the semiconductor 12 The semiconductor 12 is stacked on the surface of the buffer layer 11 in the Z arrow direction. The semiconductor 12 is formed by sequentially stacking a channel layer 121, a spacer layer 122, a barrier layer 123, and a cap layer 124. The semiconductor 12 is basically formed of a group III-V compound semiconductor material as a compound semiconductor. This will be described in detail.

[0018] (4-1) Structure of the channel layer 121 The channel layer 121 is stacked on the surface of the buffer layer 11. The channel layer 121 is formed of, for example, GaN. In the channel layer 121, carriers are accumulated in the vicinity of the spacer layer 122, and a two-dimensional electron gas 2DEG that functions as a carrier channel region is generated.

[0019] (4-2) Structure of the spacer layer 122 The spacer layer 122 is stacked on the surface of the channel layer 121. The spacer layer 122 is formed of, for example, AlN.

[0020] (4-3) Structure of the barrier layer 123 The barrier layer 123 is stacked on the surface of the spacer layer 122. The barrier layer 123 is formed of a compound semiconductor material in which carriers are accumulated in the channel layer 121 due to polarization with the channel layer 121. The barrier layer 123 is formed of, for example, Al 1-x-y Ga x In y N (0 ≦ x < 1, 0 ≦ y < 1). Specifically, the barrier layer 123 is formed of, for example, AlInN or AlGaN.

[0021] (4-4) Structure of the cap layer 124 The cap layer 124 is stacked on the surface of the barrier layer 123. In the first embodiment, the cap layer 124 is formed of GaN. The crystal structure of GaN is a hexagonal wurtzite structure. The crystal structure of the cap layer 124 will be described in detail later. Further, the cap layer 124 may be formed using silicon nitride (SiN).

[0022] Furthermore, in the first embodiment, the uppermost layer of the semiconductor 12 may be a barrier layer 123 except for the cap layer 124.

[0023] (5) Configuration of the control electrode 20 The control electrode 20 is laminated on the surface of the cap layer 124 of the semiconductor 12 and is formed as a gate electrode that forms a Schottky junction in contact with the cap layer 124. In the first embodiment, the control electrode 20 is formed of a composite film in which nickel (Ni) 201 and gold (Au) 202 are sequentially laminated in the arrow Z direction. That is, the control electrode 20 is in contact with at least the surface of the cap layer 124 and is formed of a metal having a face-centered cubic lattice structure in at least a part of the direction perpendicular (arrow Z direction) or horizontal (arrow X direction or arrow Y direction) to this surface. Here, all of the control electrode 20 is formed of a metal having a face-centered cubic lattice structure.

[0024] Note that the control electrode 20 may include the above Ni201 and Au202 and may be formed including one or more selected from copper (Cu), Al, platinum (Pt), and palladium (Pd).

[0025] (6) Configuration of the main electrode 21 The pair of main electrodes 21 are disposed on the surface of the cap layer 124 of the semiconductor 12, separated from each of the both ends in the gate length direction of the control electrode 20. One of the main electrodes 21 is used as, for example, a source electrode (S). The other main electrode 21 is used as, for example, a drain electrode (D).

[0026] The pair of main electrodes 21 are formed of an electrode material that makes an ohmic contact or a contact close to an ohmic contact with respect to the cap layer 124. The pair of main electrodes 21 are formed of, for example, a composite film in which titanium (Ti), molybdenum (Mo), Al, Ni, and Au are sequentially laminated.

[0027] In the first embodiment, although not shown, an n-type semiconductor region with a high impurity density may be disposed in the semiconductor 12 in the overlapping region of the pair of main electrodes 21. The n-type semiconductor region is used as a source region or a drain region and is electrically connected to the pair of main electrodes 21 by ohmic contact. Further, the n-type semiconductor region is formed at least up to the channel layer 121 of the semiconductor 12 in order to be electrically connected to the two-dimensional electron gas 2DEG.

[0028] (7) Crystal structure and crystal orientation of semiconductor 12 and control electrode 20 FIG. 2A shows an example of an enlarged longitudinal sectional configuration of a main part including the semiconductor 12 and the control electrode 20 of the Schottky gate type transistor Tr. As shown in FIG. 2A, in the Schottky gate type transistor Tr, the control electrode 20 is disposed on the surface of the cap layer 124 of the semiconductor 12.

[0029] FIG. 2B schematically shows an example of the crystal structure and crystal orientation of the compound semiconductor forming the cap layer 124 when the surface of the cap layer 124 is viewed from the direction of arrow Z (hereinafter, simply referred to as "in plan view"). FIG. 2C schematically shows an example of the crystal structure and crystal orientation of the metal forming the control electrode 20 in plan view. Further, FIG. 2D schematically shows an example of the crystal structure and crystal orientation having the symmetry of the metal forming the control electrode 20 shown in FIG. 2C in plan view.

[0030] The cap layer 124 of the semiconductor 12 is formed of GaN in the first embodiment. As described above, the crystal structure of GaN is a hexagonal wurtzite structure. When the cap layer 124 is grown by epitaxial growth using the epitaxial growth method, as shown in FIG. 2B, the (0001) crystal plane of GaN is formed on the surface of the cap layer 124. When the (0001) crystal plane coincides with the plane defined by the arrow X direction and the arrow Y direction, the crystal orientation coinciding with the arrow Y direction is the <1-210> direction. This direction is equivalent to the a axis. The crystal orientation in the <1-210> direction corresponds to the "first crystal orientation" according to the present technology.

[0031] On the other hand, in the first embodiment, the control electrode 20 is formed by sequentially laminating Ni201 and Au202. The crystal structures of Ni201 and Au202 are the same cubic crystal in a single crystal and have a face-centered cubic (fcc) structure. The crystal plane of the control electrode 20 is in contact with the surface of the cap layer 124. For example, when the control electrode 20 is formed of Au202, as shown in FIG. 2C, the (111) plane of Au202 is in contact with the (0001) crystal plane of GaN. When the (111) crystal plane coincides with the plane defined by the arrow X direction and the arrow Y direction, the crystal orientation coinciding with the arrow Y direction is the <11-2> direction. The crystal orientation in the <11-2> direction corresponds to the "second crystal orientation" according to the present technology.

[0032] In the Schottky gate type transistor Tr according to the first embodiment, in at least a part of the direction perpendicular or horizontal to the surface of the cap layer 124, the <1-210> direction which is the crystal orientation of the cap layer 124 and the <11-2> direction which is the crystal orientation of the control electrode 20 are made to coincide.

[0033] As shown in FIG. 2C, the crystal orientation of Au202 has directions equivalent to 120 degrees and 240 degrees clockwise respectively with respect to the <11-2> direction coinciding with the arrow Y direction from the center of the (111) crystal plane. That is, in the out-of-plane measurement of XRD, in the asymmetric reflection measurement, the crystal orientation of Au202 has three-fold symmetry. Further, as shown in FIG. 2D, when rotated 180 degrees with the center of the (111) crystal plane of Au202 as the rotation center, the crystal orientation of Au202 has three-fold symmetry different from the crystal orientation of Au202 shown in FIG. 2C. That is, in the asymmetric reflection measurement, the crystal orientation of Au202 has a total of six-fold symmetry.

[0034] (8) Analysis results of the control electrode 20 by XRD Fig. 3A shows an example of the analysis results of the control electrode 20 shown in Fig. 2A by out-of-plane measurement of XRD. Fig. 3B shows an example of the analysis results of the control electrode 20 shown in Fig. 2A by in-plane measurement of XRD. In addition, Fig. 4A shows an example of the analysis results of the control electrode of the Schottky gate transistor according to the comparative example by out-of-plane measurement of XRD. Fig. 4B shows an example of the analysis results of the control electrode of the Schottky gate transistor according to the comparative example by in-plane measurement of XRD.

[0035] Here, as described above, the control electrode 20 according to the first embodiment is formed by laminating Au202 on Ni201. The control electrode according to the comparative example is formed by laminating Au on Ni, similarly to the control electrode 20 according to the first embodiment.

[0036] As shown in Fig. 4A, in the control electrode according to the comparative example, according to the analysis results of the out-of-plane measurement of XRD, broadening is seen in the signal of the diffracted X-ray. In addition, as shown in Fig. 4B, in the control electrode according to the comparative example, according to the analysis results of the in-plane measurement of XRD, broadening is seen in the signal of the diffracted X-ray. That is, the control electrode according to the comparative example has a random crystal orientation and low crystallinity.

[0037] For the control electrode according to the comparative example, as shown in Fig. 3A, in the control electrode 20 according to the first embodiment, according to the analysis results of the out-of-plane measurement of XRD, no broadening is seen in the signal of the diffracted X-ray. In other words, in the control electrode 20, there is no dewing in the reciprocal lattice map. In addition, as shown in Fig. 3B, in the control electrode 20 according to the first embodiment, according to the analysis results of the in-plane measurement of XRD, no broadening is seen in the signal of the diffracted X-ray. That is, the control electrode 20 according to the first embodiment has a uniform crystal orientation and high crystallinity.

[0038] FIG. 5 shows an example of the measurement results of the peak half-width by the asymmetric reflection measurement of the control electrode 20 in the out-of-plane measurement of XRD. The vertical axis represents the peak half-width [sec]. As shown in FIG. 5, in the control electrode according to the comparative example, the peak half-widths of Ni and Au are around 7000 seconds. For the control electrode according to the comparative example, the peak half-width of Ni201 of the control electrode 20 according to the first embodiment is about 1000 seconds, and the peak half-width of Au202 is about 2000 seconds. That is, the peak half-widths of Ni201 and Au202 of the control electrode 20 are 5000 seconds or less.

[0039] (9) Electrical characteristics of the Schottky gate type transistor Tr FIG. 6 shows an example of the transfer characteristics of the Schottky gate type transistor Tr according to the first embodiment and the Schottky gate type transistor according to the comparative example. The horizontal axis represents the voltage (gate voltage) [V]. The vertical axis represents the current (drain current) [au]. Also, data A is the transfer characteristic of the Schottky gate type transistor Tr according to the first embodiment. Data B is the transfer characteristic of the Schottky gate type transistor according to the comparative example.

[0040] As shown by data B in FIG. 6, in the Schottky gate type transistor according to the comparative example, when the voltage (gate voltage) rises and reaches the threshold voltage Vth, a current (drain current) flows. The current flowing until the threshold voltage Vth is reached corresponds to the off-leakage current. On the other hand, as shown by data A, in the Schottky gate type transistor Tr according to the first embodiment, similarly, when the voltage rises and reaches the threshold voltage Vth, a current flows, but the off-leakage current is significantly reduced.

[0041] FIG. 7A shows an example of the on-stress test results of the Schottky gate transistor Tr according to the first embodiment. FIG. 8A shows an example of the on-stress test results of the Schottky gate transistor according to the comparative example. In each of FIGS. 7A and 8A, the horizontal axis represents temperature [°C], and the vertical axis represents the threshold voltage Vth [V].

[0042] Also, data a represents the variation of the threshold voltage Vth with respect to temperature after applying a stress such that the current flowing per unit length is 10 μA / mm. Data b represents the variation of the threshold voltage Vth with respect to temperature after applying a stress such that the current flowing per unit length is 500 μA / mm. Data c represents the variation of the threshold voltage Vth with respect to temperature after applying a stress such that the current flowing per unit length is 50 mA / mm.

[0043] As shown in FIG. 8A, in the Schottky gate transistor according to the comparative example, in the on-stress test results, the threshold voltage Vth varies with temperature change. On the other hand, as shown in FIG. 7A, in the Schottky gate transistor Tr according to the first embodiment, in the on-stress test results, the variation of the threshold voltage Vth with temperature change is small.

[0044] FIG. 7B shows an example of the off-stress test results of the Schottky gate transistor Tr according to the first embodiment. FIG. 8B shows an example of the off-stress test results of the Schottky gate transistor according to the comparative example. In each of FIGS. 7B and 8B, the horizontal axis represents temperature [°C], and the vertical axis represents the threshold voltage Vth [V].

[0045] As shown in FIG. 8B, in the Schottky gate transistor according to the comparative example, in the off-stress test results, the threshold voltage Vth varies with temperature change. On the other hand, as shown in FIG. 7B, in the Schottky gate transistor Tr according to the first embodiment, in the off-stress test results, the variation of the threshold voltage Vth with temperature change is small.

[0046] [Method for manufacturing semiconductor device 1] Next, the method for manufacturing the semiconductor device 1 described above will be explained. FIGS. 9 to 16 show an example of a process cross-section for explaining the method for manufacturing the semiconductor device 1 including the Schottky gate type transistor Tr for each process.

[0047] First, the substrate 10 is prepared, and as shown in FIG. 9, the buffer layer 11 and the semiconductor 12 are sequentially formed on the substrate 10. For the formation of each of the buffer layer 11 and the semiconductor 12, an epitaxial growth method is used. In the first embodiment, as described above, the semiconductor 12 is formed by sequentially laminating, for example, the channel layer 121, the spacer layer 122, the barrier layer 123, and the cap layer 124. The cap layer 124, which is the uppermost layer of the semiconductor 12, is formed of GaN. The surface of GaN has a crystal orientation in the first crystal orientation, specifically, in the <1-210> direction.

[0048] As shown in FIG. 10, a passivation film 3 is formed on the surface of the semiconductor 12. Here, the passivation film 3 is formed of, for example, SiN. For the formation of SiN, for example, a chemical vapor deposition (CVD) method is used.

[0049] As shown in FIG. 11, a mask 4 is formed on the surface of the passivation film 3. An opening 4H1 is formed in the mask 4 in the formation region of the control electrode 20, and an opening 4H2 is formed in the formation regions of the pair of main electrodes 21. As the mask 4, a photoresist film formed by photolithography technology is used.

[0050] Here, since the photoresist film is formed on the surface of the cap layer 124 with the passivation film 3 interposed therebetween, no disorder occurs in the crystal orientation on the surface of the cap layer 124. Further, when the photoresist film touches the surface of the cap layer 124, a cleaning process is performed on the surface of the cap layer 124.

[0051] Using the mask 4, the passivation film 3 is patterned to form openings 3H1 and 3H2 in the passivation film 3 (see FIG. 12). For example, a dry etching technique is used to form the openings 3H1 and 3H2. Subsequently, as shown in FIG. 12, the mask 4 is peeled off.

[0052] As shown in FIG. 13, an electrode material 20A for forming the control electrode 20 is formed on the surface of the passivation film 3. In the first embodiment, the electrode material 20A is formed of a composite film in which Ni201 and Au202 are sequentially laminated. For example, a vapor deposition method is used to form each of Ni201 and Au202.

[0053] Here, a part of the electrode material 20A contacts the surface of the cap layer 124 through the opening 3H1 of the passivation film 3. The surface of the GaN, which is the cap layer 124, is exposed in the opening 3H1. The electrode material 20A in contact with the surface of GaN is Ni201 in the first embodiment. The second crystal orientation of Ni201, specifically the crystal orientation in the <11-2> direction, is matched with the first crystal orientation of GaN in at least a part of the direction perpendicular or horizontal to the surface of GaN.

[0054] As shown in FIG. 14, a mask 5 is formed on the surface of the electrode material 20A. The mask 5 is formed in the formation region of the control electrode 20. A photoresist film formed by a photolithography technique is used for the mask 5.

[0055] Using the mask 5, the electrode material 20A is patterned to form the control electrode 20 from the electrode material 20A (see FIG. 15). For example, a dry etching method or a wet etching method is used for patterning. Subsequently, as shown in FIG. 15, the mask 5 is peeled off.

[0056] As shown in FIG. 16, a pair of main electrodes 21 that form an ohmic contact with the surface of the semiconductor 12 are formed through the opening 3H2 of the passivation film 3.

[0057] When these series of manufacturing processes are completed, the Schottky gate type transistor Tr according to the first embodiment is completed, and further, the semiconductor device 1 is completed.

[0058] [Operational Effects] As shown in FIGS. 1, 2A to 2D, the semiconductor device 1 according to the first embodiment includes a Schottky gate type transistor Tr. The Schottky gate type transistor Tr includes a semiconductor 12 and a control electrode 20. The semiconductor 12 has a first crystal orientation on its surface. The control electrode 20 is in contact with the surface of the semiconductor 12 and is formed of a metal having a face-centered cubic lattice structure with a second crystal orientation. In addition, the control electrode 20 aligns the second crystal orientation with the first crystal orientation at least in a part of the direction perpendicular or horizontal to the surface of the semiconductor 12.

[0059] Specifically, in the first embodiment, as shown in FIG. 1, the Schottky gate type transistor Tr is a Schottky gate type HEMT. The semiconductor 12 is a barrier layer 123 or a composite layer in which a cap layer 124 is laminated on the barrier layer 123. The barrier layer 123 is formed to contain one or more selected from Al, Ga, In, and N. The cap layer 124 is formed to contain one or more selected from Al, Ga, In, N, and Si. The control electrode 20 is formed to contain one or more selected from Ni, Cu, Al, Au, Pt, and Pd.

[0060] For example, when the cap layer 124 is GaN, as shown in FIG. 2B, the (0001) crystal plane of GaN has a <1-210> direction as the first crystal orientation. When the metal in contact with the surface of the cap layer 124 of the control electrode 20 is, for example, Au202, as shown in FIGS. 2C and 2D, the surface in contact with the cap layer 124 of Au202 has a <11-2> direction as the second crystal orientation.

[0061] In the Schottky gate type transistor Tr configured as described above, as shown in FIG. 6, the off-leakage current can be reduced with respect to the Schottky gate type transistor according to the comparative example. Therefore, in the semiconductor device 1 equipped with the Schottky gate type transistor Tr, the leakage current can be reduced.

[0062] <2. Second Embodiment> The semiconductor module 100 according to the second embodiment of the present disclosure will be described with reference to FIG. 17. FIG. 17 shows an example of the schematic structure of the semiconductor module 100 according to the second embodiment.

[0063] [Configuration of Semiconductor Module 100] The semiconductor module 100 according to the second embodiment is an antenna integrated module in which an edge antenna 101 arranged in an array shape, for example, and front-end components are mounted on a substrate 110 as one module. The front-end components include a switch 102, a low-noise amplifier 103, a band-pass filter 104, a power amplifier 105, and the like. The semiconductor module 100 can be used, for example, as a transceiver for communication.

[0064] The semiconductor module 100 includes, for example, the semiconductor device 1 according to the first embodiment as a transistor constituting the switch 102, the low-noise amplifier 103, or the power amplifier 105.

[0065] [Operation and Effect] In the semiconductor module 100 according to the second embodiment, since the semiconductor device 1 is included, power consumption can be reduced in wireless communication.

[0066] <3. Third Embodiment> The wireless communication device 300 according to the third embodiment of the present disclosure will be described with reference to FIG. 18. FIG. 18 shows an example of the schematic block configuration of the wireless communication device 300 according to the third embodiment.

[0067] [Configuration of Wireless Communication Device 300] The wireless communication device 300 according to the third embodiment includes an antenna ANT, an antenna switch circuit 301, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, a voice output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F includes, for example, a wireless LAN (W-LAN: Wireless Local Area Network), Bluetooth (registered trademark), etc. The wireless communication device 300 is, for example, a mobile phone system having multiple functions such as voice, data communication, and LAN connection.

[0068] The wireless communication device 300 includes the semiconductor device 1 according to the first embodiment as a transistor constituting the antenna switch circuit 301, the high-power amplifier HPA, the radio frequency integrated circuit RFIC, or the baseband unit BB, etc.

[0069] [Operational Effects] In the wireless communication device 300 according to the third embodiment, since the semiconductor device 1 is provided, low power consumption can be realized in wireless communication. Therefore, when the wireless communication device 300 is a portable communication terminal, the wireless communication device 300 can further extend the usage time, so that the portability can be further improved.

[0070] <4. Other Embodiments> The present technology is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

[0071] As described above, the semiconductor device according to the first embodiment of the present disclosure includes a Schottky gate type transistor. The Schottky gate type transistor includes a semiconductor and a control electrode. The semiconductor has a first crystal orientation on its surface. The control electrode is formed of a face-centered cubic lattice structure metal that contacts the surface of the semiconductor and has a second crystal orientation. In addition, the control electrode aligns the second crystal orientation with the first crystal orientation at least partially in a direction perpendicular or horizontal to the surface of the semiconductor. According to the semiconductor device configured as described above, the off-leakage current of the Schottky gate type transistor can be reduced. Therefore, in a semiconductor device incorporating the Schottky gate type transistor Tr, the leakage current can be reduced.

[0072] In the semiconductor device according to the second embodiment of the present disclosure, in the semiconductor device according to the first embodiment, the semiconductor is a barrier layer or a composite layer in which a cap layer is laminated on the barrier layer. The barrier layer or the cap layer is GaN having a <1-210> direction as the first crystal orientation. The control electrode has a <11-2> direction as the second crystal orientation. According to the semiconductor device configured as described above, similar to the semiconductor device according to the first embodiment, the leakage current can be reduced.

[0073] The semiconductor module according to the third embodiment of the present disclosure includes the semiconductor device according to the first embodiment. According to the semiconductor module configured as described above, since the leakage current can be reduced in the semiconductor device, power consumption can be reduced.

[0074] The electronic device according to the fourth embodiment of the present disclosure includes the semiconductor device according to the first embodiment. According to the electronic device configured as described above, since the leakage current can be reduced in the semiconductor device, power consumption can be reduced.

[0075] <Configuration of the present technology> The present technology has the following configuration. According to the present technology having the following configuration, in a semiconductor device, the leakage current can be reduced. In a semiconductor module and an electronic device, power consumption can be reduced.

[0076] (1) A semiconductor device including a Schottky gate transistor, wherein the Schottky gate transistor includes a semiconductor having a first crystal orientation on a surface, a control electrode that contacts the surface and is formed of a face-centered cubic lattice structure metal having a second crystal orientation, and in at least a part of a direction perpendicular or horizontal to the surface, the second crystal orientation is made to coincide with the first crystal orientation and is provided. (2) In an out-of-plane measurement of X-ray diffraction, the control electrode has no Debye ring in the reciprocal lattice map The semiconductor device according to (1) above. (3) In an out-of-plane measurement of X-ray diffraction, in an asymmetric reflection measurement, the control electrode has six-fold symmetry The semiconductor device according to (1) or (2) above. (4) In an out-of-plane measurement of X-ray diffraction, in an asymmetric reflection measurement, the full width at half maximum of the peak of the control electrode is 5000 seconds or less The semiconductor device according to any one of (1) to (3) above. (5) The semiconductor is a barrier layer or a composite layer in which a cap layer is laminated on the barrier layer The semiconductor device according to (1) above. (6) The barrier layer is formed including one or more selected from Al, Ga, In, and N The semiconductor device according to (5) above. (7) The cap layer is formed including one or more selected from Al, Ga, In, N, and Si The semiconductor device according to (5) or (6) above. (8) The control electrode is formed including one or more selected from Ni, Cu, Al, Au, Pt, and Pd The semiconductor device according to any one of (1) to (7) above. (9) The Schottky gate transistor is a Schottky gate high electron mobility transistor. The semiconductor device according to any one of (1) to (8) above. (10) The barrier layer or the cap layer is GaN having a <1-210> direction as the first crystal orientation. The control electrode is the metal having a <11-2> direction as the second crystal orientation. The semiconductor device according to (5) above. (11) A semiconductor device is provided. The semiconductor device includes a Schottky gate transistor. The Schottky gate transistor A semiconductor having a first crystal orientation on the surface, A control electrode that contacts the surface and is formed of a face-centered cubic lattice structure metal having a second crystal orientation, and the second crystal orientation is made to coincide with the first crystal orientation at least in part in a direction perpendicular or horizontal to the surface. A semiconductor module comprising the same. (12) A semiconductor device is provided. The semiconductor device includes a Schottky gate transistor. The Schottky gate transistor A semiconductor having a first crystal orientation on the surface, A control electrode that contacts the surface and is formed of a face-centered cubic lattice structure metal having a second crystal orientation, and the second crystal orientation is made to coincide with the first crystal orientation at least in part in a direction perpendicular or horizontal to the surface. An electronic device comprising the same.

Explanation of symbols

[0077] 1…Semiconductor device, 10…Substrate (first compound semiconductor), 11…Buffer layer, 12…Semiconductor, 121…Channel layer, 122…Spacer layer, 123…Barrier layer, 124…Cap layer, 2DEG…Two-dimensional electron gas, 20…Control electrode, 201…Ni, 202…Au, 21…Main electrode, Tr…Schottky gate type transistor, 100…Semiconductor module, 300…Wireless communication device.

Claims

1. A semiconductor device comprising a Schottky gate transistor, wherein the Schottky gate transistor comprises: a semiconductor having a first crystal orientation on a surface; a control electrode formed of a metal having a face-centered cubic lattice structure and having a second crystal orientation, which is in contact with the surface and has the second crystal orientation aligned with the first crystal orientation at least in part in a direction perpendicular or horizontal to the surface; and the semiconductor device is provided with the above components.

2. In an out-of-plane measurement of X-ray diffraction, the control electrode has no Debye ring in the reciprocal lattice map. The semiconductor device according to Claim 1.

3. In an out-of-plane measurement of X-ray diffraction, in an asymmetric reflection measurement, the control electrode has six-fold symmetry. The semiconductor device according to Claim 1.

4. In an out-of-plane measurement of X-ray diffraction, in an asymmetric reflection measurement, the full width at half maximum of the peak of the control electrode is 5000 seconds or less. The semiconductor device according to Claim 1.

5. The semiconductor is a barrier layer or a composite layer in which a cap layer is laminated on the barrier layer. The semiconductor device according to Claim 1.

6. The barrier layer is formed to contain one or more selected from Al, Ga, In, and N. The semiconductor device according to Claim 5.

7. The cap layer is formed to contain one or more selected from Al, Ga, In, N, and Si. The semiconductor device according to Claim 5.

8. The control electrode is formed to contain one or more selected from Ni, Cu, Al, Au, Pt, and Pd. The semiconductor device according to Claim 1.

9. The Schottky gate transistor is a Schottky gate high electron mobility transistor. The semiconductor device according to Claim 1.

10. The barrier layer or the cap layer is GaN having a <1-210> direction as the first crystal orientation, and the control electrode is the metal having a <11-2> direction as the second crystal orientation. The semiconductor device according to Claim 5.

11. A semiconductor module comprising a semiconductor device, wherein the semiconductor device comprises a Schottky gate transistor, and the Schottky gate transistor comprises: a semiconductor having a first crystal orientation on a surface; a control electrode formed of a metal having a face-centered cubic lattice structure and having a second crystal orientation, which is in contact with the surface and has the second crystal orientation aligned with the first crystal orientation at least in part in a direction perpendicular or horizontal to the surface; and the semiconductor module is provided with the above components.

12. Comprising a semiconductor device, The semiconductor device comprises a Schottky gate transistor, The Schottky gate transistor, A semiconductor having a first crystal orientation on its surface, Contacting the surface and formed of a metal having a face-centered cubic lattice structure with a second crystal orientation, and a control electrode in which the second crystal orientation is made to coincide with the first crystal orientation at least in part in a direction perpendicular or horizontal to the surface, An electronic device comprising the same.

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