Semiconductor device

Abstract

To generate a hardly fluctuating signal in response to temperature changes over a wide temperature range.SOLUTION: A semiconductor device (10) is provided with a target signal generation circuit (140) for generating a target signal, a temperature detection circuit (130) for detecting a target temperature (TMP) in the semiconductor device, and a memory (110) for holding a plurality of calibration data. The target signal generation circuit includes an adjustment circuit (ADJ) for adjusting the target signal by selectively using any of a plurality of correction data based on the detection result (DET) of the temperature detection circuit.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Among the signals generated within a semiconductor device, some signals are required to have characteristics that are less likely to vary with temperature changes. For example, a reference voltage used for comparison with other voltages is generated within the semiconductor device (see Patent Document 1 below), and the reference voltage is required to have characteristics that are less likely to vary with temperature changes.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] There is a need for a technique for generating a signal that is less likely to vary with temperature changes over a wide temperature range.

[0005] A semiconductor device according to an aspect of the present disclosure includes a target signal generation circuit configured to generate a target signal, a temperature detection circuit configured to detect a target temperature in the semiconductor device, and a memory configured to hold a plurality of calibration data. The target signal generation circuit has an adjustment circuit configured to selectively use any one of the plurality of correction data to adjust the target signal based on a detection result of the temperature detection circuit.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted as a rule. In this specification, for the sake of simplicity of description, the name of information, signal, physical quantity, functional unit, circuit, element, or component corresponding to a symbol or reference numeral may be omitted or abbreviated by writing the symbol or reference numeral for referring to the information, signal, physical quantity, functional unit, circuit, element, or component, etc.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. "Ground" refers to a reference conductor having a reference potential of 0 V (zero volts) serving as a reference or the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential may also be referred to as the ground potential. In the embodiments of the present disclosure, a voltage shown without particularly providing a reference represents a potential viewed from the ground. "Level" refers to the level of the potential, and for any signal or voltage of interest, the high level has a higher potential than the low level.

[0009] In this specification, MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0010] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0011] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other equations including physical quantities other than voltage.

[0012] FIG. 1 shows the overall configuration of a system 1 according to an embodiment of the present disclosure. The system 1 includes a semiconductor device 10, an upper device 20, and a bus 30. The semiconductor device 10 and the upper device 20 are connected to each other via a bus 30 composed of a plurality of communication wirings. The semiconductor device 10 and the upper device 20 can perform two-way communication via the bus 30. The bus 30 may be a serial bus or a parallel bus. When the bus 30 is a serial bus, the two-way communication between the semiconductor device 10 and the upper device 20 may be, for example, 2 communication by I

[0013] The upper device 20 is an external device (external circuit) provided outside the semiconductor device 10, and can transmit various commands to the semiconductor device 10 via the bus 30. The semiconductor device 10 can perform operations according to commands from the upper device 20. As described above, any communication between the semiconductor device 10 and the upper device 20 is performed via the bus 30, but the description of the bus 30 may be omitted below.

[0014] The semiconductor device 10 and the upper device 20 are each connected to the ground. A power supply voltage is supplied to each of the semiconductor device 10 and the upper device 20. The power supply voltage is a positive DC voltage. The semiconductor device 10 and the upper device 20 are each driven based on the power supply voltage supplied to itself. The power supply voltage for the semiconductor device 10 and the power supply voltage for the upper device 20 may be different from each other, but in this embodiment, it is assumed that they are a common power supply voltage VDD. That is, the power supply voltage VDD is supplied to each of the semiconductor device 10 and the upper device 20.

[0015] A signal source SS is provided outside the semiconductor device 10. An input voltage Vin is supplied from the signal source SS to the semiconductor device 10. More specifically, the semiconductor device 10 is provided with an input terminal IN for receiving the input voltage Vin, and the input voltage Vin from the signal source SS is supplied to the input terminal IN. The number of input voltages Vin supplied to the semiconductor device 10 may be one, or may be two or more. When the number of input voltages Vin supplied to the semiconductor device 10 is two or more, the semiconductor device 10 is provided with input terminals IN corresponding to the number of input voltages Vin, and the corresponding input voltage Vin is supplied to each input terminal IN.

[0016] The semiconductor device 10 has a functional circuit that performs an operation according to the input voltage Vin. The operation by the functional circuit is arbitrary. Hereinafter, unless otherwise specified, it is assumed that the semiconductor device 10 functions as a voltage monitoring device. At this time, the system 1 can be referred to as a voltage monitoring system 1.

[0017] The semiconductor device 10 (functional circuit) executes a voltage monitoring process for monitoring the level of the input voltage Vin. The voltage monitoring process is an upper limit monitoring process for monitoring whether the input voltage Vin exceeds a predetermined upper limit voltage VH LIM a lower limit monitoring process for monitoring whether the input voltage Vin is lower than a predetermined lower limit voltage VL LIM or a window monitoring process for monitoring whether the input voltage Vin is within the voltage range from the upper limit voltage VH LIM to the lower limit voltage VL LIM . The upper limit voltage VH LIM and the lower limit voltage VL LIM are preset. The values of the upper limit voltage VH LIM and the lower limit voltage VL LIM are arbitrary, but at least the upper limit voltage VH LIM is higher than the lower limit voltage VL LIM . For example, the upper limit voltage VH LIM is 3.1 V (volts), and the lower limit voltage VL LIM is 2.9 V.

[0018] The semiconductor device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing to the outside of the semiconductor device 10. The semiconductor device 10 is formed by encapsulating the semiconductor chip in a housing made of resin. Each circuit in the semiconductor device 10 is formed in the semiconductor integrated circuit. The input terminal IN is part of the plurality of external terminals provided in the semiconductor device 10. In addition, a power supply terminal that receives the power supply voltage VDD, a ground terminal connected to the ground, and communication terminals connected to each communication wiring that constitutes the bus 30 are also included in the plurality of external terminals. Note that the semiconductor device 10 is provided with an internal power supply circuit (not shown) that generates one or more internal power supply voltages based on the power supply voltage VDD, and each circuit in the semiconductor device 10 can be driven based on the internal power supply voltage.

[0019] FIG. 2 is a schematic block diagram of the semiconductor device 10. The semiconductor device 10 includes a memory 110, an actual use calibration data setting unit 120, a temperature detection circuit 130, and a target signal generation circuit 140.

[0020] The memory 110 includes a volatile memory such as a RAM (Random Access Memory) and a non-volatile memory such as a flash memory. The volatile memory may have a storage unit classified as a register. The memory 110 has a calibration data holding unit 111 (hereinafter, may be abbreviated as the holding unit 111). The calibration data holding unit 111 holds first to m-th calibration data. m is an arbitrary integer of 2 or more. Although details will become clear from the following description, each calibration data is used for adjusting a target signal described later. The calibration data holding unit 111 is constituted by a non-volatile memory and holds the first to m-th calibration data in a non-volatile manner. Each calibration data is digital data of a predetermined bit (for example, 8-bit or 12-bit digital data).

[0021] The actual use calibration data setting unit 120 (hereinafter, may be abbreviated as the setting unit 120) sets the actual use calibration data Crd based on the first to m-th calibration data supplied from the holding unit 111. The actual use calibration data Crd is the calibration data actually used in the adjustment of the target signal described later. When setting the actual use calibration data Crd, the temperature detection signal DET supplied from the temperature detection circuit 130 is referred to. That is, for example, the setting unit 120 can set any one of the first to m-th calibration data as the actual use calibration data Crd based on the temperature detection signal DET.

[0022] The temperature detection circuit 130 detects the temperature of the target position and generates a temperature detection signal DET indicating the detection result of the temperature of the target position. The temperature detection signal DET is supplied to the setting unit 120. The target position is a predetermined position in the semiconductor device 10 (more specifically, a predetermined position in the housing of the semiconductor device 10). Hereinafter, the temperature of the target position may be referred to as the target temperature TMP. The temperature detection circuit 130 includes a temperature measurement element (not shown in FIG. 2) installed at the target position, and detects the target temperature TMP using the temperature measurement element. The temperature measurement element is preferably set as close as possible to the target signal generation circuit 140, and it can be considered that the target temperature TMP substantially coincides with the temperature of the target signal generation circuit 140. The temperature measurement element may be any element whose electrical characteristics change with a change in the target temperature TMP. For example, a diode, a temperature measuring resistor, a linear resistor, or a thermistor can be used as the temperature measurement element.

[0023] The target signal generation circuit 140 has an adjustment circuit ADJ and generates and outputs a target signal using the adjustment circuit ADJ. The target signal is used by an arbitrary circuit (not shown) in the semiconductor device 10. For example, the target signal may be a voltage signal having a desired voltage amount or a current signal having a desired current amount. The adjustment circuit ADJ adjusts the target signal using the actual use calibration data Crd (that is, for example, adjusts the voltage amount or current amount of the target signal). When any one of the first to m-th calibration data is set as the actual use calibration data Crd in the setting unit 120 based on the temperature detection signal DET, the adjustment circuit ADJ selectively uses any one of the first to m-th calibration data based on the temperature detection signal DET to adjust the target signal.

[0024] As shown in FIG. 3, the adjustment circuit ADJ takes any one of the first to nth adjustment states. n is an arbitrary integer of 2 or more. Although details will be described later, for example, when generating a reference voltage that is a voltage signal as a target signal, the reference voltage can be generated by amplifying a predetermined DC voltage, and the adjustment circuit ADJ can adjust the amplification factor when generating the reference voltage from the DC voltage in n steps. At this time, for example, the states in which the amplification factor is set to the first to nth amplification factors may correspond to the first to nth adjustment states, respectively. Note that, among the first to nth adjustment states, one predetermined adjustment state is referred to as a reference adjustment state.

[0025] Referring to FIG. 4, the first to m calibration data to be held in the holding unit 111 are respectively acquired in a state where the target temperature TMP is set to predetermined evaluation temperatures Tmp[1] to Tmp[m]. The evaluation temperatures Tmp[1] to Tmp[m] are different from each other, and here it is assumed that "Tmp[i] < Tmp[i + 1]" holds for any integer i. The first to m calibration data are acquired in the shipment calibration process that is performed at the final stage of the manufacturing process of the semiconductor device 10.

[0026] The shipment calibration process will be described with reference to FIGS. 5 and 6. FIG. 5 is a flowchart of the shipment calibration process. FIG. 6 is a block diagram of parts related to the shipment calibration process. The shipment inspection device AA in FIG. 6 is connected to the semiconductor device 10 in the shipment calibration process, and the shipment calibration process is executed under the control of the shipment inspection device AA. In the shipment calibration process, the shipment inspection device AA is connected to the semiconductor device 10 in such a manner that it can acquire and measure the target signal generated by the target signal generation circuit 140, control the operation of the target signal generation circuit 140, and write data to the calibration data holding unit 111. Note that, in the shipment calibration process, the actual use calibration data setting unit 120 does not function or the operation of the actual use calibration data setting unit 120 is controlled by the shipment inspection device AA.

[0027] The shipment calibration process consists of the processes of steps S11 to S15. In the shipment calibration process, first, in step S11, 1 is assigned to the variable i managed by the shipment inspection device AA. In the subsequent step S12, the shipment inspection device AA acquires the target signal in the i-th evaluation state from the target signal generation circuit 140 and measures the acquired target signal. For example, when the target signal is a voltage signal, the voltage value of the voltage signal is measured. For example, when the target signal is a current signal, the current value of the current signal is measured.

[0028] The i-th evaluation state is a state in which the target temperature TMP is set to a predetermined evaluation temperature Tmp[i] and the state of the adjustment circuit ADJ is set to the reference adjustment state. That is, in step S12, the environment around the semiconductor device 10 is adjusted by the shipment inspector so that the target temperature TMP becomes the predetermined evaluation temperature Tmp[i]. Under this environment, the shipment inspection device AA sets the state of the adjustment circuit ADJ to the reference adjustment state and then operates the target signal generation circuit 140 to acquire and measure the target signal from the target signal generation circuit 140. Note that it is difficult to grasp the exact value of the target temperature TMP in the semiconductor device 10 or the shipment inspection device AA. Therefore, for example, in step S12, the target temperature TMP may be regarded as being a predetermined temperature ΔTmp (for example, 20°C) higher than the ambient temperature of the semiconductor device 10. In this case, when the ambient temperature of the semiconductor device 10 is lower than the evaluation temperature Tmp[i] by a predetermined temperature ΔTmp (for example, 20°C), the target temperature TMP is regarded as coinciding with the predetermined evaluation temperature Tmp[i] (the same applies to steps S112 and S212 described later). The ambient temperature of the semiconductor device 10 is the temperature of the environment in which the semiconductor device 10 is installed, and it is possible to easily measure the ambient temperature of the semiconductor device 10.

[0029] In step S13 following step S12, the shipping inspection device AA determines the i-th calibration data based on the measurement result of the target signal obtained under the i-th evaluation state, and writes the determined i-th calibration data non-volatilely to the calibration data holding unit 111. In the subsequent step S14, the shipping inspection device AA checks whether the variable i has reached the value of "m". If the variable i has not reached the value of "m", then in step S15, "1" is added to the variable i and then the process returns to step S12, and the processes of steps S12 and S13 are repeated. If the variable i has reached the value of "m", then the calibration process at the time of shipment is completed.

[0030] As a result, for each integer i satisfying "1 ≦ i ≦ m", the processes of steps S12 and S13 are executed, and when the calibration process at the time of shipment is completed, the first to m-th calibration data are written and held in the calibration data holding unit 111.

[0031] To clarify the operation during the execution of the calibration process at the time of shipment and the subsequent operation, the operation of the semiconductor device 10 after the completion of the calibration process at the time of shipment is referred to as the actual operation. In the actual operation, the actual use calibration data setting unit 120 sets the actual use calibration data Crd according to the temperature detection signal DET based on the data held in the calibration data holding unit 111, and the target signal is generated and adjusted by the target signal generation circuit 140 including the adjustment circuit ADJ based on the actual use calibration data Crd.

[0032] Hereinafter, in a plurality of embodiments, some specific configuration examples, operation examples, application technologies, modification technologies, etc. related to the semiconductor device 10 will be described. The matters described above in this embodiment are applied to the following respective embodiments unless otherwise specified and without contradiction. In each embodiment, if there are matters conflicting with the above-described matters, the description in each embodiment may be given priority. Also, without contradiction, among the plurality of embodiments shown below, the matters described in any one embodiment can be applied to any other embodiment (that is, it is also possible to combine any two or more of the plurality of embodiments).

[0033] <<First Embodiment>> The first embodiment will be described. The target signal according to the first embodiment is a voltage signal. Therefore, in the first embodiment, the value of the target signal is a voltage value, and the voltage having the value of the target signal is referred to as a reference voltage Vref (target voltage). Generally, the value of the reference voltage generated in a circuit varies somewhat depending on the temperature. In recent years, high voltage accuracy is often required within a wide temperature range. Even if the circuit design is made so that the variation due to temperature is minimized as much as possible, it is not easy to satisfy the voltage accuracy specification within a wide temperature range considering product variations.

[0034] In FIG. 7, curve 610 shows the temperature dependence of the reference voltage Vref (the dependence of the reference voltage Vref on the target temperature TMP) when it is assumed that there is no adjustment by the adjustment circuit ADJ. When it is assumed that there is no adjustment by the adjustment circuit ADJ, the reference voltage Vref changes relatively largely with respect to the temperature change within the specified operating temperature range. The specified operating temperature range is the range of the ambient temperature of the semiconductor device 10 and is the temperature range defined in the specification of the semiconductor device 10 as the temperature range in which the operation of the semiconductor device 10 is guaranteed (for example, the temperature range from -40°C to 125°C).

[0035] Fig. 8 shows the configuration of the temperature detection circuit 130A. In the first embodiment, the temperature detection circuit 130A in Fig. 8 is used as the temperature detection circuit 130 in Fig. 2. The temperature detection circuit 130A includes a diode 131, a constant current source 132, and comparators CMP1 to CMP3. The constant current source 132 is provided between the applied end of the internal power supply voltage generated within the semiconductor device 10 and the node 136. The anode of the diode 131 is connected to the node 136, and the cathode of the diode 131 is connected to the ground. The constant current source 132 supplies a constant current Icnst having a predetermined constant value to the diode 131. The constant current Icnst flows between the anode and the cathode of the diode 131 as the forward current of the diode 131. The voltage at the node 136 is referred to as voltage Va. The voltage Va is equal to the forward voltage of the diode 131. The diode 131 corresponds to the above-described temperature measurement element installed at the target position. Therefore, the voltage Va varies according to the target temperature TMP. Specifically, in accordance with the temperature characteristics of the diode 131, as the target temperature TMP increases, the voltage Va decreases, and as the target temperature TMP decreases, the voltage Va increases.

[0036] The comparators CMP1 to CMP3 each have an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminals of the comparators CMP1 to CMP3 are connected to the node 136 and thus receive the voltage Va. Threshold voltages Vth1, Vth2, and Vth3 are supplied to the non-inverting input terminals of the comparators CMP1, CMP2, and CMP3, respectively. The threshold voltages Vth1, Vth2, and Vth3 have predetermined positive voltage values and satisfy "Vth1 > Vth2 > Vth3". A circuit (not shown) for generating the threshold voltages Vth1 to Vth3 based on the power supply voltage VDD is provided in the semiconductor device 10.

[0037] Comparator CMP1 compares voltage Va with threshold voltage Vth1, generates a signal DET1 corresponding to the high-low relationship between voltage Va and Vth1, and outputs it from the output terminal. Comparator CMP2 compares voltage Va with threshold voltage Vth2, generates a signal DET2 corresponding to the high-low relationship between voltage Va and Vth2, and outputs it from the output terminal. Comparator CMP3 compares voltage Va with threshold voltage Vth3, generates a signal DET3 corresponding to the high-low relationship between voltage Va and Vth3, and outputs it from the output terminal. Signals DET1 to DET3 are binary signals each having a high level or a low level.

[0038] In principle, comparator CMP1 outputs a low-level signal DET1 when "Va > Vth1" holds, and outputs a high-level signal DET1 when "Va < Vth1" holds. However, comparator CMP1 is given a hysteresis characteristic. Therefore, more specifically, signal DET1 is generated as follows (see Fig. 10). Considering the state where signal DET1 is at a low level as a starting point, signal DET1 is maintained at a low level until "Va < Vth1" holds, and when "Va < Vth1" holds, signal DET1 switches to a high level. Thereafter, signal DET1 is maintained at a high level until "Va > Vth1 + ΔV" holds, and when "Va > Vth1 + ΔV" holds, signal DET1 returns to a low level.

[0039] In principle, comparator CMP2 outputs a low-level signal DET2 when "Va > Vth2" holds, and outputs a high-level signal DET2 when "Va < Vth2" holds. However, comparator CMP2 is given a hysteresis characteristic. Therefore, more specifically, signal DET2 is generated as follows (see Fig. 10). Considering the state where signal DET2 is at a low level as a starting point, signal DET2 is maintained at a low level until "Va < Vth2" holds, and when "Va < Vth2" holds, signal DET2 switches to a high level. Thereafter, signal DET2 is maintained at a high level until "Va > Vth2 + ΔV" holds, and when "Va > Vth2 + ΔV" holds, signal DET2 returns to a low level.

[0040] Comparator CMP3 outputs a low-level signal DET3 when "Va > Vth3" holds in principle, and outputs a high-level signal DET3 when "Va < Vth3" holds. However, the comparator CMP3 is given a hysteresis characteristic. Therefore, more specifically, the signal DET3 is generated as follows (see Figure 10). Considering the state where the signal DET3 is at a low level as a starting point, the signal DET3 is maintained at a low level until "Va < Vth3" holds, and when "Va < Vth3" holds, the signal DET3 switches to a high level. After that, the signal DET3 is maintained at a high level until "Va > Vth3 + ΔV" holds, and when "Va > Vth3 + ΔV" holds, the signal DET3 returns to a low level.

[0041] ΔV is a positive minute voltage representing the hysteresis width. The hysteresis width ΔV is smaller than the difference between the threshold voltages Vth1 and Vth2, and is also smaller than the difference between the threshold voltages Vth2 and Vth3.

[0042] The above-described temperature detection signal DET (see Figure 2) is formed by the signals DET1 to DET3. It is specified which of the four temperature ranges the target temperature TMP belongs to by the signals DET1 to DET3.

[0043] Figure 9 shows the relationship between the temperature ranges RNG[1] to RNG[4] and the signals DET1 to DET3 in the four temperature ranges. Figure 9 also shows the evaluation temperatures Tmp[1] to Tmp[4]. The relationship between the evaluation temperatures Tmp[1] to Tmp[4] and the temperature ranges RNG[1] to RNG[4] will be described later. Figure 10 shows the waveforms of the voltage Va, Vth1 to Vth3, and the signals DET1 to DET3 in a temperature monotonically increasing case where the target temperature TMP monotonically increases from a sufficiently low temperature to a sufficiently high temperature.

[0044] The temperature range RNG[1] is the temperature range below the boundary temperature Tmp_b1, the temperature range RNG[2] is the temperature range equal to or higher than the boundary temperature Tmp_b1 and lower than the boundary temperature Tmp_b2, the temperature range RNG[3] is the temperature range equal to or higher than the boundary temperature Tmp_b2 and lower than the boundary temperature Tmp_b3, and the temperature range RNG[4] is the temperature range equal to or higher than the boundary temperature Tmp_b3. The boundary temperature Tmp_b2 is higher than the boundary temperature Tmp_b1, and the boundary temperature Tmp_b3 is even higher than the boundary temperature Tmp_b2. The boundary temperatures Tmp_b1, Tmp_b2, and Tmp_b3 are, for example, -25°C, 75°C, and 125°C respectively. However, their specific temperatures are arbitrary as long as "Tmp_b1 < Tmp_b2 < Tmp_b3" holds.

[0045] When the semiconductor device 10 operates within the specified operating temperature range, the target temperature TMP belongs to any one of the temperature ranges RNG[1] to RNG[4]. When the semiconductor device 10 operates at the lower limit within the specified operating temperature range, the target temperature TMP becomes lower than the boundary temperature Tmp_b1, and when the semiconductor device 10 operates at the upper limit within the specified operating temperature range, the target temperature TMP becomes higher than the boundary temperature Tmp_b3.

[0046] The temperature detection circuit 130A determines and detects that the target temperature TMP belongs to the temperature range RNG[1] when all of the signals DET1 to DET3 have a low level. The temperature detection circuit 130A determines and detects that the target temperature TMP belongs to the temperature range RNG[2] when the signal DET1 has a high level and the signals DET2 and DET3 have low levels. The temperature detection circuit 130A determines and detects that the target temperature TMP belongs to the temperature range RNG[3] when the signals DET1 and DET2 have high levels and the signal DET3 has a low level. The temperature detection circuit 130A determines and detects that the target temperature TMP belongs to the temperature range RNG[4] when all of the signals DET1 to DET3 have high levels.

[0047] Fig. 11 shows the configuration of the reference voltage generation circuit 210 together with the peripheral circuits. The reference voltage generation circuit 210 corresponds to the target signal generation circuit 140 according to the first embodiment, and the reference voltage Vref generated by the reference voltage generation circuit 210 corresponds to the target signal according to the first embodiment. The reference voltage generation circuit 210 includes an operational amplifier 211 and a gain variable circuit 212. A voltage monitoring circuit 150 is provided in the semiconductor device 10.

[0048] A voltage Vgb is supplied to the non-inverting input terminal of the operational amplifier 211. The voltage Vgb is a positive DC voltage generated by a bandgap reference (not shown) provided in the semiconductor device 10. Although the voltage Vgb is expected to have a substantially constant voltage value over a wide temperature range, it has some temperature dependence.

[0049] The operational amplifier 211 and the gain variable circuit 212 form a non-inverting amplifier, and the gain of this non-inverting amplifier is represented by the symbol "AF". The gain AF can be changed by the gain variable circuit 212. The reference voltage Vref is output from the output terminal of the operational amplifier 211. Specifically, the gain variable circuit 212 consists of a series circuit of resistors 212a and 212b which are voltage dividing resistors. The first end of the resistor 212a is connected to the output terminal of the operational amplifier 211, the second end of the resistor 212a and the first end of the resistor 212b are commonly connected to the inverting input terminal of the operational amplifier 211, and the second end of the resistor 212b is connected to the ground. Since the operational amplifier 211 operates to make the potential difference between its non-inverting input terminal and inverting input terminal approach zero, the reference voltage Vref corresponding to the voltage Vgb and the resistance value ratio between the resistors 212a and 212b is output from the output terminal of the operational amplifier 211. The reference voltage Vref is supplied to the voltage monitoring circuit 150.

[0050] Let the resistance value of the resistor 212a be represented by the symbol "R1", and the resistance value of the resistor 212b be represented by the symbol "R2". Then, the gain AF is expressed as "AF=(R1 + R2) / R2", and the reference voltage Vref is expressed as "Vref = Vbg×(R1 + R2) / R2 = Vbg×AF". In the reference voltage generation circuit 210, the gain variable circuit 212 functions as an adjustment circuit ADJ (see Fig. 2).

[0051] The state of the amplification factor variable circuit 212 is set to any one of the first to nth adjustment states (see FIG. 3), and the resistance value ratio between the resistors 212a and 212b is different between the ith adjustment state and the jth adjustment state (where i and j here represent different natural numbers less than or equal to n). Here, for any natural number i, it is assumed that the amplification factor AF in the (i + 1)th adjustment state is larger than the amplification factor AF in the ith adjustment state.

[0052] In the actual operation, the actual use calibration data Crd from the actual use calibration data setting unit 120 is supplied to the amplification factor variable circuit 212, and based on the actual use calibration data Crd, the state of the amplification factor variable circuit 212 is set to any one of the first to nth adjustment states. Thereby, the amplification factor AF is adjusted and determined based on the actual use calibration data Crd, and as a result, the reference voltage Vref is adjusted.

[0053] FIG. 12 is a flowchart of the shipment calibration process according to the first embodiment. The block diagram of the part related to the shipment calibration process is as shown in FIG. 6, but in the first embodiment, the target signal generation circuit 140 in FIG. 6 is the reference voltage generation circuit 210. In the first embodiment, since the target temperature TMP is classified into four temperature ranges by the temperature detection circuit 130A, “m = 4”.

[0054] The shipment calibration process according to the first embodiment consists of the processes of steps S111 to S115. Steps S111 to S115 correspond to steps S11 to S15 in FIG. 5. In the shipment calibration process according to the first embodiment, first, in step S111, 1 is assigned to the variable i managed by the shipment inspection device AA. In the subsequent step S112, the shipment inspection device AA acquires the reference voltage Vref in the ith evaluation state from the reference voltage generation circuit 210 and measures the acquired reference voltage Vref. The value of the measured reference voltage Vref is referred to as the measured voltage value Vms[i].

[0055] The i-th evaluation state is a state in which the target temperature TMP is set to a predetermined evaluation temperature Tmp[i] and the state of the amplification factor variable circuit 212 is set to the reference adjustment state. That is, in step S112, the environment around the semiconductor device 10 is adjusted by the shipping inspector so that the target temperature TMP becomes the predetermined evaluation temperature Tmp[i]. Under this environment, the shipping inspection device AA sets the state of the amplification factor variable circuit 212 to the reference adjustment state and then operates the reference voltage generation circuit 210 to obtain and measure the reference voltage Vref from the reference voltage generation circuit 210. When the state of the amplification factor variable circuit 212 is set to the reference adjustment state, the amplification factor AF is fixed at the reference amplification factor AF O therein.

[0056] Here, the evaluation temperature Tmp[i] belongs to the temperature range RNG[i]. More specifically, the evaluation temperature Tmp[1] is lower than the boundary temperature Tmp_b1 (see FIG. 9). Typically, for example, the exactly intermediate temperature between the target temperature TMP when the semiconductor device 10 operates at the lower limit of the specified operating temperature range and the boundary temperature Tmp_b1 may be set as the evaluation temperature Tmp[1]. The evaluation temperature Tmp[2] is higher than the boundary temperature Tmp_b1 and lower than the boundary temperature Tmp_b2. Typically, for example, the exactly intermediate temperature between the boundary temperature Tmp_b1 and the boundary temperature Tmp_b2 may be set as the evaluation temperature Tmp[2]. The evaluation temperature Tmp[3] is higher than the boundary temperature Tmp_b2 and lower than the boundary temperature Tmp_b3. Typically, for example, the exactly intermediate temperature between the boundary temperature Tmp_b2 and the boundary temperature Tmp_b3 may be set as the evaluation temperature Tmp[3]. The evaluation temperature Tmp[4] is higher than the boundary temperature Tmp_b3. Typically, for example, the exactly intermediate temperature between the target temperature TMP when the semiconductor device 10 operates at the upper limit of the specified operating temperature range and the boundary temperature Tmp_b3 may be set as the evaluation temperature Tmp[4].

[0057] In step S113 following step S112, the shipping inspection device AA determines the ith calibration data based on the measured voltage value Vms[i] acquired under the ith evaluation state, and writes the determined ith calibration data in a non-volatile manner to the calibration data storage unit 111. In the following step S114, the shipping inspection device AA checks whether the variable i has reached the value of "m=4". If the variable i has not reached the value of "m=4", "1" is added to the variable i in step S115, and the process returns to step S112, and the processes of steps S112 and S113 are repeated. If the variable i has reached the value of "m=4", the shipping calibration process is completed.

[0058] As a result, the processing of steps S112 and S113 is executed for each integer i that satisfies "1≦i≦m=4", and at the end of the shipment calibration process, the first through mth calibration data (i.e., the first through fourth calibration data) are written and stored in the calibration data storage unit 111.

[0059] The target voltage V is calculated based on the reference voltage Vref. TG In step S113, the shipping inspection device AA compares the measured voltage value Vms[i] with the target voltage value V TG When the target temperature TMP coincides with the evaluation temperature Tmp[i], the reference voltage Vref is set to the target voltage V TG The gain AF for matching with the standard gain AF O Then, the calibration data for providing the specified amplification factor AF to the non-inverting amplifier consisting of the operational amplifier 211 and the amplification factor variable circuit 212 is determined as the i-th calibration data. Then, in actual operation, if the i-th calibration data is used as the actual use calibration data Crd when the target temperature TMP actually coincides with the evaluation temperature Tmp[i], the value of the reference voltage Vref will be the target voltage value V TG In addition, in actual operation, when the target temperature TMP is close to the evaluation temperature Tmp[i], if the i-th calibration data is used as the actual use calibration data Crd, the value of the reference voltage Vref and the target voltage value V TG The error is sufficiently small.

[0060] For example, when the target voltage value V TG is 2.5V and the reference amplification factor AF O is 2.0 times, assume that the measured voltage value Vms[1] is 2.3V. In this case, the first calibration data for realizing the amplification factor AF of "2.0×2.5 / 2.3" is held in the holding unit 111. Then, when the target temperature TMP coincides with the evaluation temperature Tmp[1] in the actual operation, the first calibration data is used as the actually used calibration data Crd, and the amplification factor AF is set to "2.0×2.5 / 2.3". As a result, the value of the reference voltage Vref coincides with the target voltage value V TG . Similarly, for example, when the target voltage value V TG is 2.5V and the reference amplification factor AF O is 2.0 times, assume that the measured voltage value Vms[2] is 2.6V. In this case, the second calibration data for realizing the amplification factor AF of "2.0×2.5 / 2.6" is held in the holding unit 111. Then, when the target temperature TMP coincides with the evaluation temperature Tmp[2] in the actual operation, the second calibration data is used as the actually used calibration data Crd, and the amplification factor AF is set to "2.0×2.5 / 2.6". As a result, the value of the reference voltage Vref coincides with the target voltage value V TG . The same applies to the third and fourth calibration data.

[0061] In the actual operation, the actual use calibration data Crd is set based on the signals DET1 to DET3. Hereinafter, for convenience, the state in which all of the signals DET1 to DET3 are at the low level is referred to as the first detected temperature state, the state in which the signal DET1 is at the high level and the signals DET2 and DET3 are at the low level is referred to as the second detected temperature state, the state in which the signals DET1 and DET2 are at the high level and the signal DET3 is at the low level is referred to as the third detected temperature state, and the state in which all of the signals DET1 to DET3 are at the high level is referred to as the fourth detected temperature state. In the actual operation, the actual use calibration data setting unit 120 sets the first calibration data as the actual use calibration data Crd in the first detected temperature state, sets the second calibration data as the actual use calibration data Crd in the second detected temperature state, sets the third calibration data as the actual use calibration data Crd in the third detected temperature state, and sets the fourth calibration data as the actual use calibration data Crd in the fourth detected temperature state.

[0062] Therefore, in the actual operation, the amplification factor variable circuit 212 corresponding to the adjustment circuit ADJ adjusts the amplification factor AF using the first calibration data (therefore adjusts the reference voltage Vref) when the detected target temperature TMP belongs to the temperature range RNG[1], and adjusts the amplification factor AF using the second calibration data (therefore adjusts the reference voltage Vref) when the detected target temperature TMP belongs to the temperature range RNG[2]. The same applies when the detected target temperature TMP belongs to the temperature range RNG[3] or RNG[4].

[0063] In FIG. 13, the curve 610 by the broken line represents the same as the curve 610 by the solid line in FIG. 7. The curve 610 shows the temperature dependence of the reference voltage Vref (the dependence of the reference voltage Vref on the target temperature TMP) assuming that there is no adjustment by the adjustment circuit ADJ in the actual operation. More specifically, the curve 610 shows that the amplification factor AF is the reference amplification factor AF in the actual operation OShows the temperature dependence of the reference voltage Vref (the dependence of the reference voltage Vref on the target temperature TMP) when it is assumed to be fixed at []. A curve 620 by a solid line is also shown in FIG. 13. The curve 620 is the temperature dependence of the actual reference voltage Vref. That is, the curve 620 shows the temperature dependence of the reference voltage Vref (the dependence of the reference voltage Vref on the target temperature TMP) when the amplification factor AF is adjusted according to the detection results (signals DET1 to DET3) of the target temperature TMP in the actual operation. Since the amplification factor AF is adjusted using appropriate calibration data for each temperature range, the variation range of the reference voltage Vref is kept low over the entire temperature ranges RNG[1] to RNG[4]. This contributes to the improvement of the product value of the semiconductor device 10, or the manufacturing yield is expected to improve because the required accuracy is easily satisfied (because the probability that each manufactured semiconductor device 10 becomes a good product increases).

[0064] In the actual operation, when the actual use calibration data setting unit 120 changes the actual use calibration data Crd from the calibration data C A to the calibration data C B it executes a step change process. In the step change process, the actual use calibration data setting unit 120 changes the actual use calibration data Crd step by step towards the calibration data C A from the calibration data C B . The calibration data C A and C B are two of the first to fourth calibration levels. For example, the calibration data C A and C B are the first and second calibration data respectively when transitioning from the first detection temperature state to the second detection temperature state, and the calibration data C A and C B are the second and first calibration data respectively when transitioning from the second detection temperature state to the first detection temperature state. Similarly, the calibration data C A and C B are the second and third calibration data respectively when transitioning from the second detection temperature state to the third detection temperature state, and the calibration data C A and CB They are the third and second calibration data, respectively. The same applies to the transition between the third and fourth detected temperature states.

[0065] FIG. 14 shows waveforms of voltages Va and Vth1 to Vth3 and signals DET1 to DET3 in a temperature monotonically increasing case where the target temperature TMP monotonically increases from a sufficiently low temperature to a sufficiently high temperature, and a time-series change of the actual use calibration data Crd. In FIG. 14, C1d, C2d, C3d, and C4d represent the first, second, third, and fourth calibration data, respectively.

[0066] In the temperature monotonically increasing case, when transitioning from the first detected temperature state to the second detected temperature state (i.e., in response to the switching of the signal DET1 from the low level to the high level), the setting unit 120 performs a step change process of changing the actual use calibration data Crd by a predetermined step amount toward the second calibration data (C2d) every time a predetermined step time elapses from the first calibration data (C1d) until the actual use calibration data Crd reaches the second calibration data (C2d). Thereafter, when transitioning from the second detected temperature state to the third detected temperature state (i.e., in response to the switching of the signal DET2 from the low level to the high level), the setting unit 120 performs a step change process of changing the actual use calibration data Crd by a predetermined step amount toward the third calibration data (C3d) every time a predetermined step time elapses from the second calibration data (C2d) until the actual use calibration data Crd reaches the third calibration data (C3d). The same applies when transitioning from the third detected temperature state to the fourth detected temperature state.

[0067] Note that the actual use calibration data Crd is digital data of a predetermined number of bits (for example, 8 - bit or 12 - bit digital data). Assume that as the value of the actual use calibration data Crd increases, the amplification factor AF changes in the first direction, and as a result, the reference voltage Vref also changes in the first direction. Conversely, assume that as the value of the actual use calibration data Crd decreases, the amplification factor AF changes in the second direction, and as a result, the reference voltage Vref also changes in the second direction. The first direction and the second direction are opposite to each other. One of the first direction and the second direction is the increasing direction, and the other is the decreasing direction.

[0068] Therefore, in the actual operation, when “Crd = C A ”, the value of the reference voltage Vref is the voltage value V A ; and when “Crd = C B ”, the value of the reference voltage Vref is the voltage value V B . If this is the case, in the process where the actually used calibration data Crd changes step by step from the calibration data C A to the calibration data C B , the value of the reference voltage Vref changes step by step from the voltage value V A to the voltage value V B . By using the step change process, a sudden change in the reference voltage Vref is suppressed, and malfunctions of the subsequent circuits that may occur due to the sudden change can be avoided.

[0069] The voltage monitoring circuit 150 (Fig. 11) is connected to the reference voltage generation circuit 210 and the input terminal IN, and the reference voltage Vref and the input voltage Vin are supplied to the voltage monitoring circuit 150. In the actual operation, the voltage monitoring circuit 150 performs a voltage monitoring process to monitor the level of the input voltage Vin using the reference voltage Vref. In conjunction with the high accuracy of the reference voltage Vref being maintained over a wide temperature range, the monitoring accuracy of the input voltage Vin can be maintained high over a wide temperature range. The voltage monitoring process may be any of the above-mentioned upper limit monitoring process, lower limit monitoring process, and window monitoring process.

[0070] The voltage monitoring circuit 150 may use the reference voltage Vref itself as the upper limit voltage VH LIM or the lower limit voltage VL LIM to perform the voltage monitoring process. In this case, the voltage monitoring circuit 150 may compare the reference voltage Vref with the input voltage Vin using a comparator (not shown). Alternatively, the voltage monitoring circuit 150 may generate a divided voltage of the input voltage Vin and perform the voltage monitoring process by comparing the generated divided voltage with the reference voltage Vref.

[0071] An AD converter (not shown) that converts the input voltage Vin itself or the divided voltage of the input voltage Vin into a digital signal may be provided for the voltage monitoring circuit 150. Then, the voltage monitoring circuit 150 determines whether the value of the digital signal obtained by the conversion is higher than the upper limit value corresponding to the upper limit voltage VH LIM or lower than the lower limit value corresponding to the lower limit voltage VL LIM to realize the voltage monitoring process. At this time, the AD converter in the voltage monitoring circuit 150 performs the above conversion using the reference voltage Vref. For example, when a 12-bit AD converter is used as the AD converter in the voltage monitoring circuit 150 and the input voltage Vin itself is converted into a digital signal by the AD converter, the value of the digital signal obtained by the conversion is "4095×Vin / Vref".

[0072] Note that the configuration for adjusting the reference voltage Vref is not limited to the configuration shown in FIG. 11. That is, for example, a DA converter (digital / analog converter) that converts the actual use calibration data Crd into an analog voltage signal is provided in the reference voltage generation circuit 210, and the reference voltage Vref may be adjusted by adjusting the potential of the non-inverting input terminal or the inverting input terminal of the operational amplifier 211 using the obtained voltage signal. In addition, any configuration that can adjust the reference voltage Vref according to the actual use calibration data Crd is acceptable.

[0073] <<Second Embodiment>> The second embodiment will be described. The adjustment technique for the voltage signal shown in the first embodiment can be applied to a current signal, and an embodiment in which the adjustment technique is applied to a current signal will be described as the second embodiment. That is, the target signal according to the second embodiment is a current signal. Therefore, in the second embodiment, the value of the target signal is a current value, and the current having the value of the target signal is referred to as a reference current Iref (target current).

[0074] It is assumed that the temperature detection circuit 130A in FIG. 8 is also used in the second embodiment. As shown in the first embodiment, the temperature detection circuit 130A detects which of the temperature ranges RNG[1] to RNG[4] the target temperature TMP belongs to (see FIG. 9).

[0075] Fig. 15 shows the configuration of the reference current generation circuit 230 together with the peripheral circuits. The reference current generation circuit 230 corresponds to the target signal generation circuit 140 according to the second embodiment, and the reference current Iref generated by the reference current generation circuit 230 corresponds to the target signal according to the second embodiment. Any one or each of the currents Ib, Ic, Id, and Ie shown in Fig. 15 corresponds to the reference current Iref. The reference current generation circuit 230 includes a DA converter 231, an operational amplifier 232, a transistor 233, a resistor 234, and a current mirror circuit 235. The current mirror circuit 235 consists of transistors 235a to 235e. Nodes 236b to 236e are internal nodes provided in the semiconductor device 10. The transistor 233 is an N-channel MOSFET. The transistors 235a to 235e are each a P-channel MOSFET.

[0076] The DA converter 231 performs DA conversion. In DA conversion, the DA converter 231 converts the actual use calibration data Crd supplied from the actual use calibration data setting unit 120 into a voltage DACout which is an analog signal. The DA conversion in the DA converter 231 is performed using a reference voltage Vref. The reference voltage Vref here may be the reference voltage Vref shown in the first embodiment. However, any DC voltage generated within the semiconductor device 10 may be the reference voltage Vref for the DA converter 231. The DA converter 231 uses the reference voltage Vref as a full scale, and generates a voltage DACout obtained by multiplying the reference voltage Vref by a coefficient of 1 or less according to the actual use calibration data Crd. The voltage DACout is proportional to the value of the actual use calibration data Crd with a positive proportionality coefficient. For example, when the actual use calibration data Crd is 12-bit digital data (i.e., the actual use calibration data Crd has an integer value of 0 or more and 4095 or less) and a 12-bit DA converter is used as the DA converter 231, the voltage DACout is represented by "DACout = Vref × Crd / 4095".

[0077] The voltage DACout is supplied to the non-inverting input terminal of the operational amplifier 232. The output terminal of the operational amplifier 232 is connected to the gate of the transistor 233. The source of the transistor 233 is connected to the inverting input terminal of the operational amplifier 232 and the first end of the resistor 234. The second end of the resistor 234 is connected to the ground.

[0078] The drain of the transistor 233 is connected to the drain and gate of the transistor 235a and to the gates of the transistors 235b to 235e. The sources of the transistors 235a to 235e are connected to the applied end of the power supply voltage VDD to receive the supply of the power supply voltage VDD. The drains of the transistors 235b to 235e are connected to the nodes 236b to 236e, respectively.

[0079] The drain current of the transistor 233 is equal to the drain current of the transistor 235a. The drain current of the transistor 233 or 235a is represented by the symbol "Ia". The drain currents of the transistors 235b, 235c, 235d, 235e are represented by the symbols "Ib", "Ic", "Id", "Ie", respectively. The drain current Ib of the transistor 235b is supplied to a subsequent stage circuit (not shown) that is connected to the node 236b and performs an operation according to the drain current Ib. The drain current Ic of the transistor 235c is supplied to a subsequent stage circuit (not shown) that is connected to the node 236c and performs an operation according to the drain current Ic. The same applies to the drain currents Id and Ie.

[0080] The operational amplifier 232 controls the gate potential of the transistor 233 such that the voltage generated across both ends of the resistor 234 matches the voltage DACout. The voltage generated across both ends of the resistor 234 is the voltage drop generated across the resistor 234 due to the current Ia flowing through the resistor 234, and is represented by the product of the value of the resistor 234 and the value of the current Ia. When the value of the resistor 234 is represented as "R234", "Ia = DACout / R234" holds. The current mirror circuit 235 generates currents Ib to Ie proportional to the current Ia. Therefore, when the value of the actual use calibration data Crd increases, the currents Ia to Ie increase along with the increase in the voltage DACout, and when the value of the actual use calibration data Crd decreases, the currents Ia to Ie decrease along with the decrease in the voltage DACout.

[0081] That is, the currents Ia to Ie can be adjusted through the adjustment of the actual use calibration data Crd, and in the reference current generation circuit 230, the DA converter 231 functions as an adjustment circuit ADJ (see FIG. 2). It can be considered that the state of the DA converter 231 is set to any one of the first to nth adjustment states (see FIG. 3), and at this time, the value of n matches the total number of values that the actual use calibration data Crd can take. That is, for example, if the actual use calibration data Crd is 12-bit digital data, then "n = 2 12 = 4096". The value of the actual use calibration data Crd in the ith adjustment state can be considered to be "i - 1".

[0082] FIG. 16 is a flowchart of the shipment calibration process according to the second embodiment. The block diagram of the part related to the shipment calibration process is as shown in FIG. 6, but in the second embodiment, the target signal generation circuit 140 in FIG. 6 is the reference current generation circuit 230. In the second embodiment, since the target temperature TMP is classified into four temperature ranges by the temperature detection circuit 130A, "m = 4". Hereinafter, for the sake of simplicity of explanation, unless otherwise specified, it is considered that only the current Ib is the reference current Iref.

[0083] The calibration process at the time of shipment according to the second embodiment consists of the processes of steps S211 to S215. Steps S211 to S215 correspond to steps S11 to S15 in FIG. 5. In the calibration process at the time of shipment according to the second embodiment, first, in step S211, 1 is assigned to the variable i managed by the shipment inspection device AA. In the subsequent step S212, the shipment inspection device AA acquires the reference current Iref in the i-th evaluation state from the reference current generation circuit 230 and measures the acquired reference current Iref. The value of the measured reference current Iref is referred to as the measured current value Ims[i].

[0084] The i-th evaluation state is a state in which the target temperature TMP is set to a predetermined evaluation temperature Tmp[i] and the state of the DA converter 231 is set to the reference adjustment state. In the reference adjustment state, the reference data Crd O fixed to the DA converter 231 is supplied as the actual use calibration data Crd. Therefore, the voltage DACout has a value proportional to each value of the reference voltage Vref and the reference data Crd O . In step S212, the environment around the semiconductor device 10 is adjusted by the shipment inspector so that the target temperature TMP becomes the predetermined evaluation temperature Tmp[i]. Under that environment, the shipment inspection device AA sets the state of the DA converter 231 to the reference adjustment state and then operates the reference current generation circuit 230 to acquire and measure the reference current Iref from the reference current generation circuit 230. The meaning of the evaluation temperature Tmp[i] is as shown in the first embodiment.

[0085] In step S213 following step S212, the shipment inspection device AA determines the i-th calibration data based on the measured current value Ims[i] acquired in the i-th evaluation state, and writes the determined i-th calibration data to the calibration data holding unit 111 in a non-volatile manner. In the subsequent step S214, the shipment inspection device AA checks whether the variable i has reached the value of "m = 4". If the variable i has not reached the value of "m = 4", then in step S215, "1" is added to the variable i and then the process returns to step S212, and the processes of steps S212 and S213 are repeated. If the variable i has reached the value of "m = 4", then the calibration process at the time of shipment is terminated.

[0086] As a result, for each integer i satisfying “1 ≦ i ≦ m = 4”, the processes of steps S212 and S213 are executed. By the time the shipment calibration process is completed, the first to mth calibration data (i.e., the first to fourth calibration data) are written and held in the calibration data holding unit 111.

[0087] A target current value I is defined with respect to the value of the reference current Iref. TG In step S213, the shipment inspection device AA determines the actual use calibration data Crd for making the value of the reference current Iref coincide with the target current value I based on the ratio between the measured current value Ims[i] and the target current value I. TG When the target temperature TMP coincides with the evaluation temperature Tmp[i], the actual use calibration data Crd is specified with reference to the reference data Crd. TG Then, the specified actual use calibration data Crd is determined as the ith calibration data. Then, in the actual operation, if the ith calibration data is used as the actual use calibration data Crd when the target temperature TMP actually coincides with the evaluation temperature Tmp[i], the value of the reference current Iref coincides with the target current value I. O Also, in the actual operation, when the target temperature TMP is close to the evaluation temperature Tmp[i], if the ith calibration data is used as the actual use calibration data Crd, the error between the value of the reference current Iref and the target current value I becomes sufficiently small. TG For example, when the target current value I is 10 μA (microampere), assume that the measured current value Ims[1] is 9.5 μA. In this case, the value of “Crd × 10 / 9.5” is set as the first calibration data and held in the holding unit 111. Then, in the actual operation, when the target temperature TMP coincides with the evaluation temperature Tmp[1], by using the first calibration data as the actual use calibration data Crd, the value of the reference current Iref coincides with the target current value I. TG Similarly, for example, when the target current value I is 10 μA, assume that the measured current value Ims[2] is 10.5 μA. In this case, “Crd

[0088] For example, when the target current value I TG is 10 μA (microampere), assume that the measured current value Ims[1] is 9.5 μA. In this case, the value of “Crd O × 10 / 9.5” is set as the first calibration data and held in the holding unit 111. Then, in the actual operation, when the target temperature TMP coincides with the evaluation temperature Tmp[1], by using the first calibration data as the actual use calibration data Crd, the value of the reference current Iref coincides with the target current value I. TG Similarly, for example, when the target current value I TG is 10 μA, assume that the measured current value Ims[2] is 10.5 μA. In this case, “CrdO Set the value of ×10 / 10.5” in the second calibration data and hold it in the holding unit 111. Then, when the target temperature TMP matches the evaluation temperature Tmp[2] in the actual operation, the second calibration data is used as the actual use calibration data Crd, and the value of the reference current Iref becomes the target current value I TG which is the same for the third and fourth calibration data.

[0089] In the actual operation, the actual use calibration data Crd is set based on the signals DET1 to DET3. The method of setting the actual use calibration data Crd based on the signals DET1 to DET3 is as described in the first embodiment. Therefore, in the actual operation, the DA converter 231 corresponding to the adjustment circuit ADJ adjusts the reference current Iref using the first calibration data when the detected target temperature TMP belongs to the temperature range RNG[1], and adjusts the reference current Iref using the second calibration data when the detected target temperature TMP belongs to the temperature range RNG[2]. The same applies when the detected target temperature TMP belongs to the temperature range RNG[3] or RNG[4]. As a result, similar to the first embodiment (see FIG. 13), the variation range of the reference current Iref is kept low over the entire temperature ranges RNG[1] to RNG[4]. This contributes to the improvement of the product value of the semiconductor device 10, or the manufacturing yield is expected to improve because the required accuracy is easily satisfied (the probability that each manufactured semiconductor device 10 becomes a good product increases).

[0090] In the actual operation, the actual use calibration data setting unit 120 can execute the step change process shown in the first embodiment. That is, the actual use calibration data setting unit 120 can change the actual use calibration data Crd step by step from the calibration data C A to the calibration data C B when switching, and can change the actual use calibration data Crd step by step from the calibration data C A to the calibration data C B toward the calibration data C A and C Bare two of the first to fourth calibration levels, for example, the first and second calibration data.

[0091] In the actual operation, when “Crd = C A ”, the value of the reference current Iref is the current value I A and when “Crd = C B ”, the value of the reference current Iref is the current value I B Assuming this is the case, in the process where the actual use calibration data Crd changes step by step from the calibration data C A to the calibration data C B in the step change process, the value of the reference current Iref changes step by step from the current value I A to the current value I B By using the step change process, a sudden change in the reference current Iref is suppressed, and malfunctions of the subsequent circuit that may occur due to the sudden change can be avoided.

[0092] Note that the configuration for adjusting the reference current Iref is not limited to the configuration shown in FIG. 15. That is, for example, a fixed voltage may be supplied to the non-inverting input terminal of the operational amplifier 232, and the resistor 234 may be configured as a variable resistor, and the reference current Iref may be adjusted by adjusting the value of the resistor 234 according to the actual use calibration data Crd. In addition, any configuration that can adjust the reference current Iref according to the actual use calibration data Crd is acceptable.

[0093] <<Third Embodiment>> The third embodiment will be described. The semiconductor device 10 may be provided with a plurality of input terminals IN. That is, in the semiconductor device 10, a plurality of input terminals IN may be provided for multiple channels. In this case, an input voltage Vin is input from the signal source SS to each of the plurality of input terminals IN. The signal source SS may be composed of a plurality of signal sources. In the third embodiment, it is assumed that the semiconductor device 10 is provided with a plurality of input terminals IN. When the first embodiment and the third embodiment are combined, the voltage monitoring circuit 150 of FIG. 11 is provided for each channel (that is, for each input terminal IN), and the level of the input voltage Vin is monitored by the voltage monitoring circuit 150 for each channel using the reference voltage Vref.

[0094] <<Fourth Embodiment>> The fourth embodiment will be described. In the fourth embodiment, some modification techniques and supplementary matters for each of the above matters will be described.

[0095] The temperature detection circuit 130 classifies and detects the target temperature TMP in m levels. In the first and second embodiments, it is assumed that "m = 4" for the sake of concreteness of the description, but the value of m can be arbitrary as long as it is 2 or more.

[0096] In the first embodiment, the reference voltage Vref is used for voltage monitoring purposes with respect to the input voltage Vin, but the reference voltage Vref of the first embodiment can be used for any application that requires a stable voltage value over a wide temperature range. Similarly, the reference current Iref of the second embodiment can be used for any application that requires a stable current value over a wide temperature range.

[0097] Regarding any signal or voltage, the relationship between their high level and low level can be reversed in a form that does not impair the above-mentioned main idea.

[0098] The type of the channel of the FET (field effect transistor) shown in the above embodiment is an example. In a form that does not impair the above-mentioned main idea, the type of the channel of any FET can be changed between P-channel type and N-channel type.

[0099] Unless there is any inconvenience, any of the above transistors may be any type of transistor. For example, any transistor described as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor as long as there is no inconvenience. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is a drain and the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a base.

[0100] Embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and of course, they can be changed to various numerical values.

[0101] [[Appendix]] An appendix is provided for the present disclosure in which specific configuration examples are shown in the above embodiments.

[0102] A semiconductor device (10) according to one aspect of the present disclosure includes a target signal generation circuit (140) configured to generate a target signal, a temperature detection circuit (130) configured to detect a target temperature (TMP) in the semiconductor device, and a memory (110) configured to hold a plurality of calibration data. The target signal generation circuit has an adjustment circuit (ADJ) configured to adjust the target signal by selectively using any of the plurality of correction data based on a detection result (DET) of the temperature detection circuit (a first configuration).

[0103] As a result, a target signal that is less likely to vary with temperature changes can be generated over a wide temperature range.

[0104] In the semiconductor device according to the first configuration, the plurality of calibration data includes first calibration data and second calibration data, and the adjustment circuit adjusts the target signal using the first calibration data when the target temperature belongs to a first temperature range, and adjusts the target signal using the second calibration data when the target temperature belongs to a second temperature range (second configuration).

[0105] In the semiconductor device according to the second configuration, when the adjustment circuit switches the calibration data used for adjusting the target signal from the first calibration data to the second calibration data, the adjustment circuit may be configured to gradually change the calibration data used for adjusting the target signal from the first calibration data to the second calibration data (third configuration).

[0106] As a result, a sudden change in the target signal can be suppressed.

[0107] In the semiconductor device according to the second or third configuration, the first calibration data is determined based on the measurement result of the target signal in a first evaluation state where the target temperature belongs to the first temperature range, and the second calibration data is determined based on the measurement result of the target signal in a second evaluation state where the target temperature belongs to the second temperature range (fourth configuration).

[0108] In the semiconductor device according to any one of the first to fourth configurations, the target signal generation circuit may be a reference voltage generation circuit (210) that generates a reference voltage (Vref) as the target signal (fifth configuration).

[0109] As a result, a reference voltage that is less likely to vary with temperature changes can be generated over a wide temperature range. That is, the accuracy of the reference voltage can be maintained high over a wide temperature range.

[0110] In the semiconductor device according to the fifth configuration, it may further include an input terminal (IN) and a voltage monitoring circuit (150) configured to monitor the level of an input voltage (Vin) supplied to the input terminal using the reference voltage (a sixth configuration).

[0111] Since the accuracy of the reference voltage can be maintained high over a wide temperature range, the monitoring accuracy of the input voltage can be maintained high over a wide temperature range.

[0112] In the semiconductor device according to any one of the first to fourth configurations, the target signal generation circuit may be a reference current generation circuit (230) that generates a reference current (Iref) as the target signal (a seventh configuration).

Explanation of Reference Signs

[0113] 1 System 10 Semiconductor device 20 Higher-level device 30 Bus SS Signal source IN Input terminal Vin Input voltage 110 Memory 111 Calibration data holding unit 120 In-use calibration data setting unit 130 Temperature detection circuit 140 Target signal generation circuit ADJ Adjustment circuit DET Temperature detection signal Crd In-use calibration data AA Shipping inspection device 130A Temperature detection circuit 131 Diode 132 Constant current source CMP1~CMP3 Comparator Icnst Constant current Va Voltage Vth1~Vth3 Threshold voltage DET1~DET3 Signals 210 Reference voltage generation circuit 211 Operational amplifier 212 Amplification Rate Variable Circuit 212a, 212b Resistors Vref Reference Voltage 230 Reference Current Generation Circuit 231 DA Converter 232 Operational Amplifier 233, 235a - 235e Transistors 234 Resistor 235 Current Mirror Circuit Iref Reference Current

Claims

1. In a semiconductor device, a target signal generation circuit configured to generate a target signal; a temperature detection circuit configured to detect a target temperature in the semiconductor device; a memory configured to hold a plurality of calibration data; and the target signal generation circuit has an adjustment circuit configured to selectively use any one of the plurality of correction data to adjust the target signal based on a detection result of the temperature detection circuit , a semiconductor device.

2. The plurality of calibration data includes first calibration data and second calibration data, and the adjustment circuit adjusts the target signal using the first calibration data when the target temperature belongs to a first temperature range, and adjusts the target signal using the second calibration data when the target temperature belongs to a second temperature range , the semiconductor device according to Claim 1.

3. When the adjustment circuit switches the calibration data used for adjusting the target signal from the first calibration data to the second calibration data, the adjustment circuit gradually changes the calibration data used for adjusting the target signal from the first calibration data to the second calibration data , the semiconductor device according to Claim 2.

4. The first calibration data is determined based on a measurement result of the target signal in a first evaluation state where the target temperature belongs to the first temperature range, and the second calibration data is determined based on a measurement result of the target signal in a second evaluation state where the target temperature belongs to the second temperature range , the semiconductor device according to Claim 2.

5. The target signal generation circuit is a reference voltage generation circuit that generates a reference voltage as the target signal , the semiconductor device according to any one of Claims 1 to 4.

6. an input terminal; and a voltage monitoring circuit configured to monitor a level of an input voltage supplied to the input terminal using the reference voltage , the semiconductor device according to Claim 5.

7. The target signal generation circuit is a reference current generation circuit that generates a reference current as the target signal , the semiconductor device according to any one of Claims 1 to 4.

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