Imaging apparatus, imaging method, and computer program

Abstract

To correct image quality reduction caused by noise generated by batch drive control.SOLUTION: A pixel 12 has a photoelectric conversion unit PD that generates electric charges by photoelectric conversion, at least two electric charge holding units MEM that hold the electric charges, transfer transistors M1L, M1S, M3L, M3S that transfer electric charges from the photoelectric conversion unit to the at least two electric charge holding units, an electric charge discharge transistor M7 that discharges electric charges accumulated in the photoelectric conversion unit, and two or more selection transistors M6, M10 that read out signals corresponding to the amount of electric charge transferred from the at least two electric charge holding units. A batch drive control that simultaneously drives a plurality of pixels for at least one of the transfer transistor and the electric charge discharge transistor is performed. At the same time, a video signal based on the electric charge generated by the photoelectric conversion unit and a correction signal that is not based on the electric charge generated by the photoelectric conversion unit are read simultaneously from two or more reading units. Thereby, correction processing is performed for noises generated from the video signal by the batch drive control using the correction signals.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to an imaging device, an imaging method, a computer program, and the like.

Background Art

[0002] Among so-called CMOS sensors, there is a GS sensor having a memory section in each pixel, that is, having a global shutter (hereinafter referred to as GS) function. That is, a pixel of the GS sensor includes a gate for transferring signal charges accumulated in a photoelectric conversion section to a charge holding section, and by transferring all pixels from the photoelectric conversion section to the charge holding section simultaneously, the timing of the start and end of signal accumulation in the photoelectric conversion section can be made the same for all pixels.

[0003] In addition, by having a plurality of charge holding sections for one photoelectric conversion section and transferring signal charges to each charge holding section a plurality of times within one frame, signal charges with different accumulation times can be held in each charge holding section, and images with different dynamic ranges can be acquired. In addition, by synthesizing them, a single image with a high dynamic range can be obtained. Patent Document 1 describes the configuration of such GS pixels.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] On the other hand, Patent Document 2 describes a configuration that performs batch transfer driving for reading out by collectively transferring pixel signals of a plurality of rows by charge transfer for controlling an exposure period, and batch reset driving for a plurality of rows. However, since a plurality of rows are transferred collectively, there is a possibility that the potential of the wiring for batch transfer driving or the wiring for batch reset driving changes during the reading of the pixel signal.

[0006] As a result, due to capacitive coupling between the wiring for batch transfer driving or the wiring for batch reset driving and other wirings, for example, potential fluctuations are propagated to pixel readout lines, power supply lines, etc., and noise is generated in the pixel signals of the row being read at that time. This becomes a factor of horizontal lines and degrades the image quality.

[0007] An object of the present invention is to provide an imaging device capable of correcting a degradation in image quality caused by noise generated by batch driving control.

Means for Solving the Problems

[0008] The imaging device according to one aspect of the present specification is provided with a plurality of pixels, and each pixel has a photoelectric conversion unit that generates charges by photoelectric conversion, at least two charge holding units that hold the charges, a transfer unit that transfers the charges from the photoelectric conversion unit to at least two of the charge holding units respectively, a charge discharging unit that discharges the charges accumulated in the photoelectric conversion unit, two or more readout units that respectively read out signals corresponding to the amounts of the charges transferred from at least two of the charge holding units, and performs batch driving control for simultaneously driving at least one of the transfer unit and the charge discharging unit for the plurality of pixels, and a control unit that simultaneously reads out a video signal based on the charges generated in the photoelectric conversion unit and a correction signal not based on the charges generated in the photoelectric conversion unit from two or more of the readout units, and is characterized by having a correction unit that performs correction processing of noise generated by the batch driving control from the video signal using the correction signal.

Effects of the Invention

[0009] According to the present invention, it is possible to provide an imaging device capable of correcting image quality degradation caused by noise generated by batch drive control.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Best Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments. In each figure, the same members or elements are denoted by the same reference numerals, and redundant descriptions are omitted or simplified.

[0012] In addition, in each of the embodiments described below, an example of an imaging device is described as the photoelectric conversion device. However, the photoelectric conversion device may be, for example, a distance measuring device using TOF (Time Of Flight), a photometric device such as measurement of incident light amount, or the like, and includes these.

[0013] <Embodiment 1> Hereinafter, the photoelectric conversion device and its driving method according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 to 5. FIG. 1 is a circuit block diagram showing a schematic configuration example of the photoelectric conversion device according to Embodiment 1 of the present invention.

[0014] As shown in FIG. 1, the photoelectric conversion device 100 according to the present embodiment includes a pixel unit 10, a vertical scanning circuit 20, a reading circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a driving control circuit 60.

[0015] The pixel unit 10 is connected to the vertical scanning circuit 20 and the reading circuit 30. The reading circuit 30 is connected to the horizontal scanning circuit 40 and the output circuit 50. The driving control circuit 60 is connected to the vertical scanning circuit 20, the reading circuit 30, and the horizontal scanning circuit 40.

[0016] The pixel unit 10 is provided with a plurality of pixels 12 arranged in a matrix so as to form a plurality of rows and a plurality of columns. Each of the plurality of pixels 12 includes a photoelectric conversion unit composed of a photoelectric conversion element such as a photodiode. The photoelectric conversion unit generates charges by photoelectric conversion, and outputs a pixel signal corresponding to the amount of incident light.

[0017] The number of rows and columns of pixels arranged in the pixel section 10 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel section 10 may also be provided with optical black pixels in which the photoelectric conversion section is shielded, dummy pixels that do not output signals, and the like.

[0018] In each column of the pixel section 10, a vertical output line 16a and a vertical output line 16b are arranged extending in a second direction (the vertical direction in FIG. 1) that intersects the first direction (the horizontal direction in FIG. 1). Each of the vertical output line 16a and the vertical output line 16b is connected to a plurality of pixels 12 arranged in the second direction and serves as a common signal line for these plurality of pixels 12.

[0019] The second direction in which the vertical output line 16a and the vertical output line 16b extend is sometimes referred to as the column direction or the vertical direction. The vertical output line 16a and the vertical output line 16b are connected to the readout circuit 30.

[0020] The vertical scanning circuit 20 has a function of receiving a control signal from the drive control circuit 60, generating a control signal for driving the pixels 12, and outputting the control signal to the pixel section 10 via the control line 14. Logic circuits such as a shift register and an address decoder are used for the vertical scanning circuit 20.

[0021] The vertical scanning circuit 20 sequentially outputs control signals to the control lines 14 of each row and sequentially drives the plurality of pixels 12 in the pixel section 10 row by row. Signals read out from the plurality of pixels 12 row by row are input to the readout circuit 30 via the vertical output line 16a and the vertical output line 16b arranged in each column of the pixel section 10.

[0022] The readout circuit 30 has a function of performing predetermined processing on the signals read out from the pixels 12, such as signal processing such as amplification processing and addition processing. The readout circuit 30 may include a signal holding section, a column amplifier, a correlated double sampling (CDS) circuit, an addition circuit, and the like. Further, the readout circuit 30 may further include other processing circuits such as an A / D (analog / digital) conversion circuit as necessary.

[0023] The horizontal scanning circuit 40 receives a control signal from the drive control circuit 60, generates a control signal for sequentially transferring the signals processed by the readout circuit 30 to the output circuit 50 column by column, and has a function of outputting the signal to the readout circuit 30.

[0024] Logic circuits such as a shift register and an address decoder are used for the horizontal scanning circuit 40. The output circuit 50 is a circuit section configured from a buffer amplifier, a differential amplifier, etc., and amplifies and outputs the signals of the columns selected by the horizontal scanning circuit 40.

[0025] The output circuit 50 may further have a signal processing section that performs predetermined signal processing on the pixel signals, such as correction processing or HDR (High Dynamic Range) synthesis processing. In this embodiment, the output circuit 50 corrects the image quality degradation caused by the potential fluctuation accompanying the global electronic shutter operation.

[0026] The drive control circuit 60 supplies control signals for controlling the operations and timings of the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40. Note that at least a part of the control signals supplied to the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40 may be supplied from outside the photoelectric conversion device 100.

[0027] FIG. 2 is an equivalent circuit diagram showing a configuration example of pixels of the photoelectric conversion device according to Embodiment 1 of the present invention. As shown in FIG. 2, each pixel 12 has a photoelectric conversion section PD and transfer transistors M1L1, M1L2, M1S1, M1S2, M3L1, M3L2, M3S1, M3S2.

[0028] Furthermore, each pixel 12 further has reset transistors M4, M8, amplification transistors M5, M9, selection transistors M6, M10, and a charge discharge transistor M7. Here, the charge discharge transistor M7 functions as a charge discharge section that discharges the charges accumulated in the photoelectric conversion section.

[0029] The photoelectric conversion unit PD can be composed of a photoelectric conversion element, for example, a photodiode. Each transistor can be composed of an N-type MOS transistor when using, for example, electrons as signal charges. Note that each transistor does not necessarily have to be an N-type MOS transistor, and each transistor can be composed of a P-type MOS transistor and holes can be used as signal charges.

[0030] The anode of the photoelectric conversion unit PD is connected to the ground node, and the cathode is connected to the sources of the transfer transistors M1L1, M1L2, M1S1, M1S2 and the charge discharge transistor M7, respectively.

[0031] The drain of the transfer transistor M1L1 is connected to the source of the transfer transistor M3L1. The connection node between the drain of the transfer transistor M1L1 and the source of the transfer transistor M3L1 includes a capacitive component and functions as a charge holding part (charge holding part MEM_L1).

[0032] The drain of the transfer transistor M1L2 is connected to the source of the transfer transistor M3L2. The connection node between the drain of the transfer transistor M1L2 and the source of the transfer transistor M3L2 includes a capacitive component and functions as a charge holding part (charge holding part MEM_L2).

[0033] The drain of the transfer transistor M1S1 is connected to the source of the transfer transistor M3S1. The connection node between the drain of the transfer transistor M1S1 and the source of the transfer transistor M3S1 includes a capacitive component and functions as a charge holding part (charge holding part MEM_S1).

[0034] The drain of the transfer transistor M1S2 is connected to the source of the transfer transistor M3S2. The connection node between the drain of the transfer transistor M1S2 and the source of the transfer transistor M3S2 includes a capacitive component and functions as a charge holding part (charge holding part MEM_S2).

[0035] Here, the charge holding parts MEM_L1, MEM_L2, MEM_S1, and MEM_S2 function as at least two charge holding parts for holding charges from the photoelectric conversion part. Also, the transfer transistors M1L1, M1L2, M1S1, and M1S2 function as transfer parts for transferring charges from the photoelectric conversion part to at least two charge holding parts respectively.

[0036] The drains of the transfer transistors M3L1 and M3L2 are each connected to the source of the reset transistor M4 and the gate of the amplification transistor M5. Also, the drains of the transfer transistors M3S1 and M3S2 are each connected to the source of the reset transistor M8 and the gate of the amplification transistor M9.

[0037] The connection nodes of the drains of the transfer transistors M3L1, M3L2, M3S1, and M3S2, the sources of the reset transistors M4 and M8, and the gates of the amplification transistors M5 and M9 constitute a so-called floating diffusion part FD (floating diffusion part). The floating diffusion part FD includes a capacitance component (floating diffusion capacitance) and has a function as a charge holding part.

[0038] The drains of the reset transistors M4 and M8, the drains of the amplification transistors M5 and M9, and the drain of the charge discharge transistor M7 are connected to the power supply voltage line (voltage VDD). Note that the voltages supplied to the drains of the reset transistors M4 and M8, the voltages supplied to the drains of the amplification transistors M5 and M9, and the voltage supplied to the drain of the charge discharge transistor M7 may be the same for any two or three of them, or all may be different.

[0039] The source of the amplification transistor M5 is connected to the drain of the selection transistor M6, and the source of the amplification transistor M9 is connected to the drain of the selection transistor M10. The source of the selection transistor M6 is connected to the vertical output line 16a, and the source of the selection transistor M10 is connected to the vertical output line 16b.

[0040] Here, the selection transistors M6 and M10 function as two or more readout units that respectively read out signals corresponding to the amounts of charges transferred from at least two of the charge holding units.

[0041] Each of the control lines 14 includes 13 signal lines. Further, each of the 13 signal lines is connected to the gates of transfer transistors M1L1, M1L2, M1S1, M1S2, M3L1, M3L2, M3S1, M3S2, reset transistors M4, M8, selection transistors M6, M10, and charge discharge transistor M7.

[0042] A control signal GS_L1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1L1. A control signal GS_L2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1L2.

[0043] A control signal GS_S1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1S1. A control signal GS_S2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1S2.

[0044] A control signal TX_L1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3L1. A control signal TX_L2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3L2.

[0045] A control signal TX_S1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3S1. A control signal TX_S2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3S2.

[0046] A control signal RES_L is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M4. A control signal RES_S is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M8.

[0047] A control signal SEL_L is output from the vertical scanning circuit 20 to a signal line connected to the gate of the selection transistor M6. A control signal SEL_S is output from the vertical scanning circuit 20 to a signal line connected to the gate of the selection transistor M10. A control signal OFG is output from the vertical scanning circuit 20 to a signal line connected to the gate of the charge discharge transistor M7.

[0048] When each transistor is composed of an N-type transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns on, and when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns off.

[0049] The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the light amount (photoelectric conversion) and accumulates the generated charge.

[0050] The transfer transistor M1L1 functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_L1 when it is turned on. The transfer transistor M3L1 functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_L1 to the floating diffusion unit FD when it is turned on.

[0051] The transfer transistor M1L2 functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_L2 when it is turned on. The transfer transistor M3L2 functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_L2 to the floating diffusion unit FD when it is turned on.

[0052] The transfer transistor M1S1 functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_S1 when it is turned on. The transfer transistor M3S1 functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_S1 to the floating diffusion unit FD when it is turned on.

[0053] The transfer transistor M1S2 functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_S2 when it is turned on. The transfer transistor M3S2 functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_S2 to the floating diffusion unit FD when it is turned on.

[0054] The amplifier transistors M5 and M9 are each configured such that a voltage VDD is supplied to the drain and a bias current is supplied from a current source (not shown) to the source via the selection transistors M6 or M10. Also, the amplifier transistors M5 and M9 constitute an amplification unit (source follower circuit) having the gate as the input node.

[0055] Thereby, the amplifier transistor M5 outputs a signal corresponding to the potential of the floating diffusion unit FD to the vertical output line 16 via the selection transistor M6. Also, the amplifier transistor M9 outputs a signal corresponding to the potential of the floating diffusion unit FD to the vertical output line 17 via the selection transistor M10. Further, the floating diffusion unit FD, the amplifier transistors M5 and M9, and the selection transistors M6 and M10 constitute an output unit that outputs a signal corresponding to the amount of charge held by the floating diffusion unit FD.

[0056] Note that in FIG. 2, a configuration is shown in which two transfer units (transfer transistors M3L1 and M3L2) share one floating diffusion unit FD or output unit, but any configuration may be adopted as long as signals based on charges transferred from two or more transfer units simultaneously are output to the vertical output line.

[0057] Similarly, although the configuration shows that two transfer units (transfer transistors M3S1 and M3S2) share one floating diffusion unit FD or the output unit, it suffices that the configuration is such that signals based on charges transferred from two or more transfer units are output to the vertical output lines.

[0058] The reset transistors M4 and M8 function as a reset unit that performs a reset operation to reset the floating diffusion unit FD to a voltage corresponding to the voltage VDD when turned on. The charge discharge transistor M7 functions as an overflow drain unit that discharges the charges held by the photoelectric conversion unit PD when turned on.

[0059] It can also be said that the charge discharge transistor M7 functions as a reset unit that performs a reset operation to reset the photoelectric conversion unit PD to a voltage corresponding to the voltage VDD when turned on.

[0060] The selection transistors M6 and M10 function as a selection unit that selects whether to output a signal corresponding to the source voltage of the amplification transistors M5 or M9 as a pixel signal to the vertical output lines 16a and 16b.

[0061] Next, a basic driving method of the photoelectric conversion device according to the present embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a timing diagram showing an example of a basic driving method regarding the exposure time of the photoelectric conversion device according to Embodiment 1 of the present invention.

[0062] FIG. 3 shows an example of the time change of the control signals GS_L1, GS_L2, GS_S1, GS_S2, and OFG supplied to the transfer transistors M1L1, M1L2, M1S1, M1S2, and the charge discharge transistor M7 in the (2N - 1)th frame and the 2Nth frame.

[0063] Here, N is an integer of 1 or more. When each control signal is at a high level, the corresponding transistor becomes active (on state). In addition, in this embodiment, since the global shutter method is used for driving, the driving related to the exposure operation and its timing are the same for the pixels 12 in all rows.

[0064] In each frame, a plurality of accumulation periods Ts (Ks times) and a plurality of accumulation periods Tl (Kl times) are executed. The accumulation period Ts is a period for accumulating signal charges in the charge holding unit MEM_S1 or the charge holding unit MEM_S2, and the accumulation period Tl is a period for accumulating signal charges in the charge holding unit MEM_L1 or the charge holding unit MEM_L2.

[0065] Hereinafter, the operations of the i-th accumulation period Tsi and the (i + 1)-th accumulation period Tsi+1 among the Ks times, and the operations of the j-th accumulation period Tlj and the (j + 1)-th accumulation period Tlj+1 among the Kl times will be described with reference to FIG. 3.

[0066] Here, i is an integer of 1 or more and Ks - 2 or less. j is an integer of 1 or more and Kl - 1 or less. Note that the numbers of times Ks and Kl can be appropriately set according to the total accumulation time within one frame period, and the numbers of times Ks and Kl may be the same or different.

[0067] First, the exposure operation in the odd frames (the (2N - 1)-th frame) will be described. In the odd frames, the signal charges generated in the photoelectric conversion unit PD are respectively accumulated in the charge holding units MEM_L1 and MEM_S1, and signals based on the signal charges accumulated in the charge holding units MEM_L2 and MEM_S2 are read out.

[0068] Just before time t10, it is assumed that the control signal OFG is at a high level. The charge discharge transistor M7 is turned on by receiving the high-level control signal OFG, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0069] At time t10, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 turns off, and the reset state of the photoelectric conversion unit PD is released.

[0070] That is, the timing at which the control signal OFG transitions from a high level to a low level becomes the start time of the accumulation period Tsi in the photoelectric conversion unit PD. The signal charges generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharge transistor M7 is off are accumulated in the photoelectric conversion unit PD.

[0071] During the period from a predetermined timing after time t10 to time t11, the vertical scanning circuit 20 controls the control signal GS_S1 to a high level. As a result, the transfer transistor M1S1 turns on, and the signal charges accumulated in the photoelectric conversion unit PD are transferred to the charge holding unit MEM_S1.

[0072] The time t11 when the transfer transistor M1S1 turns off becomes the end time of the accumulation period Tsi in the photoelectric conversion unit PD. That is, the period from time t10 to time t11 is the accumulation period Tsi of the signal charges.

[0073] After time t11, the vertical scanning circuit 20 controls the control signal OFG from a low level to a high level. As a result, the charge discharge transistor M7 turns on, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0074] At the subsequent time t12, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 turns off, and the reset state of the photoelectric conversion unit PD is released.

[0075] That is, the timing at which the control signal OFG transitions from a high level to a low level becomes the start time of the accumulation period Tlj in the photoelectric conversion unit PD. The signal charges generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharge transistor M7 is off are accumulated in the photoelectric conversion unit PD.

[0076] Here, the photoelectric conversion unit PD is reset by turning on the charge discharge transistor M7. However, in the case of a configuration that performs a complete transfer such that no signal charge remains in the photoelectric conversion unit PD during transfer, the reset of the photoelectric conversion unit PD by the charge discharge transistor M7 may be omitted.

[0077] In that case, the timing (time t11) at which the transfer transistor (here, the transfer transistor M1S1) turns off becomes the start time of the accumulation period Tlj in the photoelectric conversion unit PD. The same applies to the other accumulation periods Ts and Tl.

[0078] Furthermore, the complete transfer of the signal charge from the photoelectric conversion unit PD to the charge holding unit MEM can be realized by the potential design of the photoelectric conversion unit PD, the transfer transistor M1, the charge holding unit MEM, etc.

[0079] During the period from a predetermined timing after time t12 to time t13, the vertical scanning circuit 20 controls the control signal GS_L1 to a high level. As a result, the transfer transistor M1L1 turns on, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM_L1.

[0080] The time t13 at which the transfer transistor M1L1 turns off becomes the end time of the accumulation period Tlj in the photoelectric conversion unit PD. That is, the period from time t12 to time t13 is the accumulation period Tlj of the signal charge.

[0081] After this, the accumulation period Ts and the accumulation period Tl are repeated a predetermined number of times in the same manner as the driving during the period from time t10 to time t13. For example, as shown in FIG. 3, the accumulation period Tsi+1 is performed during the period from time t14 to time t15, the accumulation period Tlj+1 is performed during the period from time t16 to time t17, and the accumulation period Tsi+2 is performed starting from time t18.

[0082] In this way, in the odd frames, the accumulation period Ts is executed Ks times and the accumulation period Tl is executed Kl times. As a result, in the charge holding unit MEM_S1, the signal charges generated by the photoelectric conversion unit PD during the accumulation period Tshort with a length equal to the sum of the lengths of Ks periods from the accumulation period Ts1 to the accumulation period TsKs are held.

[0083] Also, in the charge holding unit MEM_L1, the signal charges generated by the photoelectric conversion unit PD during the accumulation period Tlong with a length equal to the sum of the lengths of Kl periods from the accumulation period Tl1 to the accumulation period TlKl are held.

[0084] Next, the exposure operation in the even frames (the 2Nth frames) will be described. In the even frames, the signal charges generated by the photoelectric conversion unit PD are accumulated in the charge holding units MEM_L2 and MEM_S2, while on the other hand, signals based on the signal charges accumulated in the charge holding units MEM_L1 and MEM_S1 are read out.

[0085] Just before time t20, it is assumed that the control signal OFG is at a high level. The charge discharge transistor M7 is turned on in response to the high-level control signal OFG, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0086] At time t20, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 is turned off, and the reset state of the photoelectric conversion unit PD is released.

[0087] That is, the timing at which the control signal OFG transitions from a high level to a low level is the start time of the accumulation period Tsi in the photoelectric conversion unit PD. The signal charges generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharge transistor M7 is off are accumulated in the photoelectric conversion unit PD.

[0088] In the period from a predetermined timing after time t20 to time t21, the vertical scanning circuit 20 controls the control signal GS_S2 to a high level. As a result, the transfer transistor M1S2 is turned on, and the signal charges accumulated in the photoelectric conversion unit PD are transferred to the charge holding unit MEM_S2.

[0089] The time t21 when the transfer transistor M1S2 turns off is the end time of the accumulation period Tsi in the photoelectric conversion unit PD. That is, the period from time t20 to time t21 is the accumulation period Tsi of the signal charges.

[0090] After time t21, the vertical scanning circuit 20 controls the control signal OFG from a low level to a high level. As a result, the charge discharge transistor M7 is turned on, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0091] At the subsequent time t22, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 is turned off, and the reset state of the photoelectric conversion unit PD is released.

[0092] That is, the timing at which the control signal OFG transitions from a high level to a low level is the start time of the accumulation period Tlj in the photoelectric conversion unit PD. The signal charges generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharge transistor M7 is off are accumulated in the photoelectric conversion unit PD.

[0093] In the period from a predetermined timing after time t22 to time t23, the vertical scanning circuit 20 controls the control signal GS_L2 to a high level. As a result, the transfer transistor M1L2 is turned on, and the signal charges accumulated in the photoelectric conversion unit PD are transferred to the charge holding unit MEM_L2.

[0094] The time t23 when the transfer transistor M1L2 turns off is the end time of the accumulation period Tlj in the photoelectric conversion unit PD. That is, the period from time t22 to time t23 is the accumulation period Tlj of the signal charges.

[0095] After that, in the same manner as the driving during the period from time t20 to time t23, the accumulation period Ts and the accumulation period Tl are repeatedly performed a predetermined number of times. For example, as shown in FIG. 3, the accumulation period Tsi+1 is performed during the period from time t24 to time t25, the accumulation period Tlj+1 is performed during the period from time t26 to time t27, and the accumulation period Tsi+2 is performed from time t28.

[0096] In this way, even in the even frames, the accumulation period Ts is executed Ks times and the accumulation period Tl is executed Kl times. As a result, the signal charges generated by the photoelectric conversion unit PD during the accumulation period Tshort having a length obtained by summing the lengths of Ks periods from the accumulation period Ts1 to the accumulation period TsKs are held in the charge holding unit MEM_S2.

[0097] Also, the signal charges generated by the photoelectric conversion unit PD during the accumulation period Tlong having a length obtained by summing the lengths of Kl periods from the accumulation period Tl1 to the accumulation period TlKl are held in the charge holding unit MEM_L2.

[0098] FIG. 4 is a timing diagram showing an example of a basic driving method for reading out a photoelectric conversion device according to Embodiment 1 of the present invention. In FIG. 4, control signals supplied to the transfer transistors M3L1, M3L2, M3S1, M3S2, the reset transistors M4, M8, and the selection transistors M6, M10 are shown for the (2N-1)th frame and the 2Nth frame.

[0099] That is, the time changes of the control signals TX_L1, TX_L2, TX_S1, TX_S2, RES_L, RES_S, SEL_L, and SEL_S are shown. When each control signal is at a high level, the corresponding transistor becomes active (on state). Here, the read operation of the pixel signal is sequentially executed for each row.

[0100] FIG. 4 shows the control signal supplied to the pixel 12 in the nth row and the control signal supplied to the pixel 12 in the (n+1)th row among the control signals corresponding to each of the plurality of rows constituting the pixel unit 10.

[0101] The control signal supplied to the pixel 12 in the n-th row has (n) appended to its code, and the control signal supplied to the pixel 12 in the (n + 1)-th row has (n + 1) appended to its code.

[0102] First, the read operation in the odd frame (the (2N - 1)-th frame) will be described. In the odd frame, as described above, a read operation of a signal based on the signal charges stored in the charge holding section MEM_L2 and the charge holding section MEM_S2 is performed.

[0103] In the (2N - 1)-th frame, the charge holding section MEM_L2 and the charge holding section MEM_S2 of each pixel 12 hold the signal charges accumulated in the (2N - 2)-th frame (not shown). Note that the read operation of each frame can be performed in parallel with the above-described exposure operation.

[0104] Just before time t30, it is assumed that the control signals TX_L1(n), TX_L2(n), TX_S1(n), TX_S2(n), SEL_L(n), SEL_S(n) are at a low level, and the control signals RES_L(n), RES_S(n) are at a high level.

[0105] At time t30, the vertical scanning circuit 20 controls the control signals SEL_L(n) and SEL_S(n) from a low level to a high level. As a result, the selection transistors M6, M10 of the pixel 12 in the n-th row turn on. Therefore, the amplification transistors M5, M9 of each column of the pixel 12 in the n-th row are connected to the corresponding column's vertical output line 16 via the selection transistors M6, M10, and a selection state where the pixel signal can be read is achieved.

[0106] At this time, the reset transistors M4, M8 are on, and the floating diffusion section FD is reset to a potential corresponding to the voltage VDD. Therefore, signals corresponding to the reset potential of the floating diffusion section FD are output to the vertical output lines 16, 17.

[0107] At the subsequent time t31, the vertical scanning circuit 20 controls the control signal RES(n) from a high level to a low level. As a result, the reset transistors M4 and M8 are turned off, and the reset state of the floating diffusion section FD is released.

[0108] After turning off the reset transistors M4 and M8, the voltages of the vertical output lines 16 and 17 become the reset level voltages VRES_L and VRES_S of the pixel 12. Thus, the reset level voltages VRES_L and VRES_S of the pixel 12 are read out to the vertical output lines 16 and 17.

[0109] During the period from the subsequent time t32 to time t33, the vertical scanning circuit 20 controls the control signals TX_L2(n) and TX_S2(n) from a low level to a high level. As a result, the transfer transistors M3L2 and M3S2 of the pixels 12 in the nth row are turned on, and the signal charges held in the charge holding sections MEM_L2 and MEM_S2 are transferred to the floating diffusion sections FD_L and FD_S, respectively.

[0110] Then, the floating diffusion sections FD_L and FD_S become potentials corresponding to the amounts of the signal charges transferred from the charge holding sections MEM_L2 and MEM_S2, respectively, and voltages corresponding to the potentials of the floating diffusion sections FD_L and FD_S are output to the vertical output lines 16 and 17.

[0111] After the transfer transistors M3L2 and M3S2 are turned off at time t33, the voltages of the vertical output lines 16 and 17 are the signal level voltages VSIG_L and VSIG_S of the pixel 12. Thus, the signal level voltages VSIG_L and VSIG_S of the pixel 12 based on the signal charges held in the charge holding sections MEM_L2 and MEM_S2 are read out to the vertical output lines 16 and 17.

[0112] The difference between the reset level voltage and the signal level voltage thus obtained, i.e., |VSIG_L - VRES_L|, becomes a physical quantity corresponding to the amount of signal charge held in the charge holding section MEM_L2. Also, |VSIG_S - VRES_S| becomes a physical quantity corresponding to the amount of signal charge held in the charge holding section MEM_S2.

[0113] At the subsequent time t34, the vertical scanning circuit 20 controls the control signals RES_L(n) and RES_S(n) from the low level to the high level. As a result, the reset transistors M4 and M8 of the pixel 12 in the n-th row turn on, and the floating diffusion sections FD_L and FD_S are reset to a potential corresponding to the voltage VDD.

[0114] At the subsequent time t35, the vertical scanning circuit 20 controls the control signals SEL_L(n) and SEL_S(n) from the high level to the low level. As a result, the selection transistors M6 and M10 of the pixel 12 in the n-th row turn off, and the selection of the n-th row is released.

[0115] Also, during the period from time t35 to the subsequent time t40, in the same manner as the period from time t30 to time t35, signals are read out based on the signal charges accumulated in the charge holding section MEM_L2 and the charge holding section MEM_S2 from the pixel 12 in the (n + 1)-th row. The readout operations of the pixels 12 in other rows are the same.

[0116] Next, the readout operation in the even frame (the 2N-th frame) will be described. In the even frame, as described above, a readout operation of a signal based on the signal charges accumulated in the charge holding section MEM_L1 and the charge holding section MEM_S1 is performed.

[0117] In the 2N-th frame, the signal charges accumulated in the (2N - 1)-th frame are held in the charge holding section MEM_L1 and the charge holding section MEM_S1 of each pixel 12.

[0118] Just before time t50, it is assumed that the control signals TX_L1(n), TX_L2(n), TX_S1(n), TX_S2(n), SEL_L(n), and SEL_S(n) are at a low level, and the control signals RES_L(n) and RES_S(n) are at a high level.

[0119] At time t50, the vertical scanning circuit 20 controls the control signals SEL_L(n) and SEL_S(n) from a low level to a high level. As a result, the selection transistors M6 and M10 of the pixels 12 in the n-th row are turned on, and the amplification transistors M5 and M9 of the pixels 12 in each column of the n-th row are connected to the corresponding column vertical output lines 16 and 17 via the selection transistors M6 and M10. Thereby, a selection state in which the pixel signal can be read is achieved.

[0120] At this time, the reset transistors M4 and M8 are on, and the floating diffusion parts FD_L and FD_S are reset to a potential corresponding to the voltage VDD. Therefore, signals corresponding to the reset potentials of the floating diffusion parts FD_L and FD_S are respectively output to the vertical output lines 16 and 17.

[0121] At the subsequent time t51, the vertical scanning circuit 20 controls the control signals RES_L(n) and RES_S(n) from a high level to a low level. As a result, the reset transistors M4 and M8 are turned off, and the reset states of the floating diffusion parts FD_L and FD_S are released.

[0122] After turning off the reset transistors M4 and M8, the voltages of the vertical output lines 16 and 17 become the reset level voltages VRES_L and VRES_S of the pixels 12. In this way, the reset level voltages VRES_L and VRES_S of the pixels 12 are read out to the vertical output lines 16 and 17.

[0123] During the period from the subsequent time t52 to time t53, the vertical scanning circuit 20 controls the control signals TX_L1(n) and TX_S1(n) from a low level to a high level. As a result, the transfer transistors M3L1 and M3S1 of the pixel 12 in the n-th row are turned on, and the signal charges held in the charge holding parts MEM_L1 and MEM_S1 are transferred to the floating diffusion parts FD_L and FD_S, respectively.

[0124] Then, the floating diffusion parts FD_L and FD_S become potentials corresponding to the amounts of the signal charges transferred from the charge holding parts MEM_L1 and MEM_S1, respectively, and voltages corresponding to the potentials of the floating diffusion parts FD_L and FD_S are output to the vertical output lines 16 and 17. The voltages of the vertical output lines 16 and 17 after the transfer transistors M3L1 and M3S1 are turned off at time t53 become the signal level voltages VSIG_L and VSIG_S of the pixel 12.

[0125] In this way, the signal level voltages VSIG_L and VSIG_S of the pixel 12 based on the signal charges held in the charge holding parts MEM_L1 and MEM_S1 are read out to the vertical output lines 16 and 17, respectively.

[0126] The difference between the reset level voltage and the signal level voltage V thus obtained, that is, |VSIG_L - VRES_L|, becomes a physical quantity corresponding to the amount of the signal charge held in the charge holding part MEM_L1. Also, |VSIG_S - VRES_S| becomes a physical quantity corresponding to the amount of the signal charge held in the charge holding part MEM_S1.

[0127] At the subsequent time t54, the vertical scanning circuit 20 controls the control signals RES_L(n) and RES_S(n) from a low level to a high level. As a result, the reset transistors M4 and M8 of the pixel 12 in the n-th row are turned on, and the floating diffusion parts FD_L and FD_S are reset to potentials corresponding to the voltage VDD.

[0128] At the subsequent time t55, the vertical scanning circuit 20 controls the control signals SEL_L(n) and SEL_S(n) from a high level to a low level. As a result, the selection transistors M6 and M10 of the pixels 12 in the n-th row are turned off, and the selection of the n-th row is canceled.

[0129] During the period from the subsequent time t55 to time t60, in the same manner as the period from time t50 to time t55, signals are read out from the pixels 12 in the (n + 1)-th row based on the signal charges accumulated in the charge holding section MEM_L1 and the charge holding section MEM_S1. The readout operations of the pixels 12 in other rows are the same.

[0130] In addition, in the driving example described with reference to FIGS. 3 and 4, the length of the accumulation period Tlong and the length of the accumulation period Tshort may be the same, but it is preferably different. By changing the length of the accumulation period Tlong and the length of the accumulation period Tshort, it becomes possible to acquire two types of images with different effective exposure amounts in the same frame.

[0131] One of the signals of the two types of images thus obtained is corrected according to the ratio of the lengths of the accumulation periods, and combined with the signal of the other image to be synthesized into one image, thereby obtaining an image with a wide dynamic range (HDR image). The synthesis process of the HDR image may be performed in the signal processing section in the photoelectric conversion device, or may be performed in an external signal processing device.

[0132] [Characteristic Configuration in Embodiment 1] As described above, in this embodiment, since the global shutter method of driving is performed, all the driving related to the exposure operation, that is, the transfer driving and the reset driving, are performed collectively for the pixels 12 in all rows.

[0133] That is, in the present embodiment, GS_L1, GS_L2, GS_S1, GS_S2, TX_L1, TX_L2, TX_S1, and TX_S2 in FIG. 2 correspond to batch transfer drive control, and OFG corresponds to batch reset drive control. Note that such batch drive control for simultaneously driving at least one of the transfer unit and the charge discharge unit for a plurality of pixels is performed by, for example, the control unit 218 described below.

[0134] These batch drive controls may cause potential fluctuations. When potential fluctuations propagate through power supply lines or the like, noise is superimposed on the pixel signals being read out at that time, which becomes a factor of horizontal lines. In the present embodiment, in order to correct image quality degradation associated with batch transfer drive and batch reset drive, a predetermined drive method and process are executed. This will be described with reference to FIG. 5.

[0135] FIG. 5 is a timing diagram showing an example of a drive method related to the exposure time of the photoelectric conversion device according to Embodiment 1 of the present invention. Note that in the following description, detailed description of drives similar to the basic drive in the above-described present embodiment will be omitted, and only differences will be described.

[0136] First, the exposure operation in odd frames (the (2N - 1)-th frame) will be described. In odd frames, the signal charges generated in the photoelectric conversion unit PD are accumulated in the charge holding unit MEM_L1, and video signals based on the accumulated signal charges are read out from the charge holding unit MEM_L2. In addition, in odd frames, the difference from the drive methods shown in FIGS. 3 and 4 is that a correction signal not based on the signal charges converted in the photoelectric conversion unit PD is read out from MEM_S2.

[0137] Immediately before time t70, it is assumed that the control signal OFG is at a high level. The charge discharge transistor M7 is turned on in response to the high-level control signal OFG, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0138] At time t70, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 is turned off, and the reset state of the photoelectric conversion unit PD is released.

[0139] During the period from a predetermined timing after time t70 to time t71, the vertical scanning circuit 20 controls the control signal GS_L1 to a high level. As a result, the transfer transistor M1L1 is turned on, and the signal charges accumulated in the photoelectric conversion unit PD are transferred to the charge holding unit MEM_L1.

[0140] The time t71 when the transfer transistor M1L1 is turned off is the end time of the accumulation period Tlj in the photoelectric conversion unit PD. That is, the period from time t70 to time t71 is the accumulation period Tlj of the signal charges.

[0141] After that, in the same manner as the period from time t70 to time t71, the accumulation period Tl is repeated a predetermined number of times. For example, as shown in FIG. 5, the accumulation period Tlj+1 of the signal charges is performed during the period from time t72 to time t73.

[0142] Next, the exposure operation in the even frame (the 2Nth frame) will be described. In the even frame, the signal charges generated in the photoelectric conversion unit PD are accumulated in the charge holding unit MEM_L2, and a video signal based on the accumulated signal charges is read out from the charge holding unit MEM_L1. Also, in the even frame, the difference from the driving method shown in FIGS. 3 and 4 is that a correction signal not based on the signal charges converted in the photoelectric conversion unit PD is read out from MEM_S1.

[0143] Immediately before time t80, it is assumed that the control signal OFG is at a high level. The charge discharge transistor M7 is turned on in response to the high-level control signal OFG, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0144] At time t80, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 turns off, and the reset state of the photoelectric conversion unit PD is released.

[0145] During the period from a predetermined timing after time t80 to time t81, the vertical scanning circuit 20 controls the control signal GS_L2 to a high level. As a result, the transfer transistor M1L2 turns on, and the signal charges accumulated in the photoelectric conversion unit PD are transferred to the charge holding unit MEM_L2.

[0146] The time t81 when the transfer transistor M1L2 turns off is the end time of the accumulation period Tlj in the photoelectric conversion unit PD. That is, the period from time t80 to time t81 is the accumulation period Tlj of the signal charges.

[0147] After that, in the same manner as the period from time t80 to time t81, the accumulation period Tl is repeated a predetermined number of times. For example, as shown in FIG. 5, the accumulation period Tlj+1 of the signal charges is performed during the period from time t82 to time t83.

[0148] The driving timing related to the read operation is the same as the driving timing shown in FIG. 4. Therefore, |VSIG_L-VRES_L| is read as a video signal based on the signal charges converted by the photoelectric conversion unit PD.

[0149] On the other hand, since the signal charges converted by the photoelectric conversion unit PD are not transferred to the charge holding units MEM_S1 and MEM_S2, |VSIG_S-VRES_S| is read as a correction signal not based on the signal charges converted by the photoelectric conversion unit PD. Also, the read timing of VRES_L and VRES_S is made to coincide with the read timing of VSIG_L and VSIG_S.

[0150] As described above, in Embodiment 1, it is characterized in that a video signal based on the charges generated in the photoelectric conversion unit and a correction signal not based on the charges generated in the photoelectric conversion unit are simultaneously read from two or more readout units. Such driving is performed, for example, by the control unit 218 described later.

[0151] In addition, in the driving example of FIG. 5, the signal charge transfer in odd frames is performed only on MEM_L1, and the signal charge transfer in even frames is performed only on MEM_L2. However, any combination that allows the video signal and the correction signal to be read at the same timing in the readout driving may be used.

[0152] Also, the accumulation period of the charges transferred to MEM_L1 and MEM_L2 is set to the length obtained by summing the accumulation period Tl a predetermined number of times. However, it may be accumulated in a single accumulation period without repeating multiple times.

[0153] Also, for the readout of the correction signal, the signal level voltage VSIG_S is read after turning on the transfer transistor M3S2, or the signal level voltage VSIG_S is read after turning on the transfer transistor M3S1. However, the signal level voltage VSIG_S may be read without turning on the transfer transistors M3S1 and M3S2, and used as the correction signal.

[0154] Subsequently, the correction process using the video signal and the correction signal obtained by the driving shown in FIG. 5 will be described. Assuming that the pixel unit 10 in this embodiment is composed of pixels 12 arranged in v rows and h columns, the video signal can be represented as P[m, k], and the correction signal can be represented as D[m, k]. However, m and k are integers satisfying 1 ≤ m ≤ v and 1 ≤ k ≤ h.

[0155] The video signal P[m, k] and the correction signal D[m, k] obtained by the driving shown in FIG. 5 are read at the same timing. The deterioration of the image quality due to the global electronic shutter operation occurs in the rows read at the timing when the potential is fluctuating. Therefore, since the image quality deterioration occurs in the same rows when read at the same timing, correction is performed by subtracting the correction signal D[m, k] from the video signal P[m, k].

[0156] However, the correction process of the present embodiment as described above is just an example, and other correction processes may be performed. For example, the average values D_ave[1], D_ave[2], ···, D_ave[m], D_ave[m + 1], ···, D_ave[v] of each row of the correction signal D[m,k] may be obtained respectively. Then, correction may be performed by subtracting D_ave[m] from each row of the video signal P[m,k].

[0157] However, when processing such as black level clamping is performed on the video signal and the correction signal, the correction process is performed using the value excluding the black level. Note that the correction process in the present embodiment may be performed by a signal processing unit in the photoelectric conversion device or by an external signal processing device. Thus, according to the present embodiment, a video with reduced image quality due to the global electronic shutter operation corrected can be obtained.

[0158] <Embodiment 2> FIG. 6 is an equivalent circuit diagram showing a configuration example of a pixel of the photoelectric conversion device according to Embodiment 2 of the present invention. The same components as those of the photoelectric conversion device according to Embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

[0159] The photoelectric conversion device according to the present embodiment is the same as the photoelectric conversion device according to Embodiment 1 except that the configuration of the pixel 12 is different. In the present embodiment, the description will be centered on the differences from the photoelectric conversion device of Embodiment 1, and the description of the same parts as those of the photoelectric conversion device of Embodiment 1 will be omitted as appropriate.

[0160] Each pixel 12 in the photoelectric conversion device of the present embodiment is configured as shown in FIG. 6. That is, in addition to the components of the pixel 12 of Embodiment 1 shown in FIG. 2, transfer transistors M1M1, M1M2, M3M1, M3M2, a reset transistor M11, an amplification transistor M12, and a selection transistor M13 are further provided.

[0161] The source of transfer transistor M1M1 and the source of transfer transistor M1M2 are connected to the cathode of the photodiode of the photoelectric conversion unit PD and the source of charge discharge transistor M7.

[0162] The drain of transfer transistor M1M1 is connected to the source of transfer transistor M3M1. The connection node between the drain of transfer transistor M1M1 and the source of transfer transistor M3M1 includes a capacitive component and functions as a charge holding unit (charge holding unit MEM_M1).

[0163] The drain of transfer transistor M1M2 is connected to the source of transfer transistor M3M2. The connection node between the drain of transfer transistor M1M2 and the source of transfer transistor M3M2 includes a capacitive component and functions as a charge holding unit (charge holding unit MEM_M2).

[0164] The drains of transfer transistors M3M1 and M3M2 are connected to the source of reset transistor M11 and the gate of amplifier transistor M12. The connection node of the drains of transfer transistors M3M1 and M3M2, the source of reset transistor M11, and the gate of amplifier transistor M12 constitutes a floating diffusion portion FD_M.

[0165] The floating diffusion portion FD_M includes a capacitive component (floating diffusion capacitance) and functions as a charge holding unit. The drain of reset transistor M11 and the drain of amplifier transistor M12 are connected to the power supply voltage line (voltage VDD). The source of amplifier transistor M12 is connected to the drain of selection transistor M13.

[0166] The source of selection transistor M13 is connected to the vertical output line 16c. Here, the vertical output line 16c has the same function as the vertical output lines 16a and 16b. The connection relationship of the other components of pixel 12 is as described in Embodiment 1.

[0167] Each of the control lines 14 further includes six signal lines each connected to the transfer transistors M1M1, M1M2, M3M1, M3M2, the reset transistor M11, and the selection transistor M13. A control signal GS_M1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1M1.

[0168] A control signal GS_M2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1M2. A control signal TX_M1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3M1. A control signal TX_M2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3M2.

[0169] A control signal RES_M is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M11. A control signal SEL_M is output from the vertical scanning circuit 20 to the signal line connected to the gate of the selection transistor M13.

[0170] When each transistor is composed of an N-type transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns on, and when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns off.

[0171] The transfer transistor M1M1 functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_M1 when it is turned on. The transfer transistor M1M2 functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_M2 when it is turned on.

[0172] The transfer transistors M3M1 functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_M1 to the floating diffusion unit FD_M when turned on. The transfer transistor M3M2 functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_M2 to the floating diffusion unit FD_M when turned on. The operations of the other components of pixel 12 are as described in Embodiment 1.

[0173] In Embodiment 1, for one photoelectric conversion unit PD, four charge holding units MEM_L1, MEM_L2, MEM_S1, and MEM_S2 were connected in parallel via transfer transistors M1L1, M1L2, M1S1, and M1S2, respectively.

[0174] In contrast, in the present embodiment, for the one photoelectric conversion unit PD, two more charge holding units MEM_M1 and MEM_M2 are connected in parallel via transfer transistors M1M1 and M1M2, respectively.

[0175] Therefore, according to the present embodiment, by using three charge holding units, it is possible to alternately acquire three types of images based on signal charges accumulated during different accumulation times for each frame.

[0176] By synthesizing the three types of images acquired in each frame in this way, the dynamic range can be further expanded compared to Embodiment 1. Also, according to this configuration, it is possible to read out the signal during the period of accumulating the signal charge, reduce the time region where the signal charge cannot be acquired during each frame period, and acquire a seamless video.

[0177] [Characteristic Configuration in Embodiment 2] In Embodiment 1, as a characteristic configuration, the video signal was read out from the floating diffusion unit FD_L and the correction signal was read out from the floating diffusion unit FD_S without transferring the charge from the photoelectric conversion unit PD to the charge holding units MEM_S1 and MEM_S2.

[0178] On the other hand, in Embodiment 2, two types of video signals based on signal charges accumulated during different accumulation times are read out from two of the floating diffusion parts FD_L, FD_M, and FD_S, and a correction signal not based on the signal charge converted by the photoelectric conversion part is read out from one of them. That is, by reading out the two types of video signals and the correction signal at the same timing, it is possible to correct the noise caused by the potential fluctuation associated with the global electronic shutter operation.

[0179] In addition, in this embodiment, each of the two charge holding parts is configured to output to one vertical output line. However, for example, the charges accumulated in the charge holding parts MEM_L1 and MEM_L2 may be read out from the same vertical output line as the charges accumulated in the charge holding parts MEM_M1 and MEM_M2.

[0180] In this case, the correction signal is read out from the vertical output line 16b at the same timing as the timing of reading out the video signal from MEM_L1 or MEM_L2. Also, the correction signal is read out from the vertical output line 16b at the same timing as the timing of reading out the video signal from MEM_M1 or MEM_M2.

[0181] In addition, in this embodiment, six charge holding parts are connected in parallel to one photoelectric conversion part PD, but a configuration in which eight or more charge holding parts are connected in parallel may also be used. By configuring in this way, the dynamic range can be further expanded. Thus, according to Embodiment 2, it is possible to correct the deterioration of the image quality due to the global electronic shutter operation while acquiring a high-quality video with a high dynamic range.

[0182] <Embodiment 3> The photoelectric conversion device and its driving method according to Embodiment 3 of the present invention will be described with reference to FIGS. 7 to 10. In addition, the same reference numerals are given to the same components as those in the photoelectric conversion device according to Embodiment 1 or Embodiment 2, and the description is omitted or simplified.

[0183] FIG. 7 is an equivalent circuit diagram showing a configuration example of a pixel of the photoelectric conversion device according to Embodiment 3 of the present invention. The photoelectric conversion device according to Embodiment 3 is the same as the photoelectric conversion device according to Embodiment 1 or Embodiment 2, except that the configuration of pixel 12 is different. In Embodiment 3, the description will focus on the differences from the photoelectric conversion device of Embodiment 1 or Embodiment 2, and the description of the same parts as those of the photoelectric conversion device of Embodiment 1 or Embodiment 2 will be omitted as appropriate.

[0184] Each pixel 12 in the photoelectric conversion device of Embodiment 3 has a photoelectric conversion unit PD and transfer transistors M1L, M1S, M3L, and M3S, as shown in FIG. 7. Further, each pixel 12 further has reset transistors M4 and M8, amplification transistors M5 and M9, selection transistors M6 and M10, and a charge discharge transistor M7.

[0185] The anode of the photoelectric conversion unit PD is connected to the ground node, and the cathode is connected to the sources of the transfer transistor M1L, the transfer transistor M1S, and the charge discharge transistor M7.

[0186] The drain of the transfer transistor M1L is connected to the source of the transfer transistor M3L. The connection node between the drain of the transfer transistor M1L and the source of the transfer transistor M3L includes a capacitive component and functions as a charge holding unit (charge holding unit MEM_L).

[0187] The drain of the transfer transistor M1S is connected to the source of the transfer transistor M3S. The connection node between the drain of the transfer transistor M1S and the source of the transfer transistor M3S includes a capacitive component and functions as a charge holding unit (charge holding unit MEM_S).

[0188] The drain of transfer transistor M3L is connected to the source of reset transistor M4 and the gate of amplification transistor M5. The connection node of the drain of transfer transistor M3L, the source of reset transistor M4, and the gate of amplification transistor M5 constitutes the floating diffusion part FD_L. The floating diffusion part FD_L includes a capacitive component (floating diffusion capacitance) and functions as a charge holding part.

[0189] The drain of transfer transistor M3S is connected to the source of reset transistor M8 and the gate of amplification transistor M9. The connection node of the drain of transfer transistor M3S, the source of reset transistor M8, and the gate of amplification transistor M9 constitutes the floating diffusion part FD_S. The floating diffusion part FD_S includes a capacitive component (floating diffusion capacitance) and functions as a charge holding part.

[0190] The drains of reset transistors M4 and M8, the drains of amplification transistors M5 and M9, and the drain of charge discharge transistor M7 are connected to the power supply voltage line (voltage VDD).

[0191] The source of amplification transistor M5 is connected to the drain of selection transistor M6, and the source of amplification transistor M9 is connected to the drain of selection transistor M10. The source of selection transistor M6 is connected to the vertical output line 16a. The source of selection transistor M10 is connected to the vertical output line 16b.

[0192] Each of the control lines 14 includes nine signal lines connected to the gates of transfer transistors M1L, M1S, M3L, M3S, reset transistors M4, M8, selection transistors M6, M10, and charge discharge transistor M7, respectively.

[0193] To the signal line connected to the gate of transfer transistor M1L, control signal GS_L is output from vertical scanning circuit 20. To the signal line connected to the gate of transfer transistor M3L, control signal TX_L is output from vertical scanning circuit 20.

[0194] To the signal line connected to the gate of transfer transistor M1S, control signal GS_S is output from vertical scanning circuit 20. To the signal line connected to the gate of transfer transistor M3S, control signal TX_S is output from vertical scanning circuit 20.

[0195] To the signal line connected to the gate of reset transistor M4, control signal RES_L is output from vertical scanning circuit 20. To the signal line connected to the gate of reset transistor M8, control signal RES_S is output from vertical scanning circuit 20. To the signal line connected to the gate of selection transistor M6, control signal SEL_L is output from vertical scanning circuit 20.

[0196] To the signal line connected to the gate of selection transistor M10, control signal SEL_S is output from vertical scanning circuit 20. To the signal line connected to the gate of charge discharge transistor M7, control signal OFG is output from vertical scanning circuit 20.

[0197] When each transistor is composed of N-type transistors, when a high-level control signal is supplied from vertical scanning circuit 20, the corresponding transistor turns on, and when a low-level control signal is supplied from vertical scanning circuit 20, the corresponding transistor turns off.

[0198] The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the amount of the light (photoelectric conversion) and accumulates the generated charge. Transfer transistor M1L functions as a transfer unit that performs a transfer operation of transferring the charge held by photoelectric conversion unit PD to charge holding unit MEM_L when it turns on. Transfer transistor M3L functions as a transfer unit that performs a transfer operation of transferring the charge held by charge holding unit MEM_L to floating diffusion unit FD_L when it turns on.

[0199] The transfer transistor M1S functions as a transfer unit that performs a transfer operation of transferring the charge held by the photoelectric conversion unit PD to the charge holding unit MEM_S when it is turned on. The transfer transistor M3S functions as a transfer unit that performs a transfer operation of transferring the charge held by the charge holding unit MEM_S to the floating diffusion unit FD_S when it is turned on.

[0200] The functions and operations of the reset transistors M4 and M8, the amplification transistors M5 and M9, the selection transistors M6 and M10, and the charge discharge transistor M7 are the same as those in the first embodiment.

[0201] In the first embodiment, charge holding units MEM_L1 and MEM_L2 were connected in parallel between the photoelectric conversion unit PD and the floating diffusion unit FD_L, and charge holding units MEM_S1 and MEM_S2 were connected in parallel between the photoelectric conversion unit PD and the floating diffusion unit FD_S.

[0202] In contrast, in the third embodiment, a charge holding unit MEM_L is connected between the photoelectric conversion unit PD and the floating diffusion unit FD_L, and a charge holding unit MEM_S is connected between the photoelectric conversion unit PD and the floating diffusion unit FD_S.

[0203] Next, a basic driving method of the photoelectric conversion device according to the third embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a timing diagram showing a basic driving example related to the exposure time of the photoelectric conversion device according to the third embodiment of the present invention, and FIG. 9 is a timing diagram showing a basic driving example related to the reading of the photoelectric conversion device according to the third embodiment of the present invention.

[0204] FIG. 8 shows the time changes of the control signals GS_L, GS_S, and OFG supplied to the transfer transistors M1L, M1S, and the charge discharge transistor M7, respectively. When each control signal is at a high level, the corresponding transistor becomes active (on state).

[0205] In Embodiment 3, since the global shutter method is used for driving, the driving related to the exposure operation of pixel 12 is the same for the pixels 12 in all rows. Also, in Embodiment 3, since the driving for odd frames and the driving for even frames are the same, FIG. 8 shows only the driving for one frame (the Nth frame).

[0206] In Embodiment 3, in each frame, an accumulation period Ts and an accumulation period Tl are each performed once. The accumulation period Ts is a period for accumulating signal charges in the charge holding part MEM_S, and the accumulation period Tl is a period for accumulating signal charges in the charge holding part MEM_L. Hereinafter, the operations of the accumulation period Ts and the accumulation period Tl will be described with reference to FIG. 8.

[0207] Immediately before time t90, it is assumed that the control signal OFG is at a high level. The charge discharge transistor M7 is turned on in response to the high-level control signal OFG, and the photoelectric conversion part PD is reset to a potential corresponding to the voltage VDD.

[0208] At time t90, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 is turned off, and the reset state of the photoelectric conversion part PD is released.

[0209] That is, the timing at which the control signal OFG transitions from a high level to a low level is the start time of the accumulation period Ts in the photoelectric conversion part PD. The signal charges generated by the incidence of photons on the photoelectric conversion part PD while the charge discharge transistor M7 is off are accumulated in the photoelectric conversion part PD.

[0210] During the period from time t91 to time t92, the vertical scanning circuit 20 controls the control signal GS_S to a high level. As a result, the transfer transistor M1S is turned on, and the signal charges accumulated in the photoelectric conversion part PD are transferred to the charge holding part MEM_S.

[0211] The time t92 when the transfer transistor M1S turns off is the end time of the accumulation period Ts in the photoelectric conversion unit PD. That is, the period from time t90 to time t92 is the accumulation period Ts of the signal charge.

[0212] After time t92, the vertical scanning circuit 20 controls the control signal OFG from a low level to a high level. Thereby, the charge discharge transistor M7 turns on, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0213] At the subsequent time t93, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. Thereby, the charge discharge transistor M7 turns off, and the reset state of the photoelectric conversion unit PD is released.

[0214] That is, the timing at which the control signal OFG transitions from a high level to a low level is the start time of the accumulation period Tl in the photoelectric conversion unit PD. The signal charge generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharge transistor M7 is off is accumulated in the photoelectric conversion unit PD.

[0215] During the period from a predetermined timing after time t93 to time t94, the vertical scanning circuit 20 controls the control signal GS_L to a high level. Thereby, the transfer transistor M1L turns on, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM_L.

[0216] The time t94 when the transfer transistor M1L turns off is the end time of the accumulation period Tl in the photoelectric conversion unit PD. That is, the period from time t93 to time t94 is the accumulation period Tl of the signal charge.

[0217] In this way, in each frame, the accumulation period Ts and the accumulation period Tl are executed. Thereby, the signal charge generated in the photoelectric conversion unit PD during the accumulation period Ts is held in the charge holding unit MEM_S. Also, the signal charge generated in the photoelectric conversion unit PD during the accumulation period Tl is held in the charge holding unit MEM_L.

[0218] Still, the signal charges accumulated in the photoelectric conversion unit PD can be transferred to the charge holding units MEM_S and MEM_L after the readout of the pixel signal based on the signal charges of the (N-1)th frame stored in the charge holding units MEM_S and MEM_L is completed. Here, it is assumed that the readout of the pixel signal based on the signal charges of the (N-1)th frame stored in the charge holding units MEM_S and MEM_L is completed by time t91.

[0219] FIG. 9 shows the time variations of the control signals TX_L, TX_S, SEL_L, SEL_S, RES_L, and RES_S supplied to the transfer transistors M3L, M3S, the selection transistors M6, M10, and the reset transistors M4, M8. When each control signal is at a high level, the corresponding transistor becomes active (on state).

[0220] Here, the readout operation of the pixel signal is sequentially executed for each row. FIG. 9 shows the control signal supplied to the pixel 12 of the nth row and the control signal supplied to the pixel 12 of the (n+1)th row among the control signals corresponding to each of the plurality of rows constituting the pixel unit 10. (n) is appended to the symbol of the control signal supplied to the pixel 12 of the nth row, and (n+1) is appended to the symbol of the control signal supplied to the pixel 12 of the (n+1)th row.

[0221] In each frame, the readout of the signal based on the signal charges stored in the charge holding units MEM_L and MEM_S of the pixels 12 in each row is sequentially executed for each row. At the start time of the Nth frame, the charge holding units MEM_L and MEM_S of each pixel 12 hold the signal charges accumulated during the accumulation periods Tl and Ts of the (N-1)th frame, respectively.

[0222] Just before time t100, it is assumed that the control signals TX_L(n), TX_S(n), SEL_L(n), and SEL_S(n) are at a low level, and the control signals RES_L(n) and RES_S(n) are at a high level.

[0223] At time t100, the vertical scanning circuit 20 controls the control signals SEL_L(n) and SEL_S(n) from the low level to the high level, turning on the selection transistors M6 and M10 of the pixels 12 in the n-th row.

[0224] As a result, the amplification transistors M5 of the pixels 12 in each column of the n-th row are connected to the corresponding column's vertical output line 16a via the selection transistor M6, entering a select state where the pixel signal can be read. Also, the amplification transistor M9 is connected to the corresponding column's vertical output line 16b via the selection transistor M10, entering a select state where the pixel signal can be read.

[0225] At this time, the reset transistors M4 and M8 are on, and the floating diffusion parts FD_L and FD_S are reset to a potential corresponding to the voltage VDD. Thereby, a signal corresponding to the reset potential of the floating diffusion part FD_L is output to the vertical output line 16a, and a signal corresponding to the reset voltage of the floating diffusion part FD_S is output to the vertical output line 16b.

[0226] At the subsequent time t101, the vertical scanning circuit 20 controls the control signals RES_L(n) and RES_S(n) from the high level to the low level. Thereby, the reset transistors M4 and M8 turn off, and the reset states of the floating diffusion parts FD_L and FD_S are released.

[0227] The voltage of the vertical output line 16a after turning off the reset transistor M4 is the reset level voltage VRES_L of the floating diffusion part FD_L. Also, the voltage of the vertical output line 16b after turning off the reset transistor M8 is the reset level voltage VRES_S of the floating diffusion part FD_S. In this way, the reset level voltage VRES_L is read out on the vertical output line 16a, and the reset level voltage VRES_S is read out on the vertical output line 16b.

[0228] During the period from the subsequent time t102 to time t103, the vertical scanning circuit 20 controls the control signals TX_L(n) and TX_S(n) from a low level to a high level. As a result, the transfer transistors M3L and M3S of the pixel 12 in the n-th row are turned on, and the signal charge held in the charge holding section MEM_L is transferred to the floating diffusion section FD_L, and the signal charge held in the charge holding section MEM_S is transferred to the floating diffusion section FD_S.

[0229] Then, the floating diffusion section FD_L becomes a potential corresponding to the amount of the signal charge transferred from the charge holding section MEM_L, and a voltage corresponding to the potential of the floating diffusion section FD_L is output to the vertical output line 16a. Also, the floating diffusion section FD_S becomes a potential corresponding to the amount of the signal charge transferred from the charge holding section MEM_S, and a voltage corresponding to the potential of the floating diffusion section FD_S is output to the vertical output line 16b.

[0230] The voltage of the vertical output line 16a that settles after the transfer transistor M3L is turned off at time t103 is the signal level voltage VSIG_L, and the voltage of the vertical output line 16b that settles after the transfer transistor M3S is turned off is the signal level voltage VSIG_S.

[0231] In this way, the signal level voltage VSIG_L of the pixel 12 based on the signal charge held in the charge holding section MEM_L is read out to the vertical output line 16a. And the signal level voltage VSIG_S of the pixel 12 based on the signal charge held in the charge holding section MEM_S is read out to the vertical output line 16b.

[0232] The difference between the reset level voltages VRES_L, VRES_S and the signal level voltages VSIG_L, VSIG_S obtained in this way becomes a physical quantity corresponding to the amount of the signal charge held in the charge holding section MEM_L and the charge holding section MEM_S. That is, |VSIG_L - VRES_L| and |VSIG_S - VRES_L| become physical quantities corresponding to the amount of the signal charge held in the charge holding section MEM_L and the charge holding section MEM_S, respectively.

[0233] At the subsequent time t104, the vertical scanning circuit 20 controls the control signals RES_L(n) and RES_S(n) from the low level to the high level. As a result, the reset transistors M4 and M8 of the pixels 12 in the n-th row are turned on, and the floating diffusion parts FD_L and FD_S are reset to the potential corresponding to the voltage VDD.

[0234] At the subsequent time t105, the vertical scanning circuit 20 controls the control signals SEL_L(n) and SEL_S(n) from the high level to the low level. As a result, the selection transistors M6 and M10 of the pixels 12 in the n-th row are turned off, and the selection of the n-th row is cancelled.

[0235] Also, during the period from time t105 to t106, in the same manner as the driving at the time from t100 to t105, signals are read out from the pixels 12 in the (n + 1)-th row based on the signal charges accumulated in the charge holding part MEM_L and the charge holding part MEM_S. The readout operations of the pixels 12 in other rows are the same. In this embodiment, the accumulation period Tl is performed after the accumulation period Ts, but the order may be reversed.

[0236] [Characteristic configuration in Embodiment 3] The batch control signals that cause image quality degradation in Embodiment 3 are GS_L, GS_S, TX_L, TX_S, and OFG in FIG. 8, and these are the causes of horizontal lines on the screen.

[0237] As a characteristic configuration in Embodiment 3, a driving method and processing for correcting image quality degradation associated with batch transfer driving and batch reset driving will be described with reference to FIG. 10. FIG. 10 is a timing diagram showing a characteristic driving example related to the exposure time of the photoelectric conversion device according to Embodiment 3 of the present invention. An accumulation period T is provided once in each frame.

[0238] Immediately before time t110, it is assumed that the control signal OFG is at the high level. The charge discharge transistor M7 is turned on by receiving the high-level control signal OFG, and the photoelectric conversion part PD is reset to the potential corresponding to the voltage VDD.

[0239] At time t110, the vertical scanning circuit 20 controls the control signal OFG from a high level to a low level. As a result, the charge discharge transistor M7 is turned off, and the reset state of the photoelectric conversion unit PD is released.

[0240] That is, the timing at which the control signal OFG transitions from a high level to a low level is the start time of the accumulation period T in the photoelectric conversion unit PD. The signal charges generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharge transistor M7 is off are accumulated in the photoelectric conversion unit PD.

[0241] During the period from time t111 to time t112, the vertical scanning circuit 20 controls the control signal GS_L to a high level. As a result, the transfer transistor M1L is turned on, and the signal charges accumulated in the photoelectric conversion unit PD are transferred to the charge holding unit MEM_L.

[0242] The time t112 when the transfer transistor M1L turns off is the end time of the accumulation period T in the photoelectric conversion unit PD. That is, the period from time t110 to time t112 is the accumulation period T of the signal charges.

[0243] The signal charges accumulated in the photoelectric conversion unit PD can be transferred to the charge holding unit MEM_L after the reading of the video signal based on the signal charges of the (N - 1)th frame accumulated in the charge holding unit MEM_L is completed. Here, it is assumed that the reading of the video signal based on the signal charges of the (N - 1)th frame accumulated in MEM_L is completed by time t111.

[0244] The driving timing related to the reading operation is the same as the aforementioned basic driving. Therefore, |VSIG_L - VRES_L| is read out as a video signal based on the signal charges converted by the photoelectric conversion unit PD.

[0245] On the other hand, since the signal charge converted by the photoelectric conversion unit PD is not transferred to the charge holding unit MEM_S, |VSIG_S - VRES_S| is read out as a correction signal not based on the signal charge converted by the photoelectric conversion unit PD.

[0246] In addition, the read timing of VRES_L and VRES_S is made to coincide with the read timing of VSIG_L and VSIG_S. Also, in Embodiment 3, charge transfer from the photoelectric conversion unit PD to MEM_S is not performed, and only charge transfer from the photoelectric conversion unit PD to MEM_L is performed, but the reverse is also possible.

[0247] In addition, as described above, the correction signal uses the signal read from the readout unit without transferring the charge generated in the photoelectric conversion unit to the charge holding unit, but it is also possible to use the signal read from the readout unit without transferring the charge generated in the photoelectric conversion unit to the readout unit.

[0248] Through the above driving, a video signal and a correction signal are obtained. Since the video signal and the correction signal are read at the same timing, the horizontal line noise due to batch control occurs at the same position. Therefore, it is possible to correct the horizontal line noise of the video signal using the correction signal.

[0249] The correction process in Embodiment 3 may be performed by a signal processing unit in the photoelectric conversion device or by an external signal processing device. Thus, according to this embodiment, it is possible to acquire a video with corrected image quality degradation due to the global electronic shutter operation.

[0250] <Embodiment 4> The imaging system according to Embodiment 4 of the present invention will be described with reference to FIG. 11. FIG. 11 is a functional block diagram showing a schematic configuration example of the imaging system according to Embodiment 4 of the present invention.

[0251] Some of the functional blocks shown in FIG. 11 are realized by causing a CPU or the like as a computer (not shown) included in an imaging system to execute a computer program stored in a memory as a storage medium (not shown). However, some or all of them may be realized by hardware. As the hardware, a dedicated circuit (ASIC), a processor (reconfigurable processor, DSP), or the like can be used.

[0252] Also, each functional block shown in FIG. 11 does not have to be built in the same housing, and may be configured by separate devices connected to each other via signal paths. The above description regarding FIG. 11 also applies to FIG. 12 in the same manner.

[0253] The photoelectric conversion device 100 described in the above Embodiments 1 to 3 is applicable to various imaging systems. Examples of applicable imaging systems include, for example, digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and the like.

[0254] Also, a camera module including an optical system such as a lens and an imaging device is included in the imaging system. FIG. 11 illustrates a block diagram of a digital video camera as an example of the imaging system 200.

[0255] The imaging system 200 illustrated in FIG. 11 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, and a diaphragm 204 for varying the amount of light passing through the lens 202. The lens 202 and the diaphragm 204 constitute an optical system that condenses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 configured as described in Embodiments 1 to 3, and converts the optical image formed by the lens 202 into image data.

[0256] The imaging system 200 also includes a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates video data from the digital signal output by the imaging device 201. Further, the signal processing unit 208 performs various corrections, compressions, etc. as necessary and outputs image data.

[0257] The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit and the signal processing unit 208 may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed in multiple layers on a semiconductor substrate different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed.

[0258] The imaging system 200 further includes a memory unit 210 for temporarily storing video data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like.

[0259] Furthermore, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out to / from the recording medium 214. Note that the recording medium 214 may be built into the imaging system 200 or may be detachable.

[0260] Furthermore, the imaging system 200 includes a control unit 218 that performs various operations and controls the entire digital video camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208.

[0261] The control unit 218 incorporates a CPU or the like as a computer, and functions as control means for controlling the operations of each part of the entire imaging device based on a computer program stored in a memory as a storage medium.

[0262] Further, in Embodiment 4, the control unit 218 calculates and controls the set values of each exposure, such as the imaging device 201 and the lens 202, based on the result of analyzing the video signal obtained by the signal processing unit 208. Note that a timing signal or the like may be input from the outside, and the imaging system 200 may have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0263] The imaging device 201 outputs a video signal to the signal processing unit 208, and the signal processing unit 208 performs predetermined signal processing on the video signal output from the imaging device 201 and outputs video data.

[0264] In Embodiment 4, the processing when the signal processing unit 208 corrects the image quality degradation associated with the global electronic shutter operation will be described with reference to FIG. 12. FIG. 12 is a functional block diagram showing a detailed configuration example of the signal processing unit of the imaging system according to Embodiment 4 of the present invention, and shows a configuration example for correcting the image quality degradation associated with the global electronic shutter operation in the signal processing unit 208 shown in FIG. 11.

[0265] As described above, the imaging device 201 is the photoelectric conversion device 100 having the configuration as in Embodiments 1 to 3. That is, as a characteristic drive, when correcting the image quality degradation associated with the global electronic shutter operation, a video signal and a correction signal read out at the same timing are obtained from the imaging device 201.

[0266] In the following description, the imaging device 201 is assumed to be the photoelectric conversion device 100 having v rows and h columns of pixels, and the output video signal is denoted as P[m, k], and the correction signal is denoted as D[m, k]. However, m and k are integers satisfying 1 ≦ m ≦ v and 1 ≦ k ≦ h. For example, the video signal of the 64th column in the first output row in the Nth frame is denoted as P[1, 64].

[0267] In this embodiment, the signal processing unit 208 includes a correction positioning unit 300, a correction value generation unit 301, and a correction unit 302 as blocks for correcting image quality degradation associated with the global electronic shutter operation. However, other corrections and signal processing that are different before and after the correction of image quality degradation associated with the global electronic shutter operation may be performed. Here, the correction unit 302 is for performing correction processing of noise generated by batch drive control from the video signal using a correction signal.

[0268] The correction positioning unit 300 acquires a setting value related to the exposure time of the imaging device 201 among the exposure setting values calculated by the control unit 218, and determines a row position for performing correction processing for correcting image quality degradation associated with the global electronic shutter operation.

[0269] For example, when the imaging device 201 is the photoelectric conversion device 100 having the configuration described in Embodiment 3, the row in which the signal charge is read out from MEM_L at the time t110 when the control signal OFG is controlled to the high level becomes the correction position.

[0270] In Embodiment 3, the correction position is one row, but when there are a plurality of rows where image quality degradation occurs, a plurality of rows may be used as the correction positions. Hereinafter, the correction position (row position) determined by the correction positioning unit 300 is denoted as Cpi. The subscript i is an integer of 0 or more and indicates the number of correction positions.

[0271] Note that in this embodiment, the correction position is determined based on the exposure setting value calculated by the control unit 218, but the correction position may be determined by other methods. For example, a correction signal D[m, n] for one frame may be acquired from the imaging device 201, and the average value D_ave[m] of each row may be calculated.

[0272] Furthermore, a moving average D_mave[m] of D_ave[m] may be calculated, and a row in which D_ave[m] - D_mave[m] is greater than a predetermined threshold value may be determined as the correction position.

[0273] Also, in this embodiment, the correction positioning unit 300 is provided in the signal processing unit 208 outside the imaging device 201 to determine the position to be corrected. However, the correction positioning unit 300 may be provided inside the imaging device 201, and only the correction signal for the determined correction position may be output from the imaging device 201. If configured in this way, the amount of data output from the imaging device 201 can be reduced.

[0274] The correction value generation unit 301 generates a correction value to be used for correction in the correction unit 302 based on the correction signal output from the imaging device 201 and the correction position determined by the correction positioning unit 300. Hereinafter, the correction value will be denoted as Cvali[m].

[0275] Here, the case of using linear interpolation for generating the correction value Cvali[m] will be described. For example, it is assumed that the correction value Cvali[m] is generated by linear interpolation from q points (m0, m1, ···, mj-1, mj, mj+1, ···, mq-1, mq) which are non-negative integers at the correction position Cpi.

[0276] In that case, the correction value Cvali[m] when the horizontal position is between mj and mj+1 is Cvali[m]=D[mj,Cpi]+(D[mj+1,Cpi]-D[mj,Cpi])×(m-mj) / (mj+1-mj) and can be calculated.

[0277] Here, the correction value approximated by a quadratic curve is generated by linear interpolation. However, the correction signal D[m,Cpi] at the correction position may be used as the correction value, or the correction value may be generated by a quadratic curve approximation or other approximation methods. Also, the correction value may be generated using the coefficients of a predetermined quadratic function, or the value of a linear straight line instead of a quadratic curve may be used as the correction value.

[0278] The correction unit 302 corrects the video signal P[m,k] using the correction value Cvali[m] generated by the correction value generation unit 301 with respect to the correction position Cpi determined by the correction positioning unit 300. For example, correction can be performed by performing the process of P[m,Cpi]-Cvali[m].

[0279] In Embodiment 4, the correction process was performed by the signal processing unit 208 outside the imaging device 201, but part or all of the processes may be performed by the signal processing unit inside the imaging device 201. In the actual imaging device 201, since the video signal and the correction signal are output via different charge holding units or floating diffusion units, the video signal and the correction signal are signals including variations due to individual differences.

[0280] Therefore, a correction value for correcting the image quality degradation associated with the global electronic shutter operation may be generated after performing a process of correcting individual differences on the correction signal output from the imaging device 201. Alternatively, a process of correcting the image quality degradation associated with the global electronic shutter operation on the video signal may be performed after performing a process of correcting individual differences on the correction value generated by the correction value generation unit 301.

[0281] Alternatively, a process of further correcting individual differences may be performed after performing a process of correcting the image quality degradation associated with the global electronic shutter operation. Thus, according to Embodiment 4, the photoelectric conversion device 100 according to Embodiments 1 to 3 can be applied to realize an imaging system capable of correcting the image quality degradation associated with the global electronic shutter operation.

[0282] As described above, the present invention has been described in detail based on its preferred embodiments. However, the present invention is not limited to the above embodiments, and various modifications and combinations of the above embodiments are possible based on the spirit of the present invention, and they are not excluded from the scope of the present invention. The present invention includes the following combinations.

[0283] (Configuration 1) Having a plurality of pixels, each pixel including a photoelectric conversion unit that generates charge by photoelectric conversion, At least two charge holding parts for holding the charges, a transfer part for transferring the charges from the photoelectric conversion part to at least two of the charge holding parts respectively, a charge discharging part for discharging the charges accumulated in the photoelectric conversion part, and two or more reading parts for respectively reading out signals corresponding to the amounts of the charges transferred from at least two of the charge holding parts, and at least one of the transfer part and the charge discharging part performs batch driving control for simultaneously driving the plurality of pixels, and a control part for simultaneously reading out a video signal based on the charges generated in the photoelectric conversion part and a correction signal not based on the charges generated in the photoelectric conversion part from two or more of the reading parts, and a correction part for performing correction processing of noise generated by the batch driving control from the video signal using the correction signal. An imaging device characterized by having the above.

[0284] (Configuration 2) The imaging device according to Configuration 1, characterized in that the correction signal is a signal read out from the reading part without transferring the charges generated in the photoelectric conversion part to the reading part.

[0285] (Configuration 3) The imaging device according to Configuration 1, characterized in that the correction signal is a signal read out from the reading part without transferring the charges generated in the photoelectric conversion part to the charge holding part.

[0286] (Configuration 4) The imaging device according to any one of Configurations 1 to 3, further comprising a correction position determination part for determining a row position for performing the correction processing, and the correction part performs correction for the correction position determined by the correction position determination part.

[0287] (Method) An imaging method using an imaging device having a plurality of pixels, each pixel including a photoelectric conversion unit that generates charges by photoelectric conversion, at least two charge holding units that hold the charges, a transfer unit that transfers the charges from the photoelectric conversion unit to at least two of the charge holding units respectively, a charge discharge unit that discharges the charges accumulated in the photoelectric conversion unit, and two or more readout units that respectively read out signals corresponding to the amounts of the charges transferred from at least two of the charge holding units, the method comprising: performing batch driving control for simultaneously driving at least one of the transfer unit and the charge discharge unit for the plurality of pixels; simultaneously reading out a video signal based on the charges generated in the photoelectric conversion unit and a correction signal not based on the charges generated in the photoelectric conversion unit from two or more of the readout units; and performing correction processing for noise generated by the batch driving control on the video signal using the correction signal.

[0288] (Program) A computer program for controlling each part of the imaging device according to any one of Configurations 1 to 4 by a computer.

[0289] Note that, in order to implement part or all of the control in the above embodiment, a computer program for implementing the functions of the above-described embodiment may be supplied to an imaging device or the like via a network or various storage media. Then, a computer (or a CPU, MPU, etc.) in the imaging device or the like may read out and execute the program. In that case, the program and the storage medium storing the program constitute the present invention.

Explanation of Reference Numerals

[0290] PD: Photoelectric conversion unit M1, M3: Transfer transistor M4, M8, M11: Reset transistor M5, M9, M12: Amplification transistor M6, M10, M13: Selection transistor M7: Charge discharge transistor MEM: Charge holding unit FD: Floating diffusion section 10: Pixel section 12: Pixel 14: Control line 16a: Vertical output line 16b: Vertical output line 16c: Vertical output line 20: Vertical scanning circuit 30: Readout circuit 40: Horizontal scanning circuit 50: Output circuit 60: Drive control circuit 100: Photoelectric conversion device 200: Imaging system 201: Imaging device 202: Lens 204: Diaphragm 208: Signal processing section 210: Memory section 212: External interface section (External I / F section) 214: Recording medium 216: Recording medium control interface section (Recording medium control I / F section) 218: Control section 220: Timing generation section 300: Correction positioning section 301: Correction value generation section 302: Correction section

Claims

1. having a plurality of pixels, each pixel comprising: a photoelectric conversion unit that generates electric charges by photoelectric conversion; at least two charge holding units that hold the electric charges; a transfer unit that transfers the electric charges from the photoelectric conversion unit to at least two of the charge holding units respectively; a charge discharge unit that discharges the electric charges accumulated in the photoelectric conversion unit; two or more readout units that respectively read out signals corresponding to the amounts of the electric charges transferred from at least two of the charge holding units; performing batch drive control for simultaneously driving at least one of the transfer unit and the charge discharge unit for the plurality of pixels, and a control unit that simultaneously reads out a video signal based on the electric charges generated in the photoelectric conversion unit and a correction signal not based on the electric charges generated in the photoelectric conversion unit from two or more of the readout units; an imaging device, comprising: a correction unit that performs correction processing of noise generated by the batch drive control from the video signal using the correction signal.

2. The imaging device according to claim 1, wherein the correction signal is a signal read out from the readout unit without transferring the electric charges generated in the photoelectric conversion unit to the readout unit.

3. The imaging device according to claim 1, wherein the correction signal is a signal read out from the readout unit without transferring the electric charges generated in the photoelectric conversion unit to the charge holding unit.

4. further comprising a correction position determination unit that determines a correction position for performing the correction processing, The imaging device according to claim 1, wherein the correction unit performs correction on the correction position determined by the correction position determination unit.

5. An imaging method using an imaging device having a plurality of pixels, each pixel comprising: a photoelectric conversion unit that generates electric charges by photoelectric conversion; at least two charge holding units that hold the electric charges; a transfer unit that transfers the electric charges from the photoelectric conversion unit to at least two of the charge holding units respectively; a charge discharge unit that discharges the electric charges accumulated in the photoelectric conversion unit; and two or more readout units that respectively read out signals corresponding to the amounts of the electric charges transferred from at least two of the charge holding units, the method comprising: performing batch drive control for simultaneously driving at least one of the transfer unit and the charge discharge unit for the plurality of pixels, and simultaneously reading out a video signal based on the electric charges generated in the photoelectric conversion unit and a correction signal not based on the electric charges generated in the photoelectric conversion unit from two or more of the readout units, An imaging method, characterized in that correction processing of noise generated by the batch driving control is performed on the video signal using the correction signal.

6. A computer program for controlling each part of the imaging apparatus according to any one of claims 1 to 4 by a computer.

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