SYSTEM FOR AND METHO OF GENERATING NETWORK ON CHIP (NoC) USING INCREMENTAL TOPOLOGY SYNTHESIS FOR OPTIMIZATION OF SWITCH

Abstract

To provide a system and a method of generating a network-on-chip (NoC) using sets of restrictions and inputs in order to produce or generate a NoC having all elements satisfying defined restrictions while avoiding deadlock.SOLUTION: A synthesis tool receives an input from a user through a data file or an input on a graphical user interface (display), generates a NoC from a set of physical restrictions and performance restrictions, and generate a NoC having all elements. This is authenticated and satisfies the restrictions. The synthesis tool receives, as an input, a performance scenario or performance requirement which can be used to transform an existing topology so as to satisfy newly added requirements. The tool discriminates and re-uses a switch in order to reduce the number of switches. An output obtained as a result represents a network, such as the NoC, that satisfies the requirements.SELECTED DRAWING: None

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 543,028, filed on October 6, 2023, entitled "SYSTEM AND METHOD FOR GENERATION OF NETWORKS - ON - CHIP(NoCs)USING INCREMENTAL TOPOLOGY SYNTHESIS FOR OPTIMIZATION OF SWITCHES" by Amir CHARIF et al., the entire disclosure of which is incorporated herein by reference.

[0002] Technical Field This technology is in the field of electronic system design, and more particularly, relates to generating network - on - chip (NoC).

Background Art

[0003] Background A multiprocessor system that communicates through one or more network-on-chips (NoCs) is implemented within a system-on-chip (SoC). The SoC includes instances of intellectual property (IP) that use the NoC for communication. Examples of IP include initiators and targets. An initiator sends data, which can be a transaction, to a target. Transactions in the form of packets are sent from the initiator to one or more targets using an industry standard protocol. An initiator connected to the NoC through a network interface unit (NIU) uses an address to select a target and sends a request transaction to the target. The NoC decodes the address and forwards the request from the initiator to the target. The target processes the transaction and sends a response transaction that is forwarded back to the initiator by the NoC. The NoC is an example for designing a scalable communication architecture for the SoC. When using the NoC for design purposes, it is more desirable to eliminate conditions that cause deadlocks in the network. Currently, it is known to route messages through an array of data processing nodes to facilitate multiple paths being directed towards a destination without causing message delays due to routing deadlocks. An important aspect in designing an application-specific NoC is more desirable deadlock-free operation using minimal power and area overhead. There are two main types of deadlocks known to occur in the NoC. The first type of deadlock is routing-dependent deadlock. The second type of deadlock is message-dependent deadlock.

[0004] Given a set of performance requirements such as connectivity and latency between a source and a destination, frequencies of various elements, maximum area available for NoC logic, minimum throughput between the source and the destination, and the location on the floorplan of elements attached to the NoC, creating an optimal NoC that meets all requirements with a minimum amount of logic and wires is a complex task. This is typically the job of a chip architect or chip designer to create this optimal NoC, which is a difficult and time-consuming task. In addition to this being a difficult task, the design of the NoC is usually modified whenever one of the requirements changes, such as a modification to the chip's floorplan or a modification that affects the expected performance. As a result, this task needs to be frequently re-run over the course of the chip's design time. This process is time-consuming and results in manufacturing delays. Therefore, there is a need for a system and method for efficiently generating a NoC from a set of constraints enumerated as requirements and a set of element inputs. The system needs to generate a NoC that meets the constraints and has all its elements placed on the chip's floorplan.

[0005] Reusing existing topologies is difficult and the manufacturing costs associated with wiring are expensive, so there are current problems during NoC synthesis of new connections in existing NoCs. One problem that exists is to verify that the existing NoC provides sufficient bandwidth to handle some of the communication scenarios given as inputs.

[0006] Another problem is that there is no tool that can automatically configure the NoC in an optimal way to ensure that it has sufficient bandwidth to handle some of the communication scenarios that can be given as inputs.

[0007] Another problem is that, as a result of synthesizing a set of connections in the NoC and reusing wires to minimize the global wire cost, there may be too many switches created. Therefore, there is a need for a system and method that can significantly reduce the number of switches created during the synthesis process without requiring a slow post-processing step (i.e., switch clustering) to globally regroup switches based on proximity.

[0008] Another problem exists when the NoC topology is synthesized (even if all performance scenarios are known initially), and the configuration process is not guaranteed to find a solution to support the execution of some user-provided performance scenarios. The newly created NoC (generated by topology synthesis or created manually) may not support the load generated by the scenario.

[0009] Another problem exists in that it is difficult and time-consuming to define all of the scenarios necessary to obtain a particular traffic distribution when a designer provides performance requirements to a NoC generation tool or topology synthesis process by defining a set of scenarios that are sets of communications that occur in parallel at a given speed to drive the shape of the topology using performance constraints, and it is very difficult to input.

[0010] Another problem that occurs when performing environmental NoC synthesis occurs after a specification change. For example, when new connections are added, previous results are overwritten. Therefore, there is a need for a method for designing a NoC that avoids both routing-dependent deadlocks and message-dependent deadlocks and is integrated with the topology synthesis phase of the NoC design flow. Considering the deadlock avoidance issue during topology synthesis, a more desirable NoC design can be achieved compared to conventional methods where the deadlock avoidance issue is managed separately. Additionally, it is necessary to add new connections without overwriting previous results. SUMMARY OF THE INVENTION

Means for Solving the Problem

[0011] Overview According to various embodiments and aspects of the present invention, a system and method for generating a network-on-chip (NoC) using a set of constraints and inputs to produce or generate a NoC having all elements that satisfy defined constraints while avoiding deadlocks are disclosed.

[0012] Further systems and methods are shown that are implemented by a tool that significantly reduces the number of switches created during the synthesis process without requiring a slow post-processing step to globally re-group switches based on proximity.

[0013] The elements of the NoC are placed on the floorplan of the chip. An advantage of the present invention is the simplification of the design process and the work of the chip architect or designer. The NoC generation or synthesis method has an incremental design in which the NoC generates or synthesizes one connection at a time. In particular, a set of source-destination pair nodes and each new connection are synthesized by taking the set of existing connections as input. New components, including but not limited to switches and / or links, may be created when synthesizing a new connection to define a network route from source to destination. It is within the scope of the present invention to include that the destination is, among other things, a list of components to be traversed. Further, configuring newly created components, including but not limited to clock and / or data width, is an important aspect when synthesizing a new connection.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0015] Detailed Description In the following, various examples of the present technology will be described that illustrate various aspects and embodiments of the present invention. In general, the examples can use the described aspects in any combination. All descriptions in this specification listing principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both their structural and functional equivalents. Furthermore, such equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any element developed that performs the same function regardless of its structure.

[0016] Note that as used in this specification, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Throughout this specification, references to "one aspect", "an aspect", "a particular aspect", "various aspects", or similar language mean that a particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the present invention.

[0017] Throughout this specification, the appearances of the phrases "according to one or more embodiments", "in one embodiment", "in at least one embodiment", "in an embodiment", "in a particular embodiment", and similar language are not necessarily all referring to the same embodiment or similar embodiments, although they may. Further, the aspects and embodiments of the invention described herein are merely illustrative and should not be construed as limiting the scope or spirit of the invention. The disclosed invention is effectively made or used in any embodiment that includes any novel aspect described herein. All descriptions in this specification listing the principles, aspects, and embodiments of the invention are intended to encompass both their structural and functional equivalents. Such equivalents are intended to include both currently known equivalents and equivalents developed in the future.

[0018] As used herein, "initiator" refers to similar intellectual property (IP) modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, "target" refers to similar IP modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, a transaction can be a request transaction or a response transaction. Non-limiting examples of request transactions include write requests and read requests.

[0019] As used herein, a node is defined as a distribution point and / or communication endpoint that can create, receive, and / or transmit information via a communication path or channel. A node can refer to any one of a switch, splitter, merger, buffer, and adapter. As used herein, splitters and mergers are switches. However, not all switches are splitters or mergers. As used herein, according to various aspects and embodiments of the present invention, the term "splitter" refers to a switch having a single input port and multiple output ports. As used herein, according to various aspects and embodiments of the present invention, the term "merger" refers to a switch having a single output port and multiple input ports.

[0020] In one embodiment, the set of existing connections may be empty. As a result, the NoC is synthesized from the start of the process without existing connections.

[0021] The order in which connections are made affects the quality of the topology. In one embodiment, the order may be determined based on multiple mathematical optimization techniques and / or heuristics. For example, the order may be determined by the area of the floorplan that the connection reaches. In another example, the order may be a latency-based communication policy configured to measure the delay of packet arrival at the destination and perform more secure connections with higher priority. It is within the scope of the present invention that the synthesis order is an input to a method for deterministic and incremental physical-aware NoC topology synthesis.

[0022] A system configured to automatically generate or synthesize a deadlock-free NoC from a specification includes a floorplan that is the physical layout of the chip, technical parameters including but not limited to wire delay and / or logic density, a floorplan area including but not limited to modules and / or clock constraints, a clock domain crossing (CDC) that is the crossing of signals in a synchronous digital circuit from a first clock domain to a second clock domain, performance requirements, a configuration and location on the floorplan, a connectivity requirement between a first component and a second component, and components having a communication policy between the first component and the second component.

[0023] A method of converting an existing deadlock-free network-on-chip (NoC) configuration, the existing deadlock-free network-on-chip configuration including a plurality of existing physical segments and a set of existing turns that are acceptable between segments, the plurality of existing physical segments and the set of existing turns forming a plurality of existing routes. The method includes generating a new NoC configuration by generating and / or synthesizing at least a first new connection into the existing deadlock-free network-on-chip configuration, the first new connection having a source and a destination, and generating including creating a first new deadlock-free route from the source to the destination, whereby the new network-on-chip configuration is deadlock-free, and generating the first new deadlock-free route from the source to the destination preserves the existing routes.

[0024] Generating involves, for each existing route, converting the route into segments and turns and identifying one or more new connections to be synthesized, where each of the plurality of new connections has an undefined route, a source, and a destination associated therewith, identifying one or more new connections to be synthesized, which are identified along with a synthesis order, and for each of the one or more new connections, identifying a plurality of possible routes from the source to the destination for the new connection according to a sort. The method includes the above steps.

[0025] Possible routes include a new ingress segment connecting the source to an existing deadlock-free NoC configuration, a new egress segment connecting the existing deadlock-free network-on-chip configuration to the destination, and one or more new internal segments connecting existing segments of the existing deadlock-free network-on-chip configuration, whereby the one or more new internal segments connect the source to the destination. The new internal segments generate periodic dependencies between segments, and whether a deadlock occurs thereby is not considered. The possible routes include one or more of only the new internal segments and the existing segments.

[0026] Generating also involves filtering a plurality of possible routes based on one or more criteria, where the one or more criteria include communication policy criteria based on the allowable latency of the route from the source to the destination of the new connection and any of a plurality of user-defined criteria. The generating further includes filtering, selecting one of the plurality of possible routes for synthesis, and / or synthesizing the selected possible route into the existing deadlock-free network-on-chip configuration.

[0027] According to one or more embodiments of the present invention, the first new deadlock-free route includes at least one of an existing physical segment and a new physical segment.

[0028] According to one or more embodiments of the present invention, generating a first new deadlock-free route from a source to a destination retains all existing routes.

[0029] According to one or more embodiments of the present invention, generating a new deadlock-free route is incrementally repeated.

[0030] According to one or more embodiments of the present invention, identifying a synthesis order includes sorting one or more new connections according to a heuristic.

[0031] According to one or more embodiments of the present invention, at least a portion of an existing segment is physically unchanged.

[0032] According to one or more embodiments of the present invention, the end point of at least a portion of an existing segment is a switch. The switch is physically unchanged.

[0033] According to one or more embodiments of the present invention, any component is logically changeable such that at least one existing component is reconfigured in response to the resulting new topology.

[0034] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a route that maximizes the use of an existing deadlock-free network-on-chip configuration, where existing segments are made physically unchanged except for input and output segments, switches are made physically unchanged, and at least one network element is made logically unchanged.

[0035] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis includes selecting a route that minimizes the latency of the route.

[0036] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis involves selecting a route that maximizes the use of an existing deadlock-free network-on-chip configuration, where existing segments are not physically altered, switches are enabled to have new connections, and existing network elements are logically unchanged, which includes keeping the clock frequency and other attributes unchanged.

[0037] According to one or more embodiments of the present invention, selecting one of a plurality of possible routes for synthesis involves selecting while existing segments are not physically altered, switches are enabled to have new connections, and existing network elements are reconfigurable.

[0038] A method for incrementally synthesizing and transforming a deadlock-free network-on-chip topology includes receiving an input that is a network topology. The network topology is transformed into existing segments, and the method includes reusing the existing segments within a new route, where the existing segments are formed by a path between a first node and a second node; recursively splitting the existing segments at any point along the path between the first node and the second node to form split segments; synthesizing a new route by adding new segments and new turns to the split segments in response to the splitting; and generating a deadlock-free network-on-chip topology by routing packets from turns of the existing segments to new segments to avoid deadlocks in the network.

[0039] According to one or more embodiments of the present invention, identifying a synthesis order includes sorting one or more new connections according to a heuristic.

[0040] According to one or more embodiments of the present invention, at least a portion of an existing segment is physically unchanged.

[0041] According to one or more embodiments of the present invention, the endpoints of at least a portion of an existing segment are switches. The switches are physically unchanged.

[0042] According to one or more embodiments of the present invention, any component is logically changeable such that at least one existing component is reconfigured in response to the resulting new topology.

[0043] A non-transitory computer-readable medium for storing code, which, when executed by one or more processors, causes the processors to receive an input topology of a network-on-chip (NoC) to determine source-destination pairs and at least one existing connection selected for synthesis, transfer the source-destination pairs into pairs of segments, transfer at least one existing connection into pairs of existing segments, determine whether the NoC is deadlock-free, in response to the determination that the NoC is deadlock-free, extract pairs of segments having no defined routes and sort them using heuristics, input the pairs of segments and the pairs of existing segments into a configuration explorer, where the configuration explorer uses a communication policy to determine a configuration for routing from the source to the destination of the source-destination pair, the communication policy being configured to receive user-defined parameters associated with the source-destination pair, the communication policy communicating with a configuration filtering module configured to output eligible configurations, inputting, using a configuration selection module, selecting a final configuration to be implemented to connect the source-destination pair, splitting the pairs of existing segments that need to be connected to the pairs of segments at points indicated by the final configuration, creating new segments indicated by the final configuration, activating corresponding turns to connect the pairs of existing segments to the pairs of segments, and calculating a route from the source to the destination of the source-destination pair.

[0044] Referring now to FIG. 1A, a network-on-chip (NoC) 100 according to various aspects and embodiments of the present invention is shown. The NoC 100 is an example of a network. According to various aspects and embodiments of the present invention, a network includes a set of nodes and a set of edges, each of which has a model, performs and implements transformations on the network, and can be used at the center of synthesis to converge to the best solution that meets the specified requirements. The NoC 100 includes nodes and endpoints, and uses assembled basic network functions such as network interface units (NIUs) 102, 104, 106, 108, 110, 112, 130, 132, and 134, nodes / switches 114, 116, 118, 120, and 122, adapters such as adapter 126, and buffers such as buffer 124. The NoC basic network functions typically use an internal transport protocol specific to the NoC 100 to communicate with each other based on packet transmission. The NIU converts the protocol used by an attached system-on-chip (SoC) unit (not shown) into the transport protocol used inside the NoC 100. The switch routes the flow of traffic between the source and the destination. The buffer 124 is used to store packets to insert pipeline elements for long-distance reach, or to handle rate adaptation between a high-speed transmitter and a low-speed receiver, or vice versa. The adapter 126 handles various conversions between data width domains, clock domains, and power domains.

[0045] Referring now to FIG. 1B, a NoC 150 having various elements such as NIUs, switches, and blocked regions within a floorplan is shown. The NoC 150 includes various connection elements through various switches. According to one aspect of the present invention, a set of constraints is used as input to a tool, which will be described in more detail below. According to some aspects of the present invention, the tool executes a set of sub-steps and uses the configured elements and the positions of each element on the floorplan to generate a description (synthesis) of the resulting NoC, such as NoC 150. The generated description is used to actually implement the NoC hardware using the physical information generated to provide guidance to the backend implementation flow.

[0046] Referring now to FIG. 2A, according to some aspects of the present invention, a set of constraints (210, 212, 214, 216, and scenarios) is provided to a synthesis tool 220. According to some embodiments and aspects of the present invention, the performance and functionality of the tool 220 can include third-party ASIC implementation tools such as logic synthesis, placement, and route backend tools. A designer or user constructs the set of constraints provided to the tool 220. The constraints are taken in a machine-readable format, such as a computer file, using a format defined to capture information that can be understood and processed by the tool. According to one aspect of the present invention, the format is XML. According to another aspect of the present invention, the format is JSON. The scope of the present invention is not limited by the particular format used.

[0047] Referring to FIG. 2B, the tool reads a file containing a description of the constraints and executes the synthesis process. According to some aspects of the present invention, the synthesis process is divided into a plurality of steps. A sequencer 250 is responsible for executing each step of the process. According to some aspects of the present invention, a set of steps is executed by the sequencer 250 of the tool 220 in light of the constraints indicated by the user / designer. The scope of the present invention is not limited by the number and types of steps that the sequencer 250 can call and execute.

[0048] Referring again to FIG. 2A in conjunction with FIG. 2B, according to various aspects of the present invention, a network designer provides and defines a set of constraints such as constraints 210, 212, 214, and 216. The sequencer 250 receives various inputs including an input 251 that includes a global integration roadmap having connectivity between initiators and targets, including roadmap creation and information between each initiator and target; an input 252 that includes traffic classification and main switch creation; an input 254 that includes main switch decomposition to mergers and splitters; an input 258 that includes information regarding the physical distribution of splitters and mergers in the roadmap; an input 259 that includes information regarding edge clustering; and an input 260 that includes information regarding performance recognition node clustering. According to one aspect of the present invention, the sequencer 250 also receives an input 262 that includes information regarding optimization and network reconstruction. According to one aspect of the present invention, the sequencer 250 receives 264 that includes information regarding routing and legalization. According to various aspects and embodiments of the present invention, the sequencer 250 uses all of the inputs 251-264 to generate a network. According to various aspects and embodiments of the present invention, the sequencer 250 uses a combination of the inputs 251-264 to generate a network.

[0049] According to various aspects of the present invention, input 251 includes an input regarding a global integration roadmap. The global integration roadmap includes an integration model that captures a global physical view of the connectivity of the free space in the floor plan, as well as the connectivity across / between initiators and targets. The global integration roadmap is modeled by a graph of physical nodes and canonical segments used to position the (splitter, merger, switch, adapter) nodes of the network being built. The global integration roadmap is used to fix the calculation. According to various aspects of the present invention, the global integration roadmap is persistent, which means that it is data that the system exports and re-consumes in incremental synthesis and subsequent execution.

[0050] According to some aspects of the present invention, input 259 includes information regarding edge clustering. Edge clustering aims to minimize resources and improve performance goals by appropriate algorithms and techniques. According to some aspects of the present invention, edge clustering works in conjunction with and is applied in cooperation with input 260, i.e., node clustering. Edge clustering and node clustering can be used in combination by being applied simultaneously by mixing, or by being applied sequentially. The advantages and goals are to expand the scope of synthesis and reach a larger solution space for the network.

[0051] According to various aspects of the present invention, the input 262 includes information regarding reconstruction. The reconstruction includes various transformations and capabilities. According to some aspects of the present invention, the transformation is logical in that there is a change in the structure of the network. According to some aspects of the present invention, the transformation is physical because there is a physical change in the network, such as moving a node to a new position. Other examples of reconstruction include splitting a node into smaller nodes, changing the parent between nodes, replicating a network sub-part to avoid deadlocks and handle congestion, and physically re-routing links to avoid congestion areas or to meet timing constraints.

[0052] Referring now to FIG. 3, according to various aspects of the present invention, a floorplan 300 of a chip on which a NoC is implemented is shown, having various initiator interfaces and target interfaces. Physical constraints 210 provide physical information regarding the design, including the size of the chip on which the NoC is implemented, various blocked regions on the floorplan that are rectangles representing regions of the chip where NoC logic cannot exist or be placed, free space defined by regions not covered by the blockages, and the locations of interfaces between the SoC unit and the NoC, which are the locations of initiator interfaces and target interfaces such as NIUs.

[0053] According to various aspects of the present invention, another constraint includes extending the clock domain, and a power domain 212 may also be provided. The domain 212 includes the regions of the chip where it is possible to place logic belonging to a particular domain.

[0054] According to various aspects of the present invention, the functionality of the logic library used to implement the NoC is provided. This information includes the size of the reference logic gates and the time it takes for a signal to cover a distance of 1 mm.

[0055] Referring back to FIG. 2A, according to various aspects of the present invention, the SoC includes a plurality of clock domains and a plurality of power domains. A clock domain is defined by all of the logic supplied by a given clock input. The clock input is characterized by the frequency of the clock, which is its most important parameter. A power domain is defined by all of the logic that receives power from the same power supply. According to various aspects of the present invention, the power supply is gated, and thus, the power domain can be turned on or off, or separated from other power domains. Thus, the designer provides a set 212 of clock domain constraints and power domain constraints as part of the initial design.

[0056] According to various aspects of the present invention, the initiator and the target are communicatively connected to the NoC. The initiator is a unit that sends requests, typically read and write commands. The target is a unit that services or responds to requests, typically read and write commands. Each initiator is attached or connected to the NoC through an NIU. The NIU attached to the initiator is called an Initiator Network Interface Unit (INIU). Further, each target is attached to the NoC through an NIU. The NIU attached to the target is called a Target Network Interface Unit (TNIU). The main function of the NoC is to carry each request from the initiator to the desired destination target, and when the request requires or needs a response, the NoC carries the response of each target to the corresponding requesting initiator. The initiator and the target have many different parameters that characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which they belong are defined. The width of the data bus they use to send and receive write and read payloads is the number of bits. According to various aspects of the present invention, the width of the data bus (communication path between the target) for the connection used to send write requests and receive write responses is also defined. Further, the definition of the clock and power domains is a reference to the aforementioned clock and power domains existing in the SoC as described herein.

[0057] Continuing to refer to FIGS. 2A and 2B and also referring to FIG. 4, a connection table 400 is shown. According to various aspects of the present invention, table 400 enables traffic to be defined by classification. This tool enables the use of traffic class labels for each connection between an initiator and a target. As shown in table 400, there are three traffic classes: L1, L2, and L3. The traffic class label is any label selected by a user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. Each label represents the need for independent network resources. Each label is given a separate subnetwork by the present invention, which can be physically different or, if supported by the underlying NoC technology, can use virtual networks.

[0058] According to various aspects of the present invention, it is not necessary for an initiator to be able to send requests to all targets or to the targets connected to the NoC. The exact definition of the targets that can receive requests from an initiator is outlined or described in a connection table such as table 400. Connectivity and traffic class labeling information can be represented as a matrix. Each initiator has a row and each target has a column. If an initiator has to send traffic to a target, there must be a traffic class label at the intersection between the initiator row and the target column. If there is no label at the intersection, the tool does not require connectivity between that initiator and that target. For example, initiator 1 (M1) is communicatively connected to target 1 (S1) using the defined label 1 (L1), but M1 does not communicate with S2, and thus there is no label at the intersection between M1 and S2. According to various aspects of the present invention, the actual format used to represent connectivity can vary as long as each pair of initiator - target combinations has an exact definition of its traffic class or has no classification label if there is no connection.

[0059] Referring now to FIG. 5, Table 500 according to various aspects of the present invention is shown, including various scenarios of read (RD) and write (WR) transactions (shown in FIG. 2A). Table 500 includes information defining various throughput rates provided to the tool. A scenario defines the predicted performance regarding the throughput of data between an initiator and a target. Each scenario describes the predicted required read bandwidth and the predicted required write bandwidth between each initiator and each target. Throughput is defined in units of bytes per second (B / s). A typical SoC has multiple operating modes. As an example, an SoC for a smartphone can have a game operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that depend on different throughput rates. Thus, the set of scenarios represents the different operating modes supported by the SoC and, correspondingly, the predicted NoC minimum performance regarding the throughput between the initiator and the target.

[0060] Scenarios can be represented as two matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the present invention, the read throughput requirement is used to size the response network that processes data returning from the target to the initiator. The write throughput requirement is used to size the request network, which is data moving from the initiator to the target, according to various aspects of the present invention. An example of the throughput requirements for various scenarios according to various aspects of the present invention is shown in Table 500. The actual format used to represent a scenario can vary as long as each pair of (initiator, target) has an exact definition of the minimum throughput required for read and write. In Table 500, the read transaction from M1 to S1 has a minimum performance throughput of 100 MB / s. In Table 500, the write transaction from M1 to S1 has a minimum throughput of 50 MB / s.

[0061] According to some aspects of the present invention, the tool scenario is not defined, in which case the tool optimizes the NoC synthesis process for physical costs such as minimum gate cost and / or minimum wire cost.

[0062] Referring now to FIG. 6 in conjunction with FIG. 2B, an initial network 600 is created according to various aspects of the present invention. Network 600 implements a connectivity matrix having the following defined parameters or components.

[0063] · One network interface unit per initiator, · One network interface unit per target, and · One switch is created per defined traffic class, called the main switch of the class, · One switch after each initiator / initiator NIU that splits traffic to different main switches that this initiator needs to reach, · One switch before each target / target NIU that merges traffic from different main switches that are sending traffic to that target The data width of each switch and the clock domain to which it belongs are calculated using the data width of each attached interface and their clock domains as input to the tool. According to various aspects of the present invention, each step of converting a network that is part of the NoC also performs the calculation of the data width and clock domain of the newly created network elements.

[0064] Referring now to FIGS. 7 and 2B, network 600 of FIG. 6 is shown, and the tool processes the transformation of network 600 in accordance with various aspects of the present invention. Sequencer 250 has an input 254 that represents the main switch decomposition to the merger and splitter. This tool decomposes each main switch of network 600 into an equivalent implementation using splitters and mergers. According to various aspects of the present invention, some switches have a single input port and multiple output ports. According to various aspects of the present invention, some switches have multiple input ports and a single output port. Each main switch input port is connected to a splitter, and each main switch output port is connected to a merger. In the case of a main switch, the splitter and the merger are both connected according to a connection table.

[0065] Referring now to FIG. 8, a floor plan 800 according to various aspects of the present invention is shown. Sequencer 250 has an input 256 that represents the roadmap creation between each initiator and target. Floor plan 800 includes a physical path 802 that is calculated between an initiator interface (M0) on the floor plan and each of its connected targets such as target S0, target S1, target S2, and target S3. Path 802 is referred to as the splitter roadmap of initiator M0, while although not shown, all initiators have a splitter roadmap. The tool uses any algorithm suitable for finding a path between a source point and multiple destination points, including an algorithm that minimizes the length of the path.

[0066] Referring now to FIG. 9, floor plan 800 has a calculated physical path 902 between the target interface of target S0 on the floor plan and each initiator connected thereto. Path 902 is the merge load map of target S0. As is apparent, all targets have a merge load map. The tool uses any algorithm suitable for finding a path between a plurality of source points and a plurality of destination points that can be used, including an algorithm that minimizes the length of the path. According to various aspects of the present invention, the tool maintains its functionality and transforms the network to add location information to network elements.

[0067] Referring now to FIG. 10, a floor plan 800 having a path 1002 according to various aspects of the present invention is shown. Sequencer 250 has an input 258 that provides the physical distribution of splitters and mergers on the load map. Using this tool, each switch is broken down into mergers and splitters. Using the tool, each splitter within the main switch is further broken down into a cascade of splitters, and each splitter in the cascade is placed at a branch point of the splitter load map of the attached initiator. A branch point of the load map is defined by the fact that the path is split into two or more branches.

[0068] Referring now to FIG. 11, a floor plan 800 having a path 1102 according to various aspects of the present invention is shown. Using a tool, for each switch of each merger within the main switch, the merger is further decomposed into a cascade of mergers, and each merger of the cascade is placed at a branch point of the attached target merger load map. A branch point of the load map is defined by the fact that the path is split into two or more branches. The process of decomposing a splitter into a cascade of splitters retains the original splitter function because the number of inputs to the cascade remains one and the number of outputs of the cascade is the same as the number of outputs of the original splitter. The process of decomposing a merger into a cascade of mergers retains the original merger function because the number of outputs of the cascade remains one and the number of inputs to the cascade is the same as the number of inputs to the original merger. According to various aspects of the present invention, the effect of the process is to obtain a set of basic switches represented by mergers and splitters that are physically placed near where the actual connections between switches are required.

[0069] According to various aspects of the present invention, the tool transforms the network to reduce the number of wires used between achievable switches while maintaining the performance defined in a scenario that is the set of required minimum throughputs between an initiator and a target. According to various aspects of the present invention, switches are clustered for performance-aware switching, and mergers and splitters distributed on the load map are treated the same as normal switches.

[0070] According to one aspect of the present invention, the tool uses an iterative process to merge switches under conditions where performance is still met until no further switch merges are possible. The tool uses the process described as follows.

[0071] 1) While no further switch fusions are possible, do the following. a) Select a candidate switch for fusing with one of its neighboring switches. The selection process ensures that all switches in the network are ultimately candidates.

[0072] b) Once a candidate is selected, search for a neighboring switch to fuse with. The neighboring criterion is based on the evaluation of a cost function. The cost function shall return the "most suitable" switch for fusing with the aspirant. The definition of "most suitable" depends on the embodiment, but the cost function shall be such that the potential fusion of two switches maximizes the gain with respect to at least one metric including wire length, logical area, power, and performance.

[0073] c) Test whether the performance scenario still meets all minimum throughput requirements if a fusion occurs. If not, these two switches cannot be merged. The process executed by the tool searches for another neighboring switch until no more neighboring switches can be found, in which case all switches are left as they are, or searches for another neighboring switch until one neighboring switch that can be merged with the candidate without violating the minimum throughput requirements of all scenarios is found, in which case the network is modified by merging the candidate switch with the neighboring switch.

[0074] According to various aspects of the present invention, the process can ensure that switches do not grow larger than a specific size (maximum number of ingress ports, maximum number of egress ports). If the combined switch exceeds a set threshold, the merge is prevented.

[0075] Referring now to FIG. 12, candidate switch SW3 is shown adjacent to switch SW4 for the merger according to various aspects of the present invention. Sequencer 250 has an input 260 that provides performance recognition switching clustering. The tool performs a process of merging two switches. When the switches are merged, wires that were coming from different switches are simplified into one wire from each of the connected switches to the merged switch. According to various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1, SW4, and SW3 are combined and replaced with a single connection between SW1 and SW3_4. Thus, long connections between distant switches are removed and minimized, while connections between nearby switches are removed and done inside the switches themselves.

[0076] Referring again to FIG. 2B, input 262 to sequencer 250 includes various optimizations that can be implemented to further reduce the number of wires used by the network, the area of network elements, and the power consumed by network elements. Examples of such optimizations include detection of links that can be removed because they are not being used or because their traffic can be re-routed, reducing the width of a link if the link is wider than required by the scenario, and performing wire length optimization by finding the optimal placement of all switch elements to minimize the total wire length of the network, where the total wire length of the network is the sum of the values obtained by multiplying the width of each connection between network elements by the distance that connection spans, including performing wire length optimization.

[0077] Continuing to refer to FIG. 2B, the input 264 to the sequencer 250 generates an authenticated NoC by modifying the location of network elements such that the network elements fit into the allocated free space, do not overlap, and are within the corresponding clock and power domain limits. According to various aspects of the present invention, the area occupied on the die by each network element is calculated using information provided regarding the capabilities of the technology, such as the area of a reference logic gate. Next, each element is tested for the accuracy of its placement (sufficient free space exists for the element and no other elements overlap). If the test fails, the element is moved until a suitable location is found that passes the test.

[0078] Format Referring now to FIG. 13, the floorplan 1300 shows a deadlock-free NoC that can be represented with respect to a plurality of segments and turns. The segments represent directed channels between two components, e.g., between "A" 1311 and "B" 1301, between "B" 1301 and "C" 1302, between "C" 1302 and "D" 1303, and / or between "D" 1303 and "A" 1311. The first segment 1304 holds the physical path in the floorplan between "A" 1311 and "B" 1301, the second segment 1305 holds the physical path in the floorplan between "B" 1301 and "C" 1302, the third segment 1306 holds the physical path in the floorplan between "C" 1302 and "D" 1303, and the fourth segment 1307 holds the physical path in the floorplan between "D" 1303 and "A" 1311, which is a list of physical coordinates (x i , y i ). It is within the scope of the present invention for a segment to have one or more associated cost metrics that can be utilized during synthesis and / or generation to track the cost of a particular routine.

[0079] A pair of segments, a turn, can be utilized to avoid deadlocks within a network. Given permitted turns 1308, 1309, and 1310, the network remains deadlock-free as long as there are no cycles between segments. According to another aspect or embodiment of the present invention, there may be cycles between nodes. A turn has dependencies between segments, which is the basic mechanism to ensure that the network is deadlock-free. It is within the scope of the present invention for there to be cycles between nodes so that only the channels necessary to prevent node cycles are allocated, and wires can be reused without causing deadlocks. As a result, this eliminates unnecessary channels and reduces the associated wire costs.

[0080] Referring back to FIG. 13, the presence of a first turn 1308 from a first segment 1304 to a second segment 1305 indicates that a packet can be routed from the first segment 1304 to the second segment 1305. The presence of a second turn 1309 from the second segment 1305 to a third segment 1306 indicates that a packet can be routed from the second segment 1305 to the third segment 1306. The presence of a third turn 1310 from the third segment 1306 to a fourth segment 1307 indicates that a packet can be routed from the third segment 1306 to the fourth segment 1307. Regarding segment splitting, a segment "S1" to "S2" can be split at any point (x i , y i ) of its physical route, resulting in two new segments. Since there is no turn (D, A) approaching (A, B), this network is deadlock-free.

[0081] Referring now to FIGS. 14A - 14D, an embodiment of segment splitting on NoC 1400 is shown. Segment 1403 (FIG. 14A) is defined by nodes "A" 1401 - node "B" 1402. Segment 1403 can be split 1404 (FIG. 14A) at any point (xi, yi) of its physical route into a new first segment 1409A (FIGS. 14B - 14D) and a new second segment 1409B (FIGS. 14B - 14D). FIGS. 14B - 14D best show the result of this split 1404 (FIG. 14A) where a newly created node "S" 1408 (FIGS. 14B - 14D) is formed. A first turn 1405, a second turn 1406 (FIGS. 14B - 14D), and a third turn 1407 are shown.

[0082] FIG. 14B shows the segment splitting of the NoC topology with the split segment "A" 1401 - "B" 1402 updated to use two new sub - segments "A" 1401 - "S" 1408 and "S" 1408 - "B" 1402. The newly created node "S" 1408 is a new switch within the NoC. The set of turns including the split segment is updated to use the two new sub - segments. The new turn 1406 is added while retaining turn 1407.

[0083] Since the split results in segments with variable routes, the split segments are no longer considered "as - is". This recursive representation is essential for incrementality to ensure that segments that are part of an existing route and may need to be split can still be recovered as a series of sub - segments when reconstructing the existing route. By splitting a segment, the segment can be connected to new segments, thereby obtaining a new set of turns.

[0084] FIG. 14C shows a new segment 1411 represented by a channel between node "N" 1410 and node "S" 1408 that is merged into the split segment to result in a new turn 1412.

[0085] Figure 14D shows a new segment 1413 represented by a channel between node "N" 1410 and node "S" 1408 that branches into split segments to result in a new turn 1414. The added node "N" 1410 may include, without limitation, an IP block and / or an initiator.

[0086] According to one aspect and embodiment of the present invention, the system performs a generation and synthesis process, and all existing network routes are converted into segments and turns. In one embodiment, the entire NoC is described as a set of at least one segment, such as defined by a physical path existing between two nodes (S, D). According to various aspects and embodiments of the present invention, if the network is not deadlock-free, according to one or more aspects of the present invention, the network or NoC must first be deadlock-free, so the system provides a "failure" notification and returns it to the user. The system also extracts a set of connections that do not have defined routes and / or connections that need to be synthesized. Given a heuristic, the extracted set of connections is sorted. According to various aspects and embodiments of the present invention, for each connection from source "S" to destination "D", a single connection synthesis process includes using a configuration explorer, a configuration filtering module, a configuration selection module, splitting, creation, and route calculation. Each of the newly created components, switches, and links is configured such that the bandwidth requirements are met by assigning clock domain and data width settings.

[0087] FIG. 15 is a flowchart showing a method 1500 for a NoC generator that uses topology synthesis processing. The input 1503A to be synthesized may be a new connection 1501, and / or the input 1503B may be an existing segment 1502. The new connection 1501 includes creating new components such as switches and / or links, and defining a network route from "S" to "D". The existing segment 1502 may be re-represented as at least one segment and / or a pair of segments having at least one turn. The existing network has a set of turns that cannot be changed. When a new segment is added, the turns associated with the newly added segment are also added to complete the route from "S" to "D". The added turns do not generate cycles and / or deadlocks with the existing turns.

[0088] The configuration explorer 1504 receives the input 1503A, which is a new connection 1501, and the input 1503B, which is an existing segment 1502. Since there are multiple ways to connect segment "S" to "D", the configuration explorer 1504 is influenced by the communication policy 1506 assigned to each segment to determine the best configuration. The configuration explorer 1504 explores various ways to connect "S" to "D" using the exploration of the authentication configuration 1505. The authentication configuration 1505 is a list of the described parameters. The configuration explorer 1504 is configured to traverse the segments to split the segments from the list of meaningful configurations stored in the memory, and to explore and / or consider and analyze at least one configuration indicating a location. The configuration explorer 1504 may have a configuration with a new ingress segment for connecting "S" to any segment of the NoC. If "S" is already connected, it already has an ingress segment. The configuration explorer 1504 can have a configuration with a new egress segment for connection.

[0089] The cost of a given path is updated at each step according to the communication policy 1506. In one example, moving outward from the destination within an existing segment may be more or less costly than creating a new segment that reaches the destination directly, depending on whether the communication policy 1506 prioritizes wire length and / or latency. It is within the scope of the present invention for an established shortest path algorithm to use cost updates as a way to effectively implement some communication policies, explore specific segments, and identify potential future segments.

[0090] The main configuration exploration process 1504 may be designed as a specialized version of a general shortest path algorithm including, but not limited to, A* and / or Dijkstra. A given step in the shortest path algorithm considers different points that can be reached from the current point. The current point is at least one point along the physical path of an existing segment. The path from the current point to subsequent points within the current segment is considered.

[0091] In one embodiment, the path can move one step forward along the path of the current segment. In one embodiment, when the end point of the path of the segment is reached, the path can proceed to the first point within the path of any of the next segments, such as a segment to which the current segment is directly connected and the current segment can "bend".

[0092] In one embodiment, when the destination is not connected, such as when there is no exit segment, the path can jump directly to the destination point. This corresponds to creating a new exit segment. Then, the new exit segment and / or future exit segments are added to the configuration.

[0093] In yet another embodiment, no circular dependencies are created, two segments have compatible communication policies, and the path can jump to any point in any segment as long as the communication policy allows the merge. This corresponds to creating a new internal segment that is added to the configuration.

[0094] Referring again to FIG. 15, the configuration filtering module 1507 has a predetermined list containing data including, but not limited to, which configurations are authenticated, which configurations result in deadlocks, and which configurations are not optimal. The configuration filtering module 1507 filters the configurations given a plurality of criteria including, but not limited to, criteria based on the communication policy 1506 and / or any custom criteria, and retains only a subset. In an example of custom criteria, a user such as a programmer can make the parameter be based on low latency defined by a shorter length between the route from "S" to "D". The user can define the maximum length of the route. The configuration filtering module 1507 of the communication policy 1506 removes a route if the length of the route exceeds a user-defined threshold. In another example, the parameter can be based on the use of a minimum number of extra wires. In another example, the parameter can be based on a cost function that prioritizes the route from "S" to "D" with the lowest cost. The configuration filtering module 1507 is customizable to user-defined parameters. The user can set their own filters and discard specific types of configurations.

[0095] The first criterion is a communication policy 1506 - based criterion. A user can control how a new segment is created. Communication policy 1506 is a set of parameters that can be associated with any given connection within a network. The system may have a plurality of defined communication policies, and each connection may be associated with one communication policy 1506. Communication policy 1506 has parameters and flags. In one example of a flag, low latency is when the connection is made so as to minimize the total path length from the source to the destination. In another example of a flag, enable serialization is when the links included in the path from the source to the destination are enabled to utilize serialization to save wire. Some configurations of a given connection may not be authenticated with respect to the communication policy 1506 that controls the connection. Qualified configuration 1508 is a filtered version of the authenticated configuration. In one example, if the connection "S" to "D" is set to have a low - latency communication policy, restrictions on the total length of the route and the number of hops or components traversed must be applied, and configuration candidates that do not fall within these restrictions are discarded.

[0096] Referring again to FIG. 15, after filtering, the configuration filtering module 1507 outputs a qualified configuration 1508. It is desirable to select one of the qualified configurations implemented by the configuration selection module 1509. Selecting the best configuration is achieved using the configuration selection module 1509, which holds the only final configuration to be implemented as the final composition of the connection "S" to "D". The metric used to select the best configuration is configurable and can take into account several parameters based on the community policy 1506. In one embodiment, the communication policy parameter is the total additional wire length. The length of the segments created additionally creates the wires required to traverse the route. There is a cost associated with the wires. It would be more desirable for the parameter to aim to minimize the total wire length to reduce the cost of the topology. In one embodiment, the communication policy parameter is the total route length. The total length of the route is the combination of the sum of the existing segments and the newly added segments. This parameter focuses on minimizing latency. In another embodiment, the communication policy parameter is based on the bandwidth distribution. This parameter optimizes performance by focusing on the traffic distribution on the segments and the associated congestion levels.

[0097] Once the best configuration 1510 is selected, the system implements 1511 the best configuration 1510 by splitting the segments involved and creating 1512 new segments and turns, and applies it to the network. It is within the scope of the present invention that the best configuration is the final configuration. When segments are split, they are split in all existing segments that need to be connected to the new segments at the points indicated by the selected configuration. For optimization, if the split point is within a certain distance from one of the endpoints of the segment and the endpoint is a switch, the endpoint should be reused for the connection instead of creating a new switch. This can reduce the number of switches created. Create 1512 the necessary new segments as indicated by the selected configuration and activate the corresponding turns. The newly created 1512 segments and turns are input into a routing tool 1513 that combines with the existing 1502 segments and turns to generate the final route 1514. The route is calculated from "S" to "D" given the newly created segments. The route is stored in memory. Since the routing tool 1513 defines the segments in terms of the geographical route along the floor plan, it is a routing connection on the geographical floor plan.

[0098] Figure 16A shows a NoC topology on a floor plan having nodes "S" 1601 to node "D" 1602. If there is an existing network and changes such as a request to add a new connection from node "S" 1601 to node "D" 1602 are requested, it is necessary to perform incremental synthesis. IP blocks are an example of restrictions on the floor plan that the route has to navigate. The existing nodes are connected to each other. It is desirable to create a route for the new connection within the existing network without having to modify the existing structure.

[0099] Figure 16B shows a NoC topology on a floor plan having an incremental synthesis result of a routing configuration from 'S' 1601 to 'D' 1602, with a new ingress segment 1603 having nodes 'S' 1601 and 1606, a new internal segment 1604 having nodes, and an egress segment 1605. The search for the authentication configuration 1505 is shown in the configuration shown in Figure 16B, and if the node is not yet connected to the NoC, the ingress segment 1603 is added. In one embodiment, the new ingress segment 1603 can connect 'S' 1601 to a segment of the NoC. If 'S' 1601 is already connected to a segment of the NoC, it already has an ingress segment.

[0100] In the diagram of Figure 16B, an egress segment 1605 existed because 'D' was already connected to another node. Thus, if 'D' is already connected, it already has an egress segment. The new egress segment can be a configuration option for connecting some segment of the NoC to 'D'.

[0101] Referring again to Figure 16B, it is within the scope of the present invention for any number of internal segments 1604 to exist. At least one and / or a plurality of new internal segments can connect existing segments so that the ingress segment reaches the egress segment. The connection between two existing segments is considered only if it does not create a cyclic dependency between the segments, ensuring that only deadlock-free configurations are considered. The synthesis can include calculating network routes without creating any new switches and / or segments. This applies when both 'S' and 'D' are connected to the network and the ingress segment can already reach the egress segment given only the existing turns. An important aspect of the present invention is that the configuration can define future segments, thereby not creating specific segments in the topology during the search phase.

[0102] In one embodiment, the system can pre-set some common communication policies to facilitate selection for the user. Instead of requiring the user to create a communication policy, it is more desirable for the user to select from a list of presets. Connections associated with different communication policies have physically separate synthetic routes. During synthesis, the configuration filtering module 1507 (FIG. 15) and the configuration selection module 1509 (FIG. 15) rely on the communication policy 1506 (FIG. 15) to output the best configuration 1510 for implementing the route 1511.

[0103] FIG. 17A shows a NoC topology on a floorplan having a communication policy 1700 aimed at optimizing wire length with best-effort performance. FIGS. 17A and 17B show how the same connection can result in different embodiments based on the selected communication policy. In the diagram of FIG. 17A, the focus is on connecting node "S" to node "D", and the wire length parameter is the main criterion for optimization. The configuration selection module selects an embodiment that creates a minimum amount of extra wire. By having a short ingress segment 1703 and one turn 1704 that is actuated, it is shown that the parameter requirements are met.

[0104] FIG. 17B shows a NoC topology on a floorplan having a communication policy 1710 for low-latency communication. In this example, rather than traversing several switches, there is a direct connection 1713 priority between node "S" 1711 and node "D" 1712. One turn 1714 that is actuated is near "D". This configuration generates more extra wire and is more expensive, but it is the user-selected route from "S" to "D" having the shortest length.

[0105] The basic method for incrementally synthesizing new connections while reusing existing segments is best shown in FIGS. 1A - 17B with the additional features shown in FIGS. 20 - 33. According to some embodiments, the tool divides existing segments to branch new segments. At the end of the process, only the newly created components such as clock and / or data width are configured, and the existing components remain unchanged. Referring again to FIG. 15, the existing segments and turn 1502 are changed by user control at the incremental level. The user not only controls the creation and selection of new segments within the network using communication policy 1506, but also modifies the existing topology or segments. In one example, reusing an existing segment with a new route may not be desirable due to performance considerations or previous optimizations that the user may have performed and which depend on the segment remaining unchanged. When a segment is split, hops may be added to traverse multiple routes, but this may not be the desired result. As a result, the system defines several incremental levels or modes based on the physical variability of segments, the physical variability of switches, and the logical variability of network elements. When synthesizing a new set of connections in the presence of an existing NoC topology, it is more desirable to incorporate the user's intent.

[0106] In an alternative embodiment, the incremental synthesis mode allows the user to customize how the existing topology is changed.

[0107] Regarding the physical changeability of segments, segments are changeable by default. A segment may be split to branch a new segment. For example, if it is not desired to add a switch to an existing route, the user can leave the segment unchanged.

[0108] Referring to the physical changeability of the switch, when the endpoint is a switch, a new segment can be connected to an existing endpoint of the immutable segment. If it is not desired to change the physical size of the switch, the switch may be immutable, and as a result, a new segment cannot be connected to the immutable switch.

[0109] Referring now to the logical variability of network elements, by default, existing network elements, including but not limited to data width and / or assigned clock, are not reconfigured by an incremental synthesis process. Only newly created switches and adapters are configured. This can result in inefficient configurations such as insufficient bandwidth and / or too many clock domain crossings. Any component can be marked as logically changeable so that the resulting new topology can be used to reconfigure existing components given. An example of how to define a pre-set incremental synthesis mode within a system based on the foregoing concepts describes three pre-set modes.

[0110] FIG. 18A shows an incremental synthesis mode 1800 for the initial setup of a segment connected from node "S" 1801 to node "D" 1802. High-bandwidth segment 1803 and low-bandwidth segment 1804 traverse existing NoC topology routes. During the initial setup, user parameters determine how the existing topology is changed to connect "S" 1801 to "D" 1802.

[0111] Figure 18B shows the incremental synthesis mode 1810 for the physical invariance of segments with parameters that are the smallest changes. The segment is divided at 1811, a new segment is branched at 1812, a U-turn is created within the deadlock-free network, and with minimal changes, 'S' 1801 is connected to 'D' 1802. The high-bandwidth segment 1803 is not changed to prevent division, and the traversal of the low-bandwidth segment 1804 is routed around the existing NoC topology routes.

[0112] It is more desirable to retain the maximum amount of the existing topology. All segments are made physically invariant using exceptional input and output segments since input and output segments are required to implement new connections. All switches are physically invariant and all network elements are logically invariant. In one example, if one segment from 'S' 1801 to 'D' 1802 is marked as invariant, it prevents division of the segment and facilitates routing around the existing segment. As a result, the existing segment remains unchanged.

[0113] Figure 18C shows the incremental synthesis mode 1820 for the logical invariance of segments with parameters that optimize the topology and retain the configuration. The low-bandwidth segment 1804 is divided at 1821, a new segment 1822 is branched, and a new turn is created to connect 'S' 1801 to 'D' 1802. The high bandwidth is connected to the lower bandwidth and is not fully utilized since the switches cannot be changed. It would be more desirable for some switches to be changed to adapt. This preset allows existing segments to be divided and have new connections for a more optimized topology for the switches. As a result, better costs can be achieved through reuse of existing elements. Existing network elements can be made logically invariant to maintain, for example, the clock frequency, the clock assigned to the switch, and / or other attributes without change.

[0114] Figure 18D shows the incremental synthesis mode 1830 for the variability of network elements having parameters that optimize the topology and adapt the configuration. A segment of high bandwidth 1803 is split 1831, a new segment 1832 is branched, and a new turn is created to connect "S" 1801 to "D" 1802. The high bandwidth is connected to a higher bandwidth and is fully utilized because the switch has been changed. When all segments can be split, the switch can be connected to new segments, and / or the components can be reconfigured, and the result is improved by reconfiguring the components, for example, by changing the clock and improving the performance, a higher degree of flexibility for the synthesis process is achieved.

[0115] Figure 19 shows the process of NoC synthesis based on a mesh custom sub-network description. First, a mesh segment is generated and physically optimally placed on the required space. Second, the new mesh segment, now considered an existing segment by the incremental synthesis process, is conveniently used when appropriate to generate the final route. As a result, a topology is obtained that mixes the automatically generated regular mesh topology with the newly optimally synthesized segments. In a fully connected system, for NoC 1900, each node 1901 is connected to all other nodes. Region 1902 is specified for a 3×3 mesh using the XY routing algorithm. As a result of the synthesis process 1903, NoC 1905 uses the required mesh segments and the newly synthesized segments. An automatically synthesized local tree 1904 is shown. A mesh is generated and optimally placed within the specified region 1906.

[0116] According to another aspect of the present invention, an extension of the clock domain and power domain on the floor plan is provided, and each element is tested to ensure that it is located within the boundaries of the specified clock domain and power domain. If the test fails, the element is moved until a suitable location where the test passes is found. Once a suitable placement is found for each element, routing of each connection between the elements is performed. The routing process finds a path suitable for the set of wires that make the connections between the elements. After routing is performed, distance span pipeline elements are inserted into the links as needed, using the information provided regarding the capabilities of the technology, based on the time it takes for a signal to cover a distance of 1 mm.

[0117] According to some aspects and embodiments of the present invention, the tool generates one or more computer files that describe the generated NoC, and these computer files include the following.

[0118] A list of network elements and their configurations: data width, clock domain. The position of each generated network element on the floor plan.

[0119] A set of routes through the network elements that implement connectivity. According to an aspect of the present invention, a route is an ordered list of network elements, one for each pair (initiator, target) and one for each pair (target, initiator). The route represents how traffic flows between the pairs and through which elements.

[0120] According to various aspects of the present invention, the tool is used to generate metrics regarding the generated NoC, such as a histogram of wire length distribution, the number of switches, a histogram of switches by size, etc.

[0121] Referring now to FIGS. 20-25, according to various aspects of the present invention, the tool automatically assigns a clock and data width to each of the network nodes such that all input constraints are met (performance, physical clock area, etc.).

[0122] According to various aspects of the present invention, the tool can select a clock and data width from a range of clock speeds and data widths selected according to input constraints for the parameters of the network. Thus, the automatic selection includes a machine learning model that uses feedback to improve the selection by artificial intelligence.

[0123] Various inputs 2000 are provided to the tool's checker 2010. The checker 2010 determines in step 2020 whether the current configuration is authenticated. The analysis performed by the checker is outlined herein and includes consideration of constraints and parameters to ensure that the configuration is authenticated.

[0124] The performance scenario is given at the transaction level (i.e., the high-level communication speed between components). The process automatically converts them into bandwidth requirements for each network segment. For example, according to various aspects of the present invention, the tool machine learning model can identify bandwidth requirements and receive feedback to improve the automatic selection. According to various aspects of the present invention, the tool includes a constraint solver 2110 that is utilized to generate an optimal configuration according to one or more of the following parameters or criteria.

[0125] 1) Cost (wires, energy) 2) Number of adapters (clock domain crossing, packet width adapter, etc.) According to various aspects of the present invention, the tool includes a process of checking, in step 2020, whether an existing NoC topology can support a given high-level transaction scenario by verifying that the current configuration is authenticated. According to various aspects of the present invention, if the performance check fails, segments without sufficient bandwidth are highlighted for the designer or user to take measures. The information collected from the performance check can also be provided to a machine learning model as feedback to an artificial intelligence (AI) machine implemented as part of the tool.

[0126] According to various aspects of the present invention, the tool receives, as input, the high-level specifications of the transactions that make up what is executing the application (scenario) in order to ensure that each application can be executed individually at the required speed.

[0127] Specifically referring to FIG. 22, according to various aspects of the present invention, the tool interprets a scenario, such as the scenario shown. From the high-level transactions seen in the scenario, the tool estimates the actual amount of bandwidth required for each element of each network involved. According to various aspects of the present invention, the tool can be multi-stage and receive transactions that can consume control and / or data BW in multiple networks. According to various aspects of the present invention, as a non-limiting example, a READ transaction in a non-coherent scenario generates a request (usually 1, but may be multiple cycles) in the request network and generates multiple data (multiple cycles) in the response network. According to various aspects of the present invention, for each transaction, a list of the networks affected is automatically inferred, and accordingly, the bandwidth requirements for each network component (nodes and segments) are generated. According to various aspects of the present invention, the tool performs authentication configuration generation. Thus, for each node, given the bandwidth requirements, current placement, and clock physical constraints, the tool 1) Estimate the possible configurations (clock + data width) applicable to the nodes, 2) Instead of an exhaustive list, it is represented as a set of constraints.

[0128] According to various aspects of the present invention, the tool selects the optimal configuration. The tool uses a constraint solver when seeking the optimal authentication configuration. The constraint solver is used to minimize the cost using heuristics that take as input at least one or more of, but not limited to, the following.

[0129] The cost of a clock adapter to minimize area (e.g., change in clock domain between two nodes), Wire length (prioritize lower data width), Energy consumption (select a slower clock if authentication is required), and Technical parameters, According to various aspects of the present invention, the tool converts high-level transaction speed requirements into bandwidth annotations for segments in some networks of the NoC. According to various aspects of the present invention, the tool takes into account clock tree propagation constraints (the floorplan area where a given clock can exist) to filter out illegal configurations. According to various aspects of the present invention, the tool uses a constraint solver not only to optimize wire cost and performance, but also to reduce the number of necessary adapters including clock domain crossings.

[0130] Specifically referring to FIGS. 26 to 29, according to various aspects of the present invention, the tool includes a process in which elements of a newly created NoC (generated by topology synthesis or created manually) are configured, including clock assignment and data width assignment, to meet the performance goals provided by the user in the form of a set of performance scenarios.

[0131] Referring to FIG. 26, the scenario shown in the figure requires the intermediate segment to maintain a bandwidth of 6 GB / s, which cannot be achieved by allocating two switches to the fastest clock in the design. This tool provides an incremental topology synthesis process, enabling the user to provide performance requirements late in the design flow after the topology has already been created. To achieve this, the tool includes a method for converting the existing topology to meet the newly added bandwidth requirements.

[0132] According to various aspects of the present invention, the tool identifies segments that cannot meet the bandwidth requirements. A segment is defined as a section between two switches, and a segment may already have several channels containing different communications. For each such segment, the tool creates additional channels for the segment. According to various aspects of the present invention, the tool takes a conservative number of channels, for example, one channel per communication passing through the segment. The tool optimally distributes the communications passing through the segment (route) on the new channels as follows.

[0133] Each channel groups as many communications as possible and uses as much of its bandwidth as possible.

[0134] All performance scenarios are satisfied with the current route distribution, and the new grouping of routes does not introduce new deadlocks (through the merging of routes that were previously separated into different existing channels).

[0135] Specifically referring to FIG. 27, according to various aspects of the present invention, the tool generates the route redistribution shown in the figure. Thus, when the routes are redistributed to all segments in violation, the internal arbiter of the switch may be changed and it may no longer be necessary to maintain the switch. Specifically referring to FIG. 28, the tool detects the true arbiter inside the remaining switches and splits switches with multiple separate arbiters or deletes switches that no longer have an arbiter.

[0136] Since the topology shape has changed due to the addition of new channels and the deletion / splitting of switches, the current physical layout can no longer be considered optimal. According to various aspects of the present invention, the tool calls the global placement to find a placement suitable for the newly modified topology. In the non-limiting example provided, the new placement is shown in FIG. 29.

[0137] According to various aspects of the present invention, the tool uses a configuration process as outlined herein to configure the remaining switches. In the newly created channels, as long as the scenario provided by the user is valid, it is guaranteed that a valid configuration will be found.

[0138] According to various aspects of the present invention, the tool can incrementally add new channels to the topology (after the initial topology synthesis) to maintain the specified bandwidth scenario. According to various aspects of the present invention, the tool can re-distribute routes on the new channels so as to minimize the number of channels required without introducing new deadlocks. According to various aspects of the present invention, the tool can split and delete switches that are no longer useful for arbitration purposes following route re-distribution. According to various aspects of the present invention, the tool can restart and adjust the data width and clock configuration process as needed. According to various aspects of the present invention, the tool globally adjusts the placement on the floor plan. According to various aspects of the present invention, the tool includes a machine learning model that can receive feedback used to further train the model.

[0139] According to various aspects of the present invention, the tool includes a topology synthesis process in which the topology is first created by ignoring the provided performance scenario and focusing on optimizing the wire cost, and the tool applies the above topology conversion process to support the performance scenario in the second stage. This speeds up the NoC generation or topology synthesis process by considering one requirement at a time. Moreover, by initially focusing on optimizing the wire routes and overall length, the tool ensures that any segments that could potentially be merged are already merged by the initial synthesis, and only the paths that require more bandwidth are ultimately replicated.

[0140] Specifically referring to FIGS. 30 to 33, according to various aspects of the present invention, the tool enables the user to provide the performance requirements of the topology synthesis process by defining a set of scenarios, where the scenarios are a set of communications performed in parallel at a given speed. This makes it possible to drive the shape of the topology using performance constraints, but it can be difficult and time-consuming to define and input all the scenarios required to obtain a specific traffic distribution. To mitigate this, the tool introduces a new process that enables the user to select a traffic pattern from a list of predefined patterns and apply it to a set of connections. The tool then automatically generates the required set of scenarios. According to various aspects of the present invention, the user provides or creates a traffic class for a set of connections and selects a traffic pattern for the traffic class from a list of predefined traffic patterns. The tool generates all scenarios from the set of connections included in the traffic class for each traffic class having a traffic pattern.

[0141] An exemplary topology is shown in FIG. 30. In this topology, segments are shared among several initiators to reduce wire cost. In one non-limiting example, the user desires to ensure that the selected initiator and target can communicate simultaneously at the full available bandwidth, which is equivalent to having a central crossbar with respect to bandwidth.

[0142] Specifically referring to FIG. 31, the user can simply define the traffic classes of these connections as shown. A new traffic class named "CROSSBAR" is created and configured to use the "Preserve Bandwidth" traffic pattern, thereby ensuring that the bandwidth is equivalent to that of the full crossbar. According to various aspects of the present invention, the tool then automatically uses this input to generate a set of scenarios. Each possible set of simultaneous communications is considered a separate scenario where each active input / output pair within the "virtual" crossbar communicates at the maximum bandwidth, as shown in FIG. 32. Once these scenarios are defined, the tool performs a topology synthesis process where it is possible to incrementally modify the topology to maintain the required bandwidth. According to various aspects of the present invention, the tool creates new channels within previously shared segments. According to various aspects of the present invention, the tool can apply this process not only to examples of crossbars but also to any set of traffic patterns. According to various aspects of the present invention, the tool can receive feedback from the user or from an adversarial machine learning model for further training the tool's machine learning model as input.

[0143] According to another aspect of the present invention, the tool automatically inserts various adapters and buffers into the network. The tool inserts adapters based on the adaptations required between two elements having different data widths, different clocks, and power domains. The tool inserts buffers based on scenarios and detected rate mismatches.

[0144] According to some aspects and embodiments, the tool can be used to ensure that multiple iterations of synthesis are performed for the incremental optimization of the NoC, including situations where one constraint provided to the tool is information regarding previous executions.

[0145] Referring now to FIGS. 34 - 36, according to various embodiments and aspects of the present invention, after a configuration (inlets, outlets, and internal segments and points) is selected by a configuration exploration step, optimization is performed when a new connection is being implemented. The tool attempts to avoid creating a new switch when splitting a segment if an existing switch within a certain distance can instead be safely reused. According to various embodiments and aspects of the present invention, a switch can be safely reused if it does not violate any performance requirements or constraints. According to various embodiments and aspects of the present invention, the switch reuse distance is a parameter selected by the user. According to various embodiments and aspects of the present invention, the switch reuse distance is provided and determined using input from the user and / or by a machine learning model trained based on an adversarial model or feedback from the user. Thus, the tool can ensure that reusing an existing switch is equivalent to creating a new switch with respect to the additional turns created, thereby ensuring that no new deadlocks are introduced.

[0146] According to various embodiments and aspects of the present invention, when a switch is reused, its position (placement) is optimized given the newly connected segments. The conditions for switch reusability are simple as defined by the requirements, parameters, and constraints of the NoC, such as deadlock avoidance. Thus, during the exploration step, i.e., when selecting the best configuration, the switches can be evaluated to prefer configurations that are likely to allow existing switches to be reused.

[0147] According to various embodiments and aspects of the present invention, FIG. 34 shows an example where a switch can be safely reused when the input switch of an existing segment is reused for a new segment incoming. An initiator or source (S) 3410 is shown together with the communication requirements to a target or destination (D) 3420. According to various embodiments and aspects of the present invention, a selected configuration with possible switches 3412 and 3422 is shown. The tool excludes switch 3412 (based on artificial intelligence using a user or a machine learning model) and selects to use the existing switch for the source 3410.

[0148] According to various embodiments and aspects of the present invention, FIG. 35 shows an example where a switch can be safely reused when the output switch of an existing segment is reused for a new segment that is added or transmitted. An initiator or source (S) 3510 is shown together with the communication requirements to a target or destination (D) 3520. According to various embodiments and aspects of the present invention, a selected configuration with possible switches 3512 and 3522 is shown. The tool excludes switch 3522 (based on artificial intelligence using a user or a machine learning model) and selects to use the existing switch for the source 3520. According to various embodiments and aspects of the present invention, the tool inserts or uses a new segment including at least one new switch, and the new switch is selected as a reusable switch. According to various embodiments and aspects of the present invention, the tool uses or inserts a new segment including at least one new switch, and the tool replaces the new switch with a reusable switch.

[0149] According to various embodiments and aspects of the present invention, FIG. 36 shows an embodiment by a tool when a switch used to divide a first segment is used (reused) to divide a second segment. An initiator or source (S) 3610 is shown with a plurality of routes that can be used to incorporate communication between the source 3610 and the destination 3620, along with communication requirements to the target or destination (D) 3620. According to various embodiments and aspects of the present invention, a selected configuration with possible switches 3612, 3622, 3630, and 3632 is shown. The tool excludes the switch 3632 (based on artificial intelligence using a user or machine learning model) and selects to use existing switches.

[0150] Referring now to FIG. 37, a process 3700 for optimizing the topology of a NoC is shown by exploring the topology to determine the reusability of specific elements of the NoC according to various aspects and embodiments of the present invention. The process starts at step 3710, where the tool explores the topology of the NoC to identify a plurality of existing segments, each having at least one existing switch. The tool also predicts the availability of each existing switch and identifies at least one switch selected from the existing switches that can be reused. At step 3720, the tool receives an input identifying at least one new segment to be added to the topology. At step 3730, a configuration for adding the new segment is identified. At step 3740, the tool inserts the new segment into the configuration. At step 3750, the tool determines at least one reusable switch selected from the existing switches to be reused in the configuration. At step 3760, the tool adjusts the placement of the reusable switches in the NoC topology by rearranging the reusable switches to optimize a configuration that meets the performance requirements.

[0151] According to various embodiments and aspects of the present invention, the reuse of switches during the synthesis process is applicable to the various scenarios or cases described, as well as other scenarios and cases following the same logic. According to various embodiments and aspects of the present invention, the tool can, if necessary, readjust the position of the switch when it is reused. According to various embodiments and aspects of the present invention, the tool can predict the availability of switches within a segment when selecting the best configuration in the exploration phase.

[0152] After the execution of the synthesis process by software, the results are generated in a machine-readable format such as a computer file that uses a clearly defined format for taking in information. Examples of such formats are XML, and another example of such a format is JSON. The scope of the present invention is not limited by a specific format.

[0153] Some aspects of the present invention utilize an incremental approach to network synthesis. This incremental approach is useful in many situations. For example, in some embodiments, the incremental process starts from the specifications and a clean floor plan. In these and other embodiments, some of them are those discussed above According to some aspects and embodiments, a connection can have, for example, a communication policy that specifies the sensitivity of the connection to latency.

[0154] Certain methods according to various aspects of the present invention can be executed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, when executed by one or more processors, cause a system or computer to perform the steps of the methods described herein. The non-transitory computer-readable medium includes rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is suitable for storing code including instructions according to various examples.

[0155] Although specific examples have been described herein, it will be noted that different combinations of different components from different embodiments may be possible. Distinctive features are presented to better illustrate the embodiments. However, it is clear that specific features can be added, changed, and / or omitted without changing the functional aspects of these embodiments as described.

[0156] Various embodiments are methods of using the behavior of any or a combination of machines. Embodiments of the method are completed whenever most of the constituent steps are performed. For example, according to various aspects and embodiments of the present invention, an IP element or unit includes a processor (e.g., a CPU or GPU), a random access memory (RAM - e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections such as Ethernet®, WIFI, 3G, 4G long-term evolution (LTE), 5G, and other wireless interface standard radios. The IP may also optionally include various I / O interface devices such as keyboards and mice, among other peripheral devices, for various peripheral devices such as touch screen sensors, geographical location information receivers, microphones, speakers, Bluetooth peripherals, and USB devices. By executing instructions stored in the RAM device, the processor executes the steps of the methods described herein.

[0157] Some embodiments are one or more non-transitory computer-readable media configured to store such instructions for the methods described herein. Any machine holding a non-transitory computer-readable medium containing any of the required code can implement the embodiments. Some embodiments may be implemented as physical devices such as semiconductor chips, hardware description language representations of the logical or functional behavior of such devices, and one or more non-transitory computer-readable media configured to store such hardware description language representations. The descriptions in this specification listing principles, aspects, and embodiments encompass both their structural and functional equivalents. Elements described as being coupled herein have an effective relationship that can be realized either directly or indirectly using one or more other intervening elements.

[0158] Those skilled in the art will recognize many modifications and variations. The modifications and variations include any relevant combination of the disclosed features. The description in this specification that enumerates principles, aspects, and embodiments encompasses both their structural and functional equivalents. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be realized by direct connection or by indirect connection using one or more other intervening elements. Embodiments described herein as "communicating" or "in communication with" another device, module, or element include any form of communication or link and include an effective relationship. For example, the communication link can be established using a wired connection, a wireless protocol, a near-field protocol, or RFID.

[0159] To the extent that the terms "including", "includes", "having", "has", "with", or variations thereof are used in either the detailed description or the claims, such terms are intended to be as inclusive as the term "comprising".

[0160] Accordingly, the scope of the present invention is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention are embodied by the appended claims.

Claims

1. 1. A tool for incremental generation of a network-on-chip (NoC), the tool comprising: a non-transitory computer-readable medium for storing code that, when executed by one or more processors, causes the tool to: Discovering a topology of the NoC; identifying a plurality of existing segments, each segment having at least one existing switch; predicting the availability of each existing switch; receiving as input at least one new segment to be added to the topology; selecting a configuration for adding the new segment; In the above configuration, inserting the new segment; determining at least one reusable switch selected from existing switches to be reused in the configuration; adjusting a placement of the reusable switches in the topology of the NoC by rearranging the reusable switches to optimize the configuration to meet performance requirements; A tool that allows you to do this.

2. The tool of claim 1 , wherein the new segment includes at least one new switch, and the new switch is selected as the reusable switch.

3. The tool of claim 1 , wherein the new segment includes at least one new switch, the new switch replacing the reusable switch.

4. The tool of claim 1 further comprising identifying at least one switch selected from the existing switches that can be reused.

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