Storage system and power consumption suppression method

Abstract

To provide a storage system and a power consumption suppression method for reducing power consumption without deteriorating I / O performance with a host.SOLUTION: There is provided a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host. The storage system includes: a plurality of components each configured to operate in a first power mode or at least one second power mode with lower power consumption in a switchable manner; a device operating state monitoring program 302 as an example of a state monitoring unit that monitors an operating state of each of the plurality of components; and a power mode control unit 305 that determines a power mode of at least one or more specific components to be the power saving mode being the second mode power based on a processing load related to each of the plurality of components, which is a result of monitoring by the state monitoring unit, and switches the power mode to the power saving mode to operate at least one or more specific components. The storage system executes, by the plurality of components with the storage device, control according to the data input / output request.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a storage system and a power consumption reduction method, and is suitable for application to a storage system relating to a technology for reducing power consumption according to the power mode of each device mounted on at least one controller, for example. [Background technology]

[0002] In recent years, the importance of technologies that create new value by storing and analyzing huge amounts of data, such as AI (Artificial Intelligence), is increasing. This requires storage systems with high I / O (Input / Output) performance to store and analyze the stored data, in addition to storing huge amounts of data.

[0003] On the other hand, in order to realize high performance of storage systems, the installed CPU (Central Processing Unit) and I / O modules are becoming more and more powerful. Accordingly, the power consumption of storage systems is increasing year by year, and control technology that can achieve both high performance and energy saving is required to reduce the environmental load and power costs. Regarding power control of storage systems, Patent Document 1 discloses a technology that solves the problem of increasing power consumption of SSDs (Solid State Drives).

[0004] In the technology disclosed in Patent Document 1, a function for limiting power consumption and performance is provided to the SSD, and the power mode setting is determined in advance for each product model based on the performance and power requirements (product specifications such as maximum configuration) of the installed storage system. In addition, the technology disclosed in Patent Document 1 takes measures to enable operation within the range of power that can be supplied to the storage system by determining the power mode of the SSD and CPU based on the SSD configuration and load state. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2018 / 193608 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technology disclosed in Patent Document 1 is a measure to deal with the increased power consumption of SSDs, and cannot deal with the increased power consumption of various components mounted on a storage system, and as a result, does not reduce the power consumption of the entire storage system. One possible way to reduce the power consumption of a storage system is to use devices with low processing performance but low power consumption for the various components, but any of these methods may result in a decrease in I / O performance with the host.

[0007] The present invention has been made in consideration of the above points, and aims to propose a storage system and a power consumption reduction method that can reduce power consumption without degrading I / O performance with the host. [Means for solving the problem]

[0008] In order to solve such problems, the present invention provides a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, the storage system comprising a plurality of components that can each operate by switching between a first power mode and at least one second power mode that consumes less power than the first power mode, a status monitoring unit that monitors the operating status of each of the plurality of components, and a power mode control unit that determines the power mode of at least one specific component to be the second power mode based on the processing load for each of the plurality of components as a result of monitoring by the status monitoring unit, and operates the at least one specific component in the second power mode, and the plurality of components are configured to perform control between the storage device in response to the data input / output request.

[0009] In addition, in the present invention, a power consumption reduction method for a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host includes a status monitoring step in which a status monitoring unit monitors the operating status of each of a plurality of components that can each operate by switching between a first power mode and at least one second power mode that consumes less power than the first power mode, and a power mode control step in which a power mode control unit determines the power mode of at least one specific component to be the second power mode based on the processing load for each of the plurality of components that is the result of monitoring by the status monitoring step, and operates the at least one specific component in the second power mode, and control in response to the data input / output request is performed between the storage device and the plurality of components. Effect of the Invention

[0010] According to the present invention, it is possible to reduce power consumption without degrading the input / output performance with the host. [Brief description of the drawings]

[0011] [Figure 1]1 is a system configuration diagram showing an example of the configuration of an information system including a storage system according to the present embodiment. [Diagram 2] 2 is a diagram illustrating an example of a configuration of a memory illustrated in FIG. 1; [Diagram 3] 3 is a diagram showing an example of the configuration of a program area shown in FIG. 2; [Figure 4] 3 is a diagram showing an example of the configuration of a management information area shown in FIG. 2; [Diagram 5] FIG. 13 illustrates an example of the configuration of a device management table. [Figure 6] FIG. 13 illustrates an example of the configuration of a device operation history table; [Figure 7] FIG. 11 is a diagram illustrating an example of a procedure for power consumption control processing. [Figure 8] FIG. 11 illustrates an example of a procedure for a device operation state monitoring process. [Figure 9] 10 is a flowchart showing an example of a procedure for a connected device unit power mode determination process shown in FIG. 9 . [Figure 10] 10 is a flowchart showing an example of a procedure for a device-based power mode determination process shown in FIG. [Figure 11] FIG. 11 illustrates an example of a process flow for determining a power mode for each connected device. [Figure 12] 10 is a flowchart showing an example of a procedure for a controller unit power mode determination process shown in FIG. [Figure 13] 10 is a flowchart illustrating an example of a procedure for a power mode combination determination process. [Figure 14] 10 is a flowchart illustrating an example of a procedure for a power mode change process. [Figure 15] FIG. 11 is a system configuration diagram showing a configuration example of an information system according to a second embodiment. [Figure 16] 16 is a diagram illustrating an example of a configuration of a memory of the management terminal illustrated in FIG. 15. [Figure 17] 17 is a diagram showing an example of a program stored in a program area shown in FIG. 16. [Figure 18] 17 is a diagram showing an example of information stored in a management information area shown in FIG. 16. [Figure 19] 19 is a diagram illustrating an example of the configuration of a controller management table illustrated in FIG. 18. [Figure 20] 19 is a diagram showing an example of the configuration of a controller operation history table shown in FIG. 18. [Figure 21A] 19 is a diagram showing an example of settings in the controller power setting information table shown in FIG. 18. [Figure 21B] 19 is a diagram showing an example of settings in the controller power setting information table shown in FIG. 18. [Figure 21C] 19 is a diagram showing an example of settings in the controller power setting information table shown in FIG. 18. [Figure 22] 16 is a diagram showing an example of data exchanged in a processing request and response between the storage system and the management terminal shown in FIG. 15. FIG. [Figure 23] FIG. 13 illustrates an example of a storage system management screen. [Figure 24] 10 is a flowchart illustrating an example of a procedure for a controller power consumption control process. [Diagram 25] 25 is a flowchart showing an example of a procedure for a controller operational state monitoring process shown in FIG. 24. [Figure 26] 25 is a flowchart showing an example of a procedure for a controller power mode determination and change process shown in FIG. 24. [Figure 27] FIG. 1 is a system configuration diagram showing an example of the configuration of a storage system. [Figure 28] 10 is a flowchart illustrating an example of a procedure for a power mode determination process by a controller. [Figure 29] FIG. 1 is a diagram for explaining a configuration example of OQ and IQ. [Diagram 30] 11 is a diagram illustrating a data transfer path related to host I / O processing before host I / O takeover. FIG. [Diagram 31] 11 is a diagram illustrating a data transfer sequence related to host I / O processing before host I / O takeover. FIG. [Diagram 32] FIG. 1 is a diagram illustrating an example of a P2P data transfer path. [Diagram 33]13 is a diagram illustrating a data transfer path related to host I / O processing after host I / O takeover. FIG. [Diagram 34] 11 is a diagram illustrating a data transfer sequence related to host I / O processing after host I / O takeover. FIG. [Diagram 35] 13 is a flowchart illustrating an example of a procedure for host I / O takeover processing between controllers and a power mode change processing of the controller. [Diagram 36] 13 is a flowchart illustrating an example of a procedure for a controller state monitoring process. [Figure 37] 13 is a flowchart showing an example of a procedure for restarting host I / O processing in a controller that has been set to a power saving mode and changing the power mode of the controller. [Figure 38] 13 is a diagram illustrating a data transfer path related to host I / O processing after host I / O takeover when an interrupt is used instead of polling. FIG. [Figure 39] FIG. 13 is a diagram illustrating a data transfer sequence related to host I / O processing after host I / O takeover when an interrupt is used instead of polling. [Diagram 40] 13 is a diagram illustrating a data transfer path related to host I / O processing after host I / O takeover. FIG. [Diagram 41] 11 is a diagram illustrating a data transfer sequence related to host I / O processing after host I / O takeover. FIG. [Diagram 42] 13 is a flowchart illustrating an example of a procedure for host I / O takeover processing between controllers and a power mode change processing of the controller. [Diagram 43] 13 is a flowchart showing an example of a procedure for restarting host I / O processing in a controller that has been put into a power saving mode and changing the power mode of the controller. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0013] In the following explanation, various information may be explained using the expression "xxx table", but the various information may be expressed in a data structure other than a table. To show that it does not depend on the data structure, the "xxx table" can be called "xxx information". Furthermore, in the following description, names and alphanumeric characters are used as identification information for elements, but other types of identification information (such as symbols) may be used. In addition, in the following description, when describing elements of the same type without distinguishing between them, common symbols (or reference signs) may be used, and when describing elements of the same type with distinction between them, reference signs (or element IDs) may be used. In the following description, the term "memory" refers to a primary storage device in a typical computer system, and may be one or more storage devices. For example, the memory may be at least a primary storage device among a primary storage device (typically a volatile storage device) and an auxiliary storage device (typically a non-volatile storage device). Furthermore, in the following explanation, "PDEV" refers to a physical storage device, and may typically be a non-volatile storage device (for example, an auxiliary storage device). The PDEV may be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive). In the following description, each device constituting the storage system has a function for adjusting power consumption and processing power, and the adjustable stages are called "power modes." In the following description, the "power modes" are shown as having finite, defined stages, but they may also be adjustable in an infinite number of stages. Furthermore, when processing is described below with a "program" as the subject, the program is executed by a processor (e.g., a CPU (Central Processing Unit)) included in the storage controller to perform a defined process using a storage resource (e.g., a main memory) and / or a communication interface device as appropriate, and therefore the subject of the process may be the storage controller or the processor. The storage controller may also include hardware circuits that perform some or all of the process. A computer program may be installed from a program source. The program source may be, for example, a program distribution server or a computer-readable storage medium. Furthermore, in the following description, a "host" is a host system that sends an I / O request to a storage system, and may include an interface device, a storage unit such as a memory, and a processor connected thereto. The host system may be composed of one or more host computers. At least one host computer may be a physical computer, and may include a virtual host computer in addition to a physical host computer.

[0014] (1) First embodiment 1 is a system configuration diagram showing an example of the configuration of an information system 101 including a storage system 102 according to this embodiment. The information system 101 comprises one or more storage systems 102 and one or more host machines 103.

[0015] The storage system 102 comprises one or more controllers 104, and one or more PDEV BOXes 105. The PDEV BOX 105 comprises one or more PDEV switches 112, and one or more PDEVs 113. In Fig. 1, the controller 104 and the PDEV BOX 105 are directly connected, but they may also be connected via a network (not shown).

[0016] The controller 104 comprises a CPU 106, memory 107, host I / F 108, PDEV I / F 109, accelerator 110, and network switch 111. In this embodiment, the CPU 106, memory 107, host I / F 108, PDEV I / F 109, accelerator 110, and network switch 111 included in the controller 104 are collectively referred to as "devices." Note that the devices mounted on the controller 104 are not limited to those mentioned above, and may include other devices, for example, power supply-related devices.

[0017] The controller 104 has, as each of the above devices, for example, a normal power mode (first power mode), at least one power saving mode (second power mode) that consumes less power than the normal power mode, a power OFF mode (power OFF mode) in which the power is turned off, and a standby mode (third power mode), and is equipped with a plurality of devices as an example of a plurality of components that can each be operated and can be switched between any of the plurality of modes. The controller 104 controls data input / output processing (I / O) between the controller 104 and the host machine 103 by the plurality of devices.

[0018] The CPU 106 has one or more cores 114, and controls the entire controller 104. The CPU 106 operates based on a program stored in the memory 107.

[0019] The host I / F 108 is controlled by the CPU 106, and performs the sending and receiving of I / O requests and I / O data from the host machine 103. The PDEV I / F 109 is controlled by the CPU 106, and performs the sending and receiving of data to and from the PDEV 113 via a PDEV switch 112 in the PDEV BOX 105.

[0020] The storage system 102 is configured with logical volumes capable of storing data, and a controller 104 executes input / output processing of data.

[0021] In this embodiment, the CPU 106, host I / F 108, PDEV switch, and accelerator 110 are connected via a network switch 111, but they may be connected without going through the network switch 111, for example by being directly connected to the CPU 106. The memory 107 is directly connected to the CPU 106, but it does not have to be connected directly, for example by going through the network switch 111. In addition, the controller 104 is connected via the network switch 111, but it may be connected without going through the network switch 111, for example by directly connecting the CPUs 106 to each other. In addition, the PDEV 113 is connected to the PDEV I / F 109 via the PDEV switch 112, but it may be connected without going through the PDEV switch 112.

[0022] In the above-described storage system 102, when the host I / F 108 accepts an I / O request or transmission / reception of I / O data from the host machine 103 under the control of the CPU 106 via the network switch 111, the CPU 106 controls the PDEV I / F 109 via the network switch 111 and performs input / output processing of data to / from the PDEV 113 via the PDEV switch 112 of the PDEV BOX 105. At this time, within the controller 104, each device set to a predetermined power mode consumes power according to that power mode. The CPU 106 constantly monitors the operating status of each device and obtains operating information indicating the operating status of each device.

[0023] FIG. 2 is a diagram showing an example of the configuration of the memory 107 shown in FIG. The memory 107 has a program area 201, a management information area 202, and a cache area 203. The program area 201 is an area in which each program for the CPU 106 to execute processing is stored.

[0024] The management information area 202 is an area in which various management tables are stored and is accessed by the CPU 106. The cache area 203 is an area in which data is temporarily stored when data is transferred by the host I / F 108, the PDEV I / F 109, etc.

[0025] Fig. 3 is a diagram showing an example of programs stored in the program area 201 shown in Fig. 2. The program area 201 stores, for example, a power consumption control program 301, a device operational state monitoring program 302, and a power mode determination program 303 and a power mode change program 304 as examples of a power mode control unit 305. In the following explanation, when there is no particular need to distinguish between the power mode determination program 303 and the power mode change program 304, the power mode control unit 305 may be used for explanation.

[0026] The power consumption control program 301 controls the power consumption of various devices mounted on the controller 104 of the storage system 102. The power consumption control program 301 controls the power consumption of the various devices by changing the power mode of the various devices. The power consumption control program 301 controls a device operating state monitoring program 302 and a power mode control unit 305.

[0027] The device operational status monitoring program 302 is an example of a status monitoring unit, and monitors the operational status of a plurality of devices.

[0028] The power mode control unit 305 switches the power mode of at least one specific component element having a low processing load among the multiple devices to a power saving mode in response to the result of monitoring by the device operation status monitoring program 302, thereby operating the specific device, thereby making it possible to reduce power consumption.

[0029] In this embodiment, the multiple components are multiple devices that control data input / output processing with the host. The controller 104 is equipped with these multiple devices and includes at least one controller 104 that controls data input / output processing with the host by the multiple devices, and a power mode control unit 305, and the controller 104 includes a device operation status monitoring program 302 as an example of a status monitoring unit, a power mode determination program 303 and a power mode change program 304 included in the power mode control unit 305. Note that controlling input / output processing here is not limited to specific I / O processing, and may also include, for example, functioning as a communication path and intervening in exchanges with the host.

[0030] As described above, the power mode control unit 305 includes a power mode determination program 303 and a power mode change program 304. The power mode determination program 303 is an example of a power mode determination unit, and when it is determined that changing the power mode of a specific device operating in normal mode among the multiple devices to a power saving mode will not affect data input / output processing with the host machine 103, it determines that the power mode of the specific device is to be the power saving mode. The power mode change program 304 is an example of a power mode change unit, and switches the power mode of the specific device to the determined power saving mode. Note that the above-mentioned case where it is determined that changing to the power saving mode will not affect data input / output processing with the host machine 103 also includes, for example, that changing to the power saving mode will have an effect on data input / output processing with the host machine 103 that is equal to or less than a predetermined standard. Note that the standard may be set according to the characteristics of each device.

[0031] By executing the power consumption control program 301, the storage system 102 can reduce power consumption without degrading the I / O performance of the storage system 102. During the process, the power consumption control program 301 also calls a device operating status monitoring program 302 that monitors the processing load of the devices and stores history information, and a power mode decision program 303 that decides the power mode of each device based on the above-mentioned history information, etc. During the process, the power mode decision program 303 also calls a power mode change program 304 that performs processing required when changing the power mode of the devices and changes the device to the decided power mode.

[0032] FIG. 4 is a diagram showing an example of information stored in the management information area 202. As shown in FIG. The management information area 202 stores a device management table 401 and a device operation history table 402 .

[0033] The device management table 401 manages information relating to a plurality of devices constituting the storage system 102, such as the CPU 106, and is used in the process of determining the power mode, as will be described later.

[0034] The device operation history table 402 has history information such as the processing load from the past to the present for devices constituting the storage system 102, such as the CPU 106, and is used in the process of determining the power mode. The device operation history table 402 manages the operation states of multiple devices monitored by the device operation state monitoring program 302.

[0035] The above-mentioned power mode determination program 303 determines, based on the operation states of the multiple devices managed in the device operation history table 402, that changing the power mode of a specific device to the power saving mode will not affect data input / output processing with the host machine 103 more than a predetermined standard, and then determines to set the power mode of the specific device to the power saving mode.

[0036] 5 is a diagram showing an example of the configuration of the device management table 401. The device management table 401 manages at least the power consumption and processing capacity for each of the normal power mode and the power saving mode for each of the multiple devices. The above-mentioned power mode control unit 305 determines the power saving mode for the power mode of the above-mentioned specific device based on the power consumption and processing capacity for each of the normal power mode and the power saving mode for each of the multiple devices managed in the device management table 401, and changes the power mode of the specific device to the power saving mode. This will be explained in more detail below.

[0037] The device management table 401 has entries for a device identifier (type) 501 , a power control unit 502 , a normal mode 503 , power OFF 504 , a power saving mode A 505 , and a power saving mode B 506 .

[0038] The device identifier (type) 501 is an identifier of a device mounted on the storage system 102, such as the CPU 106 or the host I / F 108.

[0039] As described above, the device management table 401 manages the power control unit 502, which is related to the range of a plurality of devices in relation to other devices in terms of power consumption control. In other words, the power control unit 502 is information that manages and prescribes a category (first category) in which the control of the power mode of a plurality of devices is executed independently of other devices, and a category (second category) in which the control is executed in combination with other devices. This power control unit 502 indicates in what unit control is performed when changing the power mode of each device. In this embodiment, for example, device units, connected device units, and controller units are provided as the power control units.

[0040] In this embodiment, such power control units are merely examples, and details will be described later, but in addition, for example, the device management table 401 may manage, as power control units, device units including devices that are independent from other devices in terms of power consumption, connected device units including devices whose power modes should be changed to match those of other devices, and controller units including a group of controllers (e.g., accelerator 110) that should exhibit approximately the same performance for each of multiple controllers 104.

[0041] Normal mode 503, power off 504, power saving mode A 505, and power saving mode B 506 indicate power modes of devices installed in the storage system 102, each having its own power consumption and processing capacity (relative values ​​when normal mode is 100%).

[0042] In this embodiment, for example, four power modes may be provided, but two or more may be provided. Also, depending on the device, the number of supported power modes may differ, or some devices may not have multiple power modes. Furthermore, in this embodiment, two items, power consumption and processing capacity, are provided, but other information required for selecting a power mode may be included, such as restrictions (e.g., functions are limited) when using the power mode.

[0043] 6 is a diagram showing an example of the configuration of the device operation history table 402. The device operation history table 402 has entries of collection time 601, device identifier (type) 602, installed controller # 603, installation position identifier 604, installation status 605, power mode 606, and processing load 607. In this embodiment, "#" indicates an identification number.

[0044] The collection time 601 indicates the time when the history of the device was collected, and may be, for example, the time elapsed since the start of the storage system 102. The device identifier (type) 602 is an identifier of a device mounted in the storage system 102, such as the CPU 106 or the host I / F 108, and indicates the correspondence with the device identifier (type) 501 in the device management table 401.

[0045] The installed controller # 603 is an identifier for identifying the controller 104 in which the device is installed. The installed location identifier 604 is an identifier for identifying where the device is installed when multiple devices are installed. The installed status 605 indicates whether the device is installed or not.

[0046] The power mode 606 indicates the power mode of the device, and is any one of the normal mode 503, power off 504, power saving mode A 505, and power saving mode B 506 in the device management table 401. The processing load 607 indicates the processing load of the device.

[0047] In this embodiment, the device is identified using the device identifier (type) 602, the mounted controller #603, and the mounting location identifier 604, but this is not limited to this and any identifier that can identify the device may be used, such as a unique identifier such as the device's serial number.

[0048] Fig. 7 is a flow chart showing an example of the procedure of power consumption control processing for reducing power consumption in the storage system 102. The power consumption control processing mainly has the following three steps. Note that the power consumption control processing is executed by each program shown in Fig. 3 under the control of the CPU 106 when the storage system 102 is started.

[0049] First, the power consumption reduction method according to the present embodiment will be outlined. The power consumption reduction method is a power consumption reduction method for a storage system having a storage device that stores data in response to a data input / output request from a host or outputs the stored data, and includes a status monitoring step in which a device operation status monitoring program 302 as an example of a status monitoring unit monitors the operation status of each of a plurality of devices that can be operated by switching between a normal power mode and at least one power saving mode that consumes less power than the normal power mode, and a power mode control step in which a power mode control unit 305 determines the power mode of at least one specific device to be a power saving mode based on the processing load on each of the plurality of devices that is the result of monitoring by the status monitoring step, and switches to the power saving mode to operate the at least one specific device, and executes control between the storage device and the plurality of devices in response to the data input / output request. An example of a power consumption control process will be specifically described below.

[0050] In this embodiment, for example, when the storage system 102 is started up, the CPU 106 executes the power consumption control program 301 stored in the program area 201 of the memory 107. When this power consumption control program 301 is executed, during the execution, a device operating status monitoring program 302, a power mode determination program 303, and a power mode change program 304 are also executed.

[0051] First, in the first step, the CPU 106 monitors the processing load of the device mounted in the storage system 102 and records it in the device operation history table 402 (step S701). More specifically, the CPU 106 starts the actual processing of the power consumption control program 301 in response to, for example, a predetermined criterion (trigger) regarding the execution of the power consumption control process being satisfied. In parallel with this, the CPU 106 can acquire a collection time 601 corresponding to the monitoring of the operation state of the device, which will be described later. In response to the progress of the processing of the power consumption control program 301, the CPU 106 executes a device operation state monitoring process for monitoring the processing load of the device to be monitored by reading and executing the device operation state monitoring program 302 from the program area 201 of the memory 107. The device operation state monitoring program 302 accesses the device management table 401 to acquire information on the device identifier 501 and the power control unit 502. The device operation state monitoring program 302 executes confirmation of the processing load, the currently applied power mode, and the like, based on the device identifier 501 and the power control unit 502. This device operation status monitoring program 302 records the power mode information and processing load information obtained as a result of the execution of the check in the device operation history table 402 together with the corresponding device identifier 602, identification information of the controller to which the device identifier 602 belongs (installed controller #603), installation position identifier 604, installation status 605, and collection time 601. Further details of this process will be described later.

[0052] In a second step, the CPU 106 (power mode control unit 305) refers to the device management table 401 and the device operation history table 402, determines the power mode of each device based on the power control unit 502 and operation history of the device, and determines and changes the power mode if necessary. The power mode change program 304 changes the power mode of the device if necessary, depending on the determination of the power mode determination program 303 (step S702). Specifically, the CPU 106 reads and executes the power mode determination program 303 as part of the processing of the power consumption control program 301. The power mode determination program 303 accesses the device operation history table 402 in the management information area 202 to obtain related information, and determines the power mode to be applied to each device. Next, the CPU 106 reads and executes the power mode change program 304 as part of the processing of the power consumption control program 301. The power mode change program 304 transmits the power mode determined by the power mode determination program 303 to a target device identified based on the device identifier 501, power control unit 502, mounted controller #603, and mounting position identifier 604, and causes the power mode to be changed. Note that, for a target device that does not have a function for actively limiting power consumption as a characteristic and whose power consumption is determined by the usage status of the CPU 106 or other devices, the CPU 106 restricts the usage status according to the power mode. Note that further details of this process will be described later.

[0053] In the third step, the CPU 106 determines the next time to execute the power consumption control process and ends the process (step S703). The next time to execute the process may be after a certain period of time has elapsed, or one or more conditions may be set, such as when an I / O request is received from the host machine 103 or when a device is installed or removed.

[0054] 8 is a flowchart showing an example of the procedure for device operational status monitoring processing performed in power consumption control processing in the storage system 102. Under the control of the CPU 106, the device operational status monitoring program 302 refers to the device management table 401 and starts monitoring from the device listed in the first row (step S801). Note that, although monitoring starts from the device listed in the first row here, the order need not be limited to this.

[0055] The device operating status monitoring program 302 acquires the possible mounting position of the device (step S802). The possible mounting position means information for identifying multiple identical devices when they are mounted in the storage system 102. For example, this corresponds to the mounted controller #603 and mounting position identifier 604 in the device operating history table 402.

[0056] The device operational state monitoring program 302 starts monitoring the top of the list of possible mounting positions for the device acquired in step S802 (step S803).

[0057] The device operational status monitoring program 302 acquires the current date and time (step S804). The date and time acquired here is information equivalent to the collection time 601 in the device operation history table 402, and may be, for example, the time of day or the elapsed time since the storage system 102 was started.

[0058] The device operating state monitoring program 302 acquires whether or not a device is installed at the target device's mountable position (step S805). Note that the presence or absence of a device may be checked by referring to a table containing device mounting information prepared in advance, or by accessing the device at this point.

[0059] Based on the result of step S805, the device operating state monitoring program 302 judges whether or not the device is mounted in the mountable position of the target device (step S806). If the result of the judgment shows that the device is mounted (step S806: Yes), step S807 is executed. On the other hand, if the device is not mounted (step S806: No), step S809 is executed.

[0060] The device operating status monitoring program 302 acquires the current power mode of the device to be monitored (step S807). Note that, regarding the power mode of the device, a table containing the current power mode of the device may be prepared and referenced, or the device may be accessed at this point to check the power mode.

[0061] The device operational status monitoring program 302 acquires the current processing load of the monitored device (step S808). The processing load of the device may be checked by preparing a table that periodically records the processing load, or by accessing the device at this point. There are several existing methods for calculating the processing load of the device, so it is sufficient to use any of these.

[0062] The device operation status monitoring program 302 adds the information acquired in steps S804, S805, S807, and S808 to the device operation history table 402 (step S809).

[0063] The device operational state monitoring program 302 refers to the list of possible mounting positions for the device acquired in step S802, and determines whether or not there is a possible mounting position next to the currently targeted possible mounting position (step S810). If the result of the determination is that there is a possible mounting position next (step S810: Yes), step S811 is executed. On the other hand, if there is no possible mounting position next (step S810: No), step S812 is executed.

[0064] The device operational state monitoring program 302 refers to the list of possible mounting positions for the device acquired in step S802, and starts monitoring the next possible mounting position after the currently targeted possible mounting position (step S811). Then, step S804 is executed.

[0065] The device operational status monitoring program 302 refers to the device management table 401 and determines whether or not there is a device next to the currently targeted device (step S812). If the determination result indicates that there is a device next to the currently targeted device (step S812: Yes), step S813 is executed. If there is no device next to the currently targeted device (step S812: No), the device operational status monitoring program 302 ends the device operational status monitoring process.

[0066] The device operational status monitoring program 302 refers to the device management table 401, and starts monitoring the next device after the currently targeted device (step S813), after which step S802 is executed.

[0067] Here, the classification of devices with respect to power modes in this embodiment will be described. The power mode determination program 303 (power mode control unit 305) classifies a plurality of devices into devices that are grouped because they have low mutual independence from the viewpoint of controlling power consumption of the plurality of devices, and devices that are not grouped because they have high mutual independence from the viewpoint of controlling power consumption of the plurality of devices, and may switch the power mode to a power saving mode according to the result of monitoring by the device operation status monitoring program 302 for each device that can be grouped and each device that cannot be grouped. Note that "independence" from the viewpoint of controlling power consumption may be considered as the degree of coupling with other devices in terms of function and performance based on the processing and performance of each device, or the contents of cooperation with other devices regarding processing. Controlling the amount of power consumption, i.e., applying a restriction, affects the performance of the target device. However, the range of influence varies depending on the function of the device and the relationship with other devices. In this embodiment, the power control unit is specified according to a range (i.e., the independence is low within the range) specified by setting a boundary at a place where the degree of coupling between the plurality of devices is low (high independence). For example, devices that are highly independent as individual devices and have little need for grouping (first category) and devices that are low in independence from other devices as individual devices but are highly independent in relation to other devices outside the combination (group) when viewed together with the other devices (second category) can be specified. Note that the criteria for determining independence can be set arbitrarily, and it is determined in advance which category each device belongs to depending on the required performance.

[0068] Furthermore, when there are multiple devices that can be grouped, the power mode determination program 303 (power mode control unit 305) may classify the devices into a first device group for which the power mode change manner should be consistent across the multiple devices to be grouped, and a second device group for which the power mode change manner does not need to be consistent across the multiple devices to be grouped, and change the power mode for the first device group so that the target power modes are consistent.

[0069] Furthermore, the power mode determination program 303 (power mode control unit 305) may classify devices into those that allow power OFF as a power saving mode and those that do not allow power OFF as a power saving mode (e.g., connected host I / F) (determined, for example, in step S1008 of FIG. 10), and for devices that allow power OFF as a power saving mode, switch the power mode to power OFF in accordance with the results of monitoring by the device operation status monitoring program 302, while for devices that do not allow power OFF as a power saving mode, switch the power mode to the power saving mode (not including power OFF) in accordance with the results of monitoring by the device operation status monitoring program 302.

[0070] 9 is a flowchart showing an example of the procedure of a power mode determination process performed in the power consumption control process. The power mode determination process is executed by the power mode determination program 303 under the control of the CPU .

[0071] The power mode decision program 303 refers to the device management table 401 and starts processing from the device listed in the first row (step S901). Note that, although processing starts from the device listed in the first row here, the order is not limited to this.

[0072] The power mode decision program 303 acquires the target device identifier (type) 501 (step S902). The power mode decision program 303 acquires the power control unit 502 of the target device (step S903).

[0073] The power mode decision program 303 determines whether the power control unit 502 is for this device based on the information acquired in step S903 (step S904). If the result of the determination is that it is for this device (step S904: Yes), step S905 is executed. On the other hand, if it is not for this device (step S904: No), step S906 is executed. The power mode decision program 303 calls a device-based power mode decision process (step S905). Then, step S910 is executed.

[0074] The power mode decision program 303 calls the device-specific power mode decision process (step S905), after which step S910 is executed.

[0075] The power mode decision program 303 determines whether the power control unit 502 is on a connected device basis based on the information acquired in step S903 (step S906). If the result of the determination is that the power control unit 502 is on a connected device basis (step S906: Yes), step S907 is executed. On the other hand, if the power control unit is not on a connected device basis (step S906: No), step S908 is executed. The power mode decision program 303 calls a connected device power mode decision process (step S907). Then, step S910 is executed.

[0076] The power mode decision program 303 determines whether the power control unit 502 is a controller unit based on the information acquired in step S903 (step S908). If the result of the determination is that it is a controller unit (step S908: Yes), step S909 is executed. On the other hand, if it is not a controller unit (step S908: No), step S911 is executed. The power mode decision program 303 calls a controller-based power mode decision process (step S909), which will be described later. Then, step S910 is executed.

[0077] The power mode decision program 303 calls a power mode change process that changes the power mode of the target device based on the power mode decided in step S905, step S907, or step S909 (step S910). Then, step S911 is executed.

[0078] The power mode decision program 303 refers to the device management table 401 and determines whether or not there is a device following the current target device (step S911). If the determination result indicates that there is a next device (step S911: Yes), step S912 is executed. On the other hand, if there is no next device (step S911: No), the power mode decision program 303 ends the power mode decision process.

[0079] The power mode decision program 303 references the device management table 401, and starts processing on the device next to the currently targeted device (step S912). After that, step S902 is executed.

[0080] Fig. 10 is a flowchart showing an example of the procedure of the device-based power mode determination process shown in Fig. 9. The device-based power mode determination process is called from a device power mode determination process carried out in the power consumption control process in the storage system 102. The device-based power mode determination process is executed by the power mode determination program 303 under the control of the CPU 106.

[0081] The power mode decision program 303 acquires the possible mounting position of the device (step S1001). The possible mounting position means information for identifying the same device when multiple devices are mounted in the storage system 102. For example, the mounted controller #603 and mounting position identifier 604 in the device operation history table 402 correspond to this.

[0082] The power mode decision program 303 starts processing for the top of the list of possible mounting positions for the device acquired in step S1001 (step S1002).

[0083] The power mode determination program 303 acquires whether or not a device is installed in the installation possible position of the target device (step S1003). Note that, regarding the presence or absence of a device, a table having device installation information may be prepared and referenced, or the device may be accessed at this point to check.

[0084] Based on the result of step S1003, the power mode decision program 303 determines whether or not a device is installed in the installation possible position of the target device (step S1004). If the result of the determination is that the device is installed (step S1004: Yes), step S1005 is executed. On the other hand, if the device is not installed (step S1004: No), step S1013 is executed.

[0085] The power mode decision program 303 refers to the device operation history table 402 and acquires information for predicting the processing load related to the device (step S1005).

[0086] The power mode decision program 303 predicts the future processing load of the device using the information acquired in step S1005 (step S1006). Hereinafter, this prediction result is also referred to as a "predicted value of future processing load." For example, by acquiring the collection time 601 and the processing load 607, it is possible to check the fluctuation in the processing load of the device in time series and predict the future processing load. Note that the future processing load may be predicted using information other than that acquired in step S1005. For example, the amount of change in the number of logical volumes defined in the storage system 102 or the amount of change in the number of connected hosts may be used. In addition, the method of predicting the future processing load may be prediction from the past operation history or the most recent operation state.

[0087] The power mode decision program 303 determines whether the predicted future processing load of the device is zero or not based on the result of step S1006 (step S1007). If the result of the determination is that the predicted future processing load is zero (step S1007: Yes), the program proceeds to step S1008. On the other hand, if the predicted future processing load is not zero (step S1007: No), the program executes step S1011.

[0088] The power mode decision program 303 judges whether the power mode of the device can be set to power OFF (step S1008). Even if the predicted value of the future processing load is zero, there are cases where the device cannot be powered OFF, and therefore, when the power mode is set to power OFF, a judgment is required individually. For example, in the case of the host I / F 108, when it is connected to the host machine 103, even if there is no I / O request from the host machine 103, if the power mode is set to power OFF, the connection with the host I / F 108 is cut off, which affects the operation of the host machine 103. Also, in the case of a device that requires time to transition from power OFF to another power mode, the long transition time may affect the I / O performance of the storage system, and in this process, these factors are combined to make a judgment.

[0089] The power mode decision program 303 determines whether the power mode of the device can be set to power OFF based on the determination result of step S1008 (step S1009). If the determination result indicates that the device can be powered OFF (step S1009: Yes), step S1010 is executed. On the other hand, if the device cannot be powered OFF (step S1009: No), step S1012 is executed.

[0090] The power mode decision program 303 decides that the power mode of the device is "power OFF" (step S1010). After that, step S1013 is executed.

[0091] The power mode decision program 303 decides the power mode of the device based on the predicted value of the future processing load obtained in step S1006 (step S1011). Note that in this process, it is assumed that a power mode that can provide processing capacity exceeding the predicted value of the future processing load of the device and minimizes power consumption is selected so as not to affect the I / O performance of the storage system 102. Note that an operation mode of the storage system that allows a decrease in I / O performance may be prepared, and the power mode may be decided so as to give priority to reducing power consumption by allowing the user of the storage system 102 to select this mode. Thereafter, step S1013 is executed.

[0092] The power mode decision program 303 decides that the power mode of the device is the one with the lowest power consumption other than power OFF (step S1012). As described above, this is a case where the predicted future processing load of the device is zero, but power OFF cannot be selected. Then, step S1013 is executed.

[0093] The power mode decision program 303 refers to the list of possible mounting positions for the target device acquired in step S1001, and determines whether or not there is a possible mounting position next to the currently targeted possible mounting position (step S1013). If the result of the determination is that there is a possible mounting position next (step S1013: Yes), step S1014 is executed. On the other hand, if there is no possible mounting position next (step S1013: No), step S1015 is executed.

[0094] The power mode decision program 303 refers to the list of possible mounting positions for the device acquired in step S1001, and starts processing for the next possible mounting position after the currently targeted possible mounting position (step S1014). Then, step S1003 is executed.

[0095] The power mode decision program 303 returns the power mode decision results calculated in steps S1010, S1011, and S1012 to the caller of the device-based power mode decision process, and ends the device-based power mode decision process (step S1015).

[0096] Fig. 11 is a flowchart showing an example of the steps of the connected device power mode determination process shown in Fig. 9. The connected device power mode determination process is called from a device power mode determination process performed in the power consumption control process in the storage system 102.

[0097] 10, the difference is that instead of determining a power mode for each device, a combination of specific devices that have a dependency relationship as a connected device is taken into consideration and a combination of power modes for the specific device combination is determined. For example, memory 107 has CPU 106 as a connected device, and CPU 106 may use memory 107 by, for example, interleave control. In this case, it is necessary to align the processing performance of multiple memories 107 connected to the same CPU 106, in other words, to select the same power mode.

[0098] The power mode decision program 303 acquires a list of devices connected to the target device (step S1101). For the connected devices, a table having connected device information may be prepared and referenced, or the device may be accessed at this point to confirm the connected devices.

[0099] The power mode decision program 303 acquires a list of possible mounting positions for the target device (step S1102). The possible mounting positions refer to information for identifying multiple identical devices when they are mounted in the storage system 102. For example, this corresponds to the mounted controller #603 and mounting position identifier 604 in the device operation history table 402.

[0100] The power mode determination program 303 classifies the possible mounting positions for each connected device based on the results of steps S1101 and S1102 (step S1103).

[0101] The power mode decision program 303 starts processing for the top of the list of possible mounting positions for each connected device, which is the result of step S1103 (step S1104).

[0102] The power mode determination program 303 acquires whether or not a device is installed at the installation possible position for each target connected device (step S1105). Note that, regarding the presence or absence of a device, a table having device installation information may be prepared and referenced, or the device may be accessed at this point to check.

[0103] The power mode determination program 303 determines whether or not a device is mounted in a mountable position for the target connection destination device based on the result of step S1105 (step S1106). Note that if at least one device is mounted, it is determined that the device is mounted. If the determination result shows that a device is mounted (step S1106: Yes), step S1107 is executed. On the other hand, if no device is mounted (step S1106: No), step S1110 is executed.

[0104] The power mode decision program 303 refers to the device operation history table 402 and acquires information for predicting the processing load related to the device (step S1107).

[0105] The power mode decision program 303 uses the information acquired in step S1107 to predict the future processing load of the device for each connected device (step S1108). For example, by acquiring the collection time 601 and the processing load 607, the fluctuation in the processing load of the device can be confirmed over time, and this can be used to predict the future processing load. Note that the future processing load may be predicted using information other than that acquired in step S1107. For example, the amount of change in the number of logical volumes defined in the storage system 102 or the amount of change in the number of connected hosts may be used. Note that the prediction method may be the same as the procedure shown in FIG. 10.

[0106] The power mode decision program 303 calls a process (power mode combination decision process in FIG. 13, described later) for deciding a combination of power modes for the device based on the predicted value of the future processing load calculated in step S1108 (step S1109).

[0107] The power mode decision program 303 references the connected device list resulting from step S1103 and determines whether or not there is a next connected device to the currently targeted device (step S1110). If the determination result indicates that there is a next device (step S1110: Yes), step S1111 is executed. On the other hand, if there is no next device (step S1110: No), step S1112 is executed.

[0108] The power mode decision program 303 references the connected device unit list resulting from step S1103, and starts processing for the next connected device unit after the currently targeted connected device unit (step S1111). Then, step S1105 is executed.

[0109] The power mode decision program 303 returns the result of the power mode decision calculated in step S1109 to the caller of the destination device power mode decision process, and ends the device power mode decision process (step S1112).

[0110] Fig. 12 is a flowchart showing an example of a procedure for the controller unit power mode determination process shown in Fig. 9. The controller unit power mode determination process is a process called from the device power mode determination process carried out in the power consumption control process.

[0111] The only difference between the controller-based power mode determination process and the connected device-based power mode determination process in Fig. 11 is whether the dependent entity is the connected device or the controller, and therefore a detailed description thereof will be omitted. An example of an instance to which the controller-based power mode determination process can be applied is the accelerator 110.

[0112] Four accelerators 110 are mounted on the controller 104, and processing requests can be distributed or consolidated as desired by the CPU 106. In other words, when the processing load of the accelerators 110 is low, a combination of power modes is possible, such as stopping processing requests to a specific accelerator 110 and turning off the power.

[0113] FIG. 13 is a flowchart illustrating an example of a procedure for a power mode combination determination process. The power mode combination determination process is called from the connected device power mode determination process sequence and the controller power mode determination process sequence. Since the power mode combination determination process involves a combination of power modes, it is called from step S1109 shown in Fig. 11 and step S1209 shown in Fig. 12. The power mode combination determination process is executed by the power mode determination program 303 under the control of the CPU 106.

[0114] In this embodiment, when the predicted future processing load for a plurality of specific devices is zero and power OFF is permitted, if it is necessary to unify the power modes of the plurality of specific devices, the power mode determination program 303 determines to unify the power modes of the plurality of specific devices to power OFF. A specific description will be given below.

[0115] The power mode decision program 303 receives a list of target devices and a predicted value of future processing load from the calling process (step S1301).

[0116] The power mode decision program 303 determines whether the future processing load value of the target device is zero based on the information received in step S1301 (step S1302). If the result of the determination is that the predicted future processing load value is zero (step S1302: Yes), step S1303 is executed. On the other hand, if the predicted future processing load value is not zero (step S1302: No), step S1306 is executed.

[0117] The power mode decision program 303 determines whether or not all of the target devices can be powered off (step S1303). Even if the predicted value of future processing load is zero, there are cases where it is not possible to power off all of the target devices, and so a decision is required. For example, in the case of devices that require time to transition from powered off to another power mode, if all devices are powered off, the I / O performance of the storage system may decrease or I / O processing may time out due to the long transition time, and this process takes these factors into consideration when making a decision.

[0118] The power mode decision program 303 determines whether or not all of the target devices can be powered off based on the result of step S1303 (step S1304). If the result of the determination is that all of the target devices can be powered off (step S1304: Yes), step S1305 is executed. On the other hand, if all of the target devices cannot be powered off (step S1304: No), step S1306 is executed.

[0119] The power mode decision program 303 decides that the power mode of all the target devices is power OFF (step S1306), after which step S1315 is executed.

[0120] The power mode decision program 303 determines whether some of the target devices can be powered off (step S1306). There are cases where some of the target devices cannot be powered off, and this determination is necessary. For example, there are cases where some processing cooperation exists between the target devices and processing cannot continue unless all devices are operating, and this process takes these into consideration when making the determination.

[0121] The power mode decision program 303 determines whether or not some of the target devices can be powered off based on the result of step S1306 (step S1307). If the result of the determination is that some of the target devices can be powered off (step S1307: Yes), step S1308 is executed. On the other hand, if some of the target devices cannot be powered off (step S1307: No), step S1309 is executed.

[0122] The power mode decision program 303 enables some of the target devices to include power OFF as a power mode, and continues processing (step S1308). After that, step S1310 is executed.

[0123] The power mode decision program 303 continues the process so as not to include power OFF as the power mode of the target device (step S1309). Then, step S1310 is executed.

[0124] The power mode decision program 303 determines whether or not it is necessary to unify the power modes of all the target devices (step S1310). For this determination, a table containing information on whether or not it is necessary to unify the power modes may be prepared and referenced, or the device may be accessed at this point to check. For example, the memory 107 has the CPU 106 as a connected device, but there are cases in which the CPU 106 uses the memory 107 in an interleaved manner. In this case, it is necessary to unify the processing performance of the multiple memories 107 connected to the same CPU 106, that is, to unify the power modes. Therefore, the determination is made taking into consideration the cooperation between these devices, etc.

[0125] The power mode decision program 303 determines whether or not it is necessary to unify the power modes of all of the target devices based on the result of step S1310 (step S1311). If the determination result indicates that it is necessary to unify the power modes of all of the target devices (step S1311: Yes), the program proceeds to process 1312. On the other hand, if it is not necessary to unify the power modes of all of the target devices (step S1311: No), step S1313 is executed.

[0126] The power mode decision program 303 continues processing to unify the power modes of the target devices (step S1312), after which step S1314 is executed.

[0127] The power mode decision program 303 determines that it is not necessary to unify the power modes of the target device and continues processing (step S1313). After that, step S1314 is executed.

[0128] The power mode determination program 303 determines the combination of power modes that will reduce power consumption the most so as to satisfy these requirements, based on the results of steps S1301, S1308, S1309, S1312, and S1313. For example, if the processing load can be concentrated on a specific device, it is possible to create a device that can reduce the processing load to zero, and by combining this with the OFF power mode, it may be possible to provide processing capacity that exceeds the predicted value of the future processing load while reducing power consumption more than by equalizing the processing load between devices.

[0129] For example, if the predicted future processing load for four accelerators 110 is 50%, and processing is uniformly distributed among the four accelerators 110, they can operate in power saving mode B 506, and the total power consumption will be 20W×4=80W (average processing capacity 50%). On the other hand, if the processing load is concentrated on two accelerators 110 and control is performed so that processing is not requested of the two accelerators 110, the accelerators on which the processing load is concentrated can operate in normal mode 503, and the remaining two accelerators 110 can operate with power OFF 504, and the total power consumption will be 30W×2+0W×2=60W (average processing capacity 50%), and if the requirements are met, the latter combination of power modes is selected.

[0130] Incidentally, an operation mode of the storage system that tolerates a decrease in I / O performance may be prepared, and the power mode may be determined so as to give priority to reducing power consumption by allowing the user of the storage system 102 to select this mode. Then, step S1315 is executed.

[0131] The power mode decision program 303 returns the result of the power mode decision calculated in step S1305 or step S1314 to the caller, and ends the power mode combination decision process (step S1315).

[0132] 14 is a flowchart showing an example of the procedure of the power mode change process. The power mode change process is called from the device power mode determination process performed in the power consumption control process described above. The power mode change process is executed by the power mode change program 304 under the control of the CPU 106.

[0133] The power mode change program 304 receives a list of target devices and the determined power mode from the calling process (step S1401).

[0134] The power mode change program 304 acquires information about the target device from the device operation history table 402 (step S1402).

[0135] The power mode change program 304 starts processing from the top of the target device list received in step S1401 (step S1403).

[0136] The power mode change program 304 compares the current power mode with the changed power mode based on the information about the target device obtained in steps S1401 and S1402, and determines whether the power mode of the target device needs to be changed (step S1404).

[0137] If the power modes are different as a result of the comparison, the power mode change program 304 determines that a power mode change is necessary, and if they are the same, determines that a power mode change is not necessary. If the determination results in a power mode change being necessary (step S1404: Yes), step S1405 is executed. On the other hand, if a power mode change is not necessary (step S1404: No), step S1415 is executed.

[0138] The power mode change program 304 determines whether the power mode to be changed to is power OFF based on the information obtained in step S1401 (step S1405). If the result of the determination is that the power mode is power OFF (step S1405: Yes), step S1406 is executed. On the other hand, if the power mode is not power OFF (step S1405: No), step S1409 is executed.

[0139] The power mode change program 304 stops the processing request to the device (step S1406). The power mode change program 304 waits until all processing requests to the device are completed (step S1407). Note that steps S1406 and S1407 are performed to ensure that the processing requests to the device are completed normally and to prevent the I / O processing of the storage system 102 from abnormally stopping.

[0140] The power mode change program 304 changes the power mode of the device to power OFF (step S1408), after which step S1415 is executed.

[0141] The power mode change program 304 determines whether or not specific processing is required when changing the power mode of the device (step S1409). Note that, in this determination, information on whether or not specific processing is required when changing the power mode for each device may be stored in advance as a table, and this may be referred to in advance.

[0142] The power mode change program 304 determines whether or not unique pre-processing is required when changing the power mode of the device based on the result of step S1409 (step S1410). If the result of the determination is that unique pre-processing is required (step S1410: Yes), step S1411 is executed. On the other hand, if unique pre-processing is not required (step S1410: No), step S1412 is executed.

[0143] The power mode change program 304 executes a unique pre-processing associated with the power mode change (step S1411). For example, when the power mode is changed from power OFF, a startup process for the device is executed.

[0144] The power mode change program 304 changes the power mode of the device to the determined one (step S1412).

[0145] Based on the result of step S1409, the power mode change program 304 determines whether or not unique post-processing is required after changing the power mode of the device (step S1413). If the result of the determination is that unique post-processing is required (step S1413: Yes), step S1414 is executed. On the other hand, if unique pre-processing is not required (step S1413: No), step S1415 is executed.

[0146] The power mode change program 304 executes a specific post-processing associated with the power mode change (step S1414). For example, after the power mode has been changed from power OFF, a processing request to the device is permitted.

[0147] The power mode change program 304 refers to the list of target devices received in step S1401 and determines whether there is a device next to the current device (step S1415). If the determination result shows that there is a next device (step S1415: Yes), step S1416 is executed. On the other hand, if there is no next device, the power mode change process is terminated. .

[0148] The power mode change program 304 refers to the list of target devices received in step S1401, and starts processing from the device next to the current device (step S1416), after which step S1404 is executed.

[0149] In this manner, in storage system 102, the power mode of each device mounted on at least one controller 104 is appropriately changed so as to minimize the power consumption of each device, without affecting the I / O performance with host machine 103. Furthermore, in storage system 102, if the I / O load from host machine 103 changes, the power mode of each device, changed as described above, is further changed, without affecting the I / O performance with host machine 103.

[0150] As described above, the storage system 100 according to this embodiment is a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, and is equipped with a plurality of components (a plurality of devices) that can each operate by switching between a normal power mode and at least one power saving mode (including a power OFF mode) that consumes less power than the normal power mode, a device operation status monitoring program 302 as an example of a status monitoring unit that monitors the operation status of each of the plurality of components, and a power mode control unit 305 (power mode determination program 303, power mode change program 304) that determines the power mode of at least one specific device to be the power saving mode based on the processing load for each of the plurality of devices as a result of monitoring by the device operation status monitoring program 302, and operates the at least one specific device in the power saving mode.

[0151] The power consumption reduction method according to this embodiment is a power consumption reduction method for a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, and includes a status monitoring step in which a device operation status monitoring program 302 as an example of a status monitoring unit monitors the operation status of each of a plurality of devices as an example of a plurality of components that can each operate by switching between a normal power mode and at least one power saving mode that consumes less power than the normal power mode, and a power mode control step in which a power mode control unit 305 determines the power mode of at least one specific device to be the power saving mode based on the processing load for each of the multiple devices that is the result of monitoring by the status monitoring step, and operates the at least one specific device in the power saving mode, and performs control between the storage device and the multiple devices in response to the data input / output request.

[0152] Generally, a storage system is composed of various devices such as multiple CPUs and I / O modules, and each of these devices has its own power management function. The power management function includes a power mode that can reduce power consumption in exchange for a decrease in processing performance, and a function that can turn off the power individually. In addition, the storage system does not always operate at maximum load, but is operated with a margin so that services can be provided without problems even if some of the redundant parts fail and the I / O performance that can be provided decreases. Therefore, as described above, the storage system 102 monitors the processing load of each device, and for devices with low processing loads, switches them to an operation mode with low power consumption within a range that does not affect I / O performance, or turns off some of the power. With the above configuration, it is possible to reduce the power consumption of the storage system 102 by suppressing the power consumption of devices that do not affect I / O performance without degrading the input / output performance with the host machine 103.

[0153] In this embodiment, the multiple components are multiple devices that control data input / output processing with the host, and the controller 104 is equipped with these multiple devices and includes at least one controller 104 that controls data input / output processing with the host by the multiple devices, and the controller 104 includes a device operating status monitoring program 302 as an example of a status monitoring unit, a power mode determination program 303 and a power mode change program 304 included in the power mode control unit 205. In this way, it is possible to reduce power consumption of the storage system 102 by suppressing power consumption of devices that do not affect I / O performance without degrading input / output performance with the host machine 103.

[0154] In this embodiment, the above-mentioned power mode control unit 305 comprises a power mode decision program 303 that decides to set the power mode of a specific device among multiple devices operating in a power saving mode to the power saving mode based on the magnitude of the impact on I / O performance with the host machine 103 when the power mode of the specific device is changed to the power saving mode, and a power mode change program 304 that switches the power mode of the specific device to the decided power saving mode. In this way, it is possible to reduce power consumption of the storage system 102 without degrading I / O performance with the host machine 103.

[0155] The storage system 102 according to this embodiment includes a device management table 401 for managing information on a plurality of devices, and a device operation history table 402 for managing the operation states of a plurality of devices monitored by a device operation status monitoring program 302, and the power mode decision program 303 decides to set the power mode of a particular device to the power saving mode when it determines, based on the operation states of the plurality of devices managed in the device operation history table 402, that changing the power mode of the particular device to the power saving mode will have an effect on data input / output processing (for example, I / O performance with the host machine 103) below a predetermined standard for the plurality of devices managed in the device management table 401. In this way, it is possible to reduce the power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0156] In this embodiment, the device management table 401 manages the power consumption and processing capacity for each of the multiple devices in the normal power mode and the power saving mode, and the power mode control unit 305 determines the power saving mode for the power mode of a specific device based on the power consumption and processing capacity for each of the multiple devices in the normal power mode and the power saving mode managed in the device management table, and changes the power mode of the specific device to the power saving mode. In this way, the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0157] In this embodiment, the device management table 401 manages the power mode control for a plurality of devices into a first category in which the control is executed independently of other devices, and a second category in which the control is executed in combination with other devices, and specifies the power control unit 502 (see FIG. 5). In this way, the power mode decision program 303 changes the power mode in detail for at least one device in consideration of the power control unit 502 in the device management table 401, so that it is possible to further reduce the power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0158] In this embodiment, the device management table 401 manages, as power control units 502, for example, device units including devices that are considered to be independent from other devices in terms of power consumption control, connected device units (for example, memory 107 groups) including devices whose power modes should be changed to match other devices, and controller units including controller groups (for example, accelerator 110 groups) that should exhibit approximately the same performance for each of a plurality of controllers 104. In this way, the power modes of devices are changed collectively in more preferable units, making it possible to further reduce power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0159] In this embodiment, the power mode control unit 305 classifies the multiple devices into devices that are to be grouped because they have low mutual independence from the viewpoint of controlling power consumption of the multiple devices, and devices that are to be not grouped because they have high mutual independence from the viewpoint of controlling power consumption of the multiple devices, and switches the power mode of each of the grouped devices and the non-grouped devices to a power saving mode according to the results of monitoring by the device operating status monitoring program 302. In this way, the power mode of each device is changed taking into consideration its independence from other devices, so that the power consumption of the storage system 102 can be further reduced without degrading the I / O performance with the host machine 103.

[0160] In this embodiment, when there are multiple devices that can be grouped, the power mode control unit 305 classifies the devices into a first device group (e.g., memory 107) for which the power mode change manner should be the same for the multiple devices to be grouped, and a second device group for which the power mode change manner does not need to be the same for the multiple devices to be grouped, and changes the power mode of the first device group so that the post-change power modes are the same. In this way, the first device group for which the power mode change manner should be the same for the multiple devices that can be grouped is controlled so that the post-change power modes are the same, so that the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0161] In this embodiment, the power mode control unit 305 classifies devices into those that allow power OFF as a power saving mode and those that do not allow power OFF as a power saving mode (for example, a host I / F connected to the host machine 103) (for example, determined in S1008 of FIG. 10), and for devices that allow power OFF as a power saving mode, the power mode is switched to power OFF according to the result of monitoring by the device operation status monitoring program 302, while for devices that do not allow power OFF as a power saving mode, the power mode is switched to a power saving mode (not including power OFF) according to the result of monitoring by the device operation status monitoring program 302. In this way, if the devices are classified appropriately, devices that allow power to be completely stopped do not consume any power at all, so that it is possible to further reduce the power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0162] In this embodiment, the power mode decision program 303 takes into consideration a combination of specific devices that have dependencies as connection destination devices and decides the power mode for the specific combination of devices. In this way, a combination of power modes for a plurality of devices that have dependencies is decided, so that the dependency of the specific combination of devices is not broken, and it is possible to reduce power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0163] In this embodiment, when the predicted future processing load for a plurality of specific devices is zero and power OFF is permitted, if it is necessary to unify the plurality of specific devices, the power mode decision program 303 decides to unify the power modes of the plurality of specific devices to power OFF. In this way, it is possible to reduce power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0164] (2) Second embodiment In the second embodiment, the description of the configuration and operation similar to those of the first embodiment will be omitted, and the following description will focus mainly on the differences from the first embodiment.

[0165] 15 is a system configuration diagram showing an example of the configuration of an information system 1501 according to the second embodiment. In the first embodiment, the power mode according to the processing load is controlled in units of a plurality of components constituting a storage system, for example, a device such as various electronic devices and parts, but in the second embodiment, the power mode according to the processing load is controlled in units of a plurality of components implemented in a storage system 1502, for example, each controller 1506.

[0166] The information system 1501 comprises one or more storage systems 1502, one or more host machines 1503, and one or more storage area networks (SAN) 1504. One or more management terminals 1505 are configured as part of the storage system 1502, for example.

[0167] The storage system 1502 comprises one or more controllers 1506, one or more inter-storage controller networks 1507, one or more PDEV BOXes 1508, and one or more networks for management terminals.

[0168] The PDEV BOX 1508 includes one or more PDEVs 1514. Although not shown, the PDEV BOX 1508 may have the same configuration as the PDEV BOX 105. In Fig. 15, the controller 1506 and the PDEV BOX 1508 are directly connected, but they may also be connected via a network (not shown).

[0169] The controller 1506 comprises a host I / F 1510, an inter-controller I / F 1511, a PDEV I / F 1512, and a management terminal I / F 1513. Although not shown, the controller 1506 may have the same configuration as the controller 104 of Fig. 1 in the first embodiment, and may include a CPU (Central Processing Unit), memory, an accelerator, and a network switch.

[0170] The host I / F 1510 is connected to a host machine 1503 via a SAN 1504, and performs I / O requests and sending / receiving I / O data. The inter-controller I / F 1511 is connected to an inter-controller I / F 1511 of another controller 1506 via an inter-storage controller network 1507, and performs processing requests / responses and data transfer between the controllers 1506.

[0171] The PDEV I / F 1512 transmits and receives data to and from a PDEV 1514 in a PDEV BOX 1508. The management terminal I / F 1513 is connected to a management terminal 1505 via a management terminal network 1509, receives processing requests from the management terminal 1505, and responds with processing results.

[0172] The management terminal 1505 includes a CPU 1515 , a memory 1516 , an auxiliary storage device 1517 , an input device 1518 , an output device 1519 , and a network I / F 1520 .

[0173] The CPU 1515 controls the entire management terminal 1505, and operates based on a program stored in a memory 1516. The auxiliary storage device 1517 is controlled by the CPU 1515, and writes / reads the programs and management information stored in the memory 1516, thereby making them non-volatile.

[0174] The input device 1518 is controlled by the CPU 1515, and is used when the storage administrator operates the management terminal 1505. The output device 1519 is controlled by the CPU 1515, and is used when the storage administrator refers to information held by the management terminal 1505. The network I / F 1520 is controlled by the CPU 1515, and requests processing from the controller 1506 in the storage system 1502, and receives the processing results.

[0175] In this embodiment, the management terminal 1505 is configured independent of the storage system 1502, but may be built into the storage system 1502. Also, those connected via a network, such as the SAN 1504, the network between storage controllers 1507, and the management terminal network 1509, may be directly connected, and those not connected via a network may be connected via a network.

[0176] FIG. 16 is a diagram showing an example of the configuration of the memory 1516 of the management terminal 1505 shown in FIG. In the memory 1516, a program area 1601 and a management information area 1602 are secured.

[0177] The program area 1601 is an area in which various programs for executing processes by the CPU 1515 are stored. The management information area 1602 is an area in which various management tables are stored and is accessed by the CPU 1515. The program area 1601 and the management information area 1602 will be described in detail later.

[0178] Fig. 17 is a diagram showing an example of programs stored in the program area 1601 shown in Fig. 16. Fig. 17 corresponds to Fig. 3 in the first embodiment, except that the control target of the power mode is different. The program area 1601 stores, for example, a controller management program 1701, a controller power consumption control program 1702, a controller operational state monitoring program 1703, and a controller power mode determination and change program 1704.

[0179] The management terminal 1505 executes a controller management program 1701 to implement input / output control and the like so that a storage administrator can manage the controller 1506 .

[0180] Furthermore, by executing the controller power consumption control program 1702, the management terminal 1505 can reduce power consumption without degrading the I / O performance of the storage system 1502. The controller power consumption control program 1702 has the same functions as the power consumption control program 301 in the first embodiment, except that the power mode control target is the controller 1506 instead of a device.

[0181] During the course of its processing, the controller power consumption control program 1702 also calls a controller operational status monitoring program 1703 which monitors the processing load of the controller 1506 and stores historical information, and a power mode determination and change program 1704 which controls the power mode of each controller 1506 based on the aforementioned historical information, etc.

[0182] Here, the storage system according to this embodiment is a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, and includes a plurality of components (a plurality of controllers 1506) as an example of a plurality of components that can each be operated by switching between a normal power mode and at least one power saving mode that consumes less power than the normal power mode. The storage system according to this embodiment includes a controller operational status monitoring program 1703 as an example of a status monitoring unit that monitors the operational status of each of the plurality of components, and a controller power mode determination and change program 1704 as an example of a power mode control unit that determines the power mode of a specific component to be the power saving mode based on the processing load for each of the plurality of components that is a result of monitoring by the controller operational status monitoring program 1703, and operates the specific component in the power saving mode.

[0183] In this embodiment, the above-mentioned components are a plurality of controllers 1506 which control data input / output processing with the host, and the storage system according to this embodiment comprises a management terminal 1505 which controls the plurality of controllers, and the management terminal 1505 comprises a controller operation status monitoring program 1703 as an example of a status monitoring unit, and a controller power mode determination and change program 1704 as an example of a power mode control unit.

[0184] The controller operational status monitoring program 1703 has the same functions as the device operational status monitoring program 302 in the first embodiment, except that the power mode control target is the controller 1506 instead of the device.

[0185] Except for the fact that the power mode is controlled by the controller 1506 instead of the device, the power mode control unit 305 has the same functions as the power mode control unit 305 (the power mode determination program 303 and the power mode change program 304) in the first embodiment.

[0186] In this embodiment, the controller power mode determination and change program 1704 selects a specific power mode that can immediately transition to a state in which input / output processing can be executed by the other controller in response to detection of a failure that has occurred in one of the multiple controllers, based on a redundancy setting (for example, durability against controller failure (N-redundancy)). In this way, even if a failure occurs in one of the controllers, input / output processing can be executed immediately.

[0187] In this embodiment, the controller power mode determination and change program 1704 enables the other controllers to transition to a state in which they can execute input / output processing immediately after the above, while operating some of the cores of a CPU (Central Processing Unit) that has multiple cores, and putting the other cores on standby. In this way, the CPU is operated with the minimum number of cores, so that power consumption can be further reduced.

[0188] Fig. 18 is a diagram showing an example of information stored in the management information area 1602 shown in Fig. 16. In the management information area 1602, a controller management table 1801, a controller operation history table 1802, and a controller power setting information table 1803 are stored.

[0189] The controller management table 1801 has information relating to the controller 1506 that constitutes the storage system 1502, and is used in the process of determining the power mode. The controller management table 1801 will be described in detail later.

[0190] The controller operation history table 1802 has history information such as the processing load from the past to the present in the controller 1506 constituting the storage system 1502, and is used in the process of determining the power mode. The controller operation history table 1802 will be described in detail later.

[0191] The controller power setting information table 1803 has information set by the storage system administrator to control the power consumption and the like of the storage system 1502. The controller power setting information table 1803 will be described in detail later.

[0192] Fig. 19 is a diagram showing an example of the configuration of the controller management table 1801 shown in Fig. 18. The controller management table 1801 has entries for a controller identifier 1901, a normal mode 1902 (first power mode), power OFF 1903, a standby mode 1904 (third power mode), a power saving mode A 1905 (one of the second power modes), and a power saving mode B 1906 (one of the second power modes).

[0193] The controller identifier 1901 is an identifier of the controller 1506 mounted in the storage system 1502. For example, the controllers 1506 in Fig. 15 are assigned identifiers ABC_1, ABC_2, ABC_3, and ABC_4 from top to bottom, respectively.

[0194] Normal mode 1902, power off 1903, standby mode 1904, power saving mode A 1905, and power saving mode B 1906 corresponding to each controller identifier 1901 indicate the power modes of the controller 1506 installed in the storage system 1502, and each has its own power consumption and processing capacity (relative values ​​when normal mode is 100%).

[0195] In this embodiment, the number of power modes is five, but it is sufficient that the number is two or more. Also, depending on the controller 1506, the number of corresponding power modes may differ, or some controllers may not have multiple power modes. Here, referring to a case where no power mode is present, it means a case where, in a storage system 1502 having multiple controllers 1506, some controllers have a changeable power mode, while other controllers are set so that the power mode cannot be changed, or do not have a function for changing the power mode. Also, in this embodiment, the two items of power consumption and processing capacity are mainly mentioned, but other items such as restrictions (functions are limited) when the power mode is used, and other information required for selecting a power mode may be mentioned.

[0196] Here, the difference between the power OFF 1903 and the standby mode 1904 will be described. Both of them have a common point that the processing capacity is 0% and I / O processing cannot be executed in the current state. The power OFF 1903 is a state in which the controller 1506 is stopped, and although the power consumption is zero, it is a mode that takes time to make the I / O processing executable (start). On the other hand, the standby mode 1904 is a mode that consumes some power, but takes an extremely short time to make the I / O processing executable. This standby mode 1904 focuses on the multi-core configuration of the CPU used generally in the controller 1506 and utilizes its advantages. For example, the standby mode 1904 is implemented in such a way that only one core of the CPU mounted on the controller 1506 is started and the remaining cores are stopped, and when it becomes necessary to transition to a state in which I / O processing can be executed, the stopped core of the CPU and the device required for I / O can be immediately started. Generally, in a storage system used for business purposes, it is necessary to be able to continue I / O processing even if at least one storage controller stops due to a failure. This is because even if the processing load of the storage system 1502 is low and the processing capacity is not affected even if some storage controllers are stopped, there are cases where it is necessary to assume a storage controller failure and keep the system in a state where I / O processing can be performed immediately, and in such cases, using the standby mode 1904 is very useful in achieving both power saving and continuity (availability) of I / O processing.

[0197] Fig. 20 is a diagram showing an example of the configuration of the controller operation history table 1802 shown in Fig. 18. The controller operation history table 1802 has entries of a collection time 2001, a controller identifier 2002, a status 2003, a power mode 2004, and a processing load 2005.

[0198] The collection time 2001 indicates the time when the history of the storage controller was collected. The collection time 2001 may be, for example, the time elapsed since the storage system was started. The controller identifier 2002 is an identifier of the controller 1506, and indicates the correspondence with the controller identifier 1901 in the controller management table 1801.

[0199] The status 2003 indicates the operating status of the controller 1506. The status 2003 has information such as "normal" or "abnormal (unable to start, unable to process I / O)". The power mode 2004 indicates the power mode of the storage controller. The power mode 2004 is one of the normal mode 1902, power off 1903, standby mode 1904, power saving mode A 1905, and power saving mode B 1906 in the controller management table 1801. The processing load 2005 indicates the processing load of the controller 1506.

[0200] Figures 21A to 21C are diagrams showing example settings of the controller power setting information table 1803 shown in Figure 18. Note that Figures 21A to 21C collectively show the power setting information of the controllers 1506 included in the storage system 1502, and are managed separately from the power modes set for the individual controllers 1506.

[0201] The controller power setting information table 1803 has entries for a power saving mode setting 2101, a redundancy setting value 2102, and a power consumption upper limit value 2103. Here, an example of stored information is shown based on three setting examples, which will be explained below.

[0202] 21A shows a case where the method of reducing power consumption in this embodiment is not used (the normal mode is always used as the power mode of the controller 1506 as in the past). At this time, the redundancy setting value 2102 and the power consumption upper limit value 2103 do not contain information.

[0203] The setting example of FIG. 21B shows a case where a method of reducing power consumption according to processing load without degrading I / O processing performance in this embodiment is applied to the storage system 1502. At this time, the redundancy setting value 2102 shows information on whether the system is operated at an arbitrary degree of multiplexing (redundancy) so that I / O processing can be continued when the controller 1506 fails. In this embodiment, the redundancy is defined as "n multiplexing (n: natural number)", and redundancy 1 indicates 2 multiplexing (i.e. duplication), meaning that any I / O can be processed by two or more controllers 1506, and indicating that I / O processing can be continued even if one storage controller fails. In other words, in the case of N multiplexing (in other words, when N-1 redundancy is given), it means that any I / O can be processed by N or more controllers 1506, and indicating that I / O processing can be continued even if N-1 storage controllers fail. In addition, in such a situation where a storage controller fails, if any of the normally operating storage controllers detects that the current redundancy of the storage system 1502 is below the designated redundancy, the normally operating storage controller starts up the storage controller that is powered off or set to standby mode in response to the detection, and recovers the redundancy. In addition, in this recovery process, for example, if there are both a powered off storage controller and a standby mode storage controller, the standby mode storage controller is shifted to active, and the powered off storage controller is shifted to standby mode. This enables a quick recovery process of redundancy, and also makes it possible to prepare a stock of standby mode storage controllers that can be quickly started up in the event of further storage controller failures.

[0204] 21C shows a case where an upper limit value for power consumption is further set in the storage system 1502 so that a desired power consumption is not exceeded even if the processing load increases. At this time, the upper limit value for power consumption set by the user is stored in the power consumption upper limit value 2103.

[0205] FIG. 22 is a diagram showing an example of data exchanged in a processing request and response between the storage system 1502 and the management terminal 1505 shown in FIG.

[0206] An operation information acquisition request 2201 is sent to the storage system 1502 when the management terminal 1505 wishes to acquire operation information of each controller 1506. The operation information acquisition request 2201 includes the identifier of the destination controller 1506, the request source, and the contents of the request.

[0207] The response 2202 to the operation information acquisition request is sent from the controller 1506 that acquired the operation information to the management terminal 1505 in the storage system 1502. The response 2202 to the operation information acquisition request includes the destination, the identifier of the controller 1506 that issued the request, the contents of the request, and the acquired operation information. Note that the operation information corresponds to one entry in the controller operation history table 1802.

[0208] The power mode change request 2203 is sent from the management terminal 1505 to the storage system 1502 when it is desired to change the power mode of the controller 1506. The power mode change request 2203 includes the identifier of the destination controller 1506, the request source, the contents of the request, and information on the power mode to which the change is to be made.

[0209] The response 2204 to the power mode change request is sent from the controller 1506 that has completed the power mode change in the storage system 1502 to the management terminal 1505. The response 2204 to the power mode change request includes the destination, the identifier of the controller 1506 that made the request, and the result (content) of the processing.

[0210] 23 is a diagram showing an example of the storage system management screen 2301. The storage system management screen 2301 is displayed on the management terminal 1505.

[0211] A storage system management screen 2301 comprises a menu bar 2302 and a screen 2303 corresponding to each menu. Here, the screen is shown in a state where the power mode setting menu has been selected.

[0212] The screen 2303 has system operation information 2304 , controller-based operation information 2305 , power saving mode setting information 2306 for the storage system 1502 , and redundancy setting information 2307 for the storage system 1502 .

[0213] The system-based operation information 2304 displays information related to the storage system 1502 managed by the management terminal 1505. For example, the information includes the current processing load value, the predicted future processing load value, the current power consumption value, the current power reduction effect (according to this embodiment), the maximum power consumption (upper limit value), and the maximum processing capacity, and other information set by the user.

[0214] Per-controller operational information 2305 displays current information about each controller 1506 included in the storage system 1502, such as the controller identifier, status, power mode, and processing load.

[0215] The power saving mode setting information 2306 is an interface that accepts user input for selecting a power saving mode for the storage system 1502, and also functions as a display interface for referring to the current setting information.

[0216] The redundancy setting information 2307 is an interface for receiving a user input for selecting a redundancy (how many layers the storage system should be operated with) for the storage system 1502, and also functions as a display interface for referring to the current setting information. Information such as the maximum power consumption (upper limit) included in the power saving mode setting information 2306, the redundancy setting information 2307 and the operation information 2304 is also reflected in the controller power setting information table 1803 shown in Figs. 21A to 21C, and is used for setting the power mode for each controller 1506. Note that the screen configuration shown here is an example, and may be implemented in a format other than this. For example, an interactive command line interface may be used.

[0217] 24 is a flowchart showing an example of a procedure for controller power consumption control processing. The controller power consumption control processing is processing for reducing power consumption in the management terminal 1505.

[0218] This controller power consumption control process is executed by CPU 1515 when management terminal 1505 is started, and is therefore an example of automatically executing power consumption reduction control (for example, a case can be assumed in which "automatic" is selected as the power saving mode setting information in FIG. 23).

[0219] An overview of the process of monitoring the processing load of each controller 1506, and the request / response process of the power mode to be set for each controller 1506 determined based on the monitoring results, the set redundancy, and the specified maximum power consumption is shown in FIG. 22 above.

[0220] 24, for example, the following three steps are executed in automatically executing the controller power consumption control process. Note that the execution of these steps can be realized by the CPU 1515 reading out a controller management program 1701 stored in the program area 1601 of the memory 1516 in response to the start-up of the management terminal 1505 or the update of the power saving mode setting information 2306, and by executing this controller management program 1701, a controller power consumption control program 1702, a controller operating state monitoring program 1703, and a controller power mode determination and change program 1704 are executed.

[0221] In the first step, when the management terminal 1505 is started up, the CPU 1515 monitors the processing load of the controller 1506 connected to the management terminal 1505, and records it in the controller operation history table 1802 (step S2401). More specifically, for example, when automatic is specified as the power saving mode setting, optimization of the power mode is executed periodically or in response to a user instruction. First, the controller management program 1701 is executed, and as a step included in the processing, the CPU 1515 reads and executes the controller operation status monitoring program 1703, and executes monitoring of the processing load of the controller 1506.

[0222] The controller operational status monitoring program 1703 accesses the controller management table 1801 to acquire information on the controller identifier 1901. The controller operational status monitoring program 1703 determines the other party (destination) to which a request for confirmation of the processing load status is to be made based on the controller identifier 1901, and transmits the request source (i.e., the management terminal 1505) and the request contents (request to acquire operational information) together as an operational information acquisition request 2201 to the storage system 1502. In parallel with these processes, the CPU 1515 records the collection time 2001, and this recording is performed, for example, in step S2502 shown in Fig. 25 described later.

[0223] When any of the controllers 1506 in the storage system 1502 receives the operation information acquisition request 2201, the controller 1506 transfers the operation information acquisition request 2201 to the controller 1506 to which the corresponding controller identifier 1901 is assigned, in accordance with the controller identifier 1901 included in the operation information acquisition request 2201.

[0224] The controller 1506 that has received the transferred operation information acquisition request 2201 acquires its own operation information in accordance with the request for operation information acquisition contained in the operation information acquisition request 2201. Next, the controller 1506 executes a response 2202 to the operation information acquisition request, which includes a completion notice of operation information acquisition in response to the operation information acquisition request 2201, sender information (i.e., the controller identifier 1901 assigned to itself as the requester) and destination information (the management terminal 1505), for the acquired operation information. Note that the operation information includes, for example, information such as the controller identifier 1901, status, applied power mode, and processing load. Note that, as an example of the processing load, a percentage is displayed obtained by dividing the I / O processing volume per any unit time by the maximum volume specified, but the definition of the processing load is not limited to this.

[0225] The management terminal 1505, which has received the response 2202 to the performance information acquisition request, writes the performance information into the controller performance history table 1802 stored in the memory 1516 as shown in Fig. 20. Further details of this step 2401 will be explained with reference to Fig. 25.

[0226] Next, in a second step, the controller power mode determination and change program 1704 refers to the controller management table 1801, the controller operation history table 1802, and the controller power setting information table 1803, and determines the power mode of each controller 1506 based on the operation history and setting information, and changes the power mode if necessary (step S2402). Note that the details of the processing content in steps S2401 and S2402 when automated will be described later, but for example, the following processing is executed.

[0227] First, the controller management program 1701 reads and executes the controller power consumption control program 1702. The controller power consumption control program 1702 accesses the management information area 1602 to obtain related information and determines the power mode to be applied to each controller 1506. The determined power mode is transmitted from the management terminal 1505 to the storage system 1502.

[0228] For example, as shown in FIG. 22 above, the management terminal 1505 issues a power mode change request 2203 to the storage system 1502, which includes destination information (controller identifier 1901), the request source (i.e. the management terminal 1505), instruction content (i.e. the power mode change request), and a specified power mode (the power mode requested to be applied). The issued power mode change request 2203 is received by one of the controllers 1506, and transferred to the corresponding controller 1506 based on the controller identifier 1901. For example, when the controller 1506 receives the power mode change request 2203 addressed to itself, the controller 1506 executes the necessary processing. This necessary processing includes step S1407 (waiting for processing request) and step S1411 (unique pre-processing) of FIG. 14 in the first embodiment.

[0229] The controller 1506, which has processed the issued power mode change request 2203, executes a response to the management terminal 1505 (response to the power mode change request 2204).

[0230] In the third step, the CPU 1515 determines the next opportunity to execute the power consumption control process and ends the process (step S2403). The next opportunity may be, for example, after a certain period of time has elapsed, or one or more conditions may be set, such as when the storage administrator operates the management terminal 1505 or when a storage controller is installed or removed. In any case, information regarding the determined opportunity may be stored in a designated area (not shown) of the management information area 1602 as a variable related to the start of the controller management program 1701.

[0231] Fig. 25 is a flow chart showing an example of the procedure of the controller operational status monitoring process shown in Fig. 24. The controller operational status monitoring process is executed by the storage system power consumption control process executed in the management terminal 1505.

[0232] The CPU 1515 refers to the controller management table 1801 and starts monitoring from the controller described in the first row (step S2501). Note that, although monitoring is started from the controller described in the first row here, the order is not limited to this. That's good.

[0233] The CPU 1515 acquires the current date and time (step S2502). The date and time acquired here is information equivalent to the collection time 2001 in the controller operation history table 1802, and may be the time of day or the elapsed time since the storage system 102 was started, for example.

[0234] The CPU 1515 issues a processing request to the target controller 1506 to obtain operating information (status, power mode, and processing load), puts the processing on hold until the result is received, and proceeds to the next process upon receipt of the result (step S2503).

[0235] The CPU 1515 acquires operation information of the target controller 1506 (step S2504), and adds the acquired information (current date and time, status, power mode, and processing load) to a storage system management history table (not shown) (step S2505).

[0236] The CPU 1515 refers to the controller management table 1801 and judges whether or not there is a storage controller next to the currently targeted storage controller (step S2506). If the result of the judgment indicates that there is a next storage controller (step S2506: Yes), the process proceeds to step S2507. On the other hand, if there is no next storage controller (step S2506: No), the process ends.

[0237] The CPU 1515 refers to the controller management table 1801, targets the storage controller next to the currently targeted storage controller, starts the controller operational status monitoring program 1703, and starts monitoring the load of each controller 1506 (step S2507). Then, the process proceeds to step S2502.

[0238] Fig. 26 is a flowchart showing an example of the procedure for the controller power mode determination and change processing shown in Fig. 24. The controller power mode determination and change processing shows an example of a process (for example, process 2402 shown in Fig. 24) implemented in the storage system power consumption control processing in the management terminal 1505.

[0239] The CPU 1515 starts the controller power mode determination and change program 1704, and references the controller power setting information table 1803 to acquire setting information (power saving mode, redundancy setting value, and power consumption upper limit) (step S2601).

[0240] The controller power mode determination and change program 1704 judges whether the power saving mode of the storage system 1502 is OFF or not based on the information acquired in step S2601 (i.e., it is confirmed whether the power saving mode setting function of the storage system 1502 is stopped or not). If the result of the judgment is that it is not OFF (step S2602: Yes), the program proceeds to step S2603. On the other hand, if the result of the judgment is that it is OFF (step S2602: No), the program proceeds to step S2604.

[0241] The controller power mode determination and change program 1704 calculates the minimum number of storage controllers capable of I / O processing (X) that can maintain redundancy based on the redundancy setting value acquired in step S2601 (step S2603). Note that an "I / O processing capable storage controller" refers to a controller whose processing capacity is not zero, such as a power mode of "power off" or "standby mode." For example, if the redundancy setting value is 1 and 2-multiplex, (X) will be 2, and if the redundancy setting value is 2 and 3-multiplex, (X) will be 3. Then, the process proceeds to step 2605.

[0242] The controller power mode determination and change program 1704 determines the power mode of all the controllers 1506 in the storage system 1502 to be “normal mode” (step S2604).

[0243] The controller power mode determination and change program 1704 refers to the controller operation history table 1802 and predicts the future processing load (step S2605). For example, by acquiring the collection time 2001 and the processing load 2005, it is possible to check the fluctuation in the processing load of the device in chronological order and predict the future processing load. Note that the future processing load may be predicted using information other than the controller operation history table 1802. For example, the amount of change in the number of logical volumes defined in the storage system 1502 or the amount of change in the number of connected hosts may be used.

[0244] Next, the controller power mode determination and change program 1704 calculates the minimum number of I / O processing capable storage controllers (Y) that can support the future processing load (step S2606). For example, this calculation method can employ a method of determining how many controllers can support the future processing load based on the maximum processing performance of the controller. That is, in an apparatus using a general-purpose semiconductor device such as a storage controller, when a predetermined I / O processing capacity is to be provided, the minimum number of controllers (Y) that is estimated to be capable of supporting the future processing load based on the maximum processing performance of the controller is calculated, so that the storage system 1502 can determine conditions that allow the storage system 1502 to execute I / O processing of a required scale while avoiding performance degradation and minimizing power consumption. In this embodiment, the controllers 1506 mounted on the storage system 1502 have substantially the same design performance. In addition, in calculating the above-mentioned minimum number of controllers (Y), a margin may be added to the estimated maximum processing performance, or a margin may be added to the number of controllers (Y) itself.

[0245] The controller power mode determination and change program 1704 compares (X) and (Y) obtained in steps S2603 and S2606, and judges whether (X)≦(Y) (step S2607). If the judgment result is (X)≦(Y) (step S2607: Yes), the program proceeds to step S2608. On the other hand, if the judgment result is not (X)≦(Y) (step S2607: No), the program proceeds to step S2609.

[0246] The controller power mode determination and change program 1704 determines that the number of I / O processable storage controllers (required number) was calculated in step S2606 (Y), and continues processing (step S2608).

[0247] The controller power mode determination and change program 1704 sets the number of I / O processable storage controllers (required number) as calculated in step 2603 (X) and continues processing (step S2609).

[0248] The controller power mode determination and change program 1704 calculates a combination (Z) of power modes of the controllers 1506 that can minimize power consumption (step S2610). For example, if the processing load can be concentrated on a specific controller 1506, a device can be created that can reduce the processing load to zero, and by combining power modes OFF, it may be possible to provide processing capacity that exceeds the predicted future processing load while reducing power consumption more than by equalizing the processing load between devices. However, in order to maintain redundancy, the combination is determined so that the controllers 1506 in excess of the aforementioned (required number) are in a power mode other than "power OFF" and "standby mode".

[0249] Also, for example, the number of storage controllers capable of I / O processing identified in step 2608 or step 2609 may have a margin for the expected processing load because it is calculated based on the maximum processing performance of one controller 1506. In such a case, it is possible to assign the normal mode to a specific controller 1506 and assign the power saving mode A or the power saving mode B to the other controllers 1506. Any method can be adopted as this assignment method, and one or more combinations may be specified. In any case, a combination (Z) of power modes that can minimize power consumption is specified. Also, when a controller 1506 breaks down, if there is another controller 1506 that is not currently capable of I / O processing, it is possible to restore redundancy by changing the other controller 1506 to a state capable of I / O processing. At this time, the shorter the time (transition time) for transitioning the other controller 1506 to a state capable of I / O processing, the more the availability of the controller 1506 can be improved and the more the time for which the processing capacity is reduced can be shortened. Therefore, in a power mode combination in which there is another controller 1506 that is not capable of I / O processing, by setting one controller to the power mode "standby mode," the transition time described above can be significantly shortened compared to the case of "power OFF."

[0250] The controller power mode determination and change program 1704 references the power saving mode setting information 2306 acquired in step S2601 (i.e., accesses the controller power setting information table 1803) and determines whether the power saving mode is "specified" (step S2611). If the result of the determination is that the power saving mode is "specified" (step S2611: Yes), the program proceeds to step S2612. On the other hand, if the result of the determination is that the power saving mode is not "specified", the program proceeds to step S2615.

[0251] The controller power mode determination and change program 1704 calculates the maximum power consumption value (α) for the combination (Z) of power modes calculated in step S2610 (step S2612).

[0252] The controller power mode determination and change program 1704 determines whether the power consumption value (α) for the power mode combination (Z) calculated in step S2612 exceeds the power consumption upper limit value 2103 acquired in step S2601 (step S2613). If the determination result shows that it exceeds the power consumption value (α) (step S2613: Yes), the process proceeds to step S2614. On the other hand, if the determination result shows that it does not exceed the power consumption value (step S2613: No), the process proceeds to step S2615.

[0253] The controller power mode determination and change program 1704 changes the combination (Z) of power modes that can reduce power consumption the most obtained in step S2610 so as not to exceed the power consumption upper limit 2103 (step S2614). Specifically, the controller power mode determination and change program 1704 calculates the combination (Z) of power modes that does not exceed the power consumption upper limit 2103 and has the highest processing capacity when the number of storage controllers capable of I / O processing (required number) is set to (X) obtained in step S2603. In other words, even if the minimum number (Y) of storage controllers capable of I / O processing that is expected to be necessary to support the expected processing load is larger than (X), the number (X) of storage controllers capable of I / O processing that can ensure redundancy is updated to (required number) with a priority given to reducing power consumption, and then a combination of power modes that can provide the maximum processing performance while observing the conditions of the power consumption upper limit 2103 is determined. Then, the process proceeds to step S2615 (I). It may be configured to ask the user for confirmation as to whether or not to prioritize reduction in power consumption. For example, when the (required number) has been determined based on (Y) and it is determined that further reduction (for example, (X) is set as the (required number)) is necessary in relation to the power consumption upper limit value 2103, the administrator of the storage system 1502 may be prompted to confirm whether to accept or reject the reduction. Furthermore, in addition to or instead of the confirmation as to whether or not to accept, the user may be notified (warned) that a power mode that may not be able to support future processing loads has been set so as not to exceed the power consumption upper limit value 2103. By providing these notification functions, the storage system 1502 can be provided in a form that is more convenient for the user and in line with the desired performance index (processing performance and reduction in power consumption).

[0254] The controller power mode determination and change program 1704 confirms the combination of power modes (Z) obtained in the above process and proceeds with the subsequent process (step S2615). The (Y) or (X) number of controllers 1506 are assigned a power mode capable of executing I / O processing, while the controllers 1506 that are capable of executing I / O processing at the time the controller power mode determination and change process starts and that are not included in the above (Y) and (X) transition to standby mode or power-off mode. The method of selecting the (X) or (Y) number of controllers, or the method of selecting controllers to be excluded from the (X) or (Y) number of controllers, can employ any criteria, such as operation history or accumulated processing load.

[0255] The controller power mode determination and change program 1704 requests the storage system 1502 to change the power mode of the controller 1506, waits for a completion response, and ends the process when the completion response is received (step S2616). Note that when changing the power mode of the controller 1506, the storage system 1502 needs to perform processes such as rebalancing the processing load between the multiple controllers 1506 and changing the destination of an I / O processing request from the host machine 1503. However, these are realized by utilizing a method in which, for example, when a controller 1506 breaks down, another controller 1506 takes over the processing.

[0256] The storage system according to this embodiment is a storage system having a storage device that stores data in response to a data input / output request from a host or outputs the stored data, and includes a plurality of components (a plurality of controllers 1506) that can be switched between a normal power mode and at least one power saving mode that consumes less power than the normal power mode and can operate, a controller operation status monitoring program 1703 as an example of a status monitoring unit that monitors the operation status of each of the plurality of components, and a power mode control unit (controller power mode decision and change program 1704) that determines the power mode of at least one specific component to the power saving mode based on the processing load on each of the plurality of components that is the result of monitoring by the controller operation status monitoring program 1703, and operates the at least one specific component in the power saving mode, and executes control between the plurality of components and the storage device in response to the data input / output request. In this way, power consumption can be reduced without degrading the I / O performance with the host.

[0257] The power consumption reduction method for a storage system according to this embodiment is a power consumption reduction method for a storage system having a storage device that stores data in response to a data input / output request from a host or outputs the stored data, and includes a status monitoring step in which a controller operation status monitoring program 1703 as an example of a status monitoring unit monitors the operation status of each of a plurality of components that can each operate by switching between a normal power mode and at least one power saving mode that consumes less power than the normal power mode, and a power mode control step in which a controller power mode determination and change program 1704 as an example of a power mode control unit determines the power mode of at least one or more specific components to the power saving mode based on the processing load for each of the plurality of components that is a result of monitoring by the status monitoring step, and operates the specific component in the power saving mode, and the plurality of components executes control between the storage device in response to the data input / output request.

[0258] In this embodiment, the above-mentioned components are a plurality of controllers 1506 which control data input / output processing with the host, and the storage system according to this embodiment comprises a management terminal 1505 which controls the plurality of controllers, and the management terminal 1505 comprises a controller operation status monitoring program 1703 as an example of a status monitoring unit, and a controller power mode determination and change program 1704 as an example of a power mode control unit.

[0259] In this embodiment, the controller power mode determination and change program 1704 selects a specific power mode that can immediately transition to a state in which I / O processing can be executed by the other controller in response to detection of a failure that has occurred in any of the multiple controllers 1506, based on a redundancy setting (for example, a setting of durability against controller failure (N-fold)). In this way, even if a failure occurs in any of the controllers, I / O processing can be executed immediately thereafter.

[0260] In this embodiment, the controller power mode determination and change program 1704 allows other controllers to transition to a state in which they can execute input / output processing immediately after the above, while operating some of the multiple-core CPU (Central Processing Unit) cores and putting the other cores on standby. In this way, the CPU is operated with the minimum number of cores, making it possible to further reduce power consumption.

[0261] In addition, the method of changing the power consumption mode with the storage controller as the control unit described in the above embodiment can be expanded from the storage controller to the component level in terms of the control unit. Specifically, it is possible to apply the ideas of redundancy, power OFF mode, and standby mode shown in the second embodiment to the ideas shown in the first embodiment.

[0262] 1 as an example, each CPU 106 has multiple cores 114 (four in this figure), and a redundant configuration is provided between each of the cores 114 included in one CPU. An example of this aspect is as follows.

[0263] For example, two of the four cores 114 included in the CPU 106 are set to an Active state (capable of executing I / O processing), and the remaining two cores 114 are set to a Standby state (not capable of executing I / O processing). Furthermore, the Active state is configured so that it can be selectively set for each core 114 between a state in which functions can be used without any particular restrictions (normal Active) and a state in which techniques such as power saving techniques using operating frequency changes and voltage change control are applied (power saving Active). The setting of this Active state is assumed to be controlled and managed, for example, as follows.

[0264] The power mode setting for each core 114 (Active state) is set in conjunction with the power mode of the controller 1506 described in the second embodiment. For example, when the power mode of the controller 1506 is "normal", normal Active is applied to the cores in the Active state among the multiple cores provided in the CPU included in the controller 1506. When any one of the power saving modes is applied to the controller 1506, at least a part of the cores in the Active state transition to the power saving Active state in response to the power saving mode. Note that "at least a part" means that the cores in the Active state may be uniformly shifted to the power saving Active state, or a core that continues to operate in the normal Active state may be combined with a core that transitions to the power saving Active state, in order to satisfy the condition of the maximum power consumption allowed in the predetermined power saving mode set for the controller 1506. In addition, by making the multiple cores multiplexed in this way, it is possible to provide redundancy to the functions in the CPU 106. For example, even if one of the cores in the Active state fails, the CPU 106 can continue processing to the outside by the other cores in the Active state, and in addition to controlling the power consumption according to the processing load, it is possible to improve fault tolerance.

[0265] On the other hand, the setting of the Standby state can be realized by applying clock gating or power gating. The number of cores in the Active state and the Standby state in the CPU can be arbitrarily designed according to the performance required for the controller. The difference between the Active state and the Standby state is, for example, whether or not a change in the power mode linked to the power mode applied to the controller is applied. In this example, the linked change operation is applied to the core in the Active state.

[0266] A core in standby state is configured to be able to operate as a new core in active state in response to detection that the redundancy of the cores in the CPU falls below an arbitrarily set value due to failure of one or more cores in active state operating in the same CPU as itself. In order to speed up switching from standby state to active state, it is preferable that at least one core in standby state has its power limited by a power saving technology (clock gating) suitable for fast startup, and the other cores have their power consumption reduced by a technology such as power gating that has a large effect of reducing power consumption. By configuring in this way, it is possible to improve the availability of the CPU while contributing to power saving as a storage system.

[0267] Regarding the above-mentioned Active state and Standby state settings, the power control method applied to each core may be different between the two settings, or at least some of the methods may be common. Even if there is an Active state core and I / O processing is possible, if the state of the controller to which the CPU including the core belongs is, for example, standby mode or power off mode, the CPU as a whole does not perform I / O processing. In addition, although the power control and redundancy in a multi-core CPU are described here, the described concept can be applied to devices included in other controllers (especially devices that are multiplexed). In that case, power control for the target device that is different from clock gating and power gating (such as limiting the maximum applied voltage) can be used. In addition, the clock gating and power gating described above are examples of the power control technology to be used, and are not limited to these.

[0268] (3) Third embodiment The storage system according to the third embodiment is similar to the storage systems according to the first and second embodiments, except for the differences described below, and therefore the description of the similar parts will be omitted. Note that the storage system according to the third embodiment may have different reference numerals for each component, such as a CPU and a controller, from the storage systems according to the first and second embodiments, but has the same configuration and functions as the storage systems according to the first and second embodiments unless otherwise specified in the following description.

[0269] A storage system according to the third embodiment will be described with reference to FIG. 27 to FIG. 27 is a system configuration diagram showing an example of the configuration of a storage system 2700 according to the third embodiment. The storage system 2700 includes controllers 2701, 2721, and a PDEV BOX 2740 having a plurality of PDEVs including PDEVs 2742, 2762.

[0270] A logical volume capable of storing data is configured in the storage system 2700, and data input / output processing is executed by controllers 2701, 2721.

[0271] The controller 2701 includes a host I / F (Interface) 2702, a CPU 2703, a memory 2704, and a non-transparent bridge (NTB) 2708. The host I / F 2702, the CPU 2703, and the NTB 2708 are interconnected, for example, by a PCIe (Peripheral Component Interconnect Express) link. Similarly, the controller 2721 includes a host I / F 2722, a CPU 2723, a memory 2724, and an NTB 2728. The host I / F 2722, the CPU 2723, and the NTB 2728 are interconnected by a PCIe link. The CPU 2703 and the memory 2704, and the CPU 2723 and the memory 2724 are each connected by a memory bus.

[0272] Similarly to the controller 104 in FIG. 1 in the first embodiment, the controllers 2701 and 2721 may each include a CPU 2703 or 2723 and an accelerator (not shown) connected via, for example, a PCIe link.

[0273] Furthermore, the controllers 2701, 2721 each include management terminal I / Fs 2771, 2772 for connecting to a management terminal 2774 via a management terminal network 2773. The management terminal 2774 includes functions equivalent to the management terminal 1505 of Fig. 15 in the second embodiment.

[0274] The CPU 2703 includes therein a plurality of cores 2705 and an uncore 2706 which is the other part. In this embodiment, the term "uncore" refers to a component other than the so-called core component which executes calculations in a processor such as a CPU (Central Processing Unit). The uncore 2706 includes, for example, a DMA (Direct Memory Access) 2707. Similarly, the CPU 2723 includes therein a plurality of cores 2725 and an uncore 2726 which is the other part. The uncore 2726 includes a DMA 2727.

[0275] The host machines 2750, 3100 that access the storage system 2700 are connected to the storage system 2700 via host I / Fs 2702, 2722, respectively. The host machines 2750, 3100 and the host I / Fs 2702, 2722 are connected by transmission lines such as Fibre Channel cables or Ethernet cables. Alternatively, the host machines 2750, 3100 and the host I / Fs 2702, 2722 may be connected via a storage area network (not shown) made up of a plurality of transmission lines and a plurality of switches.

[0276] The host I / Fs 2702 and 2722 convert the data transfer protocol between the host machines 2750 and 3100 and the storage system 2700 and the data transfer protocol within the controllers 2701 and 2721 .

[0277] The PDEV BOX 2740 is connected to the controllers 2701 and 2721 via links 2731, 2732, 2751 and 2752. The PDEV BOX 2740 includes PDEV switches 2741 and 2761 that connect the PDEVs 2742 and 2762 via links 2743, 2744, 2763 and 2764. In this embodiment, the links 2731, 2732, 2743, 2744, 2751, 2752, 2763 and 2764 are, for example, PCIe links. The PDEV switches 2741 and 2761 are PCIe switches, and the PDEVs 2742 and 2762 are NVMe drives with dual ports. In this embodiment, the PDEV I / F is not used to connect the CPU and the PDEV switch, and the CPU and the PDEV switch are directly connected by a PCIe link.

[0278] The CPUs 2703, 2723 control data transfer between the host machines 2750, 3100 connected via the host I / Fs 2702, 2722 and the PDEVs 2742, 2762 connected via the PDEV switches 2741, 2761. Furthermore, the CPUs 2703, 2723 control data transfer between the controllers.

[0279] The memories 2704 and 2724 are primary storage devices for the CPUs 2703 and 2723, respectively, and store programs (storage control programs, etc.) executed by the CPUs 2703 and 2723, and management tables referenced by the CPUs 2703 and 2723. The memories 2704 and 2724 are also used as cache memories for the controllers 2701 and 2721, respectively.

[0280] The NTB 2708 and the NTB 2728 are connected via an inter-controller link 2711, which is, for example, a PCIe link. The CPU 2703 and the CPU 2723 can communicate with each other via the inter-controller link 2711. In this manner, the storage system 2700 configures a dual controller with two controllers 2701, 2721. The CPUs 2703, 2723 transfer data received from the host that is duplicated between the two controllers and metadata used for controller control over the inter-controller link 2711.

[0281] The memories 2704 and 2724 have an OQ (Outbound Queue) and an IQ (Inbound Queue) which are queues for controlling message transfer between the CPUs 2703 and 2723 and the host I / Fs 2702 and 2722. The OQ is a queue for controlling message transfer from the host I / F to the CPU, and the IQ is a queue for controlling message transfer from the CPU to the host I / F. The memory 2704 has an OQ 2709 and an IQ 2710 which are queues for controlling message transfer between the CPU 2703 and the host I / F 2702. The memory 2724 also has an OQ 2729 and an IQ 2730 which are queues for controlling message transfer between the CPU 2723 and the host I / F 2722.

[0282] In FIG. 27, OQ2709 is displayed as "OQ01", IQ2710 as "IQ01", OQ2729 as "OQ11", and IQ2730 as "IQ11".

[0283] The process in which the host I / F 2702, 2722 stores data received from the host machine 2750, 3100 in the memory 2704, 2724, or the process in which the host I / F 2702, 2722 transmits data from the memory 704, 2724 to the host machine 2750, 3100, and related processes will be referred to as "host I / O processing."

[0284] Furthermore, the process of writing data stored in the memories 2704, 2724 to the PDEVs 2742, 2762, or the process of reading data stored in the PDEVs 2742, 2762 to the memories 2704, 2724, and related processes will be referred to as back-end processes.

[0285] Furthermore, the process of duplicating data received from the host machines 2750, 3100 between the memory 2704 and the memory 2724 using the DMAs 2707, 2727 and related processes will be referred to as "data duplication process."

[0286] In the PCIe link used in this embodiment, ASPM (Active State Power Management), which is a power management function of the PCIe link, is enabled as necessary. In ASPM, the state in which the PCIe link is active and capable of executing transactions is the L0 state in which the power consumption of the link is at its maximum. In ASPM, examples of states in which the link is in a power-saving state include L1, L2, and L3. 0S There are two states: L0 and L1. For example, when data is being transferred between the CPU and the PDEV, the PCIe link between them is in the L0 state. When data is not being transferred between the CPU and the PDEV and they are in an idle state, the PCIe link between them automatically transitions to a power-saving state, such as the L1 state.

[0287] Fig. 28 is a flowchart of controller power mode decision processing in the storage system 2700. Below, this processing flow will be explained as being executed by the management terminal 2774, but it may also be executed by the CPU 2703 or CPU 2723. This processing flow will be referred to as a controller power mode decision program 2800. Note that in the second embodiment, this controller power mode decision program 2800 may be executed as part of the processing carried out in the storage system power consumption control processing (step S2402 in Fig. 24).

[0288] 21B, the storage system 2700 has the power saving mode setting set to "automatic" and the redundancy setting value set to "redundancy 1." That is, on the management screen of the management terminal 2774 similar to the storage system management screen 2301 of Fig. 23, the power saving mode setting information 2306 is displayed as "automatic" and the redundancy setting information as "redundancy 1 (2 multiplex)."

[0289] First, the controller power mode decision program 2800, like the controller power mode decision and change program 1704 of the second embodiment, predicts the future processing load of each of the controllers 2701, 2721 constituting the dual controller (step S2801).

[0290] In the storage system 2700 of this embodiment, the controller power mode decision program 2800 sets some of the multiple cores of the CPU set to the power saving mode to the Active state, and sets the other cores to the Standby state (corresponding to the above-mentioned "Standby state"). In this way, it is possible to operate the CPU with the minimum number of cores necessary, thereby reducing the power consumption of the CPU.

[0291] That is, in this embodiment, the controller power mode determination program 2800 as an example of a power mode control unit compares the power consumption in a first case (A) (corresponding to this embodiment) in which the power mode of the components having a high predicted processing load is set to a power saving mode C1 as an example of a predetermined second power mode (for example, of the cores provided in the controller, setting N cores to an Active state and the remaining cores to a Standby state) and the power mode of the components having a low predicted processing load is set to a power saving mode C2 as an example of a specific second power mode (for example, lowering the operating frequency of the CPU uncore below that when the power mode of the controller is in normal mode as the first power mode) with the power consumption in a second case (B) (corresponding to the above first and second embodiments) in which a power mode is determined for each component, and, on the condition that the power consumption in the second case (B) is greater than the power consumption in the first case (A), sets the power mode of the components having a high predicted processing load to the predetermined second power mode (for example, power saving mode C1) and sets the power mode of the components having a low predicted processing load to the specific second power mode (for example, power saving mode C2). On the other hand, if the condition is not met, for example, the power mode control such as that of the first and second embodiments described above is performed.

[0292] The above-mentioned multiple components are, for example, multiple partial elements (e.g., cores and uncores constituting CPU2703 or CPU2723) of each processor of multiple controllers (e.g., CPU2703 of "CPU0" and CPU2723 of "CPU1"). During operation, one processor (CPU2723 of "CPU1") of one controller 2721 switches control of a core as an example of a partial element of the one processor to the other processor (e.g., CPU2703 of "CPU0") of the other controller, sets the power mode of the one processor to power saving mode C2 as a specific second power mode, and sets the power mode of the other processor to power saving mode C3 as a predetermined second power mode that consumes more power than power saving mode C2 as an example of the specific second power mode. 1 to Set it up.

[0293] The controller power mode decision program 2800 is an example of a power mode control unit, and switches so that the other processor uses one uncore, which is an example of a partial element of the one controller, to control a data I / O request from the host. The storage device (e.g., "memory 2724") of the one controller described above includes a control queue (IQ11 (2730), OQ11 (2729) described below), and the other processor uses an uncore, which is a partial element of the one controller, to access the control queue and control a data I / O request from the host. A specific description will be given below.

[0294] First, the controller power mode decision program 2800 calculates the minimum number N of active cores capable of I / O processing that can support the future processing load per dual controller (step S2802).

[0295] This calculation method can employ a method of determining how many active cores can support future processing loads based on the maximum processing performance of the active cores. That is, in a device using a general-purpose CPU such as a storage controller, when a predetermined I / O processing capacity is to be provided, the minimum number of active cores N that is estimated to be capable of supporting future processing loads is calculated based on the maximum processing performance per active core. This allows the storage system 2700 to determine conditions that allow I / O processing of a required scale to be executed while avoiding performance degradation and minimizing power consumption. In this embodiment, the CPUs 2703 and 2723 mounted on the storage system 2700 have substantially the same design performance in terms of the number of cores, operating frequency, etc. In addition, when calculating the number of active cores N described above, a margin may be added to the estimated maximum processing performance, or a margin may be added to the number of active cores N itself. In addition, when calculating the number of active cores N, a condition that the impact on input / output processing of data with the host machine is below a predetermined standard may be included in the calculation.

[0296] Next, the controller power mode decision program 2800 compares the number of cores per controller with the number of active cores N (step S2803). In the storage system 2700, the number of cores per controller is the number of cores each of the CPUs 2703, 2723 has. If the number of cores per controller is equal to or greater than the number of active cores N (step S2803: Yes), the controller power mode decision program 2800 proceeds to step S2804. If not (step S2803: No), the program proceeds to step S2807.

[0297] It may be difficult to express the processing performance of a controller in terms of the number of active cores when the performance such as the number of cores or the operating frequency differs among the CPUs mounted on the controllers constituting a dual controller, when the core performance or the core operating frequency is not uniform even within a single CPU, etc. In such a case, instead of steps S2802 and S2803, it may be determined whether or not the future processing load per dual controller of the storage system 2700 can be processed by only one of the controllers.

[0298] In step S2804, the controller power mode decision program 2800 calculates the power consumption (A) of the storage system 2700 when the power mode of the controller with the higher processing load predicted in step S2801 is set to power saving mode C1, and the power mode of the controller with the lower processing load is set to power saving mode C2. The controller power mode decision program 2800 calculates the power consumption (B) of the storage system 2700 when a power mode is set for each controller using a method similar to that of Fig. 12 of the first embodiment. The controller power mode decision program 2800 compares the power consumption (A) and the power consumption (B).

[0299] Here, the power saving mode C1 involves setting N cores out of the cores included in the controller to an active state and the remaining cores to a standby state.

[0300] The power saving mode C2 also includes setting the cores other than the core executing the controller state monitoring processing program (FIG. 36, 3600) described later to the Standby state. The power saving mode C2 also includes lowering the operating frequency of the CPU uncore compared to when the controller power mode is the normal mode, and enabling the ASPM of the PCIe link.

[0301] Here, the purpose of setting the different power modes, power saving mode C1 and power saving mode C2, for each controller constituting a dual controller will be explained. If the processing load can be concentrated on one of the dual controllers, the processing load on the other controller will decrease, and power consumption can be reduced in many devices. There are cases where the power consumption of the storage system can be reduced more than by reducing power consumption for each controller. In other words, there are cases where the power consumption per storage system can be reduced more by setting one of the dual controllers to power saving mode C1 and the other to power saving mode C2.

[0302] In the following, setting the power mode of one controller of a dual controller to power saving mode C1 and the power mode of the other controller to power saving mode C2 may be simply referred to as setting the power mode to power saving mode C.

[0303] Next, the controller power mode decision program 2800 proceeds to step S2806 (step S2805: Yes) if the power consumption (A) when power saving mode C is set is smaller than the power consumption (B) when a power mode is set for each controller by a method similar to that of Fig. 12 in the first embodiment. If not (step S2805: No), the program proceeds to step S2807.

[0304] The controller power mode decision program 2800 decides that the power mode of the controller with the higher processing load predicted in step S2801 is to be power saving mode C1, and the power mode of the controller with the lower processing load is to be power saving mode C2 (step S2806).

[0305] The controller power mode decision program 2800 decides the power mode for each controller using a method similar to that shown in FIG. 12 of the first embodiment (step S2807).

[0306] The redundancy setting value of the storage system 2700 is 1 (dual multiplexing), and input / output processing can be executed even if a failure occurs in either of the two controllers. Even when the power mode of the dual controller is set to power saving mode C, the redundancy setting value of the storage system 2700 of this embodiment is 1 (dual multiplexing), and input / output processing can be executed even if a failure occurs in either of the two controllers.

[0307] In order for the storage system 2700 to maintain a state of redundancy level 1 (dual multiplexing) even when the power mode is set to power saving mode C, the host I / O processing that was being executed by the controller whose power mode is set to power saving mode C2 is taken over by the controller whose power mode is set to power saving mode C1. Furthermore, even after the host I / O processing has been taken over between the controllers, data duplication processing that duplicates data received from the host machine between memory 2704 and memory 2724 continues. The following describes this host I / O takeover processing, data duplication processing, and the associated operations of the controllers. To First, the OQ and IQ used to control the host I / O processing will be explained.

[0308] 29 is a diagram for explaining an example of the configuration of an OQ and an IQ in a storage system 2700. As an example, an OQ 2729 and an IQ 2730 will be explained, but the same applies to the configurations of other OQs and IQs such as an OQ 2709 and an IQ 2710.

[0309] Both OQ2729 and IQ2730 store entries in a total of N elements numbered from 0 to N-1. In OQ2729, the contents of an entry are, for example, a host I / O command received from a host machine. In IQ2730, the contents of an entry are, for example, a response corresponding to a completed host I / O command, or a data transfer list instructed by the CPU to the host I / F. Each entry also includes exchange identification information (i.e., exchange ID) that indicates which host I / O exchange the entry relates to. An exchange refers to a series of tasks related to read operations, write operations, etc. between a host machine and storage.

[0310] In OQ2729 in Figure 29, for example, 4 An entry is stored in the (i-1)th element. The other elements of OQ2729 are empty. OQPI (Producer Index) 2901 indicates the location of the element where the host I / F will store the next entry. OQCI (Consumer Index) 2902 indicates the location of the element where the entry the CPU will read next is stored. When OQPI 2901 and OQCI 2902 indicate the same element, this indicates that no unprocessed entries are stored in OQ2729 and it is empty. In addition, the latest entry that has finished being processed is stored in the (i-1)th element. The CPU can determine which exchange-related entry processing has been completed by checking the exchange ID of this entry.

[0311] In the IQ2730 in Figure 29, for example, jAn entry is stored in the +3rd element. The other elements of IQ2730 are empty. IQPI2911 indicates the location of the element where the CPU will store the next entry. IQCI2912 indicates the location of the element where the entry the host I / F will read next is stored. When IQPI2911 and IQCI2912 point to the same element, this indicates that IQ2730 does not store any unprocessed entries and is empty. In addition, the j-1th element stores the most recent entry that has finished being processed. By checking the exchange ID of this entry, the CPU can determine which exchange-related entry processing has been completed.

[0312] The queue indexes OQPI, OQCI, IQPI, and IQCI are stored at predetermined addresses in memory, or in registers of the host I / F, or in both, as necessary.

[0313] 30 is a diagram illustrating data transfer paths related to host I / O processing before host I / O takeover in the storage system 2700. As an example, a data transfer path will be described in the case where the core 3000 of the CPU 2723 controls the host I / F 2722 in the controller 2721.

[0314] The host I / F 2722 that receives host I / O from the host machine 3100 accesses the OQ 2729 and IQ 2730 in the memory 2724 and their queue indexes OQPI and IQCI via a data transfer path 3001 that passes through the CPU 2723 .

[0315] Furthermore, the host I / F 2722 stores data received from the host machine 3100 in the memory 2724 via the data transfer path 3001 , or transmits data stored in the memory 2724 to the host machine 3100 .

[0316] The core 3000 accesses the OQ 2729 in the memory 2724 , its queue index OQPI, and the IQ 2730 via a data transfer path 3002 .

[0317] Furthermore, the core 3000 accesses OQCI, which is the queue index of the OQ 2729 , and IQPI, which is the queue index of the IQ 2730 , in the host I / F 2722 via a data transfer path 3003 .

[0318] Furthermore, the core 3000 transfers data received from the host machine 3100 and stored in the memory 2724 to the memory 2704 of the controller 2701 using the DMA 2727 via a data transfer path 3004 passing through the CPU 2723, the inter-controller link 2711, and the CPU 2703. This allows the data received from the host machine 3100 to be duplicated in the memory 2704 of the controller 2701 and the memory 2724 of the controller 2721.

[0319] FIG. 31 is a diagram illustrating a data transfer sequence related to host I / O processing before host I / O takeover in the storage system 2700.

[0320] Here, as an example, a case will be described in which the host I / F 2722 and the core 3000 of the CPU 2723 use the OQ 2729 and IQ 2730 in the memory 2724. In addition, in Fig. 31, OQ 2729 is displayed as "OQ11" and IQ 2730 is displayed as "IQ11".

[0321] First, the host machine 3100 transmits a host I / O command 3101 to the host I / F 2722. The host I / F 2722, which receives the host I / O command 3101, enqueues an entry 3102 including the command contents to the OQ 2729 (step S3103).

[0322] Next, the host I / F 2722 updates the OQPI of the OQ 2729 in the memory 2724 to notify the core 3000 that the entry 3102 has been enqueued in the OQ 2729 (step S3104).

[0323] The core 3000 checks whether there is an unprocessed entry in the OQ 2729 by polling the OQPI of the OQ 2729 (step S3105). If there is an unprocessed entry, the core 3000 reads the entry in which the contents of the host I / O command are stored from the OQ 2729 (step S3106). Furthermore, the core 3000 updates the OQCI of the OQ 2729 in the host I / F 2722 (step S3107).

[0324] Next, the core 3000 enqueues an entry including a data transfer list corresponding to the host I / O command 3101 in the IQ 2730 (step S3108). Furthermore, the core 3000 updates the IQPI of the IQ 2730 in the host I / F 2722 (step S3109).

[0325] After the IQPI is updated, the host I / F 2722 reads an entry including a data transfer list from the IQ 2730 (step S3110). Next, the host I / F 2722 transfers data between the host machine 3100 and the memory 2724 according to the data transfer list included in the entry read from the IQ 2730 (step S3111).

[0326] When the data transfer is completed, the host I / F 2722 updates the IQCI of the IQ 2730 in the memory 2724 (step S3112). CPU2723 The CPU core 3000 can process a host I / O command 3101 received by the host I / F 2722 .

[0327] FIG. 32 is a diagram for explaining an example of a P2P (peer-to-peer) data transfer path in the CPU 2723. As shown in FIG.

[0328] The uncore 2726 of the CPU 2723 includes a PCIe root complex 3201. The root complex 3201 further includes a plurality of root ports including root ports 3202 and 3203. The root port 3202 is connected to the host I / F 2722, and the root port 3203 is connected to the NTB 2728. As shown in FIG. 27, the NTB 2728 is connected to another controller 2701 via an inter-controller link 2711. Data transfer performed on a path 3204 passing through the root port 3202, the root complex 3201, and the root port 3203 is called a P2P data transfer.

[0329] Fig. 33 is a diagram illustrating a data transfer path related to host I / O processing after host I / O takeover in the storage system 2700. As an example, a data transfer path will be described in the case where the core 3300 of the CPU 2703 belonging to the controller 2701 controls the host I / F 2722 of the controller 2721.

[0330] The host I / F 2722 that receives host I / O from the host machine 3100 accesses the OQ 2729 and IQ 2730 in the memory 2724 and their queue indexes OQPI and IQCI via a data transfer path 3301 that passes through the CPU 2723 .

[0331] Furthermore, the host I / F 2722 stores data received from the host machine 3100 in the memory 2724 via the data transfer path 3301 , or transmits data stored in the memory 2724 to the host machine 3100 .

[0332] The core 3300 accesses the OQ 2729 in the memory 2724 , its queue index OQPI, and the IQ 2730 via a data transfer path 3302 that passes through the inter-controller link 2711 and the CPU 2723 .

[0333] Furthermore, the core 3300 accesses OQCI, which is a queue index of the OQ 2729, and IQPI, which is a queue index of the IQ 2730, in the host I / F 2722, via a data transfer path 3303 that passes through the inter-controller link 2711 and the CPU 2723. The data transfer path 3303 includes a P2P data transfer path in the CPU 2723.

[0334] Furthermore, the core 3300 transfers data received from the host machine 3100 and stored in the memory 2724 to the memory 2704 of the controller 2701 using the DMA 2707 via a data transfer path 3304 passing through the CPU 2723, the inter-controller link 2711, and the CPU 2703. This allows the data received from the host machine 3100 to be duplicated in the memory 2704 of the controller 2701 and the memory 2724 of the controller 2721.

[0335] FIG. 34 is a diagram illustrating a data transfer sequence related to host I / O processing after host I / O takeover in the storage system 2700.

[0336] Here, as an example, a case will be described in which the host I / F 2722 and the core 3300 of the CPU 2703 use the OQ 2729 and IQ 2730 in the memory 2724. In addition, in Fig. 34, OQ 2729 is displayed as "OQ11" and IQ 2730 is displayed as "IQ11".

[0337] First, the host machine 3100 transmits a host I / O command 3401 to the host I / F 2722. The host I / F 2722, which receives the host I / O command 3401, enqueues an entry 3402 including the command contents to the OQ 2729 (step S3403).

[0338] Next, the host I / F 2722 updates the OQPI of the OQ 2729 in the memory 2724 to notify the core 3300 that the entry 3402 has been enqueued in the OQ 2729 (step S3404). The core 3300 checks whether there is an unprocessed entry in the OQ 2729 by polling the OQPI of the OQ 2729 (step S3405). If there is an unprocessed entry, the core 3300 reads the entry in which the contents of the host I / O command are stored from the OQ 2729 (step S3406). Furthermore, the core 3300 updates the OQCI of the OQ 2729 in the host I / F 2722 (step S3407).

[0339] Next, the core 3300 enqueues an entry including a data transfer list corresponding to the host I / O command 3401 in the IQ 2730 (step S3408). Furthermore, the core 3300 updates the IQPI of the IQ 2730 in the host I / F 2722 (step S3409). After the IQPI has been updated, the host I / F 2722 reads an entry including the data transfer list from the IQ 2730 (step S3410).

[0340] Next, the host I / F 2722 transfers data between the host machine 3100 and the memory 2724 in accordance with the data transfer list included in the entry read from the IQ 2730 (step S3411). When the data transfer is completed, the host I / F 2722 updates the IQCI of the IQ 2730 in the memory 2724 (step S3412).

[0341] In this manner, the core 3300 can process the host I / O command 3401 received by the host I / F 2722 .

[0342] 35 is a flowchart showing an example of the procedure for host I / O takeover processing between controllers and power mode change processing of the controllers in the storage system 2700. This processing flow is executed by the CPU 2703 or CPU 2723 of the controller that has received a power mode change instruction to power saving mode C from the management terminal 2774. Hereinafter, this processing flow will be referred to as a host I / O takeover processing program 3500. As an example, a case will be described in which the controller 2701 takes over host I / O processing from the controller 2721, and the power mode of the controller 2701 changes to power saving mode C1 and the power mode of the controller 2721 changes to power saving mode C2.

[0343] First, the host I / O takeover processing program 3500 stops the host I / F 2722 driver currently being executed by the CPU 2723 of the controller 2721 (step S3501). / F (It may also be called "host IF") Stopping the driver means stopping processing for the control queue of the host IF. Therefore, even if the host IF driver is stopped, the host IF is not initialized, so host link down or the like does not occur. Next, the host I / O takeover processing program 3500 executes the host I / F 2722 driver in the CPU 2703 of the controller 2701 (step S3502). Execution of the host IF driver here means stopping processing for the control queue of the host IF. Where This means the start of processing. Therefore, even if the host IF driver is executed, the host IF is not initialized, so that host link down or the like does not occur. The host I / F 2722 driver running on the CPU 2703 can take over the host I / O processing of the host I / F 2722 driver running on the CPU 2723 by checking the queue indexes of the OQ 2729 and IQ 2730. In other words, even if the subject operating the host IF control queue is changed, the host IF can continue to operate. Also, the CPU 2703 transitions the cores other than the N cores to be set to the Active state to a Standby state to which power gating or the like is applied. As a result, the power mode of the controller 2701 is changed to the power saving mode C1.

[0344] Next, the host I / O takeover processing program 3500 stops the back-end processing being executed by the CPU 2723 of the controller 2721 (step S3503). 3100 Since the data received from is duplicated in memory 2704 and memory 2724, even if the back-end processing of the CPU 2723 is stopped, as long as the CPU 2703 is executing the back-end processing, the operation of the storage system 2700 can continue.

[0345] Next, the host I / O takeover processing program 3500 reduces the operating frequency of the uncore 2726 of the CPU 2723 of the controller 2721 to a range in which the impact on P2P data transfer and data duplication processing is below a predetermined standard (step S3504). As described in Fig. 33, the data duplication processing after host I / O takeover uses the DMA 2707 of the CPU 2703. This allows the data duplication processing to be executed without problems even if the operating frequency of the uncore 2726 is reduced.

[0346] A core of the CPU 2723 that is no longer executing host I / O processing, back-end processing, or other processing transitions to a Standby state to which power gating, etc. is applied. Note that in any of the cores of the CPU 2723 in this state, at least the controller state monitoring process (FIG. 36, 3600) described below is being executed.

[0347] As a result, the power mode of the controller 2721 changes to the power saving mode C2. When the CPU 2723 no longer executes back-end processing, the PCIe links 2751 and 2752 between the CPU 2723 and the PDEV BOX 2740 transition to the L1 state, which is a power saving mode, by ASPM. Furthermore, when the CPU 2703 executes back-end processing, only the PCIe link 2731 between the CPU 2703 and the PDEV BOX 2740 is used, and the PCIe link 2732 is not used. As a result, the PCIe link 2732 and the PCIe links (e.g., 2763 and 2764) between the PDEV switch 2761 and the PDEVs 2742 and 2762 also transition to the L1 state, which is a power saving mode. In particular, when the storage system 2700 is equipped with a large number of PDEVs, the link connecting one PCIe port of a large number of dual-port PDEVs transitions to the power saving state, resulting in a large power consumption reduction effect.

[0348] In addition to enabling ASPM, the PCIe link speed may be reduced to reduce the power consumption of the PCIe link. e Power consumption of a PCIe link may be reduced by lowering the link speed of the link.

[0349] 36 is a flowchart showing an example of a controller status monitoring process procedure in the storage system 2700. This process flow is executed by the CPU 2703 or CPU 2723 of the controller that has transitioned to the power saving mode C2. Hereinafter, this process flow will be referred to as the controller status monitoring program 3600. As an example, a case will be described in which the controller status monitoring program 3600 is executed by any of the cores of the CPU 2723 of the controller 2721 that has transitioned to the power saving mode C2.

[0350] First, the controller status monitoring program 3600 checks the operating status of the controller 2701. For example, the CPU 2723 checks the operating status of the controller 2701 by reading out operating information of the controller 2701 stored in the memory 2704 and a predetermined register of the CPU 2703 via the inter-controller link 2711 (step S3601).

[0351] Next, if the controller 2701 is normal (step S3602: Yes), the controller status monitoring program 3600 proceeds to step S3603. If not, that is, if an abnormality is detected in the controller 2701 (step S3602: No), the controller status monitoring program 3600 proceeds to step S3608.

[0352] Next, the controller status monitoring program 3600 checks the operating status of the devices in the controller 2721 (step S3603).

[0353] Next, if the device is normal (step S3604: Yes), the controller status monitoring program 3600 proceeds to step S3606. If not (if an abnormality has been detected in the device) (step S3604: No), the controller status monitoring program 3600 proceeds to step S3605.

[0354] Next, the controller status monitoring program 3600 that has detected an abnormality in the device blocks the device in which the abnormality has been detected (step S3605).

[0355] Next, the controller state monitoring program 3600 transitions the core on which the controller state monitoring program 3600 is running to a Standby state to which power gating or the like is applied (step S3606).

[0356] Next, the controller status monitoring program 3600 waits for a predetermined time (step S3607). As a result, the core on which the controller status monitoring program 3600 is running remains in the standby state for the predetermined time, making it possible to reduce power consumption of the CPU 2723 executing the controller status monitoring program 3600.

[0357] After a predetermined time has elapsed, the controller status monitoring program 3600 transitions the core to the Active state, and then the controller status monitoring program 3600 returns to step S3601 to repeat the controller status monitoring flow.

[0358] The controller status monitoring program 3600, which detects an abnormality in the controller 2701 in step S3602, blocks the controller 2701 (step S3608).

[0359] Next, in order to resume the host I / O processing and back-end processing in the controller 2721, the controller status monitoring program 3600 increases the operating frequency of the uncore 2726 of the CPU 2723 of the controller 2721 (step S3609).

[0360] Next, the controller status monitoring program 3600 restarts the host I / F 2722 driver in the CPU 2723 of the controller 2721 (step S3610).

[0361] Next, the controller status monitoring program 3600 restarts the back-end processing in the CPU 2723 of the controller 2721 (step S3611).

[0362] In the controller 2721 set to the power saving mode C2, at least one core of the CPU 2723 executes the controller state monitoring program 3600, and the other cores are transitioned to a standby state to which power gating, etc. is applied. This makes it possible to reduce the power consumption of the CPU 2723 while the controller state monitoring program 3600 is being executed.

[0363] Also, the host machine 3100 When the frequency of access to the storage system 2700 from the uncore 2726 decreases and the future processing load of the controllers 2701 and 2721 is predicted to be small, the power consumption of the CPU 2723 during low processing load may be reduced by applying clock gating to the uncore 2726 as well. The clock gating of the uncore 2726 is effective, for example, when all the cores of the CPU 2723 transition to the Standby state and there is no access to the memory 2724 via the uncore 2726. Therefore, by changing the setting of the interval of polling from the core 3300 to the OQ 2729 (FIG. 34, S3405) to a longer interval, the possibility that the clock gating of the uncore 2726 is effective can be increased. Furthermore, in this embodiment, when the uncore 2726 stops its clock by clock gating, the memory connected to the uncore 2726 also enters a power saving state (for example, self-refresh mode), so that the power consumption of the memory can also be reduced.

[0364] 37 is a flowchart showing an example of the procedure for resuming host I / O processing in a controller that has been set to power saving mode C2 in the storage system 2700, and for changing the power mode of the controller. This processing flow is executed by the CPU 2703 or CPU 2723 of the controller that has received an instruction to change the power mode to normal mode from the management terminal 2774. Hereinafter, this processing flow will be referred to as a host I / O resume processing program 3700. As an example, a case will be described in which the controller 2721 takes over host I / O processing from the controller 2701, and the power mode of the controller 2721 changes from the power saving state (power saving mode) C2 to the power saving state (power saving mode) C1.

[0365] First, the host I / O resume processing program 3700 increases the operating frequency of the uncore 2726 of the CPU 2723 of the controller 2721 (step S3701). Next, the host I / O resume processing program 3700 stops the host I / F 2722 driver being executed by the CPU 2703 of the controller 2701 (step S3702). Stopping the host IF driver here means stopping processing of the control queue of the host IF. Therefore, even if the host IF driver is stopped, the host IF is not initialized, so no host link down or the like occurs.

[0366] Next, the host I / O resume processing program 3700 resumes the host I / F 2722 driver in the CPU 2723 of the controller 2721 (step S3703). Resuming the host IF driver here means resuming processing for the control queue of the host IF. Therefore, even if the host IF driver is resumed, the host IF is not initialized, so that a host link down or the like does not occur. The host I / F 2722 driver running in the CPU 2723 can take over the host I / O processing of the host I / F 2722 driver running in the CPU 2703 by checking the queue indexes of the OQ 2729 and IQ 2730. In other words, even if the entity operating the host IF control queue is changed, the host IF can continue to operate.

[0367] Next, the host I / O resume processing program 3700 resumes back-end processing in the CPU 2723 of the controller 2721 (step S3704). In the CPU 2723, the cores that execute host I / O processing, back-end processing, and other processing are set to the Active state, and the other cores are set to the Standby state.

[0368] As a result of the above, host I / O processing is taken over from the controller 2701 to the controller 2721, and the power mode of the controller 2721 changes to the power saving state (power saving mode) C1.

[0369] As described above, in the third embodiment, the dual-controller storage system 2700 determines whether the future processing load can be processed by only one of the controllers and whether power consumption can be reduced. If it is determined that this is possible, the storage system 2700 shifts the host I / O processing and back-end processing of one of the controllers to the other controller, and lowers the uncore operating frequency of the CPU that is in a low-load state. This reduces the power consumption of the storage system 2700.

[0370] In addition, in the storage system 2700, the CPU of one controller accesses the host I / F of the other controller via the inter-controller link and the P2P data transfer path of the CPU, and takes over host I / O processing between the controllers. This maintains the availability of the dual controllers when operating in power saving mode. Furthermore, even if the CPU of one controller is in a power saving state, the DMA of the CPU of the other controller is used to duplicate data received from the host machine between the memories of the dual controllers. This maintains the redundancy of the dual controllers when operating in power saving mode.

[0371] As described above, in this embodiment, the controller power mode determination program 2800 as an example of a power mode control unit compares the power consumption in a first case (A) (corresponding to this embodiment) in which the power mode of the components having a high predicted processing load is set to power save mode C1 as an example of a predetermined second power mode (for example, of the cores provided in the controller, setting N cores to an Active state and the remaining cores to a Standby state) and the power mode of the components having a low predicted processing load is set to power save mode C2 as an example of a specific second power mode (for example, lowering the operating frequency of the CPU uncore below that when the power mode of the controller is in normal mode as the first power mode) with the power consumption in a second case (B) (corresponding to the above first and second embodiments) in which a power mode is determined for each component, and, on the condition that the power consumption in the second case (B) is greater than the power consumption in the first case (A), sets the power mode of the components having a high predicted processing load to the predetermined second power mode (for example, power save mode C1), and sets the power mode of the components having a low predicted processing load to the specific second power mode (for example, power save mode C2). On the other hand, if the condition is not satisfied, the power mode control is performed as in the first and second embodiments described above. portion Since the power consumption of each element can be controlled, further power saving can be achieved.

[0372] The above-mentioned multiple components are, for example, multiple partial elements (cores, uncores) of each processor of multiple controllers (e.g., CPU2703 of "CPU0" and CPU2723 of "CPU1"). During operation of one processor (CPU2723 of "CPU1") of one controller 2721, control of a core as an example of a partial element of the one processor is switched to the other processor (CPU2703 of "CPU0") of the other controller, the power mode of the one processor is set to power saving mode C2 as a specific second power mode, and the power mode of the other processor is set to power saving mode C3 as a specific second power mode that consumes more power than the specific second power mode (e.g., power saving mode C4). 1 toIn this way, power consumption for each of the multiple subelements (cores, uncores) can be controlled more precisely, leading to further power savings.

[0373] The controller power mode decision program 2800 (power mode control unit) switches so that the other processor uses one uncore as an example of a partial component of the one controller to control data I / O requests from the host. The storage device (e.g., "memory 2724") of the one controller described above includes a control queue (IQ11 (2730), OQ11 (2729) described below), and the other processor uses an uncore, which is a partial element of the one controller, to access the control queue and control data I / O requests from the host. In this way, power consumption can be controlled in detail, thereby further reducing power consumption.

[0374] (4) Fourth embodiment A storage system according to the fourth embodiment will be described with reference to Figures 38 and 39. The configuration of the storage system according to the fourth embodiment is similar to that of the storage system according to the third embodiment shown in Figures 27 to 37, except for the differences described below, and therefore a description of the similar parts will be omitted. Note that the storage system according to the fourth embodiment may have different reference numerals assigned to the components such as the CPU and the controller from those of the storage system according to the third embodiment, but has the same configuration and functions as the storage system according to the third embodiment unless otherwise noted in the following description.

[0375] 38 is a system configuration diagram showing an example of the configuration of a storage system according to the fourth embodiment. As described above, the storage system according to the fourth embodiment basically has the same configuration and functions as the storage system according to the third embodiment.

[0376] In the storage system of the fourth embodiment, as shown in Figures 38 and 39, instead of the core 3300 polling the OQPI of the OQ2729, the host I / F 2722 notifies the core 3300 that it has enqueued an entry related to a new host I / O in the OQ2729 by sending an interrupt.

[0377] That is, instead of polling, which will be described later, the controller power mode determination program 2800 as an example of a power mode control unit causes the host I / F 2722 to send a predetermined interrupt to the other processor (CPU 2703 of "CPU0") via one processor (CPU 2723 of "CPU1"), thereby causing the other processor to access the uncore 2726 as an example of a partial element that constitutes a part of the one processor (CPU 2723 of "CPU1") after the clock is restarted. The processing by the controller power mode determination program 2800 will be specifically described below.

[0378] Fig. 38 is a diagram for explaining the data transfer path for host I / O processing after host I / O takeover when using interrupts instead of polling. Fig. 38 is the same as Fig. 33 except for the differences explained below, so only the differences will be explained.

[0379] The host I / F 2722 transmits an interrupt to the core 3300 via a data transfer path 4201 that passes through the CPU 2723 and the inter-controller link 2711. The data transfer path 4201 includes a P2P data transfer path in the CPU 2723.

[0380] Moreover, the core 3300 accesses the OQ 2729 in the memory 2724, its queue index OQPI, and IQ 2730, via a data transfer path 4202 that passes through the inter-controller link 2711 and the CPU 2723. However, in FIG. 38, the core 3300 does not poll the OQPI.

[0381] Fig. 39 is a diagram illustrating a data transfer sequence for host I / O processing after host I / O takeover when using interrupts instead of polling. Fig. 39 is the same as Fig. 34 except for the differences described below, so only the differences will be described.

[0382] In step S3405 in Fig. 34, the core 3300 checks whether there is an unprocessed entry in the OQ 2729 by polling the OQPI of the OQ 2729. In Fig. 39, the host I / F 2722 enqueues the entry 3402 in the OQ 2729 (step S3403) and updates the OQPI of the OQ 2729 in the memory 2724 (step S3404), and then the host I / F 2722 sends an interrupt 4301 to the core 3300.

[0383] The core 3300 that has received the interrupt 4301 reads the OQPI of the OQ 2729 (step S4302). After reading the OQPI, the core 3300 determines whether there is an unprocessed entry in the OQ 2729, and if there is, reads the entry that stores the contents of the host I / O command from the OQ 2729 (step S3406).

[0384] In this way, the polling process of the OQPI of the OQ2729 by the core 3000, which was performed before the host I / O takeover from the core 3000 to the core 3300, is changed to an interrupt process from the host I / F 2722 to the core 3300 after the host I / O takeover. This reduces the frequency of access from the core 3300 to the uncore 2726, so that the clock gating of the uncore 2726 works effectively, and the power consumption of the CPU 2723 can be reduced. Furthermore, in this embodiment, the power consumption of the memory 2724 can also be reduced during the clock stop period of the uncore 2726.

[0385] Furthermore, when the clock of the uncore 2726 is stopped, if the core 3300 attempts to access the OQ 2729, IQ 2730, etc., the clock of the uncore 2726 must be restarted, which may result in a long access time. Therefore, in this embodiment, the host I / F 2722 transmits an interrupt via the CPU 2723 prior to accessing the OQ 2729, IQ 2730, etc., as described above, to cause the core 3300 to access the uncore 2726 after the clock has been restarted. Then, when the core 3300 accesses the OQ 2729, IQ 2730, etc., the clock of the uncore 2726 has been restarted, so that an increase in access time can be suppressed.

[0386] As described above, in this embodiment, the controller power mode determination program 2800 as an example of a power mode control unit causes the other processor (e.g., the CPU 2703 of "CPU0") to access the uncore 2726 as an example of a partial element constituting a part of the one processor (e.g., the CPU 2723 of "CPU1") after the clock is restarted by sending a predetermined interrupt to the other processor (e.g., the CPU 2703 of "CPU0") via the one processor (e.g., the CPU 2723 of "CPU1") via the host I / F 2722 instead of the core 3300 polling the OQPI of the OQ 2729. In this way, as described above, when the core 3300 accesses the OQ 2729, the clock of the uncore 2726 has been restarted, so that an increase in access time can be suppressed.

[0387] (5) Fifth embodiment A storage system according to the fifth embodiment will be described with reference to Fig. 40 to Fig. 43. The configuration of the storage system according to the fifth embodiment is similar to that of the storage system according to the third embodiment shown in Fig. 27 to Fig. 37 and the storage system according to the fourth embodiment shown in Fig. 38 and Fig. 39, except for the differences described below, and therefore a description of the similar parts will be omitted. Note that the storage system according to the fifth embodiment may have different reference numerals for each component such as a CPU and a controller from those of the storage systems according to the third and fourth embodiments, but has the same configuration and functions as the storage systems according to the third and fourth embodiments unless otherwise specified in the following description.

[0388] Fig. 40 is a diagram illustrating a data transfer path related to host I / O processing after host I / O takeover in the storage system 3800. Here, it is assumed that the host I / O received by the host I / F 3822 is taken over from the controller 3821 to the controller 3801, similar to the storage system 2700 according to the third embodiment.

[0389] The storage system 3800 has the same configuration as the storage system 2700, except for the controllers 3801 and 3821. The controllers 3801 and 3821 have the same configuration as the controllers 2701 and 2721, except for the host I / Fs 3802 and 3822.

[0390] The host I / Fs 3802, 3822 have functions almost similar to those of the host I / Fs 2702, 2722 in the above-described embodiments, but differ from the host I / Fs 2702, 2722 in the above-described embodiments in that, for example, a different OQ and IQ pair (the pair of "OQ02" 3809 and "IQ02" 3810, and the pair of "OQ11" 3829 and "1Q11" 3830) can be assigned to each core ("Core00" 3300, [Core11] 3000) of the CPUs 3703, 2723 that control the host I / Fs 3802, 3822.

[0391] For example, when the core 3000 of the CPU 2723 controls the host I / F 3822, it uses the pair of OQ 3829 and IQ 3830 in the memory 2724. On the other hand, when the core 3300 of the CPU 2703 controls the host I / F 3822, it uses the pair of OQ 3809 and IQ 3810 in the memory 2704. In this embodiment, an instruction from the CPU 2703 or CPU 2723 to the host I / F 3822 determines which pair of OQ and IQ the host I / F 3822 will access.

[0392] As an example, a data transfer path in the case where the core 3300 of the CPU 2703 belonging to the controller 3801 controls the host I / F 3822 of the controller 3821 will be described.

[0393] The host I / F 3822, which receives host I / O from the host machine 3100, accesses the pair of OQ 3809 and IQ 3810 in the memory 2704 and their queue indexes OQPI and IQCI via a data transfer path 3811 that passes through the CPU 2723, the inter-controller link 2711, and the CPU 2703. The data transfer path 3811 includes a P2P data transfer path in the CPU 2723.

[0394] Furthermore, the host I / F 3822 stores data received from the host machine 3100 in the memory 2724 , or transmits data stored in the memory 2724 to the host machine 3100 via the data transfer path 3812 .

[0395] The core 3300 accesses the OQ 3809 in the memory 2704 , its queue index OQPI, and the IQ 3810 via a data transfer path 3813 .

[0396] Furthermore, the core 3300 accesses OQCI, which is the queue index of the OQ 3809, and IQPI, which is the queue index of the IQ 3810, in the host I / F 3822, via a data transfer path 3814 that passes through the inter-controller link 2711 and the CPU 2723. The data transfer path 3814 includes a P2P data transfer path in the CPU 2723.

[0397] In addition, the core 3300 transfers data received from the host machine 3100 and stored in the memory 2724 to the controller 2725 by using the DMA 2707 via a data transfer path 3815 passing through the CPU 2723, the inter-controller link 2711, and the CPU 2703. 3801 In this way, the data received from the host machine 3100 is transferred to the memory 2704 of the controller 2702. 38 21 and the memory 2724 of the controller 2721 can be duplicated.

[0398] The data transfer path when the core 3000 of the CPU 2723 belonging to the controller 3821 controls the host I / F 3822 of the controller 3821 is the same as that shown in FIG. 30 already described, and therefore will not be described again.

[0399] Fig. 41 is a diagram explaining a data transfer sequence related to host I / O processing after host I / O takeover in the storage system 3800. Here, as an example, a case will be described in which the host I / F 3822 and the core 3300 of the CPU 2703 use OQ 3809 and IQ 3810 in the memory 2704. Note that in Fig. 41, OQ 3809 is displayed as "OQ02" and IQ 3810 is displayed as "IQ02".

[0400] First, the host machine 3100 transmits a host I / O command 3901 to the host I / F 3822. The host I / F 3822, which receives the host I / O command 3901, enqueues an entry 3902 including the command contents to the OQ 3809 (step S3903).

[0401] Next, the host I / F 3822 updates the OQPI of OQ 3809 in the memory 2704 to notify the core 3300 that the entry 3902 has been enqueued in the OQ 3809 (step S3904). The core 3300 checks whether there is an unprocessed entry in the OQ 3809 by polling the OQPI of the OQ 3809 (step S3905). If there is an unprocessed entry, the core 3300 reads from the OQ 3809 an entry in which the contents of the host I / O command are stored (step S3906). Furthermore, the core 3300 updates the OQCI of OQ 3809 in the host I / F 3822 (step S3907).

[0402] Next, the core 3300 enqueues an entry including a data transfer list corresponding to the host I / O command 3901 to the IQ 3810 (step S3908). Furthermore, the core 3300 updates the IQPI of the IQ 3810 in the host I / F 3822 (step S3909).

[0403] The host I / F 3822, whose IQPI has been updated, reads an entry including a data transfer list from the IQ 3810 (step S3910). Next, the host I / F 3822 transfers data between the host machine 3100 and the memory 2724 in accordance with the data transfer list included in the entry read from the IQ 3810 (step S3911). When the data transfer is complete, the host I / F 3822 updates the IQCI of the IQ 3810 in the memory 2704 (step S3912).

[0404] In this manner, the core 3300 of the CPU 2703 can process the host I / O command 3901 received by the host I / F 3822 .

[0405] 42 is a flowchart showing an example of the procedure for host I / O takeover processing between controllers and controller power mode change processing in the storage system 3800. This processing flow is executed by the CPU 2703 or CPU 2723 of the controller that has received an instruction to change the power mode to power saving mode C from the management terminal. Hereinafter, this processing flow will be referred to as a host I / O takeover processing program 4000. As an example, a case will be described in which the controller 3801 takes over host I / O processing from the controller 3821, and the power mode of the controller 3801 changes to power saving mode C1 and the power mode of the controller 3821 changes to power saving mode C2.

[0406] First, the host I / O takeover processing program 4000 executes the host I / F 3822 driver in the CPU 2703 of the controller 3801 (step S4001). At this time, the OQ 3809 and IQ 3810 are empty, and host I / O processing using them has not yet been performed. Execution of the host IF driver here means the start of processing for the control queue of the host IF. Therefore, even if the host IF driver is executed, the host IF is not initialized, so host link down, etc. does not occur.

[0407] Next, the host I / O takeover processing program 4000 instructs the host I / F 3822 to switch queues (step S4002). Before receiving the queue switching instruction, the host I / F 3822 3100Host I / F 3822 enqueues entries related to host I / O commands received from OQ3829 into OQ3829. After receiving a queue switch instruction, host I / F 3822 enqueues entries related to host I / O commands with new exchange IDs that are received thereafter into OQ3809. While there are incomplete entries remaining in OQ3829, host I / O processing related to OQ3829 and IQ3830 and host I / O processing related to OQ3809 and IQ3810 are executed in parallel. After the queue switch instruction, no new entries are enqueued into OQ3829, so eventually there will be no incomplete entries in OQ3829 and IQ3830.

[0408] Next, the host I / O takeover processing program 4000 waits until OQ3829 and IQ3830 become empty (step S4003: No). If OQ3829 and IQ3830 become empty (step S4003: Yes), the host I / O takeover processing program 4000 proceeds to step S4004.

[0409] Next, the host I / O takeover processing program 4000 stops the host I / F 3822 driver being executed by the CPU 2723 of the controller 3821 (step S4004). Stopping the host IF driver here means stopping processing of the control queue of the host IF. Therefore, even if the host IF driver is stopped, the host IF is not initialized, so that a host link down or the like does not occur.

[0410] Next, the host I / O takeover processing program 4000 stops the back-end processing being executed by the CPU 2723 of the controller 3821 (step S4005). 3100 Since the data received from is duplicated in the memories 2704 and 2724, even if the back-end processing of the CPU 2723 is stopped, as long as the CPU 2703 is executing the back-end processing, the operation of the storage system 3800 can continue.

[0411] Next, the host I / O takeover processing program 4000 reduces the operating frequency of the uncore 2726 of the CPU 2723 of the controller 3821 to a range in which the impact on P2P data transfer and data duplication processing is below a predetermined standard (step S4006). As described in Fig. 40, the data duplication processing after host I / O takeover uses the DMA 2707 of the CPU 2703. This allows the data duplication processing to be executed without problems even if the operating frequency of the uncore 2726 is reduced.

[0412] 43 is a flowchart showing an example of the procedure for resuming host I / O processing in a controller that has been set to power saving mode C2 and changing the power mode of the controller in the storage system 3800. This processing flow is executed by the CPU 2703 or CPU 2723 of the controller that has received an instruction to change the power mode to normal mode from the management terminal. Below, this processing flow is executed by the host I / O resume processing program 4100. As an example, a case will be described in which the controller 3821 takes over host I / O processing from the controller 3801 and the power mode of the controller 3821 changes from power saving mode C2 to power saving mode C1.

[0413] First, the host I / O resume processing program 4100 increases the operating frequency of the uncore 2726 of the CPU 2723 of the controller 3821 (step S4101).

[0414] Next, the host I / O resume processing program 4100 resumes the host I / F 3822 driver in the CPU 2723 of the controller 3821 (step S4102). At this time, the OQ 3829 and IQ 3830 are empty, and host I / O processing using them has not yet been performed. Resuming the host IF driver here means resuming processing for the control queue of the host IF. Therefore, even if the host IF driver is resumed, the host IF is not initialized, so host link down, etc. does not occur.

[0415] Next, the host I / O resume processing program 4100 resumes back-end processing in the CPU 2723 of the controller 3821 (step S4003). In the CPU 2723, the cores that execute host I / O processing, back-end processing, and other processing are set to the Active state, and the other cores are set to the Standby state.

[0416] Next, the host I / O resume processing program 4100 instructs the host I / F 3822 to switch queues (step S4104). Before receiving the queue switch instruction, the host I / F 3822 3100 Host I / F 3822 enqueues entries related to host I / O commands received from OQ3809 to OQ3809. After receiving a queue switch instruction, host I / F 3822 enqueues entries related to host I / O commands with new exchange IDs that are received thereafter to OQ3829. While there are incomplete entries remaining in OQ3809, host I / O processing related to OQ3809 and IQ3810 and host I / O processing related to OQ3829 and IQ3830 are executed in parallel. After the queue switch instruction, no new entries are enqueued to OQ3809, so eventually there will be no incomplete entries in OQ3809 and IQ3810.

[0417] Next, the host I / O resume processing program 4100 waits until OQ3809 and IQ3810 become empty (step S4105: No). If OQ3809 and IQ3810 become empty (step S4105: Yes), the host I / O resume processing program 4100 proceeds to step S4106.

[0418] Next, the host I / O resume processing program 4100 stops the host I / F 3822 driver being executed by the CPU 2703 of the controller 3801 (step S4106). Stopping the host IF driver here means stopping processing of the control queue of the host IF. Therefore, even if the host IF driver is stopped, the host IF is not initialized, so host link down, etc. does not occur.

[0419] The above steps are performed on the controller. 3801 From the controller 38 21 takes over the host I / O processing, and the power mode of the controller 2721 changes to the power saving state (power saving mode) C1.

[0420] The power control for the cores in the CPU can be realized by controlling the related elements and circuits in the CPU using the functions of software via the operating system of the controller, the BIOS of the CPU, etc. For other devices, it may be realized by using firmware and drivers specific to each device.

[0421] The present invention is not limited to the above-described embodiment, and includes various modified examples and equivalent configurations within the spirit of the appended claims. For example, the above-described embodiment has been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to a configuration having all the described configurations. For example, the "power mode control unit" can be read as a power mode control circuit or a power mode control function. Therefore, the functional units and means included in the above-described embodiments of the present invention may be realized as a dedicated device using hardware resources, as an electronic circuit on a board, or as a function of software or a program, or may be realized by a combination of these means. In addition, each element described in parallel in this embodiment may be in a form in which at least one of the elements is connected in series to the other elements. [Industrial Applicability]

[0422] The present invention can be applied to a storage system relating to a technique for suppressing power consumption according to the power mode of each device mounted on at least one controller. [Explanation of symbols]

[0423] 102...storage system, 103...host machine, 301...power consumption control program, 302...device operation status monitoring program, 303...power mode determination program, 304...power mode change program, 305...power mode control unit, 1701...controller management program, 1702...controller power consumption control program, 1703...controller operation status monitoring program, 1704...controller power mode determination program, 2700...storage system, 2701, 2721...controller, 3800...storage system, 3801, 3821...controller

Claims

1. A storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, a plurality of components each operable by switching between a first power mode and at least one second power mode consuming less power than the first power mode; A status monitoring unit that monitors the operating status of each of the plurality of components; a power mode control unit that determines a power mode of at least one specific component to be the second power mode based on a processing load for each of the plurality of components as a result of monitoring by the state monitoring unit, and operates the at least one specific component in the second power mode; Equipped with The plurality of components executes control in response to the data input / output request between the storage device and the storage device. A storage system comprising:

2. The plurality of components include: A plurality of devices that control data input / output processing between the host and the The storage system includes: The device is equipped with the plurality of devices, and the plurality of devices are used to communicate with the host. At least one controller for controlling data input / output processing; The controller: The state monitoring unit; The power mode control unit; The storage system according to claim 1 , further comprising:

3. The power mode control unit is a power mode determination unit that determines, based on a degree of impact on input / output processing of the data when the power mode of the specific component among the plurality of devices operating in the first power mode is changed to the second power mode, to set the power mode of the specific component to the second power mode; a power mode changing unit that switches the power mode of the specific component to the determined second power mode; The storage system according to claim 2 , further comprising:

4. a device management table for managing information about the plurality of devices; a device operation history table for managing the operation states of the plurality of devices monitored by the state monitoring unit, The power mode determination unit is When it is determined that the influence on the data input / output processing is equal to or less than a predetermined standard even if the power mode of the specific component is changed to the second power mode based on the operation states of the multiple devices managed in the device operation history table, it is determined to set the power mode of the specific component to the second power mode.

4. The storage system according to claim 3.

5. The device management table includes: managing power consumption and processing capability for each of the plurality of devices in each of the first power mode and the second power mode; The power mode control unit is determining the second power mode for the power mode of the specific component based on the power consumption and processing capacity for the first power mode and the second power mode for each of the plurality of devices managed in the device management table, and changing the power mode of the specific component to the second power mode; 5. The storage system according to claim 4.

6. The device management table includes: The power control unit is managed to define a first category for controlling the power modes of the plurality of devices independently of other devices and a second category for controlling the power modes of the plurality of devices in combination with other devices.

5. The storage system according to claim 4.

7. The device management table includes, as the power control unit, a device unit that includes a device that is independent of other devices in terms of power consumption; a connected device unit including a device whose power mode should be changed to match the power mode of the other device; A controller unit including a group of controllers each of which is to exhibit substantially the same performance; 5. The storage system according to claim 4, further comprising:

8. The power mode control unit is classifying the plurality of devices into devices that are to be grouped because they have low mutual independence from the viewpoint of controlling power consumption with respect to the plurality of devices, and devices that are to be not grouped because they have high mutual independence from the viewpoint of controlling power consumption with respect to the plurality of devices; For each of the devices to be grouped and the devices not to be grouped, the power mode is switched to the second power mode in accordance with a result of monitoring by the state monitoring unit.

6. The storage system according to claim 5.

9. The power mode control unit is When there are a plurality of devices that can be grouped, the devices are classified into a first device group in which the plurality of devices to be grouped should have the same power mode change manner, and a second device group in which the plurality of devices to be grouped do not need to have the same power mode change manner; The power mode of the first device group is changed so that the power modes of the first device group are the same as those of the first device group.

9. The storage system according to claim 8.

10. The power mode control unit is classifying devices into devices that allow power off as the second power mode and devices that do not allow power off as the second power mode; For a device that allows power off as the second power mode, the power mode is switched to power off in accordance with a result of monitoring by the state monitoring unit, while for a device that does not allow power off as the second power mode, the power mode is switched to the second power mode in accordance with a result of monitoring by the state monitoring unit.

9. The storage system according to claim 8.

11. The power mode control unit is When the predicted value of the future processing load for the plurality of specific components is zero and power-off is permitted, if it is necessary to unify the plurality of specific components, it is determined to unify the power modes of the plurality of specific components to power-off.

2. The storage system according to claim 1.

12. The plurality of components include: A plurality of controllers for controlling data input / output processing between the host and the storage device; a management terminal for controlling the plurality of controllers, The management terminal includes: The state monitoring unit; The power mode control unit; The storage system according to claim 1 , further comprising:

13. The power mode control unit is Based on the redundancy setting, in response to detection of a fault occurring in any one of the plurality of controllers, a power mode is selected that enables the other controller to immediately transition to a state in which input / output processing can be executed. The storage system according to claim 12 .

14. The power mode control unit is The other controller is enabled to transition to a state in which it can execute input / output processing immediately after the above, while some of a CPU (Central Processing Unit) cores having multiple cores are operated and the other cores are put on standby. The storage system according to claim 13 .

15. The power mode control unit is A power consumption in a first case in which the power mode of a component having a high predicted processing load is set to the predetermined second power mode and the power mode of a component having a low predicted processing load is set to the specific second power mode is compared with a power consumption in a second case in which a power mode is determined for each component, and, on condition that the power consumption in the second case is greater than the power consumption in the first case, the power mode of the component having a high predicted processing load is set to the predetermined second power mode and the power mode of the component having a low predicted processing load is set to the specific second power mode.

2. The storage system according to claim 1.

16. The plurality of components include: a plurality of subelements of each processor of a plurality of controllers; While one processor of one controller is operating, control of a part of the subelements of the one processor is switched to the other processor of the other controller, the power mode of the one processor is set to the specific second power mode, and the power mode of the other processor is set to the predetermined second power mode having a higher power consumption than the specific second power mode.

16. The storage system according to claim 15.

17. The power mode control unit is The other processor switches to control data I / O requests from the host using a subelement of the one controller.

17. The storage system according to claim 16.

18. The storage device includes: Includes a control queue, The other processor accesses the control queue when controlling a data I / O request from the host using a subelement of the one controller.

20. The storage system according to claim 17.

19. The power mode control unit is By sending a predetermined interrupt via the one processor, the other processor is allowed to access a subelement that constitutes a part of the one processor after the clock is restarted.

17. The storage system according to claim 16.

20. A power consumption reduction method for a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, comprising: a status monitoring step in which a status monitoring unit monitors the operation status of each of a plurality of components that can be operated by switching between a first power mode and at least one second power mode having a lower power consumption than the first power mode; a power mode control step of determining, by a power mode control unit, the power mode of at least one specific component to be the second power mode based on a processing load for each of the plurality of components as a result of monitoring by the state monitoring step, and operating the at least one specific component in the second power mode; A power consumption reduction method for a storage system, comprising the steps of: executing control between the storage device and the plurality of components in response to the data input / output request;

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