Power conversion device

Abstract

To provide a power conversion device which achieves suppression in current unbalance.SOLUTION: A power conversion device includes: a plurality of semiconductor packages which constitutes upper and lower arm circuits and is electrically connected in parallel with each other; and a wiring board on which the plurality of semiconductor packages is mounted and which is electrically connected to each of the semiconductor packages. Each of the plurality of semiconductor packages includes: a semiconductor element in which electrodes are formed on both surfaces; a first conductor which is connected to one electrode of the semiconductor element and the high-potential side of the upper and lower arm circuits; a second conductor which is connected to the other electrode of the semiconductor element and the low-potential side of the upper and lower arm circuits; and a sealing member which seals the first conductor, the second conductor, and the semiconductor element such that a heat dissipation surface being the surface on the side opposite to the surface on the side connected with the semiconductor element is exposed in the second conductor. The wiring board includes a conductive member electrically connected to the heat dissipation surface of the second conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] Regarding measures to reduce inductance in a power conversion device, for example, Patent Document 1 listed below discloses a structure in which high-potential side terminals and low-potential side terminals of adjacent semiconductor packages are arranged alternately to reduce inductance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2023-62905 Summary of the Invention [Problem to be solved by the invention]

[0004] The technique described in Patent Document 1 has a problem in that it is not possible to suppress imbalances in currents flowing through a plurality of switching elements that are caused by differences in wiring inductance on the source side. [Means for solving the problem]

[0005] The power conversion device comprises a plurality of semiconductor packages that form upper and lower arm circuits and are electrically connected in parallel to each other, and a wiring board on which the plurality of semiconductor packages are mounted and electrically connected to each of the plurality of semiconductor packages, the plurality of semiconductor packages comprising a semiconductor element having electrodes formed on both sides, a first conductor connected to one electrode of the semiconductor element and a high potential side of the upper and lower arm circuits, a second conductor connected to the other electrode of the semiconductor element and a low potential side of the upper and lower arm circuits, and a sealing member that seals the first conductor, the second conductor, and the semiconductor element so that a heat dissipation surface of the second conductor, which is the surface opposite to the surface to which the semiconductor element is connected, is exposed, and the wiring board has a conductive member electrically connected to the heat dissipation surface of the second conductor. Effect of the Invention

[0006] According to the present invention, it is possible to provide a power conversion device that realizes suppression of current imbalance. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor module according to an embodiment of the present invention; [Diagram 2] FIG. 1 is a plan view of a plurality of semiconductor modules according to an embodiment of the present invention. [Diagram 3] Figure 2 Power conversion circuit diagram [Figure 4] FIG. 3 is a plan view of the first layer of the wiring board of the semiconductor module of FIG. [Diagram 5] FIG. 3 is a plan view of the second layer of the wiring board of the semiconductor module of FIG. 2. [Figure 6] A plan view of the third layer of the wiring board of the semiconductor module of FIG. 2. [Figure 7] FIG. 3 is a plan view of the fourth layer of the wiring board of the semiconductor module of FIG. 2. [Figure 8] Plan view and A-A' cross-sectional view of a semiconductor package in a semiconductor module [Figure 9] Plan view, B-B' cross section, and C-C' cross section of the semiconductor package in Figure 8 with the sealing resin removed [Figure 10] A plan view and a cross-sectional view along the line D-D' of the semiconductor package of FIG. 9 with the second conductor removed. [Figure 11] A plan view and an E-E' cross-sectional view of the semiconductor package of FIG. 9 with the first conductor removed. [Figure 12] First variant of the invention [Figure 13] Second variant of the invention DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (One embodiment and overall configuration) (Figure 1) A semiconductor package 10, which is a semiconductor module included in a power conversion device, has a semiconductor element 2, a first conductor 21, a second conductor 22, and a bent terminal 24. In the semiconductor package 10, the semiconductor element 2, the first conductor 21, and the second conductor 22 are molded and sealed with a sealing member 11. The switching circuit of the semiconductor element 2 constituting the semiconductor package 10 is, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0011] The semiconductor element 2 has electrodes formed on both sides. A first conductor 21 connected to the high potential side of the upper and lower arm circuits configured in the semiconductor package 10 is connected to one electrode of the semiconductor element 2. A second conductor 22 connected to the low potential side of the upper and lower arm circuits configured in the semiconductor package 10 is connected to the other electrode of the semiconductor element 2.

[0012] The second conductor 22 has a heat dissipation surface 16. The sealing member 11 seals the first conductor 21, the second conductor 22, and the semiconductor element 2 such that the heat dissipation surface 16, which is the surface of the second conductor 22 opposite to the surface to which the semiconductor element 2 is connected, is exposed from the sealing member 11. Note that, in order to ensure thermal connection with a heat dissipation fin 9 (FIGS. 12 and 13) described below, the semiconductor package 10 may be sealed with the sealing member 11 such that, in addition to exposing the heat dissipation surface 16 of the second conductor 22, a surface 21a of the first conductor 21 opposite to the surface connected to the semiconductor element 2 is exposed.

[0013] The wiring board 1 has a conductive member 7 formed of a material such as copper inlay. A second conductor 22, which is a conductor on the source side in the semiconductor package 10, electrically connects the heat dissipation surface 16 to the surface of the conductive member 7 of the wiring board 1, thereby electrically connecting the second conductor 22 to the main circuit of the wiring board 1.

[0014] The bent terminal 24 has a bent portion 24a that is bent in the stacking direction of the semiconductor package 10. The bent terminal 24 is electrically connected to a side wiring pattern 7a formed on a side of the conductive member 7 on the wiring board 1 via solder 24b. By having the bent terminal 24 in this way, the semiconductor package 10 can not only reduce the size of the wiring board 1 in the longitudinal direction, but also reduce stress on the solder 24b used to join the semiconductor package 10 and the wiring board 1, thereby improving the reliability of the power conversion device.

[0015] (Figs. 2 to 4) The conductive member 7 has one common surface that joins the heat dissipation surface 16 (FIG. 1) of the second conductor 22 that is connected to the source side of each of the multiple semiconductor packages 10. The multiple semiconductor packages 10 that configure the upper and lower arm circuits are electrically connected to each other in parallel. The multiple semiconductor packages 10 are mounted on a wiring board 1, and the multiple semiconductor packages 10 are each electrically connected to the wiring board 1. FIG. 2 illustrates, for example, a state in which positive electrode semiconductor packages P1 to P4 and negative electrode semiconductor packages N1 to N4, which are semiconductor packages 10, are arranged on the board 1.

[0016] The wiring board 1 has a wiring pattern P of a positive bus bar, a wiring pattern N of a negative bus bar, and an AC wiring pattern AC. The AC wiring pattern AC is a high potential wiring 4, and the wiring pattern N of the negative bus bar is a low potential wiring 3. A drive circuit 6 is provided outside the wiring board 1. The drive circuit 6 is connected to the gate wiring 5 on the wiring board 1 to control the switching of the semiconductor package 10.

[0017] A description will be given of the inductance generated between the wiring board 1 and the semiconductor package 10. For convenience of explanation, the inductance generated on the wiring pattern N side of the negative bus bar will be described, and a description of the inductance generated on the wiring pattern P side of the positive bus bar will be omitted.

[0018] 3, inductances Lb1, Lb2, and Lb3 are generated between terminals connected to semiconductor packages N1 to N4 on the wiring pattern N of the negative bus bar provided on the wiring board 1. Inductance L_PKG is generated in each terminal connecting the wiring pattern N of the negative bus bar to each semiconductor package 10 on the wiring board 1. Inductances La1, La2, and La3 are generated between connection surfaces (heat dissipation surfaces 16) of the semiconductor packages N1 to N4 and the conductive members 7 connected to the second conductors 22 of the semiconductor packages N1 to N4.

[0019] In this way, by arranging the semiconductor package 10 on the wiring board 1, the wiring inductance difference on the source side of the semiconductor package 10 can be further reduced compared to the conventional state in which the high potential side terminals and the low potential side terminals of the semiconductor package 10 are arranged alternately to reduce inductance, thereby suppressing current imbalance.

[0020] (Figs. 4 to 7) The wiring board 1 is formed by stacking four layers of substrates, and the configurations of the first to fourth layers are shown in Figures 4 to 7. In each layer, the wiring patterns of the positive bus bar and the negative bus bar are different, but the positions where the conductive members 7 are provided are the same.

[0021] (Figure 8) 8(a) is a plan view of the semiconductor package 10, and FIG. 8(b) is an A-A' cross-sectional view of FIG. 8(a). In the semiconductor package 10, the high-potential side signal terminal 12, the low-potential side signal terminal 13, the high-potential side terminal 14, and the low-potential side terminal 15 each protrude to the outside from the sealing member 11. The semiconductor element 2 is electrically connected to the first conductor 21 and the second conductor 22 via the solder 2c. As shown in the A-A' cross-sectional view, the low-potential side signal terminal 13 and the high-potential side terminal 14 are bent terminals having a bent portion 24a that is bent in the stacking direction of the semiconductor package 10. Although not shown, the high-potential side signal terminal 12 and the low-potential side terminal 15 are also bent terminals having a bent portion 24a.

[0022] (Fig. 9) Fig. 9(a) is a diagram of a semiconductor package 10 with the sealing member 11 removed, Fig. 9(b) is a cross-sectional view taken along line B-B' in Fig. 9(a), and Fig. 9(c) is a cross-sectional view taken along line C-C' in Fig. 9(a). The semiconductor element 2 is connected to the high-potential side signal terminal 12 and the low-potential side signal terminal 13 via bonding wires 17. The low-potential side terminal 15 is a terminal that is connected to the second conductor 22 via solder 15a. The high-potential side terminal 14 is a terminal that is connected to the first conductor 21.

[0023] (Fig. 10, Fig. 11) Fig. 10(a) is a plan view of the first conductor 21 seen from the side on which the semiconductor element 2 is mounted, with the second conductor 22 removed from Fig. 9, and Fig. 10(b) is a D-D' cross-sectional view of Fig. 10(a). Fig. 11(a) is a plan view of the second conductor 22 seen from the side on which the semiconductor element 2 is mounted, with the first conductor 21 removed from Fig. 9, and Fig. 11(b) is an E-E' cross-sectional view of Fig. 11(a).

[0024] The high potential side signal terminal 12 is connected to a high potential side signal input section 18 of the semiconductor element 2 by a bonding wire 17. The low potential side signal terminal 13 is connected to a low potential side signal input section 19 of the semiconductor element 2 by a bonding wire 17.

[0025] In the semiconductor element 2, the low potential side plane 2b is a surface that is connected to the second conductor 22. In addition, in the semiconductor element 2, the high potential side plane 2a is a surface that is connected to the first conductor 21. Therefore, the connection side of the first conductor 21 is the high potential side, and the connection side of the second conductor 22 is the low potential side.

[0026] (First Modification) (Fig. 12) FIG. 12(a) is a cross-sectional view showing a state where a through hole 8 is provided in a conductive member 7 of a wiring board 1, and FIG. 12(b) is a plan view of the wiring board 1 of FIG. 12(a). The wiring board 1 has a plurality of through holes 8 penetrating the wiring board 1 in the plate thickness direction. The conductive member 7 is connected to the through hole 8, and is thermally connected to a heat dissipation fin 9 via the through hole 8. The semiconductor package 10 is thermally connected to the heat dissipation fin 9 via the conductive member 7 and the through hole 8. The heat dissipation fin 9 is also thermally connected to the surface of the first conductor 21 that is not connected to the semiconductor element 2 in the semiconductor package 10 via an insulating / heat dissipation joint 23, thereby promoting heat dissipation of the semiconductor element 2. The insulating / heat dissipation joint 23 is configured by, for example, sandwiching an insulating ceramic plate between two TIMs (Thermal Interface Materials). In this way, the thermal resistance can be reduced.

[0027] (Second Modification) (Fig. 13) The wiring board 1 may have a conductive member 7 made of a copper plate 25 that is provided continuously from one surface to the other surface along the plate thickness direction of the wiring board 1. This allows heat generated in the semiconductor element 2 to be dissipated from the connection side of the second conductor 22 connected to the source side of the semiconductor package 10 to the heat dissipation fins 9 via the copper plate 25, thereby reducing thermal resistance.

[0028] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0029] (1) The power conversion device includes a plurality of semiconductor packages 10 that constitute upper and lower arm circuits and are electrically connected in parallel to each other, and a wiring board 1 on which the plurality of semiconductor packages 10 are mounted and electrically connected to each of the plurality of semiconductor packages 10, the plurality of semiconductor packages 10 each having electrodes formed on both sides, a first conductor 21 connected to one electrode of the semiconductor element 2 and the high potential side of the upper and lower arm circuits, a second conductor 22 connected to the other electrode of the semiconductor element 2 and the low potential side of the upper and lower arm circuits, and a sealing member 11 that seals the first conductor 21, the second conductor 22, and the semiconductor element 2 so that a heat dissipation surface 16 of the second conductor 22, which is the surface opposite to the surface to which the semiconductor element 2 is connected, is exposed, and the wiring board 1 has a conductive member 7 that is electrically connected to the heat dissipation surface 16 of the second conductor 22. In this way, a power conversion device that realizes suppression of current imbalance can be provided.

[0030] (2) The semiconductor package 10 includes heat dissipation fins 9 that promote heat dissipation from the semiconductor element 2, the wiring board 1 includes a plurality of through holes 8 that penetrate the wiring board 1 in the plate thickness direction, and the conductive members 7 are connected to the through holes 8 and are thermally connected to the heat dissipation fins 9 via the through holes 8. This ensures a heat dissipation path from the source surface side, thereby reducing thermal resistance.

[0031] (3) The semiconductor packages 10 each include a bent terminal 24 having a bent shape in the stacking direction, and the bent terminal 24 is electrically connected to a wiring pattern 7a formed on a side of a conductive member 7 on the wiring board 1. This reduces stress at the joint of the solder 24b, improving the reliability of the power conversion device.

[0032] (4) The conductive member 7 extends from one surface to the other surface along the thickness direction of the wiring board 1. This ensures a heat dissipation path from the source surface side, thereby reducing thermal resistance.

[0033] The present invention is not limited to the above-described embodiment, and various modifications and other configurations can be combined without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiment, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0034] 1. Wiring board 2. Semiconductor elements 2a High potential side plane 2b Low potential side plane 2c solder 3 Low potential wiring 4 High potential wiring 5 Gate wiring 6 Drive circuit P1~P4 Semiconductor package (positive electrode) N1~N4 Semiconductor package (negative electrode) 7 Conductive materials 7a Side wiring pattern 8 Through Hole 9 Heat dissipation fin 10 Semiconductor Package 11 Sealing member 12 High potential signal terminal 13 Low potential signal terminal 14 High potential terminal 15 Low potential terminal 15a solder 16 Heat dissipation surface 17 Bonding Wire 18 High potential signal input section 19 Low potential side signal input section 21 First Conductor 21a Exposed surface 22 Second Conductor 23 Insulating / heat dissipating joint 24 Bend terminal 24a Bend part 24b solder 25 Copper plate

Claims

1. a plurality of semiconductor packages that configure upper and lower arm circuits and are electrically connected in parallel to each other; a wiring board on which the plurality of semiconductor packages are mounted and which is electrically connected to each of the plurality of semiconductor packages; The plurality of semiconductor packages each include a semiconductor element having electrodes formed on both sides, a first conductor connected to one electrode of the semiconductor element and a high potential side of the upper and lower arm circuits, a second conductor connected to the other electrode of the semiconductor element and a low potential side of the upper and lower arm circuits, and a sealing member that seals the first conductor, the second conductor, and the semiconductor element such that a heat dissipation surface of the second conductor, which is a surface opposite to a surface to which the semiconductor element is connected, is exposed; The wiring board has a conductive member electrically connected to the heat dissipation surface of the second conductor. Power conversion equipment.

2. The power conversion device according to claim 1, the semiconductor package includes heat dissipation fins that promote heat dissipation from the semiconductor element; the wiring board includes a plurality of through holes penetrating the wiring board in a thickness direction thereof; The conductive member is connected to the through hole and is thermally connected to the heat dissipation fin via the through hole. Power conversion equipment.

3. The power conversion device according to claim 1, The semiconductor packages each include a bent terminal having a bent shape in a stacking direction, The bent terminal is electrically connected to a wiring pattern formed on a side of the conductive member on the wiring board. Power conversion equipment.

4. The power conversion device according to claim 1, The conductive member is continuous from one surface to the other surface along a thickness direction of the wiring board. Power conversion equipment.

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