Semiconductor device

Abstract

To control a joint member which joins the front face of a semiconductor chip and a lead frame together, to a uniform thickness.SOLUTION: A semiconductor unit includes: a semiconductor chip 12 which includes a main electrode on its front face; a conductive plate 11c which has a chip region where the reverse face of the semiconductor chip 12, set on its front face; a conductive plate 11d which is provided adjacently to the conductive plate 11c in plan view; a support conductive plate 11c2 which is provided on the opposite side to the conductive plate 11d with respect to a chip region, and insulated from the conductive plate 11c; and a lead frame 13 which includes a wiring joint part 13a joined to the support conductive plate 11c2, a wiring joint part 13b joined to the conductive plate 11d, and an electrode joint part 13c joined to a main electrode of the semiconductor chip 12 through a joint member 15b.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes two semiconductor chips and a clip that connects electrodes on the front surfaces of the two semiconductor chips (see, for example, Patent Document 1). Further, a semiconductor device includes two power semiconductor chips disposed on a P potential lead and inner leads that respectively join the electrodes on the front surfaces of the two power semiconductor chips and an N potential lead (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a semiconductor device in which the thickness of a bonding member that bonds the front surface of a semiconductor chip and a lead frame is uniformly controlled.

Means for Solving the Problems

[0005] According to one aspect of the present invention, there is provided a semiconductor device having a lead frame including: a semiconductor chip having a main electrode on a front surface; a first conductive plate including a first main surface in which a chip region to which the back surface of the semiconductor chip is joined is set; a second conductive plate provided adjacent to the first conductive plate in a plan view; a support portion provided on the opposite side of the second conductive plate with respect to the chip region and insulated from the first conductive plate; a first joint portion joined to the support portion; a second joint portion joined to the second conductive plate; and an electrode joint portion joined to the main electrode of the semiconductor chip via a joint member.

[0006] Further, the support portion may be disposed in an opening region formed in the first conductive plate without contacting the first conductive plate. Further, the support portion may be made of the same material as the first conductive plate.

[0007] Further, in the lead frame, a first length from the electrode joint portion to the first joint portion and a second length from the electrode joint portion to the second joint portion may be equal. Further, the lead frame includes a flat first linking portion connecting between the electrode joint portion and the first joint portion, and a flat second linking portion connecting between the electrode joint portion and the second joint portion. A first height from the first joint portion to the first linking portion and a second height from the second joint portion to the second linking portion may be respectively higher than a third height from the electrode joint portion to the first linking portion and a fourth height from the electrode joint portion to the second linking portion.

[0008] Further, in a plan view, the lead frame may extend linearly from the electrode joint portion to the first joint portion. Further, in a plan view, the lead frame may extend linearly from the electrode joint portion to the second joint portion.

[0009] Further, in a plan view, the lead frame may extend linearly from the first joint portion to the second joint portion. Further, the lead frame may include a plurality of the second joints and may extend linearly from the electrode joint to each of the plurality of the second joints in a plan view.

[0010] Further, the electrode joint may correspond to the position of the center of gravity of the lead frame in a plan view. Further, the lead frame may include elastic portions between the electrode joint and the first joint and between the electrode joint and the second joint, respectively. Further, the lead frame includes a flat first connecting portion connecting between the electrode joint and the first joint and a flat second connecting portion connecting between the electrode joint and the second joint, the elastic portions are respectively provided on the first connecting portion and the second connecting portion, and the elastic portions of each of the first connecting portion and the second connecting portion may be bent in the thickness direction over the entire width of the first connecting portion and the second connecting portion.

[0011] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Effect of the Invention

[0012] According to the disclosed technology, the thickness of the bonding member that bonds the front surface of the semiconductor chip and the lead frame can be uniformly controlled.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the "front surface" and the "upper surface" represent the X-Y plane facing upward (+Z direction) in the semiconductor device in the figure. Similarly, "up" represents the upward (+Z direction) in the semiconductor device in the figure. The "back surface" and the "lower surface" represent the X-Y plane facing downward (-Z direction) in the semiconductor device in the figure. Similarly, "down" represents the downward (-Z direction) in the semiconductor device in the figure. Other drawings may also have the same directionality as described above as necessary. "Higher" and "upper" represent positions on the upper side (+Z direction) in the semiconductor device in the figure. Similarly, "lower" and "lower" represent positions on the lower side (-Z direction) in the semiconductor device in the figure. The "front surface", "upper surface", "up" and the "back surface", "lower surface", "down" and the "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the gravitational direction. In the following description, "main component" means a case where it contains 80 vol% or more. Also, "substantially the same" may be within a range of ±10%. Also, "vertical", "orthogonal", and "parallel" may be within a range of ±10°.

[0015] [First Embodiment] The semiconductor device 1 of the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the semiconductor device of the first embodiment, and FIG. 2 is a side view of the semiconductor device of the first embodiment. Note that FIG. 2 is a side view of the X-Z plane in FIG. 1 viewed in the +Y direction.

[0016] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, 10c and a housing 20 that houses the semiconductor units 10a, 10b, 10c. The semiconductor units 10a, 10b, 10c housed in the housing 20 may be sealed with a sealing member (not shown).

[0017] Note that the semiconductor units 10a, 10b, and 10c all have the same configuration. When not distinguished, the semiconductor units 10a, 10b, and 10c will be described as the semiconductor unit 10. Details of the semiconductor unit 10 will be described later.

[0018] The housing 20 includes a frame portion 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a, 25b, 25c.

[0019] The frame portion 21 has a substantially rectangular shape in plan view and is surrounded by outer walls 21a, 21b, 21c, and 21d on all four sides. The outer walls 21a and 21c correspond to the long sides of the frame portion 21 in plan view, and the outer walls 21b and 21d similarly correspond to the short sides of the frame portion 21. In plan view, the corners of the connection portions of the outer walls 21a, 21b, 21c, and 21d do not necessarily have to be right angles. These corners may be chamfered, as shown in FIG. 1. Fixing holes 21i penetrating the frame portion 21 are formed at the corners of the front surface of the frame portion 21. Note that the fixing holes 21i formed at such corners of the frame portion 21 may be formed below (-Z direction) the front surface of the frame portion 21.

[0020] The frame portion 21 includes unit accommodation portions 21e, 21f, and 21g along the outer walls 21a and 21c on the front surface. The unit accommodation portions 21e, 21f, and 21g have a rectangular shape and are open in plan view. The semiconductor units 10a, 10b, and 10c are respectively accommodated in the unit accommodation portions 21e, 21f, and 21g. The semiconductor units 10a, 10b, and 10c are respectively joined to the top plate 31 of a cooling device 3 described later. The frame portion 21 is attached to the top plate 31 of such a cooling device 3. When attaching, the unit accommodation portions 21e, 21f, and 21g of the frame portion 21 respectively surround (accommodate) the semiconductor units 10a, 10b, and 10c arranged in the cooling device 3. Note that an inlet 33a and an outlet 33b are formed on the bottom surface 33d of the cooling device 3 (the surface opposite to the top plate 31 to which the semiconductor unit 10 is attached). Details of the cooling device 3 will be described later.

[0021] In plan view, the frame portion 21 is provided with first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c along the outer wall 21a on the front surface on the outer wall 21a side. One outer end portion of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c is exposed on the front surface on the outer wall 21a side. The other inner end portion is exposed in the unit accommodation portions 21e, 21f, 21g and is electrically connected to the semiconductor units 10a, 10b, 10c. Note that nuts facing the openings of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c on the front surface of the frame portion 21 may be accommodated in regions facing the openings.

[0022] On the front surface on the outer wall 21c side, a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c are provided along the outer wall 21c. One outer end portion of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c protrudes from the outer wall 21c. The other inner end portion is exposed in the unit accommodation portions 21e, 21f, 21g and is electrically connected to the semiconductor units 10a, 10b, 10c.

[0023] In this way, on the front surface of the frame portion 21, the first connection terminal 22a, the second connection terminal 23a, and the U-phase output terminal 24a are provided with the unit accommodation portion 21e interposed therebetween. The first connection terminal 22b, the second connection terminal 23b, and the V-phase output terminal 24b are provided with the unit accommodation portion 21f interposed therebetween. The first connection terminal 22c, the second connection terminal 23c, and the W-phase output terminal 24c are provided with the unit accommodation portion 21g interposed therebetween.

[0024] Furthermore, in a plan view, the frame portion 21 is provided with control terminals 25a, 25b, and 25c along the outer wall 21c on the +Y direction side of the unit storage portions 21e, 21f, and 21g. The control terminals 25a, 25b, and 25c may each be provided in two parts. The control terminals 25a, 25b, and 25c may, for example, form an L shape and may include an outer end portion and an inner end portion. The outer end portions of the control terminals 25a, 25b, and 25c may extend vertically upward (+Z direction) from the front surface of the frame portion 21. The other end portions of the control terminals 25a, 25b, and 25c are exposed within the unit storage portions 21e, 21f, and 21g. Note that the shape and the number of arrangements of the control terminals 25a, 25b, and 25c are not limited to this and can be changed as appropriate.

[0025] Such a frame portion 21 includes first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a, 25b, 25c, and is integrally formed by injection molding using a thermoplastic resin. Examples of the thermoplastic resin include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0026] Also, the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal having excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy having at least one of these as a main component. A plating process may be performed on the surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c. In this case, examples of the plating material used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0027] The sealing member (not shown) that seals the unit storage portions 21e, 21f, and 21g of the housing 20 may be a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. Preferably, it is an epoxy resin. Further, a filler may be added to the sealing member. The filler may be a material that is insulating and has high heat conductivity. Examples of the material include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0028] The housing 20 having the above configuration is an example. The housing 20 may accommodate the semiconductor units 10a, 10b, and 10c as long as the power conversion function can be realized using the semiconductor units 10a, 10b, and 10c.

[0029] The cooling device 3 includes an inlet 33a through which a refrigerant flows into the interior and an outlet 33b through which the refrigerant that has circulated inside flows out to the exterior. The cooling device 3 cools the semiconductor unit 10 by allowing the heat from the semiconductor unit 10 to flow out through the refrigerant. Examples of the refrigerant used here include water, antifreeze (ethylene glycol aqueous solution), and long-life coolant. Further, the cooling device 3 may include a pump and a heat radiating device (radiator). The pump causes the refrigerant to flow into the inlet 33a of the cooling device 3, and circulates the refrigerant by causing the refrigerant that has flowed out from the outlet 33b to flow back into the inlet 33a. The heat radiating device receives the refrigerant that has flowed out from the cooling device 3 and radiates the heat of the refrigerant to which the heat of the semiconductor unit 10 has been conducted to the exterior.

[0030] Such a cooling device 3 has a top plate 31, a side wall 32 annularly connected to the back surface of the top plate 31, and a cooling bottom plate 33 facing the top plate 31 and connected to the back surface of the side wall 32. The top plate 31 has a rectangular shape surrounded by long sides and short sides in plan view, and fastening holes are respectively formed at the four corners. The corners of the top plate 31 in plan view may be chamfered. On the front surface of the top plate 31, semiconductor units 10a, 10b, 10c are joined along the ±X directions. The side wall 32 is continuously formed in an annular shape on the back surface of the top plate 31. A plurality of heat dissipation fins (not shown) are formed in the region of the back surface of the top plate 31 corresponding to the region where the semiconductor units 10a, 10b, 10c are arranged.

[0031] The cooling bottom plate 33 has a flat plate shape and has the same shape as the top plate 31 in plan view. The cooling bottom plate 33 has a rectangular shape similar to that of the top plate 31 in plan view. Also, the corners of the cooling bottom plate 33 may also be chamfered. Further, the front surface and the bottom surface 33d of the cooling bottom plate 33 are parallel. The bottom surface 33d of the cooling bottom plate 33 is a flat surface without a step and forms the same plane. The bottom surface 33d of the cooling bottom plate 33 is formed with an inlet 33a and an outlet 33b through which the refrigerant flows in and out, respectively. A water distribution head is attached to the inlet 33a and the outlet 33b via an annular rubber packing surrounding the periphery of the inlet 33a and the outlet 33b (not shown). A water distribution pipe connected to a pump is attached to the water distribution head.

[0032] Next, the semiconductor unit 10 will be described with reference to FIGS. 3 to 5. FIG. 3 is a plan view of the semiconductor unit included in the semiconductor device according to the first embodiment. FIGS. 4 and 5 are the first and second cross-sectional views of the semiconductor unit included in the semiconductor device according to the first embodiment. Note that FIG. 4 is a cross-sectional view taken along the dashed line X-X in FIG. 3, and FIG. 5 is a cross-sectional view taken along the dashed line Y-Y in FIG. 3. Also, in FIGS. 3 to 5, in order to explain the configuration of the semiconductor unit 10, a case without warping is shown.

[0033] The semiconductor unit 10 includes an insulating circuit board 11, two semiconductor chips 12, and two lead frames 13, 14. The semiconductor chips 12 are joined to the insulating circuit board 11 by joining members 15a. The lead frames 13, 14 are joined to the main electrodes on the front surface of the semiconductor chips 12 and the insulating circuit board 11 by joining members 15b.

[0034] As shown in FIGS. 4 and 5, the insulating circuit board 11 includes an insulating plate 11a, conductive plates 11b, 11c, 11d, and a metal plate 11e. The inner ends of the second connection terminals 23a, 23b, 23c are respectively joined to the regions indicated by the broken lines of the conductive plate 11d in FIG. 3. The inner ends of the first connection terminals 22a, 22b, 22c are respectively joined to the regions indicated by the broken lines of the conductive plate 11b in FIG. 3. The inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are respectively joined to the regions indicated by the broken lines of the conductive plate 11c in FIG. 3.

[0035] The insulating plate 11a and the metal plate 11e are rectangular in plan view. The corners of the insulating plate 11a and the metal plate 11e may be chamfered with an R-chamfer or a C-chamfer. The size of the metal plate 11e is smaller than that of the insulating plate 11a in plan view and is formed inside the insulating plate 11a.

[0036] The insulating plate 11a includes side surfaces 11a1 to 11a4 that sequentially surround the four sides of the front surface. The side surfaces 11a1, 11a3 correspond to the long sides of the insulating plate 11a in plan view. The side surfaces 11a2, 11a4 correspond to the short sides of the insulating plate 11a in plan view. The insulating plate 11a also includes four corners 11a5 to 11a8 respectively. The corner 11a5 is formed by the side surfaces 11a1, 11a2. The corner 11a6 is formed by the side surfaces 11a2, 11a3. The corner 11a7 is formed by the side surfaces 11a3, 11a4. The corner 11a8 is formed by the side surfaces 11a4, 11a1.

[0037] Such an insulating plate 11a is made of a material with high insulation and excellent thermal conductivity. Such an insulating plate 11a may be made of ceramics. Examples of ceramics include aluminum oxide, aluminum nitride, and silicon nitride.

[0038] The conductive plates 11b, 11c, and 11d are formed on the front surface of the insulating plate 11a. The conductive plates 11b, 11c, and 11d are made of a metal with excellent conductivity. Examples of such a metal include copper, aluminum, or an alloy mainly composed of at least one of these. A plating process may be performed on the surfaces of the conductive plates 11b, 11c, and 11d to improve corrosion resistance. In this case, examples of the plating material used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0039] The conductive plate 11b is in the half region on the side of the side surface 11a4 of the front surface of the insulating plate 11a and occupies the whole area from the side surface 11a1 to the side surface 11a3. A chip region 11b3 (see FIG. 7) is set on the front surface of the conductive plate 11b. The chip region 11b3 corresponds to the planar shape of the semiconductor chip 12, and the semiconductor chip 12 is joined thereto. Also, at the end side in the -Y direction of the front surface of the conductive plate 11b, the broken line region shown in the -X direction is where the inner ends of the first connection terminals 22a, 22b, and 22c are joined. The joining at this time may be by a joining member, laser welding, or ultrasonic joining. Or, the broken line region shown on the conductive plate 11b and the inner ends of the first connection terminals 22a, 22b, and 22c may be joined via a conductive block body.

[0040] Also, the conductive plate 11b is provided on the opposite side (+X direction side) of the conductive plate 11c with respect to the chip region 11b3 (semiconductor chip 12) and includes a support conductive plate 11b2 that is insulated from the conductive plate 11b.

[0041] In the case of FIG. 3, the conductive plate 11b has a recess 11b1 formed in the end side on the opposite side (+X direction side) of the conductive plate 11c with respect to the chip region 11b3 (semiconductor chip 12). The recess 11b1 may face the chip region 11b3 (semiconductor chip 12). In particular, here, the recess 11b1 faces the chip region 11b3 (semiconductor chip 12) directly in the ±X directions. The recess 11b1 is a region where a part of the end side of the conductive plate 11b on the +X direction side is recessed in the -X direction. Examples of the shape of the recess 11b1 in plan view include a U shape, a semicircular shape, and a rectangular shape. FIG. 3 shows the case where the recess 11b1 is U-shaped.

[0042] The support conductive plate 11b2 may be made of, for example, the same material as the conductive plate 11b. The support conductive plate 11b2 is provided in the recess 11b1 of the conductive plate 11b. That is, the support conductive plate 11b2 is formed on the insulating plate 11a without contacting the conductive plate 11b. For this reason, the support conductive plate 11b2 and the conductive plate 11b are electrically insulated from each other. The shape and size of the support conductive plate 11b2 in plan view may be such that it can be arranged within the recess 11b1 and can include the end portion (wiring joint portion 14b) of the lead frame 14 described later. In the case of FIG. 3, the shape and size of the support conductive plate 11b2 correspond to the shape of the recess 11b1. The width of the support conductive plate 11b2 in the ±Y directions is wider than the width of the lead frame 14 in the same directions.

[0043] Note that such a support conductive plate 11b2 does not necessarily need to be provided at the end side of the conductive plate 11b in the +X direction. The support conductive plate 11b2 may be provided on the conductive plate 11b on the opposite side (+X direction side) of the conductive plate 11c with respect to the chip region 11b3 (semiconductor chip 12). The support conductive plate 11b2 may be provided, for example, between the chip region 11b3 (semiconductor chip 12) and the end side of the conductive plate 11b in the +X direction on the conductive plate 11b. In this case, the conductive plate 11b may have an opening region formed at a position corresponding to the support conductive plate 11b2 without the recess 11b1 being formed. The opening region in this case may also have a shape and size such that the support conductive plate 11b2 does not contact the conductive plate 11b.

[0044] The conductive plate 11c occupies half of the side surface 11a2 side on the front surface of the insulating plate 11a. Further, the conductive plate 11c occupies the area from the side surface 11a3 of the front surface of the insulating plate 11a to the front of the side surface 11a1. A chip region 11c3 (see FIG. 7) is set on the front surface of the conductive plate 11c. The chip region 11c3 corresponds to the planar shape of the semiconductor chip 12, and the semiconductor chip 12 is joined thereto. Also, at the front edge of the conductive plate 11c in the +Y direction, in the broken line region shown in the +X direction, the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are respectively joined. Here, the broken line region is set on the +X direction side (the conductive plate 11b side) of the side portion of the support conductive plate 11c2 (the depression 11c1) described later. The joining at this time may be a joining member, laser welding, or ultrasonic joining. Alternatively, the broken line region shown in the conductive plate 11c and the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c may be joined via a conductive block body.

[0045] Also, the conductive plate 11c includes a support conductive plate 11c2 that is provided on the opposite side (+Y direction side) of the conductive plate 11d with respect to the chip region 11c3 (semiconductor chip 12) and is electrically insulated from the conductive plate 11c.

[0046] In the case of FIG. 3, in the conductive plate 11c, a depression 11c1 is formed at the edge on the opposite side (+Y direction side) of the conductive plate 11d with respect to the chip region 11c3 (semiconductor chip 12). The depression 11c1 may face the chip region 11c3 (semiconductor chip 12). Particularly here, the depression 11c1 faces the chip region 11c3 (semiconductor chip 12) in the ±Y direction. The depression 11c1 is a region where a part of the edge on the +Y direction side of the conductive plate 11c is recessed in the -Y direction. Examples of the planar shape of the depression 11c1 include a U shape, a semicircular shape, and a rectangular shape. FIG. 3 shows the case where the depression 11c1 is U-shaped.

[0047] The support conductive plate 11c2 may be made of, for example, the same material as the conductive plate 11c. The support conductive plate 11c2 is provided in the depression 11c1 of the conductive plate 11c. That is, the support conductive plate 11c2 is formed on the insulating plate 11a without contacting the conductive plate 11c. Therefore, the support conductive plate 11c2 and the conductive plate 11c are electrically insulated from each other. The shape and size of the support conductive plate 11c2 in plan view may be such that it can be arranged within the depression 11c1 and can include the end portion (wiring joint portion 13a) of the lead frame 13 described later. In the case of FIG. 3, the support conductive plate 11c2 corresponds to the shape of the depression 11c1. The width of the support conductive plate 11c2 in the ±X direction is wider than the width of the lead frame 13 in the same direction.

[0048] Note that such a support conductive plate 11c2 does not necessarily have to be provided at the +Y direction end side of the conductive plate 11c. The support conductive plate 11c2 may be provided on the conductive plate 11c on the opposite side (+Y direction side) of the chip region 11c3 (semiconductor chip 12) with respect to the conductive plate 11d. The support conductive plate 11c2 may be provided, for example, between the chip region 11c3 (semiconductor chip 12) and the +Y direction end side of the conductive plate 11c on the conductive plate 11c. In this case, an opening region may be formed at a position corresponding to the support conductive plate 11c2 on the conductive plate 11c without forming the depression 11c1. The opening region in this case may also have a shape and size such that the support conductive plate 11c2 does not contact the conductive plate 11c.

[0049] The conductive plate 11d occupies the region surrounded by the conductive plates 11b and 11c on the front surface of the insulating plate 11a. The width of the conductive plate 11d in the ±X direction is equal to the width of the conductive plate 11c in the same direction. The broken line regions shown in the conductive plate 11d are where the inner ends of the second connection terminals 23a, 23b, and 23c are joined. The joining at this time may be by a joining member, laser welding, or ultrasonic joining. Alternatively, the region surrounded by the broken line shown in the conductive plate 11d and the inner ends of the second connection terminals 23a, 23b, and 23c may be connected via a conductive block body.

[0050] Such conductive plates 11b, 11c, and 11d are formed on the front surface of the insulating plate 11a as follows. A metal layer is formed on the front surface of the insulating plate 11a, and a process such as etching is performed on this metal layer to obtain conductive plates 11b, 11c, and 11d with a predetermined shape. Further, the periphery of a predetermined range of the conductive plates 11b and 11c may be peeled off by etching to form support conductive plates 11b2 and 11c2 separated from the conductive plates 11b and 11c.

[0051] Alternatively, conductive plates 11b, 11c, and 11d including recesses 11b1 and 11c1 cut out in advance from a metal layer may be pressure-bonded to the front surface of the insulating plate 11a, and further, support conductive plates 11b2 and 11c2 may be pressure-bonded into the recesses 11b1 and 11c1.

[0052] The corners of the conductive plates 11b, 11c, and 11d may be chamfered with an R or C shape. Note that the conductive plates 11b, 11c, and 11d are just examples. The number, shape, size, and position of the conductive plates 11b, 11c, and 11d may be appropriately selected as needed.

[0053] As shown in FIGS. 4 and 5, the metal plate 11e is formed on the back surface of the insulating plate 11a. The metal plate 11e has a rectangular shape. The area of the metal plate 11e in a plan view is smaller than the area of the insulating plate 11a and larger than the area of the region where the conductive plates 11b, 11c, and 11d are formed. The corners of the metal plate 11e may be chamfered with an R or C shape. The metal plate 11e is smaller than the size of the insulating plate 11a and is formed on the entire surface of the insulating plate 11a excluding the edge portions. This metal includes, for example, copper, aluminum, or an alloy containing at least one of these. A plating process may be performed on the surface of the metal plate 11e to improve corrosion resistance. In this case, examples of the plating material used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0054] As the insulated circuit board 11 having such a configuration, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. The insulated circuit board 11 may be attached to the front surface of the cooling device 3 via a joining member (not shown). Heat generated in the semiconductor chip 12 can be conducted to the cooling device 3 via the conductive plates 11b and 11c, the insulating plate 11a, and the metal plate 11e and dissipated.

[0055] The joining members 15a and 15b are solder. Solder is lead-free solder. The lead-free solder may mainly comprise an alloy containing at least two of, for example, tin, silver, copper, zinc, antimony, indium, and bismuth. Further, the solder may contain an additive. The additive is, for example, nickel, germanium, cobalt, or silicon. By containing the additive, the solder can improve wettability, gloss, and bonding strength, and thus improve reliability.

[0056] Also, the joining member (not shown) for joining the semiconductor unit 10 and the cooling device 3 may be solder, brazing material, or thermal interface material. Solder is lead-free solder. The brazing material may mainly comprise at least any one of, for example, aluminum alloy, titanium alloy, magnesium alloy, zirconium alloy, and silicon alloy. The thermal interface material is an adhesive and may include, for example, an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, and phase change material. By attaching the semiconductor unit 10 to the cooling device 3 via such brazing material or thermal interface material, the heat dissipation performance of the semiconductor unit 10 can be improved.

[0057] The semiconductor chip 12 includes a power device element. The power device element is an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor) mainly composed of silicon. The RC-IGBT has the combined functions of an IGBT which is a switching element and an FWD (Free Wheeling Diode) which is a diode element. On the front surface of such a semiconductor chip 12, there are provided a control electrode 12a (gate electrode) and an output electrode (emitter electrode) which is a main electrode 12b. On the back surface of the semiconductor chip 12, there is provided an input electrode (collector electrode) which is a main electrode (not shown in the figure). Note that the control electrode 12a may be provided along one side (or at the center of one side) of the front surface of the semiconductor chip 12. The output electrode is provided at the center of the front surface of the semiconductor chip 12. The input electrode is provided including the center of the back surface of the semiconductor chip 12.

[0058] As another power device element, there is a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) mainly composed of silicon carbide. In the power MOSFET, the body diode may function as the FWD. Such a semiconductor chip 12 is provided with a control electrode 12a (gate electrode) and an output electrode (source electrode) which is a main electrode 12b on the front surface respectively. The semiconductor chip 12 is provided with an input electrode (drain electrode) which is a main electrode on the back surface.

[0059] The lead frame 13 electrically connects and wires the main electrode 12b of the semiconductor chip 12 on the conductive plate 11c and the conductive plate 11d. The lead frame 14 electrically connects and wires the main electrode 12b of the semiconductor chip 12 on the conductive plate 11b and the conductive plate 11c. The semiconductor unit 10 may be a device constituting an inverter circuit for one phase.

[0060] As shown in FIGS. 4 and 5, the lead frames 13 and 14 include wiring joints 13a and 14a, electrode joints 13c and 14c, and wiring joints 13b and 14b. Note that the wiring joints 13a and 14a are examples of the first joints, and the wiring joints 13b and 14b are examples of the second joints. Further, the lead frames 13 and 14 each include linking portions 13d and 14d that link the wiring joints 13a and 14a and the electrode joints 13c and 14c, and linking portions 13e and 14e that link the electrode joints 13c and 14c and the wiring joints 13b and 14b. The lead frames 13 and 14 integrally include these and form a straight line in a plan view. The lead frames 13 and 14 may have the same overall width in a plan view. The thicknesses of the wiring joints 13a and 14a, the electrode joints 13c and 14c, and the wiring joints 13b and 14b in the (+Z direction) may be uniformly the same. The thicknesses of the linking portions 13e and 14e and the linking portions 13d and 14d may be uniformly the same and may be thinner than the thicknesses of the wiring joints 13a and 14a, the electrode joints 13c and 14c, and the wiring joints 13b and 14b.

[0061] The wiring joints 13a and 14a are respectively joined to the support conductive plates 11c2 and 11b2 via joining members 15a. The wiring joints 13a and 14a are, for example, in a flat plate shape. The wiring joints 13a and 14a may have a shape and size that fit within the support conductive plates 11c2 and 11b2 in a plan view. A plurality of bosses 13a1 and 14a1 may be formed on the back surfaces of the wiring joints 13a and 14a. Note that the plurality of bosses 13a1 and 14a1 may be, for example, in a cylindrical shape or a prismatic shape. Also, the heights of the plurality of bosses 13a1 and 14a1 are substantially uniform. The plurality of bosses 13a1 and 14a1 can maintain the thickness of the joining member 15a between the wiring joints 13a and 14a and the support conductive plates 11c2 and 11b2 to be substantially constant.

[0062] The electrode joints 13c and 14c are respectively joined to the main electrodes 12b of the semiconductor chip 12 via joint members 15b. The electrode joints 13c and 14c are, for example, in a flat plate shape. The electrode joints 13c and 14c may have a shape and size corresponding to the main electrodes 12b of the semiconductor chip 12 in a plan view. A boss may not be formed on the back surface of the electrode joints 13c and 14c.

[0063] The wiring joints 13b and 14b are respectively joined to the conductive plates 11d and 11c via joint members 15a. The wiring joints 13b and 14b are, for example, in a flat plate shape. The wiring joints 13b and 14b may have a shape and size that can fit within the conductive plates 11d and 11c in a plan view. A plurality of bosses 13b1 and 14b1 may be formed on the back surface of the wiring joints 13b and 14b. The plurality of bosses 13b1 and 14b1 may be, for example, in a cylindrical shape or a prismatic shape. Also, the heights of the plurality of bosses 13b1 and 14b1 are substantially uniform. The plurality of bosses 13b1 and 14b1 can maintain the thickness of the joint member 15a between the wiring joints 13b and 14b and the conductive plates 11d and 11c to be substantially constant.

[0064] The linking portions 13d and 14d are in a flat plate shape. The linking portions 13d and 14d integrally connect the end sides on the electrode joint 13c and 14c sides of the wiring joints 13a and 14a and the end sides on the wiring joint 13a and 14a sides of the electrode joints 13c and 14c in a plan view.

[0065] Also, the connecting portions 13d and 14d extend vertically upward (+Z direction) from the end sides on the electrode connecting portions 13c and 14c sides of the wiring connecting portions 13a and 14a to a predetermined height (first height) in a side view, and bend at a right angle toward the electrode connecting portions 13c and 14c sides. Further, the connecting portions 13d and 14d extend toward the electrode connecting portions 13c and 14c, bend on the end sides on the wiring connecting portions 13a and 14a sides of the electrode connecting portions 13c and 14c, and extend vertically downward (-Z direction) to a predetermined height (third height) and connect to the end sides. At this time, the first height is longer (higher) than the third height, and is longer than the length obtained by adding the respective thicknesses (+Z direction) of the third height and the semiconductor chip 12. That is, the electrode connecting portions 13c and 14c are located above (+Z direction) the wiring connecting portions 13a and 14a. The intermediate portions of the connecting portions 13d and 14d are parallel to the main surface of the insulating circuit board 11. Note that the first height is a predetermined height from the wiring connecting portions 13a and 14a to the connecting portions 13d and 14d, and the third height is a predetermined height from the electrode connecting portions 13c and 14c to the connecting portions 13d and 14d.

[0066] Such a configuration of the connecting portions 13d and 14d is an example. The connecting portions 13d and 14d only need to be able to connect the wiring connecting portions 13a and 14a and the electrode connecting portions 13c and 14c. The connecting portions 13d and 14d may be, for example, an arch shape whose apex forms an R surface. Alternatively, the connecting portions 13d and 14d may connect the wiring connecting portions 13a and 14a and the electrode connecting portions 13c and 14c having different heights in a straight line.

[0067] The connecting portions 13e and 14e are flat plate-shaped. In a plan view, the connecting portions 13e and 14e integrally connect the end sides on the wiring connecting portions 13b and 14b sides of the electrode connecting portions 13c and 14c and the end sides on the electrode connecting portions 13c and 14c sides of the wiring connecting portions 13b and 14b.

[0068] Further, the connecting portions 13e and 14e extend vertically upward (+Z direction) from the end sides on the wiring connection portion 13b and 14b sides of the electrode connection portions 13c and 14c to a predetermined height (fourth height) in side view, and bend at a right angle toward the wiring connection portions 13b and 14b. Further, the connecting portions 13e and 14e extend toward the wiring connection portions 13b and 14b, bend on the end sides on the electrode connection portions 13c and 14c sides of the wiring connection portions 13b and 14b, and extend vertically downward (-Z direction) to a predetermined height (second height) and connect to the end sides. At this time, the second height is longer (higher) than the fourth height, and is longer than the length obtained by adding the respective thicknesses (+Z direction) of the fourth height and the semiconductor chip 12. That is, the electrode connection portions 13c and 14c are located above (+Z direction) the wiring connection portions 13b and 14b. The intermediate portions of the connecting portions 13e and 14e are parallel to the main surface of the insulating circuit board 11. Further, the intermediate portions of the connecting portions 13e and 14e may be in the same plane as the intermediate portions of the connecting portions 13d and 14d. Note that the second height is the predetermined height from the wiring connection portions 13b and 14b to the connecting portions 13e and 14e, and the fourth height is the predetermined height from the electrode connection portions 13c and 14c to the connecting portions 13e and 14e.

[0069] Such a configuration of the connecting portions 13e and 14e is an example. The connecting portions 13e and 14e only need to be able to connect the electrode connection portions 13c and 14c and the wiring connection portions 13b and 14b. The connecting portions 13e and 14e may be, for example, an arch shape whose apex forms an R surface. Alternatively, the connecting portions 13e and 14e may connect the electrode connection portions 13c and 14c with different heights and the wiring connection portions 13b and 14b in a straight line.

[0070] Such lead frames 13 and 14 are linear in plan view. For this reason, the wiring connection portions 13a and 14a, the electrode connection portions 13c and 14c, and the wiring connection portions 13b and 14b are also arranged in a row. At this time, the electrode connection portions 13c and 14c may be located in the middle of the wiring connection portions 13a and 14a and the wiring connection portions 13b and 14b. Therefore, in plan view, the connecting portions 13d and 14d and the connecting portions 13e and 14e may have the same length.

[0071] Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIG. 6. FIG. 6 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. First, a preparation step of preparing the component parts of the semiconductor device 1 is performed (step S1 in FIG. 6). Examples of the component parts to be prepared include the insulating circuit board 11, the semiconductor chip 12, the cooling device 3, the housing 20, and the lead frames 13 and 14. Other than these, component parts necessary for the semiconductor device 1 may be prepared. Also, manufacturing equipment used for manufacturing the semiconductor device 1 may be prepared. Here, the insulating circuit board 11 prepared here will be described with reference to FIG. 7. FIG. 7 is a plan view of the insulating circuit board included in the semiconductor device according to the first embodiment.

[0072] As described above, the insulating circuit board 11 includes the insulating plate 11a, the conductive plates 11b, 11c, 11d, and the metal plate 11e (see FIGS. 4 and 5). Further, as shown in FIG. 7, the conductive plates 11b, 11c, 11d are formed on the front surface of the insulating plate 11a.

[0073] A chip region 11b3 where the semiconductor chip 12 is disposed is set at approximately the center of the conductive plate 11b. The conductive plate 11b has a recess 11b1 formed in an end side on the opposite side (+X direction side) of the conductive plate 11c with respect to the chip region 11b3. A support conductive plate 11b2 is formed in the recess 11b1.

[0074] A chip region 11c3 where the semiconductor chip 12 is disposed is set at approximately the center of the conductive plate 11c. The conductive plate 11c has a recess 11c1 formed in an end side on the opposite side (+Y direction side) of the conductive plate 11d with respect to the chip region 11c3. A support conductive plate 11c2 is formed in the recess 11c1. The conductive plate 11d is formed in a region surrounded by the conductive plates 11b and 11c on the front surface of the insulating plate 11a.

[0075] Next, a setting process is performed in which the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 are stacked and set in this order (step S2 in FIG. 6). The setting process will be described with reference to FIGS. 7 and 8. FIG. 8 is a diagram showing the setting process included in the method for manufacturing a semiconductor device according to the first embodiment. Note that FIG. 8 is a cross-sectional view of the set configuration after the setting process. FIG. 8 is a cross-sectional view at the position corresponding to FIG. 4. Here, the lead frame 13 will be described in detail, but the lead frame 14 is treated in the same manner.

[0076] First, the semiconductor chips 12 are respectively set on the chip regions 11b3 and 11c3 of the insulating circuit board 11 via the bonding plates 15a1. Further, as shown in FIG. 8, the support conductive plate 11c2, the main electrode 12b of the semiconductor chip 12 on the chip region 11c3, and the conductive plate 11d are respectively set via the bonding plate 15b1 to the wiring bonding portion 13a, the electrode bonding portion 13c, and the wiring bonding portion 13b of the lead frame 13.

[0077] The support conductive plate 11b2, the main electrode 12b of the semiconductor chip 12 on the chip region 11b3, and the conductive plate 11c are respectively set via the bonding plate 15b1 to the wiring bonding portion 14a, the electrode bonding portion 14c, and the wiring bonding portion 14b of the lead frame 14. Note that the bonding plates 15a1 and 15b1 are formed of the same material as the bonding members 15a and 15b and have a plate shape.

[0078] Next, a first bonding process is performed to bond the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 (step S3 in FIG. 6). The first bonding process will be described with reference to FIGS. 8 and 9. FIG. 9 is a diagram showing the first bonding process included in the method for manufacturing a semiconductor device according to the first embodiment. Note that FIG. 9 is also a cross-sectional view at the same position as FIG. 8. Also, here, the lead frame 13 will be described, but the first bonding process is similarly performed for the lead frame 14.

[0079] Heat the insulating circuit board 11, semiconductor chip 12, and lead frames 13 and 14 set in step S2. At this time, the bonding plates 15a1 and 15b1 provided between them, as shown in FIG. 8, are also heated and become the molten bonding members 15a and 15b.

[0080] Also, due to the difference in the coefficient of thermal expansion of each of the insulating plate 11a, conductive plates 11b, 11c, and 11d, and metal plate 11e of the insulating circuit board 11, warping occurs during heating. The warping is, for example, convex downward with the metal plate 11e side at the bottom.

[0081] Thereafter, heating is stopped, and the curing of the molten bonding members 15a and 15b begins. The lead frame 13 starts to be joined to the support conductive plate 11c2 and the conductive plate 11b by the bonding member 15a at the wiring joints 13a and 13b. Further, the electrode joint 13c starts to be joined to the main electrode 12b of the semiconductor chip 12 by the bonding member 15b.

[0082] The lead frame 13 joined to the insulating circuit board 11 warped convex downward is being fixed to the support conductive plate 11c2 and the conductive plate 11b at the wiring joints 13a and 13b, respectively. For this reason, the lead frame 13 is supported with two points, the wiring joint 13a and the wiring joint 13b, serving as fulcrums. As a result, the inclination of the lead frame 13 and the electrode joint 13c is suppressed, and the thickness of the bonding member 15b is maintained substantially uniformly. The bonding member 15b cures in a state where the thickness is uniformly controlled, and the electrode joint 13c and the main electrode 12b of the semiconductor chip 12 are joined. By joining the electrode joint 13c to the main electrode 12b of the semiconductor chip 12 in this way, the inclination of the electrode joint 13c is prevented, and the variation in the thickness of the bonding member 15b is suppressed.

[0083] Also, the wiring joints 13a and 13b include a plurality of bosses 13a1 and 13b1. For this reason, the wiring joints 13a and 13b can maintain the thickness of the bonding member 15a between the support conductive plate 11c2 and the conductive plate 11b substantially uniformly. Thus, the semiconductor unit 10 is configured.

[0084] Note that, in the first bonding step described here, the case where the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 are bonded at once is explained. Not limited to this case, the semiconductor chip 12 may be bonded to the insulating circuit board 11 by the bonding member 15a, and then the lead frames 13 and 14 may be bonded to the insulating circuit board 11 and the semiconductor chip 12 by the bonding member 15b.

[0085] Next, a second bonding step of bonding the semiconductor unit 10 to the cooling device 3 is performed (step S4 in FIG. 6). The semiconductor units 10a, 10b, and 10c are bonded to the front surface of the top plate 31 of the cooling device 3 along the longitudinal direction of the top plate 31 via a bonding member (not shown).

[0086] Next, a housing attachment step of attaching the housing 20 onto the cooling device 3 is performed (step S5 in FIG. 6). The housing 20 is attached onto the top plate 31 of the cooling device 3 with an adhesive (not shown). At this time, the semiconductor units 10a, 10b, and 10c on the top plate 31 are housed in the unit housing portions 21e, 21f, and 21g of the housing 20.

[0087] Next, a wiring and sealing step of wiring the semiconductor units 10a, 10b, and 10c housed in the housing 20 and sealing the inside of the unit housing portions 21e, 21f, and 21g of the housing 20 is performed (step S6 in FIG. 6).

[0088] First, in the semiconductor units 10a, 10b, and 10c housed in the unit housing portions 21e, 21f, and 21g of the housing 20, the control electrode 12a of the semiconductor chip 12 is connected to the inner ends of the control terminals 25a, 25b, and 25c with a wire (not shown). Also, the inner ends of the first connection terminals 22a, 22b, and 22c are respectively bonded to the conductive plate 11b of the insulating circuit board 11. Similarly, the inner ends of the second connection terminals 23a, 23b, and 23c are respectively bonded to the conductive plate 11d. Further, similarly, the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are respectively bonded to the conductive plate 11c.

[0089] Then, a sealing member (not shown) is filled in the unit storage portions 21e, 21f, and 21g of the housing 20 to seal the semiconductor units 10a, 10b, and 10c. Thus, the semiconductor device 1 shown in FIGS. 1 and 2 is obtained.

[0090] Here, the semiconductor device of the reference example will be described. The semiconductor device of the reference example has the same configuration as the semiconductor device 1 except for the semiconductor unit 10. The semiconductor unit included in the semiconductor device of the reference example is different from the semiconductor unit 10 included in the semiconductor device 1 of the first embodiment. Here, the semiconductor unit included in the semiconductor device of the reference example will be described with reference to FIG. 10. FIG. 10 is a plan view of the semiconductor unit included in the semiconductor device of the reference example. Note that FIG. 10 corresponds to FIG. 3 of the first embodiment.

[0091] The semiconductor unit 100 of the reference example includes an insulating circuit board 11, a semiconductor chip 12, and lead frames 13 and 14, similar to the semiconductor unit 10 of the first embodiment. However, the conductive plates 11b, 11c, and 11d included in the insulating circuit board 11 do not have depressions 11b1 and 11c1 and do not include support conductive plates 11b2 and 11c2.

[0092] Accordingly, the lead frames 13 and 14 include wiring joint portions 13b and 14b, electrode joint portions 13c and 14c, and linking portions 13e and 14e that connect these. That is, the lead frames 13 and 14 do not include the wiring joint portions 13a and 14a and the linking portions 13d and 14d of the first embodiment. Also, in the reference example, bosses are formed on the back surfaces of the electrode joint portions 13c and 14c (boss 13c1 is shown in FIGS. 11 and 12). The wiring joint portions 13b and 14b are joined to the conductive plates 11d and 11c via joining members 15a. The electrode joint portions 13c and 14c are joined to the main electrodes 12b of the semiconductor chip 12 via joining members 15b. Note that the semiconductor chip 12 is joined to the conductive plates 11c and 11d via the joining member 15a, respectively.

[0093] A semiconductor device including such a semiconductor unit 100 can also be manufactured in accordance with the flowchart of FIG. 6. Next, a method for manufacturing this semiconductor device will be described with reference to FIG. 6. Note that in the following manufacturing method, descriptions of the same steps as those in the first embodiment are omitted or simplified.

[0094] First, as in the first embodiment, a preparation step of preparing the components of the semiconductor device of the reference example is performed (step S1 in FIG. 6). Next, a setting step of sequentially setting the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 is performed (step S2 in FIG. 6). The setting step will be described with reference to FIG. 11. FIG. 11 is a diagram showing the setting step included in the method for manufacturing the semiconductor device of the reference example. Note that FIG. 11 is a cross-sectional view of the set configuration after the setting step. FIG. 11 is a cross-sectional view at a position corresponding to the dashed-dotted line X-X in FIG. 10.

[0095] Here too, the semiconductor chips 12 are each set in the chip region (not shown) of the insulating circuit board 11 via the bonding plates 15a1. Further, as shown in FIG. 11, the main electrodes 12b of the semiconductor chips 12 and the electrode bonding portions 13c and wiring bonding portions 13b of the lead frame 13 are set to the conductive plate 11d via the bonding plates 15b1, respectively.

[0096] Next, a first bonding step of sequentially bonding the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 is performed (step S3 in FIG. 6). The first bonding step will be described with reference to FIGS. 11 and 12. FIG. 12 is a diagram showing the first bonding step included in the method for manufacturing the semiconductor device of the reference example. Note that FIG. 12 is also a cross-sectional view at the same position as FIG. 11. Here, the lead frame 13 will be described, but the same applies to the lead frame 14.

[0097] The insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 set in step S2 are heated. At this time, the bonding plates 15a1 and 15b1 provided therebetween, as shown in FIG. 11, are also heated to become the molten bonding members 15a and 15b.

[0098] Further, due to the difference in the coefficient of thermal expansion of each of the insulating plate 11a, the conductive plates 11b, 11c, 11d, and the metal plate 11e, the insulating circuit board 11 warps when heated. The warp is convex downward with the metal plate 11e side at the bottom, for example.

[0099] Thereafter, the heating is stopped, and the curing of the molten joining members 15a, 15b begins. The lead frame 13 starts to be joined to the conductive plate 11d by the joining member 15a at the wiring joint 13b. Further, the electrode joint 13c starts to be joined to the main electrode 12b of the semiconductor chip 12 by the joining member 15b.

[0100] Since the insulating circuit board 11 warps convex downward, even if the boss 13c1 is formed, the inclination of the electrode joint 13c of the lead frame 13 joined to such an insulating circuit board 11 cannot be suppressed. For this reason, the thickness of the joining member 15b varies. Along with this, the semiconductor chip 12 inclines, and the thickness of the joining member 15a also varies.

[0101] When the thickness of the joining member 15b varies and the electrode joint 13c is connected to the main electrode 12b of the semiconductor chip 12 in an inclined manner, there is a possibility that the heat dissipation performance of the semiconductor chip 12 also varies. Variations in heat dissipation performance may reduce the cooling performance and cause a failure of the semiconductor chip 12. Thereafter, the steps S4, S5, and S6 in FIG. 6 are sequentially performed, and a semiconductor device including the semiconductor unit 100 of the reference example is obtained.

[0102] The semiconductor device 1 described above includes a semiconductor unit 10. The semiconductor unit 10 includes a semiconductor chip 12 having a main electrode 12b on its front surface, a conductive plate 11c (an example of a first conductive plate) having a chip region 11c3 to which the back surface of the semiconductor chip 12 is joined set on its front surface, a conductive plate 11d (an example of a second conductive plate) provided adjacent to the conductive plate 11c in a plan view, a support conductive plate 11c2 (an example of a support portion) provided on the side opposite to the conductive plate 11d with respect to the chip region 11c3 and insulated from the conductive plate 11c, a wiring joint portion 13a (an example of a first joint portion) joined to the support conductive plate 11c2, a wiring joint portion 13b (an example of a second joint portion) joined to the conductive plate 11d, and an electrode joint portion 13c joined to the main electrode 12b of the semiconductor chip 12 via a joint member 15b, and includes a lead frame 13. In such a semiconductor unit 10, the lead frame 13 is supported at two points of the wiring joint portions 13a and 13b, the inclination of the lead frame 13 is suppressed, and the thickness of the joint member 15b is maintained substantially uniform. The joint member 15b is cured in a state where its thickness is uniformly controlled, and the electrode joint portion 13c and the main electrode 12b of the semiconductor chip 12 are joined. By joining the electrode joint portion 13c to the main electrode 12b of the semiconductor chip 12 in this way, the inclination of the electrode joint portion 13c is prevented, and the variation in the thickness of the joint member 15b is suppressed. As a result, the variation in the heat dissipation performance of the semiconductor chip 12 is suppressed, and the occurrence of failures of the semiconductor chip 12 is reduced. Therefore, the decrease in the reliability of the semiconductor device 1 is suppressed.

[0103] The support conductive plate 11c2 is disposed in a recess 11c1 (an example of an opening region) formed in the conductive plate 11c without contacting the conductive plate 11c. In such a configuration, the support conductive plate 11c2 can be used as a wiring path for an auxiliary emitter by connecting the control terminal 25a and the support conductive plate 11c2 with, for example, a bonding wire. Further, by joining the wiring joint portion 13a of the lead frame 13 and the support conductive plate 11c2, the contact area of the lead frame 13 with respect to the support conductive plate 11c2 increases as compared with the structure of FIG. 10, so that the heat dissipation performance is improved.

[0104] In a plan view, the lead frame 13 extends linearly from the electrode joint portion 13c to the wiring joint portion 13a and also extends linearly from the electrode joint portion 13c to the wiring joint portion 13b. That is, in a plan view, the lead frame 13 extends linearly from the wiring joint portion 13a to the wiring joint portion 13b. With such a configuration, the electrode joint portion 13c of the lead frame 13 can be lifted (separated in the +Z direction) from the semiconductor chip 12, so that the variation in the thickness of the joint member 15b can be more reliably suppressed.

[0105] The lead frame 13 includes a flat plate-shaped linking portion 13d (an example of the first linking portion) connecting between the electrode joint portion 13c and the wiring joint portion 13a and a flat plate-shaped linking portion 13e (an example of the second linking portion) connecting between the electrode joint portion 13c and the wiring joint portion 13b. The first height from the wiring joint portion 13a to the linking portion 13d and the second height from the wiring joint portion 13b to the linking portion 13e are respectively higher than the third height from the electrode joint portion 13c to the linking portion 13d and the fourth height from the electrode joint portion 13c to the linking portion 13e. Note that the second height is preferably longer than the length obtained by combining the fourth height and the thickness of the semiconductor chip 12 in the +Z direction, and the first height is preferably longer than the length obtained by combining the third height and the thickness of the semiconductor chip 12 in the +Z direction. Further, it is more preferable that the first height and the second height are equal, and the third height and the fourth height are equal. With such a configuration, the electrode joint portion 13c can be more reliably lifted (separated in the +Z direction) from the semiconductor chip 12, so that the variation in the thickness of the joint member 15b can be suppressed.

[0106] (Modification Example 1-1) The semiconductor unit 10 of Modification Example 1-1 of the first embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 is a plan view of the semiconductor unit included in the semiconductor device of the first embodiment (Modification Example 1-1). FIG. 14 is a cross-sectional view of the semiconductor unit included in the semiconductor device of the first embodiment (Modification Example 1-1). Note that FIGS. 13 and 14 correspond to FIGS. 3 and 4 of the first embodiment. FIG. 14 is a cross-sectional view taken along the dashed-dotted line X-X in FIG. 13.

[0107] The semiconductor device of Modification 1-1 is different from the semiconductor device 1 of the first embodiment in that the semiconductor unit 10 is different. In the semiconductor unit 10 of Modification 1-1, in the semiconductor unit 10 of the first embodiment, the depressions 11b1 and 11c1 are not formed in the conductive plates 11b and 11c, and the support conductive plates 11b2 and 11c2 are not provided. That is, the conductive plates 11b and 11c of the semiconductor unit 10 of Modification 1-1 have no depressions or openings, and the front surface is flat and rectangular.

[0108] In such a semiconductor unit 10 of Modification 1-1, the wiring joints 13a and 14a of the lead frames 13 and 14 are joined to the conductive plates 11c and 11d via the support block portions 11b4 and 11c4. For example, as shown in FIG. 14, in the lead frame 13, the wiring joint 13b is joined to the conductive plate 11d by a joining member 15a. The wiring joint 13a is supported by the support block portion 11c4 disposed on the conductive plate 11c. The wiring joint 13a may maintain the same height as the wiring joint 13b. The support block portion 11c4 may be made of an insulating material. Such a material is, for example, resin. The height of the support block portion 11c4 may be any height that can maintain the wiring joint 13a. Thereby, the wiring joint 13a is electrically insulated from the conductive plate 11c. Further, the support block portion 11c4 may be disposed in the depression 11c1 provided in the conductive plate 11c in the same manner as in the first embodiment.

[0109] The remaining configuration of the lead frame 13 of Modification 1-1 may be the same as that of the lead frame 13 of the first embodiment. Further, the lead frame 14 of Modification 1-1 has the same configuration as the lead frame 13 of Modification 1-1.

[0110] Even in such a semiconductor unit 10 of Modification 1-1, as in the first embodiment, the inclination of the electrode joint 13c is prevented, and the variation in the thickness of the joining member 15b is suppressed. Thereby, the variation in the heat dissipation of the semiconductor chip 12 is suppressed, and the occurrence of failure of the semiconductor chip 12 is reduced. Therefore, the decrease in the reliability of the semiconductor device 1 is suppressed.

[0111] [Second Embodiment] In the second embodiment, in the first embodiment, when the lead frames 13 and 14 are not in a straight line in a plan view, it will be described with reference to FIG. 15. FIG. 15 is a plan view of a semiconductor unit included in the semiconductor device of the second embodiment.

[0112] The semiconductor unit 10 of the second embodiment may have the same configuration as the semiconductor unit 10 of the first embodiment except for the lead frames 13 and 14. The lead frames 13 and 14 of such a second embodiment have the wiring joint portions 13b and 14b of the lead frames 13 and 14 of the first embodiment divided into wiring joint portions 13b2, 13b3 and wiring joint portions 14b2, 14b3, respectively. Note that for the lead frames 13 and 14 of the second embodiment, except for the wiring joint portions 13b2, 13b3 and the wiring joint portions 14b2, 14b3, the configurations of the lead frames 13 and 14 in FIGS. 4 and 5 can be referred to. The wiring joint portions 13b2, 13b3 and the wiring joint portions 14b2, 14b3 are respectively connected to the conductive plates 11d, 11c via the joint members 15b.

[0113] Accordingly, the lead frames 13 and 14 of the second embodiment include linking portions 13e2, 13e3 and linking portions 14e2, 14e3. The linking portions 13e2, 13e3 and the linking portions 14e2, 14e3 are each linear. The linking portion 13e2, 13e3 connects between the electrode joint portion 13c and the wiring joint portions 13b2, 13b3. The linking portion 14e2, 14e3 connects between the electrode joint portion 14c and the wiring joint portions 14b2, 14b3. Also, here, the linking portions 13e2, 13e3 and the linking portions 14e2, 14e3 have the same length.

[0114] A semiconductor device including such lead frames 13 and 14 can also be manufactured in accordance with the flowchart of FIG. 6. In the first bonding step of step S3 in the flowchart of FIG. 6, when heating is stopped and the molten bonding members 15a and 15b are cured, the electrode bonding portions 13c and 14c of the lead frame 13 are supported by the wiring bonding portions 13a and 13b, the wiring bonding portions 13b2 and 13b3, and the wiring bonding portions 14b2 and 14b3. Therefore, in the second embodiment, the inclination of the lead frame 13 and the electrode bonding portion 13c can be suppressed more stably than in the case of the first embodiment. For this reason, the thickness of the bonding member 15b is also more reliably maintained substantially uniformly.

[0115] In the second embodiment, the case where the lead frames 13 and 14 include the wiring bonding portions 13b2 and 13b3 and the wiring bonding portions 14b2 and 14b3 that are divided into two is described as an example. The wiring bonding portions 13b and 14b of the lead frames 13 and 14 in the first embodiment are not limited to two, and may be divided into three or more. Also, the wiring bonding portions 13a and 14a of the lead frames 13 and 14 in the first embodiment may be divided into two or more. In this case, openings or depressions are formed in the conductive plates 11c and 11b according to the number of divisions of the wiring bonding portions 13a and 14a. Alternatively, the wiring bonding portions divided into two or more may be joined to the conductive plates 11c and 11b via the support block portions of Modification 1-1, respectively.

[0116] Also, when at least any one of the wiring bonding portions 13a and 14a and the wiring bonding portions 13b and 14b of the lead frames 13 and 14 in the first embodiment are divided into a plurality, the electrode bonding portions 13c and 14c may be provided at the positions of the centers of gravity of the lead frames 13 and 14. When the lead frames 13 and 14 are joined to the insulating circuit board 11 and the semiconductor chip 12 (step S3 in FIG. 6), the inclination of the lead frames 13 and 14 and the electrode bonding portions 13c and 14c can be suppressed more stably, and the thickness of the bonding member 15b can be maintained more uniformly.

[0117] [Third Embodiment] In the third embodiment, a case where the lead frames 13 and 14 included in the semiconductor unit 10 of the first embodiment include elastic portions will be described with reference to FIG. 16. FIG. 16 is a diagram showing a first bonding step included in the method of manufacturing a semiconductor device according to the third embodiment. Note that the semiconductor device of the third embodiment can also be manufactured in accordance with the flowchart of FIG. 6 of the first embodiment.

[0118] The semiconductor unit 10 of the third embodiment includes elastic portions 13f and 13g in the lead frame 13 of the semiconductor unit 10 of the first embodiment. The semiconductor unit 10 of the third embodiment has the same configuration as the semiconductor unit 10 of the first embodiment with respect to other configurations. Also, the lead frame 14 of the third semiconductor unit also has the same configuration as the lead frame 13 of the third embodiment.

[0119] Here, the elastic portions 13f and 13g included in the flat linking portions 13d and 13e of the lead frame 13 form a concave shape in which the entire width of the linking portions 13d and 13e is bent in either the +Z direction or the -Z direction in the thickness direction. Note that the elastic portions 13f and 13g are the ranges surrounded by broken lines in FIG. 16. Also, FIG. 16 shows a case where one concave elastic portion 13f and 13g is provided in each of the linking portions 13d and 13e. The number of elastic portions 13f and 13g may be two or more. Also, since the elastic portions 13f and 13g only need to exhibit elasticity in the linking portions 13d and 13e, they may have other shapes instead of necessarily being concave. Note that the lead frame 14 may also include similar elastic portions.

[0120] When the lead frames 13 and 14 include elastic portions in this way, similar to the second embodiment, the electrode bonding portions 13c and 14c may be provided at the positions of the centers of gravity of the lead frames 13 and 14. When bonding the lead frames 13 and 14 to the insulating circuit board 11 and the semiconductor chip 12 (step S3 in FIG. 6), the inclination of the lead frames 13 and 14 and the electrode bonding portions 13c and 14c can be suppressed more stably, and the thickness of the bonding member 15b can be maintained more uniformly.

[0121] Also, when manufacturing a semiconductor device including such a semiconductor unit 10 along the flowchart of FIG. 6, even if the semiconductor unit 10 is externally impacted between the first bonding step of step S3 and the wiring / encapsulation step of step S6, it is alleviated by the elastic portion. Therefore, it is possible to suppress the electrode bonding portions 13c and 14c of the lead frames 13 and 14 from detaching from the semiconductor chip 12.

Explanation of Reference Numerals

[0122] 1 Semiconductor device 2 Semiconductor module 3 Cooling device 10, 10a, 10b, 10c Semiconductor unit 11 Insulating circuit board 11a Insulating plate 11a1, 11a2, 11a3, 11a4 Side surface 11a5, 11a6, 11a7, 11a8 Corner 11b, 11c, 11d Conductive plate 11b1, 11c1 Depression 11b2, 11c2 Support conductive plate 11b3, 11c3 Chip region 11b4, 11c4 Support block portion 11e Metal plate 12 Semiconductor chip 12a Control electrode 12b Main electrode 13, 14 Lead frame 13a, 13b, 14a, 14b, 13b2, 13b3, 14b2, 14b3 Wiring bonding portion 13a1, 13b1, 13c1, 14a1, 14b1 Boss 13c, 14c Electrode bonding portion 13d, 13e, 14d, 14e, 13e2, 13e3, 14e2, 14e3 Linkage portion 13f, 13g Elastic portion 15a, 15b Bonding member 15a1, 15b1 Bonding plate 20 Housing 21 Frame part 21a, 21b, 21c, 21d Outer wall 21e, 21f, 21g Unit storage part 21i Fixing hole 22a, 22b, 22c First connection terminal 23a, 23b, 23c Second connection terminal 24a U-phase output terminal 24b V-phase output terminal 24c W-phase output terminal 25a, 25b, 25c Control terminal 31 Top plate 32 Side wall 33 Cooling bottom plate 33a Inlet 33b Outlet 33d Bottom surface

Claims

1. A semiconductor chip including a main electrode on a front surface, a first conductive plate including a first main surface having a chip region to which the back surface of the semiconductor chip is joined, a second conductive plate provided adjacent to the first conductive plate in a plan view, a support portion provided on the opposite side of the second conductive plate with respect to the chip region and insulated from the first conductive plate, a lead frame including a first joint portion joined to the support portion, a second joint portion joined to the second conductive plate, and an electrode joint portion joined to the main electrode of the semiconductor chip via a joining member, A semiconductor device having the same.

2. The support portion is disposed in an opening region formed in the first conductive plate without contacting the first conductive plate, The semiconductor device according to claim 1.

3. The support portion is made of the same material as the first conductive plate, The semiconductor device according to claim 2.

4. In the lead frame, a first length from the electrode joint portion to the first joint portion is equal to a second length from the electrode joint portion to the second joint portion, The semiconductor device according to claim 1.

5. The lead frame includes a flat first linking portion connecting between the electrode joint portion and the first joint portion, and a flat second linking portion connecting between the electrode joint portion and the second joint portion, A first height from the first joint portion to the first linking portion and a second height from the second joint portion to the second linking portion are each higher than a third height from the electrode joint portion to the first linking portion and a fourth height from the electrode joint portion to the second linking portion, The semiconductor device according to claim 1.

6. In a plan view, the lead frame extends linearly from the electrode joint portion to the first joint portion, The semiconductor device according to claim 1.

7. In a plan view, the lead frame extends linearly from the electrode joint portion to the second joint portion, The semiconductor device according to claim 6.

8. In a plan view, the lead frame extends linearly from the first joint portion to the second joint portion, The semiconductor device according to claim 6.

9. The lead frame includes a plurality of the second joint portions, and in a plan view, extends linearly from the electrode joint portion to each of the plurality of the second joint portions, The semiconductor device according to claim 6.

10. The electrode joint portion corresponds to the position of the center of gravity of the lead frame in a plan view, The semiconductor device according to claim 9.

11. The lead frame includes elastic portions between the electrode bonding portion and the first bonding portion and between the electrode bonding portion and the second bonding portion, respectively. The semiconductor device according to claim 1.

12. The lead frame includes a flat first linking portion connecting between the electrode bonding portion and the first bonding portion, and a flat second linking portion connecting between the electrode bonding portion and the second bonding portion. The elastic portions are respectively provided on the first linking portion and the second linking portion. In each of the elastic portions of the first linking portion and the second linking portion, the entire widths of the first linking portion and the second linking portion are bent in the thickness direction. The semiconductor device according to claim 11.

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