Semiconductor structure

Abstract

To provide a high electron mobility transistor having a novel semiconductor structure that improves a leakage current at gates causing device failure.SOLUTION: A normally-off high electron mobility transistor includes a substrate 100, a semiconductor barrier layer 140, and a gate electrode 180. The semiconductor barrier layer is arranged on the substrate. The gate electrode is arranged on the semiconductor barrier layer, and has a first gate barrier layer 182, a second gate barrier layer 184, and a low-resistance metal layer 186. The first gate barrier layer is arranged between the semiconductor barrier layer and the second gate barrier layer. A work function of the first gate barrier layer is larger than a work function of the semiconductor barrier layer. A work function of the second gate barrier layer is larger than the work function of the first gate barrier layer.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a high electron mobility transistor.

Background Art

[0002] In recent years, the demand for high-frequency and high-power products has been increasing. Semiconductor power devices made of gallium nitride such as aluminum gallium nitride / gallium nitride (AlGaN / GaN) can achieve very high switching speeds due to their wide energy bandgap and fast-moving electrons. In addition, because they operate at high frequencies, high power, and high temperatures, they are widely used especially in high-power semiconductors for radio frequency and power applications. Conventionally, high electron mobility transistors have been made by laminating III-V semiconductors and forming a heterojunction at their interface. Since the energy band of the heterojunction bends, a potential well is formed at the deep part of the bend of the conduction band, and a two-dimensional electron gas (2DEG) is formed in the potential well.

[0003] Generally, a high electron mobility transistor is a normally-on (D-mode) device, or a so-called depletion mode device, which requires a negative bias voltage to turn off the device. In addition to being relatively inconvenient to use, the operating range of the device is also limited. On the other hand, another type of enhancement-mode transistor with high electron mobility has also been proposed. This type of transistor destroys the lattice structure of the gallium aluminum nitride layer by fluorine ion bombardment before forming the metal gate, or performs etching to form a recess in the gallium aluminum nitride layer, or is formed by the gate stack structure of the P-type impurity gallium nitride layer, so it does not require an additional bias voltage to turn off the normally-off (E-mode) device of the two-dimensional electron gas.

[0004] However, in currently common E-mode gallium nitride high electron mobility transistors, when the gate-source drive voltage (Vgs) reaches 7V - 10V, the gate leakage current becomes too high, resulting in hard breakdown of the gate. Therefore, the operating range is limited to 0V - 6V. On the other hand, in common D-mode gallium nitride high electron mobility transistors, the gate leakage current is relatively high and can reach up to about milliamperes. During the operation of the above device, as the gate voltage increases, the gate leakage current also increases. Since the increase in the gate leakage current leads to device failure, it is necessary to effectively control the gate leakage current of the device. To overcome the above problems, developing an innovative semiconductor structure that can improve the gate leakage current causing device failure has become an urgent issue in the industry.

Summary of the Invention

[0005] The main object of the present invention is to provide an innovative semiconductor structure. By increasing the gate breakdown voltage, the voltage operating range of the device is expanded, and the problem of device failure caused by high gate leakage current in conventional high electron mobility transistors is improved.

[0006] To achieve the above object, the present invention provides a semiconductor structure including a substrate, a semiconductor barrier layer, and a gate electrode. The semiconductor barrier layer is disposed on the substrate. The gate electrode is disposed on the semiconductor barrier layer and has a first gate barrier layer and a second gate barrier layer. The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer. The work function of the first gate barrier layer is larger than the work function of the semiconductor barrier layer. The work function of the second gate barrier layer is larger than the work function of the first gate barrier layer.

[0007] In an embodiment of the present invention, the first gate barrier layer is a conductive metal compound having a work function of 4 eV or more.

[0008] In an embodiment of the present invention, the material of the conductive metal compound is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

[0009] In an embodiment of the present invention, the second gate barrier layer is a conductive material having a work function of 5 eV or more.

[0010] In an embodiment of the present invention, the conductive material is one selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

[0011] In an embodiment of the present invention, the semiconductor structure further includes a source electrode and a drain electrode disposed on the semiconductor barrier layer.

[0012] In an embodiment of the present invention, the materials of the source electrode and the drain electrode are one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof.

[0013] In an embodiment of the present invention, the semiconductor barrier layer is a gallium aluminum nitride layer.

[0014] In an embodiment of the present invention, the semiconductor structure further includes a gallium nitride layer, and the aluminum gallium nitride layer is disposed on the gallium nitride layer.

[0015] In an embodiment of the present invention, the semiconductor structure further includes a P-type doped gallium nitride layer disposed between the aluminum gallium nitride layer and the first gate barrier layer, and the work function of the first gate barrier layer is greater than the work function of the P-type doped gallium nitride layer.

[0016] In an embodiment of the present invention, the semiconductor barrier layer under the gate electrode has a recess, and the first gate barrier layer fills the recess.

[0017] In an embodiment of the present invention, a part of the aluminum gallium nitride layer under the gate electrode is doped with fluorine ions.

[0018] In an embodiment of the present invention, the gate electrode further has a low-resistance metal layer disposed on the second gate barrier layer.

[0019] In an embodiment of the present invention, the material of the low-resistance metal layer is one selected from aluminum, platinum, titanium, nickel, tungsten, copper, palladium, gold, or a combination thereof.

[0020] To achieve the above object, the present invention provides a semiconductor structure including a substrate, a semiconductor barrier layer, an anode electrode, and a cathode electrode. The semiconductor barrier layer is disposed on the substrate. The anode electrode and the cathode electrode are disposed at two opposite ends on the semiconductor barrier layer. The anode electrode has a first anode barrier layer and a second anode barrier layer. The first anode barrier layer is disposed between the semiconductor barrier layer and the second anode barrier layer. The work function of the first anode barrier layer is greater than the work function of the semiconductor barrier layer. The work function of the second anode barrier layer is greater than the work function of the first anode barrier layer.

[0021] In an embodiment of the present invention, the first anode barrier layer is a conductive metal compound having a work function of 4 eV or more.

[0022] In an embodiment of the present invention, the material of the conductive metal compound is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

[0023] In an embodiment of the present invention, the second anode barrier layer is a conductive material having a work function of 5 eV or more.

[0024] In an embodiment of the present invention, the conductive material is one selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

[0025] In an embodiment of the present invention, the semiconductor barrier layer is a gallium aluminum nitride layer, and the semiconductor structure further includes a P-type doped gallium nitride layer disposed between the gallium aluminum nitride layer and the first anode barrier layer, and the work function of the first anode barrier layer is greater than the work function of the P-type doped gallium nitride layer.

[0026] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below.

Brief Description of the Drawings

[0027]

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Embodiments for Carrying Out the Invention

[0028] Hereinafter, the content of the present invention will be described through examples. It should be noted that the examples of the present invention are examples of embodiments and are not intended to be limited to the environments, applications, or specific aspects as described in the examples. Therefore, the description of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and the drawings, components not directly related to the present invention are omitted and not shown. The dimensional relationships of the components in the drawings are for facilitating understanding and do not limit the actual dimensions.

[0029] FIG. 1 shows a semiconductor structure and a manufacturing method thereof according to an embodiment of the present invention. In particular, it shows a normally-on or so-called depletion-mode (D-Mode) high electron mobility transistor and a manufacturing method thereof. On a substrate 100, a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140 are sequentially formed. The material of the substrate 100 is silicon, sapphire, diamond, gallium nitride, silicon carbide, gallium arsenide, etc. The nucleation layer 110 is disposed on the substrate 100. The thickness of the nucleation layer 110 is about several tens of nanometers to several hundreds of nanometers, and the lattice mismatch between the substrate 100 and the semiconductor barrier layer 140 can be reduced. The nucleation layer 110 is a group III-V material containing materials such as aluminum nitride, gallium nitride, aluminum gallium nitride, etc. The buffer layer 120 is disposed on the nucleation layer 110, and its thickness is about several micrometers to several tens of micrometers. The buffer layer 120 is made of a group III-V material, and similarly, the lattice mismatch between the substrate 100 and the semiconductor barrier layer 140 can be reduced, and the lattice mismatch can be decreased. In this embodiment, the buffer layer 120 is a single-layer structure or a multi-layer structure. For example, it is a multi-layer super lattice multilayer film, or a group III-V semiconductor single-layer film of aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0030] The channel layer 130 is formed on the buffer layer 120 and has a first energy gap. The semiconductor barrier layer 140 is formed on the channel layer 130 and has a second energy gap. The second energy gap is higher than the first energy gap. The lattice constant of the semiconductor barrier layer 140 is smaller than the lattice constant of the channel layer 130. In this embodiment, the materials of the channel layer 130 and the semiconductor barrier layer 140 are aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), where 0 ≦ x < 1 and 0 ≦ x + y ≦ 1. In this embodiment, the channel layer 130 is a gallium nitride layer. The semiconductor barrier layer 140 is an aluminum gallium nitride layer or an indium gallium nitride layer. Due to the spontaneous polarization in the channel layer 130 and the semiconductor barrier layer 140, and the piezoelectric polarization between the channel layer 130 and the semiconductor barrier layer 140, a two-dimensional electron gas 2DEG is formed at the hetero-junction between the channel layer 130 and the semiconductor barrier layer 140.

[0031] As shown in FIG. 2, a separation and insulation process is performed between the active region and the non-active region of the element. For example, a MESA etching process or an ion implantation process is performed. In this embodiment, ion implantation of nitrogen, argon, boron, oxygen, arsenic, etc. is performed to separate the elements. As shown in FIG. 3, next, an insulating protective layer 150 covering the substrate is formed to define the source region and the drain region. The material of the insulating protective layer 150 is silicon nitride, aluminum nitride, aluminum oxide, silicon dioxide, silicon oxynitride, or silicon carbide. As shown in FIG. 4, a source electrode 160 and a drain electrode 170 that are in ohmic contact with the semiconductor barrier layer 140 are formed on the source region and the drain region on the semiconductor barrier layer 140. Specifically, the source electrode and the drain electrode are made of an alloy material formed by metal evaporation on a gallium aluminum nitride layer, and an ohmic contact is formed by high temperature. The alloy material is one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof. Specifically, the materials of the source electrode and the drain electrode are metal alloys such as titanium / aluminum / nickel / gold, titanium / aluminum / titanium / gold, titanium / aluminum / molybdenum / gold, titanium / aluminum / titanium / titanium nitride.

[0032] Next, as shown in FIG. 5, a gate electrode region is defined in the insulating protection layer 150 such that a part of the semiconductor barrier layer 140 is exposed. A metal vapor deposition process is performed in this gate electrode region, and a gate electrode 180 is formed on a part of the exposed semiconductor barrier layer 140. In order to solve the problem of hard breakdown due to the high leakage current of the gate in a conventional high electron mobility transistor, the present invention suppresses the leakage current of the gate by an innovative gate structure having a double barrier layer. Specifically, the gate electrode 180 according to the present invention has a first gate barrier layer 182 and a second gate barrier layer 184. The first gate barrier layer 182 is disposed on a part of the exposed semiconductor barrier layer 140. The second gate barrier layer 184 is disposed on the first gate barrier layer 182. In particular, the work function of the first gate barrier layer 182 is larger than the work function of the semiconductor barrier layer 140. The work function of the second gate barrier layer 184 is larger than the work function of the first gate barrier layer 182. In a specific embodiment, the first gate barrier layer 182 is a conductive metal compound or a conductive ceramic. The work function of the conductive metal compound is 4 eV or more, but is not limited thereto. The material of the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second gate barrier layer 184 is a conductive material having a work function of 5 eV or more, for example, a metal material having a relatively high work function, but is not limited thereto. The conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. Note that the gate electrode 180 further has a low-resistance metal layer 186 disposed on the second gate barrier layer 184. The material of the low-resistance metal layer is selected from one or a combination of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold.

[0033] FIG. 6 is a graph comparing the gate current and voltage of the normally-on high electron mobility transistor (D-mode HEMT) of the present invention with those of a conventional D-mode HEMT device. In FIG. 6, curve I represents the current and voltage of the conventional D-mode HEMT device. On the other hand, curve II represents the current and voltage of the D-mode HEMT device of the present invention. Comparing the current-voltage curves I and II in FIG. 6, it can be seen that the gate leakage current of the conventional D-mode HEMT device is relatively high, about 1.00E-02 to 1.00E-03 amperes. In contrast, in the present invention, by significantly suppressing the gate leakage current due to the difference in the work function of the double barrier layer of the gate, the gate leakage current of the D-mode HEMT device can be reduced to about one-thousandth, to about 1.00E-05 to 1.00E-07 amperes.

[0034] It should be noted that the above content is described as one of the embodiments of the present invention for a normally-on or so-called depletion-mode high electron mobility transistor. In fact, those skilled in the art can apply the technical features of the gate structure having a double barrier layer of the present invention to a normally-off high electron mobility transistor. This will be described with reference to FIGS. 1, 7, and the above content. Similar to the manufacturing of the D-mode HEMT device, the E-mode HEMT device is manufactured by sequentially forming a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140 on a substrate 100. In this embodiment, the material compositions and formation methods of the substrate 100, the nucleation layer 110, the buffer layer 120, the channel layer 130, and the semiconductor barrier layer 140 can refer to the content disclosed above, and the description thereof will be omitted. Next, a P-type doped semiconductor layer is formed on the semiconductor barrier layer 140. In this embodiment, this P-type doped semiconductor layer is a P-type doped gallium nitride layer 190. Specifically, the gallium nitride layer is doped with a P-type dopant. The P-type dopant is, for example, magnesium, calcium, zinc, beryllium, carbon, or a combination thereof. In a specific embodiment, the P-type doped gallium nitride layer 190 has a thickness of about 1 nm to about 100 nm.

[0035] As shown in FIG. 8, a separation and insulation process between the active region and the inactive region of the element is performed. In this embodiment, as in the previous embodiment, ion implantation such as nitrogen, argon, boron, oxygen, arsenic, etc. is performed by an ion implantation process to separate the elements. Next, as shown in FIG. 9, etching is performed on the P-type doped gallium nitride layer 190 to define a gate structure. As shown in FIG. 10, as in the previous embodiment, an insulating protection layer 150 is formed on the semiconductor barrier layer 140, and a source region and a drain region are defined. In this embodiment, the material composition and formation method of the insulating protection layer 150 can refer to the content disclosed above, and the description thereof is omitted. Next, as shown in FIG. 11, a source electrode 160 and a drain electrode 170 that are ohmic contact with the semiconductor barrier layer 140 are formed in the source region and the drain region on the semiconductor barrier layer 140. The material composition and formation method of the source electrode and the drain electrode can refer to the content disclosed above, and the description thereof is omitted.

[0036] Next, as shown in FIG. 12, a gate electrode region is defined in the insulation protection layer 150 such that a part of the P-type doped gallium nitride layer 190 is exposed. A metal deposition process is performed on this gate electrode region, and a gate electrode 180 is formed on a part of the exposed P-type doped gallium nitride layer 190. In this embodiment, in order to solve the problem of hard breakdown due to the high leakage current of the gate in a conventional high electron mobility transistor, the leakage current of the gate is suppressed by an innovative gate structure having a double barrier layer. Specifically, similar to the previous embodiment, the gate electrode 180 according to the present invention has a first gate barrier layer 182 and a second gate barrier layer 184. The first gate barrier layer 182 is disposed on a part of the exposed P-type doped gallium nitride layer 190. The second gate barrier layer 184 is disposed on the first gate barrier layer 182. In particular, the work function of the first gate barrier layer 182 is greater than the work function of the P-type doped gallium nitride layer 190. The work function of the second gate barrier layer 184 is greater than the work function of the first gate barrier layer 182. In a specific embodiment, the first gate barrier layer 182 is a conductive metal compound or a conductive ceramic. The work function of the conductive metal compound is 4 eV or more, but is not limited thereto. The material of the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second gate barrier layer 184 is a conductive material having a work function of 5 eV or more, for example, a metal material having a relatively high work function, but is not limited thereto. The conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. Note that the gate electrode 180 further has a low-resistance metal layer 186 disposed on the second gate barrier layer 184. The material of the low-resistance metal layer is selected from one of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, gold, or a combination thereof.

[0037] FIG. 13 is a graph comparing the gate current and voltage of the p-type doped gallium nitride enhancement-mode high electron mobility transistor (pGaN E-mode HEMT) of the present invention with those of a conventional pGaN E-mode HEMT device. In FIG. 13, the curve formed by connecting the square-shaped marking points represents the current-voltage curve I of the current and voltage of the conventional pGaN E-mode HEMT device. On the other hand, in FIG. 13, the curve formed by connecting the diamond-shaped marking points represents the current-voltage curve II of the current and voltage of the pGaN E-mode HEMT device according to the present invention. Comparing the current-voltage curves I and II in FIG. 13, it can be seen that when the gate voltage of the conventional pGaN E-mode HEMT device is 7V to 10V, the gate leakage current is too high, so gate hard breakdown occurs. Therefore, the operating range is limited to 0V to 6V. In contrast, in the gate structure according to the present invention, the gate leakage current is suppressed by the difference in the work function of different materials in the double barrier layer, so the gate voltage of the pGaN E-mode HEMT device according to the present invention can be increased from 7V to about 19V, and the operable voltage range of the high electron mobility transistor can be significantly improved.

[0038] Note that the above is only one embodiment of the normally-off high electron mobility transistor of the present invention, and the technical features of the gate structure having a double barrier layer disclosed in the present invention are also applicable to other normally-off HEMT devices. FIG. 14 shows a normally-off HEMT device having a recess gate structure. Specifically, this gate electrode 180 also has a gate structure having a double barrier layer including a first gate barrier layer 182 and a second gate barrier layer 184. However, different from the previous embodiment, there is no P-type doped gallium nitride layer 190 under the gate electrode 180, and there is a recess 142 in the semiconductor barrier layer 140 under the gate electrode 180. The first gate barrier layer 182 is filled in the recess 142 so as to enhance the ability of the gate to control the electron channel. In this embodiment, even in the gate having a double barrier layer with a recess, by utilizing the difference in work functions of different materials of the double barrier layer in the gate structure, the effect of suppressing the gate leakage current can be obtained.

[0039] On the other hand, FIG. 15 shows another normally-off HEMT device to which the present invention is applied. Specifically, similar to the previous embodiment, in the HEMT device of the embodiment shown in FIG. 15, the gate electrode 180 also has a gate structure having a double barrier layer including a first gate barrier layer 182 and a second gate barrier layer 184. A part of the semiconductor barrier layer (i.e., aluminum gallium nitride layer) 140 under the gate electrode 180 is doped with fluorine ions. In this way, the bending of the energy band between the semiconductor barrier layer and the channel layer can be changed, and the gate voltage required to open the electron channel can be adjusted. Note that by utilizing the difference in work functions of different materials of the double barrier layer of the gate, the effect of suppressing the gate leakage current intended by the present invention can be obtained.

[0040] The technical feature of the present invention of suppressing leakage current by means of a multi-layer barrier layer can also be applied to a Schottky Barrier Diode (SBD). Details will be described below. FIG. 16 shows an embodiment of a D-mode SBD device to which the double barrier layer structure of the present invention is applied. This structure has, from bottom to top, a substrate 100, a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140. In this embodiment, the material compositions and formation methods of the substrate 100, the nucleation layer 110, the buffer layer 120, the channel layer 130, and the semiconductor barrier layer 140 can refer to the content disclosed above, and the description thereof will be omitted. As an example of the semiconductor barrier layer 140, a gallium aluminum nitride layer is mentioned. The anode electrode 200 and the cathode electrode 210 are disposed at two opposite ends above the semiconductor barrier layer 140. The anode electrode 200 has a first anode barrier layer 202 and a second anode barrier layer 204. The first anode barrier layer 202 is disposed between the semiconductor barrier layer 140 and the second anode barrier layer 204. The work function of the first anode barrier layer 202 is greater than the work function of the semiconductor barrier layer 140. The work function of the second anode barrier layer 204 is greater than the work function of the first anode barrier layer 202. In a specific embodiment, the first anode barrier layer 202 is a conductive metal compound having a work function of 4 eV or more. The material of the conductive metal compound is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. Note that the second anode barrier layer 204 is a conductive material having a work function of 5 eV or more. The conductive material is one selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. The material of the cathode electrode 210 is one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof.

[0041] FIG. 17 shows an embodiment of an E-mode SBD device to which the double barrier layer structure of the present invention is applied. This example is substantially the same as FIG. 16. This E-mode SBD device further includes a P-type doped gallium nitride layer 220 disposed between a semiconductor barrier layer 140 (i.e., an aluminum gallium nitride layer) and a first anode barrier layer 202. The work function of the first anode barrier layer 202 is greater than the work function of the P-type doped gallium nitride layer 220.

[0042] The above-described examples are for explaining the embodiments of the present invention and for explaining the characteristic configurations of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the scope of the claims.

Description of Reference Numerals

[0043] 100 Substrate 110 Nucleation layer 120 Buffer layer 130 Channel layer 140 Semiconductor barrier layer 142 Concave portion 150 Insulating protection layer 160 Source electrode 170 Drain electrode 180 Gate electrode 182 First gate barrier layer 184 Second gate barrier layer 186 Low-resistance metal layer 190 P-type doped gallium nitride layer 200 Anode electrode 202 First anode barrier layer 204 Second anode barrier layer 210 Cathode electrode 220 P-type doped gallium nitride layer

Claims

1. 1. A semiconductor structure comprising: A substrate; a semiconductor barrier layer disposed on the substrate; a gate electrode disposed on the semiconductor barrier layer and having a first gate barrier layer and a second gate barrier layer; the first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer, the first gate barrier layer having a work function greater than a work function of the semiconductor barrier layer, and the second gate barrier layer having a work function greater than a work function of the first gate barrier layer.

2. 2. The semiconductor structure of claim 1, wherein the first gate barrier layer is a conductive metal compound having a work function of 4 eV or greater.

3. 3. The semiconductor structure of claim 2, wherein the conductive metal compound material is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

4. 3. The semiconductor structure of claim 2, wherein the second gate barrier layer is a conductive material having a work function of 5 eV or greater.

5. 5. The semiconductor structure of claim 4, wherein said conductive material is a member selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

6. 2. The semiconductor structure of claim 1 further comprising source and drain electrodes disposed over said semiconductor barrier layer.

7. 7. The semiconductor structure of claim 6, wherein the material of the source electrode and the drain electrode is one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof.

8. 2. The semiconductor structure of claim 1 wherein said semiconductor barrier layer is an aluminum gallium nitride layer.

9. 10. The semiconductor structure of claim 8 further comprising a gallium nitride layer, said aluminum gallium nitride layer being disposed on said gallium nitride layer.

10. 10. The semiconductor structure of claim 8, further comprising a P-type doped gallium nitride layer disposed between the aluminum gallium nitride layer and the first gate barrier layer, the first gate barrier layer having a work function greater than a work function of the P-type doped gallium nitride layer.

11. 2. The semiconductor structure of claim 1, wherein the semiconductor barrier layer beneath the gate electrode has a recess, and the first gate barrier layer fills the recess.

12. 9. The semiconductor structure of claim 8, wherein a portion of said aluminum gallium nitride layer beneath said gate electrode is doped with fluorine ions.

13. 2. The semiconductor structure of claim 1, wherein said gate electrode further comprises a low resistance metal layer disposed over said second gate barrier layer.

14. 14. The semiconductor structure of claim 13, wherein the material of the low resistance metal layer is one selected from the group consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold, or a combination thereof.

15. 1. A semiconductor structure comprising: A substrate; a semiconductor barrier layer disposed on the substrate; an anode electrode and a cathode electrode having a first anode barrier layer and a second anode barrier layer disposed at two opposite ends on the semiconductor barrier layer; The first anode barrier layer is disposed between the semiconductor barrier layer and the second anode barrier layer, the first anode barrier layer having a work function greater than a work function of the semiconductor barrier layer, and the second anode barrier layer having a work function greater than a work function of the first anode barrier layer.

16. 16. The semiconductor structure of claim 15, wherein the first anode barrier layer is a conductive metal compound having a work function of 4 eV or greater.

17. 17. The semiconductor structure of claim 16, wherein the conductive metal compound material is a member selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

18. 17. The semiconductor structure of claim 16, wherein the second anode barrier layer is a conductive material having a work function of 5 eV or greater.

19. 20. The semiconductor structure of claim 18, wherein said conductive material is a member selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

20. 20. The semiconductor structure of claim 18, wherein the semiconductor barrier layer is an aluminum gallium nitride layer, the semiconductor structure further comprising a P-type doped gallium nitride layer disposed between the aluminum gallium nitride layer and the first anode barrier layer, the first anode barrier layer having a work function greater than a work function of the P-type doped gallium nitride layer.

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