Memory device and operating method thereof

Abstract

To provide a memory device and an operating method thereof capable of improving retention characteristics of the memory device.SOLUTION: The present technology relates to a memory device and an operating method thereof. A memory device 1100 includes: a plurality of memory blocks MB1 to MBk, each of which includes a plurality of memory cells MC1 to MC16; a peripheral circuit 200 for performing background and overwrite operations on a selected memory block selected from the plurality of memory blocks MB1 to MBk; and a control logic 300 that controls the peripheral circuit 200 to perform the background and overwrite operations. The control logic 300 controls the peripheral circuit 200 to execute an overwrite operation that raises a threshold voltage value of the plurality of memory cells in the memory block selected based on the number of effective data stored in the selected memory block to be a set a threshold voltage value or greater.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a memory device and an operation method thereof.

Background Art

[0002] Non-volatile memory devices have relatively slow write and read speeds, but retain stored data even when the power supply is cut off. Therefore, non-volatile memory devices are used to store data that should be retained regardless of the presence or absence of a power supply. Examples of non-volatile memory devices include ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, PRAM (Phase change Random Access Memory), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (registered trademark) (Ferroelectric RAM), and the like. Flash memory is classified into NOR type and NAND type.

[0003] Flash memory has the advantages of RAM, where data can be freely programmed and erased, and ROM, where stored data can be saved even when the power supply is cut off. Flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, PDAs (Personal Digital Assistants), and MP3 players.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a memory device and an operation method thereof that can improve the retention characteristics of the memory device.

Means for Solving the Problems

[0005] The memory device according to an embodiment of the present invention includes a plurality of memory blocks each including a plurality of memory cells, a peripheral circuit for performing a background operation and an overwrite operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit to perform the background operation and the overwrite operation. The control logic controls the peripheral circuit to perform the overwrite operation of setting a threshold voltage of the plurality of memory cells of the selected memory block based on the number of valid data stored in the selected memory block and increasing the threshold voltage to be equal to or higher than a threshold voltage value.

[0006] The operation method of the memory device according to an embodiment of the present invention includes a step of checking the number of valid data stored in a selected memory block, a step of performing a copy-back operation on the selected memory block when the number of valid data is smaller than a set value, and a step of performing an overwrite operation on a selected memory cell corresponding to an erased state or the erased state and at least one programmed state among the memory cells included in the selected memory block.

[0007] The operation method of the memory device according to an embodiment of the present invention includes a step of checking the number of valid data stored in a selected memory block on which a background operation has been performed, a step of determining the selected memory block as an overwrite target memory block based on the number of valid data, a step of performing a copy-back operation of moving and storing the valid data stored in the selected memory block determined as the overwrite target memory block in a target memory block, and a step of performing an overwrite operation of setting a threshold voltage of a selected memory cell corresponding to an erased state or the erased state and at least one programmed state among the memory cells included in the selected memory block after the copy-back operation and increasing the threshold voltage to be equal to or higher than a threshold voltage value.

[0008] The operation method of the memory device according to the embodiment of the present invention includes a step of checking the number of valid data stored in the first memory block among a plurality of memory blocks, and when the number of the checked valid data is less than a set data amount, executing a copy-back operation of storing the valid data stored in the first memory block in the second memory block among the plurality of memory blocks, and executing an overwrite operation of setting the threshold voltage of a large number of memory cells included in the first memory block based on the number of the checked valid data in the first memory block and increasing the threshold voltage to be equal to or higher than a threshold voltage value.

Effect of the Invention

[0009] According to the present technology, an overwrite operation can be executed on a memory block in which the number of valid data is less than the set number, so as to improve the retention characteristics of the memory cells.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

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Figure 6b

Figure 6c

Figure 6d

Figure 6e

Figure 7

Figure 8

Figure 9a

Figure 9b

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Figure 13

Embodiments for Carrying Out the Invention

[0011] Specific structural or functional descriptions of examples according to the concept of the present invention disclosed in this specification or application are merely exemplified for the purpose of explaining examples according to the concept of the present invention. Examples according to the concept of the present invention can be implemented in various forms and should not be construed as being limited to the examples described in this specification or application.

[0012] In the following, in order to explain in detail to the extent that those with ordinary knowledge in the technical field to which the present invention pertains can easily implement the technical idea of the present invention, examples of the present invention will be described with reference to the accompanying drawings.

[0013] FIG. 1 is a drawing for explaining a memory system according to an example of the present invention.

[0014] Referring to FIG. 1, a memory system 1000 may include a memory device 1100 in which data is stored and a memory controller 1200 that controls the memory device 1100 according to the control of a host 2000.

[0015] The host 2000 can communicate with the memory system 1000 using an interface protocol such as PCI-E (Peripheral Component Interconnect-Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), or SAS (serial attached SCSI). Also, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above examples and may be one of other interface protocols such as USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics).

[0016] The memory controller 1200 can overall control the operation of the memory system 1000 and control data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 can control the memory device 1100 in response to a request from the host 2000 to program or read data. According to an embodiment, the memory device 1100 can include DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), or flash memory. The memory controller 1200 can control the memory device 1100 to autonomously execute a background operation regardless of a request from the host 2000. For example, the memory controller 1200 can control the memory device 1100 to execute a read reclaim, garbage collection, or read refresh operation.

[0017] The memory device 1100 can execute a program, read, erase operation, or background operation according to the control of the memory controller 1200.

[0018] If the number of valid data among the data programmed in the selected memory block is less than the set number, or if there is no valid data, the memory device 1100 can perform an overwrite operation on the selected memory block. For example, when the number of valid data among the data programmed in the selected memory block is less than the set number, the memory device 1100 can perform a copy-back operation of reading the program valid data from the selected memory block and programming it to another memory block, and then perform an overwrite operation on the selected memory block. Also, when there is no valid data among the data programmed in the selected memory block, the memory device 1100 can perform an overwrite operation on the selected memory block without performing the above-described copy-back operation. The overwrite operation can be an operation of raising the threshold voltage of the memory cells corresponding to the erased state or the erased state and at least one program state among the memory cells included in the selected memory block to be equal to or higher than a set value. The at least one program state can be a program state with a relatively low threshold voltage distribution among a number of program states.

[0019] FIG. 2 is a diagram for explaining the memory device of FIG. 1.

[0020] Referring to FIG. 2, the memory device 1100 can include a memory cell array 100 in which data is stored. The memory device 1100 can include a peripheral circuit 200 configured to perform a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data.

[0021] The memory device 1100 can include a control logic 300 that controls the peripheral circuit 200 according to the control of a memory controller (1200 in FIG. 1).

[0022] The memory cell array 100 can include a plurality of memory blocks MB1 to MBk (k is a positive integer). Local lines LL and bit lines BL1 to BLm (m is a positive integer) can be connected to each of the memory blocks MB1 to MBk. For example, the local line LL can include a first select line, a second select line, and a plurality of word lines arranged between the first and second select lines. Also, the local line LL can include dummy lines arranged between the first select line and the word lines and between the second select line and the word lines. Here, the first select line can be a source select line, and the second select line can be a drain select line. For example, the local line LL can include word lines, drain and source select lines, and source lines. For example, the local line LL may further include dummy lines. For example, the local line LL may further include pipe lines. According to an embodiment of the present invention, the word lines can be divided into a plurality of groups.

[0023] The local line LL can be connected to each of the memory blocks MB1 to MBk, and the bit lines BL1 to BLm can be commonly connected to the memory blocks MB1 to MBk. The memory blocks MB1 to MBk can be realized in a two-dimensional or three-dimensional structure. For example, in a two-dimensional memory block, pages can be arranged in a direction parallel to the substrate. For example, in a three-dimensional memory block, pages can be arranged in a direction perpendicular to the substrate.

[0024] The peripheral circuit 200 can be configured to execute program, read, and erase operations of a memory block selected according to the control of the control logic 300. Further, the peripheral circuit 200 can perform a copy-back operation of moving and storing valid data stored in the selected memory block to another memory block among a plurality of memory blocks MB1 to MBk included in the memory cell array 100, and an overwrite operation of increasing the threshold voltage of the memory cells included in the selected memory block to be equal to or higher than a set value.

[0025] For example, the peripheral circuit 200 can supply a verification voltage and a pass voltage to the first selection line, the second selection line, and the word line according to the control of the control logic 300, and selectively discharge the first selection line, the second selection line, and the word line, and verify the memory cells connected to the selected word line among the word lines. For example, the peripheral circuit 200 can include a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, and a sensing circuit 260.

[0026] The voltage generating circuit 210 can generate various operation voltages Vop used for program, read, and erase operations in response to the operation signal OP_CMD. Further, the voltage generating circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generating circuit 210 can generate a program voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, and a source line voltage, etc., according to the control of the control logic 300.

[0027] The row decoder 220 can transmit the operating voltage Vop to the local line LL connected to the selected memory block in response to the row address RADD.

[0028] The page buffer group 230 can include a plurality of page buffers PB1 to PBm connected to the bit lines BL1 to BLm. The page buffers PB1 to PBm can operate in response to the page buffer control signals PBSIGNALS. For example, the page buffers PB1 to PBm can temporarily store the data received via the bit lines BL1 to BLm, or can sense the voltage or current of the bit lines BL1 to BLm during a read or verify operation.

[0029] The column decoder 240 can transmit data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 can exchange data with the page buffers PB1 to PBm via the data line DL, or can exchange data with the input / output circuit 250 via the column line CL.

[0030] The input / output circuit 250 can transmit the command CMD and the address ADD transmitted from the memory controller (1200 in FIG. 1) to the control logic 300, or can exchange data DATA with the column decoder 240.

[0031] During a read operation or a verify operation, the sensing circuit 260 can generate a reference current in response to the allowable bit VRY_BIT<#>, compare the sensing voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current, and output a pass signal PASS or a fail signal FAIL.

[0032] The control logic 300 can control the peripheral circuit 200 by outputting an operation signal OP_CMD, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD. Further, the control logic 300 can determine whether a verification operation has passed or failed in response to a pass or fail signal PASS or FAIL.

[0033] The control logic 300 can control the peripheral circuit 200 to perform a program operation or an erase operation on a selected memory block among a plurality of memory blocks MB1 to MBk included in the memory cell array 100.

[0034] The control logic 300 can control the peripheral circuit 200 to perform a copy-back operation of programming valid data stored in a selected memory block to another memory block, that is, a target memory block. After performing the copy-back operation, the control logic 300 can control the peripheral circuit 200 to perform an overwrite operation of programming the memory cells included in the selected memory block to have a threshold voltage equal to or higher than a set value.

[0035] The control logic 300 can include an overwrite management unit 310 for controlling the copy-back operation and the overwrite operation for a selected memory block. The overwrite management unit 310 checks the number of valid data among the data stored in the selected memory block, and if the number of the checked valid data is smaller than a set value, the overwrite management unit 310 can control the peripheral circuit 200 to perform the copy-back operation and the overwrite operation for the selected memory block.

[0036] FIG. 3 is a diagram for explaining the overwrite management unit of FIG. 2.

[0037] Referring to FIG. 3, the overwrite management unit 310 can include a memory block state determination unit 311, a copy-back operation control unit 312, an overwrite operation control unit 313, and a control signal generation unit 314.

[0038] The memory block state determination unit 311 can determine the selected memory block as an overwrite operation target memory block based on the number of valid data among the data stored in the selected memory block. For example, when the number of valid data among the data stored in the selected memory block is less than a set value, the memory block state determination unit 311 can determine the selected memory block as an overwrite operation target memory block. Also, when the number of valid data among the data stored in the selected memory block is the same as or greater than the set value, the memory block state determination unit 311 can determine that the selected memory block is not an overwrite operation target memory block.

[0039] As another example, the memory block state determination unit 311 may determine the selected memory block as an overwrite operation target memory block based on the ratio of valid data among all the data stored in the selected memory block. For example, when the ratio of valid data among all the data stored in the selected memory block is less than a set value, the memory block state determination unit 311 can determine the selected memory block as an overwrite operation target memory block. Also, when the ratio of valid data among all the data stored in the selected memory block is the same as or greater than the set value, the memory block state determination unit 311 can determine that the selected memory block is not an overwrite operation target memory block.

[0040] For example, the memory block state determination unit 311 can count the number of pages in which valid data is stored among the plurality of pages included in the selected memory block, and calculate the number of valid data or the ratio of valid data in the selected memory block.

[0041] When the memory block state determination unit 311 determines that the selected memory block is the memory block to be overwritten and there is at least one piece of valid data, it can generate and output a copy-back activation signal ACT_CB and an overwrite activation signal ACT_OW.

[0042] When the memory block state determination unit 311 determines that the selected memory block is the memory block to be overwritten and determines that there is no valid data, it can deactivate the copy-back activation signal ACT_CB and generate and output only the overwrite activation signal ACT_OW. As a result, the copy-back operation can be skipped.

[0043] The copy-back operation control unit 312 generates and outputs a copy-back control signal CB_CTR corresponding to a read operation for the valid data stored in the selected memory block in response to the copy-back activation signal ACT_CB and a valid data programming operation for storing the read valid data in another memory block other than the selected memory block.

[0044] The overwrite operation control unit 313 generates and outputs an overwrite control signal OW_CTR corresponding to an overwrite operation for increasing the threshold voltage value of the memory cells included in the selected memory block to be equal to or higher than the set value in response to the overwrite activation signal ACT_OW.

[0045] The control signal generation unit 314 can generate an operation signal OP_CMD, a row address RADD, and a page buffer control signal PBSIGNALS so as to execute a read operation for the valid data stored in the selected memory block in response to the copy-back control signal CB_CTR and a valid data programming operation for storing the read valid data in another memory block other than the selected memory block, and output them to the peripheral circuit 200 in FIG. 2.

[0046] The control signal generation unit 314 generates an operation signal OP_CMD, a row address RADD, and a page buffer control signal PBSIGNALS so as to execute an overwrite operation that increases the threshold voltage value of the memory cells included in the memory block selected in response to the overwrite control signal OW_CTR to be equal to or higher than a set value, and can output them to the peripheral circuit 200 in FIG. 2.

[0047] FIG. 4 is a diagram for explaining the memory block in FIG. 2.

[0048] Referring to FIG. 4, the memory block can be connected to a plurality of word lines arranged in parallel with each other between a first selection line and a second selection line. Here, the first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. More specifically, the memory block can include a plurality of memory strings ST connected between bit lines BL1 to BLm and a source line SL. The bit lines BL1 to BLm can be respectively connected to the memory string ST, and the source line SL can be commonly connected to the memory string ST. Since the memory strings ST can be configured to be the same as each other, the memory string ST connected to the first bit line BL1 will be specifically described as an example.

[0049] The memory string ST can include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series with each other between the source line SL and the first bit line BL1. One memory string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and the memory cells MC1 to MC16 may also be included in a number more than that shown in the figure.

[0050] The source of the source selection transistor SST can be connected to the source line SL, and the drain of the drain selection transistor DST can be connected to the first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different memory strings ST can be connected to the source selection line SSL, the gates of the drain selection transistors DST can be connected to the drain selection line DSL, and the gates of the memory cells MC1 to MC16 can be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different memory strings ST can be defined as a page PG. Therefore, the memory block can include as many pages PG as the number of word lines WL1 to WL16.

[0051] The memory cells MC1 to MC16 can be composed of a single level cell (SLC) that stores one data bit, a multi level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quad level cell (QLC) that can store four data bits.

[0052] FIG. 5 is a diagram for explaining an embodiment of a three-dimensionally configured memory block.

[0053] Referring to FIG. 5, the memory cell array 100 can include a plurality of memory blocks MB1 to MBk. In FIG. 5, for ease of understanding, the internal configuration of the first memory block MB1 is illustrated, and the internal configurations of the remaining memory blocks MB2 to MBk are omitted. The second to k-th memory blocks MB2 to MBk can also be configured in the same manner as the first memory block MB1.

[0054] The first memory block MB1 can include a plurality of memory strings ST11 to ST1m, ST21 to ST2m. Each of the plurality of memory strings ST11 to ST1m, ST21 to ST2m can extend along the vertical direction (Z direction). In the first memory block MB1, m memory strings can be arranged in the row direction (X direction). In FIG. 5, although it is illustrated that two memory strings are arranged in the column direction (Y direction), this is for convenience of explanation, and three or more memory strings may be arranged in the column direction (Y direction).

[0055] Each of the plurality of memory strings ST11 to ST1m, ST21 to ST2m can include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0056] The source selection transistor SST of each memory string can be connected between the source line SL and the memory cells MC1 to MCn. The source selection transistors of the memory strings arranged in the same row can be connected to the same source selection line. The source selection transistors of the memory strings ST11 to ST1m arranged in the first row can be connected to the first source selection line SSL1. The source selection transistors of the memory strings ST21 to ST2m arranged in the second row can be connected to the second source selection line SSL2. As another example, the source selection transistors of the memory strings ST11 to ST1m, ST21 to ST2m may be commonly connected to one source selection line.

[0057] The first to nth memory cells MC1 to MCn of each memory string can be connected in series with each other between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn can be respectively connected to the first to nth word lines WL1 to WLn.

[0058] As an example, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding memory string can be stably controlled. Thereby, the reliability of the data stored in the memory block MB1 can be improved.

[0059] The drain selection transistor DST of each memory string can be connected between the bit line and the memory cells MC1 to MCn. The drain selection transistors DST of the memory strings arranged in the row direction can be connected to a drain selection line extending in the row direction. The drain selection transistors DST of the memory strings ST11 to ST1m in the first row can be connected to the first drain selection line DSL1. The drain selection transistors DST of the memory strings ST21 to ST2m in the second row can be connected to the second drain selection line DSL2.

[0060] FIGS. 6a, 6b, 6c, 6d and 6e are diagrams for explaining the phenomenon of the threshold voltage reduction of the memory cell due to holes existing in the region between the memory cells.

[0061] Referring to FIG. 6a, when the memory cell corresponding to the second word line WL2 among the memory cells including the channel CH, the tunnel insulating film Tox, the charge storage film CTN, the blocking insulating film Box, and the gate electrode GA is in the erased state or a programmed state with a relatively low threshold voltage distribution, the charge storage layer CTN can contain a large number of holes (+).

[0062] Referring to FIG. 6b, the large number of holes (+) contained in the charge storage layer CTN of the memory cell programmed to the erased state or a programmed state with a relatively low threshold voltage distribution will diffuse in the direction of the adjacent memory cell as time passes. Thereby, some of the holes (+) can be located inside the charge storage layer CTN between the memory cells.

[0063] Referring to FIG. 6c, when programming a memory cell corresponding to the second word line WL2 to a relatively high program state among a number of program states, electrons (-) in the channel CH can tunnel through the tunnel insulating film Tox and be trapped in the charge storage film CTN of the memory cell corresponding to the second word line WL2.

[0064] Referring to FIG. 6d, a number of electrons (-) contained in the charge storage layer CTN of the memory cell corresponding to the second word line WL2 can diffuse into the charge storage layer CTN between the memory cells by holes (+) present inside the charge storage layer CTN between the memory cells, and the electrons (-) diffused in the charge storage layer CTN between the memory cells and the holes (+) can combine.

[0065] Referring to FIG. 6e, the number of electrons (-) trapped in the charge storage layer CTN of the memory cell corresponding to the second word line WL2 decreases due to the electrons (-) diffused into the charge storage layer CTN between the memory cells, and thereby the threshold voltage of the memory cell corresponding to the second word line WL2 decreases.

[0066] FIG. 7 is a diagram showing the threshold voltage distribution accompanying the degradation of the retention characteristics of the programmed memory cells.

[0067] In an embodiment of the present invention, the threshold voltage distribution of the memory cells programmed in the MLC method is described.

[0068] Referring to FIG. 7, the memory cells included in the selected memory block are programmed to an erase state E and a plurality of program states P1, P2, P3. For example, the memory cells in the erase state E may have a threshold voltage lower than 0V, and the threshold voltage of the memory cells programmed to the first program state P1 may be higher than the first read voltage R1 and lower than the second read voltage R2. Also, the threshold voltage of the memory cells programmed to the second program state P2 may be higher than the second read voltage R2 and lower than the third read voltage R3, and the threshold voltage of the memory cells programmed to the third program state P3 may be higher than the third read voltage R3.

[0069] At least one or more program states with a relatively high threshold voltage distribution among the memory cells, for example, the memory cells programmed to the second program state P2 and the third program state P3, as shown in FIGS. 6a, 6b, 6c, 6d, and 6e described above, the trapped electrons can diffuse in the direction of adjacent memory cells, and the threshold voltage distribution can be downward. As a result, the threshold voltage distribution of some of the memory cells programmed to the second program state P2 can be lower than the second read voltage R2, and the threshold voltage distribution of some of the memory cells programmed to the third program state P3 can be lower than the third read voltage R3, thereby reducing the reliability of the data stored in the programmed memory block.

[0070] FIG. 8 is a flowchart for explaining an operation method of a memory device according to an embodiment of the present invention.

[0071] Referring to FIGS. 2 to 8, an operation method of a memory device according to an embodiment of the present invention will be described as follows.

[0072] In step S810, the memory device 1100 counts the number of valid data in the selected memory block.

[0073] Memory device 1100 can perform a background operation on a selected memory block (e.g., MB1). For example, the background operation can be a read reclaim, garbage collection, or read refresh operation.

[0074] After the background operation on the selected memory block MB1, memory device 1100 counts the number of valid data among the data stored in the selected memory block MB1.

[0075] The memory block state determination unit 311 of the overwrite management unit 310 can count the number of valid data among the data stored in the selected memory block MB1. The memory block state determination unit 311 counts the number of valid data among the data stored in the selected memory block MB1, and determines whether the selected memory block MB1 is a memory block to be overwritten based on the counted number of valid data in the selected memory block MB1. For example, when the number of valid data in the selected memory block MB1 is less than the set value, the memory block state determination unit 311 can determine that the selected memory block MB1 is a memory block to be overwritten. Also, when the number of valid data among the data stored in the selected memory block MB1 is the same as or greater than the set value, the memory block state determination unit 311 can determine that the selected memory block MB1 is not a memory block to be overwritten.

[0076] As another example, the memory block state determination unit 311 can determine that the selected memory block MB1 is the memory block to be overwritten based on the ratio of valid data among all the data stored in the selected memory block MB1. For example, when the ratio of valid data among all the data stored in the selected memory block MB1 is smaller than the set value, the memory block state determination unit 311 can determine that the selected memory block MB1 is the memory block to be overwritten. Also, when the ratio of valid data among all the data stored in the selected memory block MB1 is the same as or larger than the set value, the memory block state determination unit 311 can determine that the selected memory block is not the memory block to be overwritten.

[0077] When the memory block state determination unit 311 determines that the selected memory block is the memory block to be overwritten and there is at least one piece of valid data, it can generate and output a copy-back activation signal ACT_CB and an overwrite activation signal ACT_OW.

[0078] When the memory block state determination unit 311 determines that the selected memory block MB1 is the memory block to be overwritten and determines that there is no valid data, it can generate and output only the overwrite activation signal ACT_OW without generating the copy-back activation signal ACT_CB.

[0079] In step S820, the memory device 1100 programs the valid data of the selected memory block MB1 into a target memory block (for example, MB2) other than the selected memory block MB1.

[0080] When the memory block MB1 selected by the memory block state determination unit 311 is determined to be the memory block to be overwritten, the peripheral circuit 200 reads the valid data stored in the selected memory block MB1 and executes a copy-back operation of programming the read valid data into the target memory block MB2.

[0081] For example, the copy-back operation control unit 312 of the overwrite management unit 310 generates and outputs a copy-back control signal CB_CTR corresponding to a read operation for the valid data stored in the memory block MB1 selected in response to the copy-back activation signal ACT_CB and a valid data programming operation of storing the read valid data in a target memory block MB2 other than the selected memory block MB1. The control signal generation unit 314 generates an operation signal OP_CMD, a row address RADD, and a page buffer control signal PBSIGNALS so as to execute a read operation for the valid data stored in the memory block MB1 selected in response to the copy-back control signal CB_CTR. The peripheral circuit 200 reads the valid data stored in the memory block MB1 selected in response to the operation signal OP_CMD, the row address RADD, and the page buffer control signal PBSIGNALS.

[0082] Also, the control signal generation unit 314 generates an operation signal OP_CMD, a row address RADD, and a page buffer control signal PBSIGNALS so as to execute a programming operation of storing the valid data read in response to the copy-back control signal CB_CTR in the target memory block MB2. The peripheral circuit 200 programs the valid data read in response to the operation signal OP_CMD, the row address RADD, and the page buffer control signal PBSIGNALS into the target memory block MB2.

[0083] Although the memory block MB1 selected by the memory block state determination unit 311 is determined to be the memory block to be overwritten, if it is determined that there is no valid data in the selected memory block MB1, the above-described copy-back operation can be skipped.

[0084] In step S830, the memory device 1100 executes an overwrite operation on the selected memory block MB1.

[0085] The memory cells of the selected memory block MB1 for which the background operation and the copy-back operation have been executed are in an erased state E and a state programmed in a plurality of program states P1 to P3.

[0086] The overwrite operation control unit 313 of the overwrite management unit 310 generates and outputs an overwrite control signal OW_CTR corresponding to the overwrite operation of the selected memory block MB1 in response to the overwrite activation signal ACT_OW.

[0087] The control signal generation unit 314 can output an operation signal OP_CMD, a row address RADD, and a page buffer control signal PBSIGNALS to the peripheral circuit 200 so as to execute an overwrite operation for increasing the threshold voltage value of the memory cells included in the selected memory block MB1 to be equal to or higher than a set value in response to the overwrite control signal OW_CTR.

[0088] For example, the voltage generation circuit 210 generates and outputs a program voltage in response to the operation signal OP_CMD, and the row decoder 220 can transmit the program voltage to the word lines of the selected memory block MB1 based on the row address RADD. Further, the page buffer group 230 can apply a program enable voltage (for example, a ground voltage) to the bit lines BL1 to BLm in response to the page buffer control signal PBSIGNALS.

[0089] The overwrite operation can be executed in the SLC programming method, MLC programming method, TLC programming method, or QLC programming method.

[0090] The overwrite operation can be a programming operation that raises the threshold voltage of memory cells in the erased state E among the memory cells included in the selected memory block MB1 to be equal to or higher than a set value.

[0091] During the overwrite operation, the voltage generation circuit 210 can generate an overwrite program voltage that selectively raises only the threshold voltage of memory cells in the erased state E. The voltage generation circuit 210 can generate the overwrite program voltage a set number of times, and the row decoder 220 can apply the overwrite program voltage to the selected word line or all word lines a set number of times. As another example, the voltage generation circuit 210 can generate the overwrite program voltage for a set time, and the row decoder 220 can apply the overwrite program voltage to the selected word line or all word lines for a set application time.

[0092] As another example, the overwrite operation can be a programming operation that raises the threshold voltages of memory cells in the erased state E and at least one or more program states among the memory cells included in the selected memory block MB1 to be equal to or higher than a set value. The at least one or more program states can be the first program state P1 with the lowest threshold voltage distribution among the plurality of program states P1 to P3.

[0093] During the overwrite operation described above, after applying the overwrite program voltage to the selected word line or all word lines of the selected memory block MB1, the verification operation of checking whether the threshold voltage values of the memory cells included in the selected memory block MB1 are equal to or higher than the set value may be skipped.

[0094] The operations of the memory device 1100 from step S810 to step S830 described above can be executed immediately after the background operation of the selected memory block, and as another example, it may be executed when the memory device 1100 is in the IDLE state.

[0095] FIG. 9a is a diagram showing the threshold voltage distribution of memory cells for explaining the overwrite operation of a memory device according to an embodiment of the present invention.

[0096] Referring to FIG. 9a, memory cells in the erased state E among a plurality of memory cells included in the selected memory block are selectively programmed to the overwrite state OWP.

[0097] The plurality of memory cells can have threshold voltage values corresponding to the erased state E and a plurality of program states P1, P2, P3. For example, the threshold voltage of a memory cell in the erased state E may be lower than 0V, and the threshold voltage of a memory cell programmed to the first program state P1 may be higher than the first read voltage R1 and lower than the second read voltage R2. Also, the threshold voltage of a memory cell programmed to the second program state P2 may be higher than the second read voltage R2 and lower than the third read voltage R3, and the threshold voltage of a memory cell programmed to the third program state P3 may be higher than the third read voltage R3.

[0098] During the overwrite operation, memory cells corresponding to the erased state E among the plurality of memory cells are selectively programmed to increase the threshold voltage. As a result, the threshold voltage of the memory cells corresponding to the erased state E can be increased to the overwrite state OWP. The overwrite state OWP can have a threshold voltage distribution greater than the overwrite reference voltage R_OW. The overwrite reference voltage R_OW may be greater than 0V.

[0099] Among the memory cells included in the memory block selected by the overwrite operation, the memory cells in the erased state E in which holes exist in the charge storage film are programmed to the overwrite state OWP. As a result, as shown in FIG. 6b described above, the phenomenon in which holes diffuse into the region between the memory cells is prevented. Therefore, when the subsequent programming operation of the selected memory block is performed, the problem that the threshold voltage distribution decreases can be improved.

[0100] FIG. 9b is a diagram showing the threshold voltage distribution of memory cells for explaining the overwrite operation of a memory device according to another embodiment of the present invention.

[0101] Referring to FIG. 9b, among the plurality of memory cells included in the selected memory block, the memory cells in the erased state E and at least one programmed state (for example, P1) are selectively programmed to the overwrite state OWP.

[0102] The plurality of memory cells can have threshold voltage values corresponding to the erased state E and the plurality of programmed states P1, P2, P3. For example, the threshold voltage of the memory cell in the erased state E may be lower than 0V, and the threshold voltage of the memory cell programmed to the first programmed state P1 may be higher than the first read voltage R1 and lower than the second read voltage R2. Further, the threshold voltage of the memory cell programmed to the second programmed state P2 may be higher than the second read voltage R2 and lower than the third read voltage R3, and the threshold voltage of the memory cell programmed to the third programmed state P3 may be higher than the third read voltage R3.

[0103] During the overwrite operation, memory cells corresponding to the erase state E and the first program state P1 with relatively low threshold voltage distributions are selectively programmed to increase the threshold voltage. As a result, the threshold voltages of the memory cells corresponding to the erase state E and the first program state P1 can be increased to the overwrite state OWP. The overwrite state OWP can have a threshold voltage distribution greater than the overwrite reference voltage R_OW. The overwrite reference voltage R_OW may be greater than the first read voltage R1.

[0104] Among the memory cells included in the memory block selected by the overwrite operation, the memory cells in the erase state E and the first program state P1 in which holes are present in the charge storage film are programmed to the overwrite state OWP. As a result, as shown in FIG. 6b described above, the phenomenon of holes diffusing into the region between the memory cells is prevented. Therefore, during subsequent program operations of the selected memory block, the problem of the threshold voltage distribution decreasing can be improved.

[0105] FIG. 10 is a diagram for explaining another embodiment of a memory system including the memory device shown in FIG. 2.

[0106] Referring to FIG. 10, the memory system 30000 can be implemented by a cellular phone, a smart phone, a tablet PC, a PDA (personal digital assistant), or a wireless communication device. The memory system 30000 can include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 can control data access operations of the memory device 1100, such as program operations, erase operations, or read operations, according to the control of the processor 3100.

[0107] The data programmed in the memory device 1100 can be output via the display 3200 under the control of the memory controller 1200.

[0108] The radio transceiver 3300 can communicate wireless signals via the antenna ANT. For example, the radio transceiver 3300 can change the wireless signal received via the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signal processed by the processor 3100 into the memory device 1100. Also, the radio transceiver 3300 can change the signal output from the processor 3100 into a wireless signal and output the changed wireless signal to an external device via the antenna ANT. The input device 3400 is a device that can input a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be realized by a pointing device such as a touch pad and a computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200 so that the data output from the memory controller 1200, the data output from the radio transceiver 3300, or the data output from the input device 3400 can be output via the display 3200.

[0109] According to an embodiment, the memory controller 1200 that can control the operation of the memory device 1100 can be realized as a part of the processor 3100, or may be realized on a separate chip from the processor 3100.

[0110] FIG. 11 is a diagram for explaining another embodiment of a memory system including the memory device shown in FIG. 2.

[0111] Referring to FIG. 11, the memory system 40000 can be implemented by a PC (personal computer), a tablet PC, a net-book, an e-reader, a PDA (personal digital assistant), a PMP (portable multimedia player), an MP3 player, or an MP4 player.

[0112] The memory system 40000 can include a memory device 1100 and a memory controller 1200 that can control the data processing operation of the memory device 1100. The memory device 1100 can execute data access operations, such as a program operation, an erase operation, or a read operation, according to the control of the memory controller 1200.

[0113] The processor 4100 can output the data stored in the memory device 1100 via the display 4300 according to the data input via the input device 4200. For example, the input device 4200 can be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0114] The processor 4100 can control the overall operation of the memory system 40000 and can control the operation of the memory controller 1200. The memory controller 1200 that can control the operation of the memory device 1100 according to an embodiment can be implemented as a part of the processor 4100 or can be implemented on a separate chip from the processor 4100.

[0115] FIG. 12 is a diagram for explaining another embodiment of a memory system including the memory device shown in FIG. 2.

[0116] Referring to FIG. 12, the memory system 50000 can be implemented by an image processing device, such as a digital camera, a mobile phone with a digital camera, a smartphone with a digital camera, or a tablet PC with a digital camera.

[0117] The memory system 50000 includes a memory device 1100 and a memory controller 1200 that can control data processing operations of the memory device 1100, such as program operations, erase operations, or read operations.

[0118] The image sensor 5200 of the memory system 50000 can convert an optical image into a digital signal, and the converted digital signal can be transmitted to a processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signal can be output via a display 5300 or stored in the memory device 1100 via the memory controller 1200. Also, the data stored in the memory device 1100 can be output via the display 5300 under the control of the processor 5100 or the memory controller 1200.

[0119] The memory controller 1200 that can control the operation of the memory device 1100 according to an embodiment can be implemented as a part of the processor 5100 or can be implemented on a separate chip from the processor 5100.

[0120] FIG. 13 is a diagram for explaining another embodiment of a memory system including the memory device shown in FIG. 2.

[0121] Referring to FIG. 13, the Memory System 70000 can be implemented by a memory card or a smart card. The Memory System 70000 can include a Memory Device 1100, a Memory Controller 1200, and a Card Interface 7100.

[0122] The Memory Device 1100 can execute data access operations, such as program operations, erase operations, or read operations, according to the control of the Memory Controller 1200.

[0123] The Memory Controller 1200 can control the data exchange between the Memory Device 1100 and the Card Interface 7100. According to an embodiment, the Card Interface 7100 can be, but is not limited to, an SD (secure digital) card interface or an MMC (multi-media card) interface.

[0124] The Card Interface 7100 can interface the data exchange between the HOST 60000 and the Memory Controller 1200 according to the protocol of the HOST 60000. According to an embodiment, the Card Interface 7100 can support the USB (Universal Serial Bus) protocol and the IC (InterChip)-USB protocol. Here, the card interface can mean the hardware that can support the protocol used by the HOST 60000, the software installed on the hardware, or the signal transmission method.

[0125] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 via the card interface 7100 and the memory controller 1200 according to the control of the microprocessor 6100.

[0126] In the detailed description of the present invention, specific embodiments have been described, but various changes are possible within the scope and technical idea of the present invention. Therefore, the scope of the present invention should not be determined only by the above-described embodiments, but should be determined not only by the claims described below, but also by those equivalent to the claims of the present invention.

Explanation of Reference Numerals

[0127] 1000 Memory System 1100 Memory Device 1200 Memory Controller 100 Memory Cell Array 200 Peripheral Circuit 300 Control Logic 210 Voltage Generation Circuit 220 Row Decoder 230 Page Buffer Group 240 Column Decoder 250 Input / Output Circuit 260 Sensing Circuit 310 Overwrite Management Unit 311 Memory Block State Judgment Unit 312 Copyback Operation Control Unit 313 Overwrite Operation Control Unit 314 Control Signal Generation Unit

Claims

1. a plurality of memory blocks each including a plurality of memory cells; a peripheral circuit for performing a background operation and an overwrite operation on a selected memory block among the plurality of memory blocks; control logic for controlling the peripheral circuitry to perform the background operation and the overwrite operation; The control logic controls the peripheral circuit to perform the overwrite operation to raise the threshold voltages of the memory cells of the selected memory block above a set threshold voltage value based on the number of valid data stored in the selected memory block.

2. 2. The memory device of claim 1, wherein the control logic includes an overwrite management unit that checks the number of valid data stored in the selected memory block, and if the checked number of valid data is less than a set value, controls a peripheral circuit to perform a copyback operation and the overwrite operation on the selected memory block.

3. the overwrite management unit counts the number of valid data stored in the selected memory block, and based on the counted number of valid data, determines whether the selected memory block is a target memory block for the overwrite operation, and generates and outputs a copyback activation signal and an overwrite activation signal; a copy-back operation control unit which generates and outputs a copy-back control signal corresponding to a copy-back operation including a read operation for the valid data stored in the selected memory block in response to the copy-back activation signal and a valid data program operation for storing the read valid data in a target memory block other than the selected memory block among the plurality of memory blocks; an overwrite operation control unit for generating and outputting an overwrite control signal corresponding to the overwrite operation for the selected memory block in response to the overwrite activation signal; 3. The memory device of claim 2, further comprising: a control signal generator that generates a control signal for controlling the peripheral circuit in response to the copyback control signal or the overwrite control signal.

4. the memory block state determination unit determines, when the number of valid data stored in the selected memory block is less than a set value, that the selected memory block is a target memory block for the overwrite operation; 4. The memory device of claim 3, wherein if it is determined that the valid data is not stored in the selected memory block, the copyback activation signal is deactivated to skip the copyback operation.

5. 4. The memory device of claim 3, wherein the memory block state determination unit counts the number of valid data by counting the number of pages in which the valid data is stored among a plurality of pages included in the selected memory block.

6. 2. The memory device of claim 1, wherein the peripheral circuitry applies an overwrite program voltage to selected word lines or all word lines of the selected memory block during the overwrite operation.

7. 2. The memory device of claim 1, wherein the peripheral circuit increases the threshold voltage of a memory cell corresponding to an erased state among the plurality of memory cells included in the selected memory block to above the set threshold voltage value during the overwrite operation.

8. 2. The memory device of claim 1, wherein the peripheral circuit increases the threshold voltage of memory cells corresponding to an erased state and at least one programmed state among the plurality of memory cells included in the selected memory block to above the set threshold voltage value during the overwrite operation.

9. 9. The memory device of claim 8, wherein the at least one program state is a program state having a relatively low threshold voltage distribution among a plurality of program states.

10. The memory device of claim 1 , wherein the set threshold voltage value is greater than 0V.

11. checking the number of valid data stored in the selected memory block; performing a copyback operation on the selected memory block if the number of valid data is less than a set value; performing an overwrite operation on selected memory cells corresponding to an erased state or the erased state and at least one programmed state among memory cells included in the selected memory block.

12. 12. The method of claim 11, further comprising: reading the valid data of the selected memory block during the copyback operation; and programming the read valid data to a target memory block other than the selected memory block.

13. 12. The method of claim 11, further comprising skipping the copy-back operation if it is determined that there is no valid data stored in the selected memory block.

14. 12. The method of claim 11, wherein the overwrite operation applies an overwrite program voltage to a selected word line or all word lines of the selected memory block to raise the threshold voltage value of the selected memory cell above a set threshold voltage value.

15. 15. The method of claim 14, wherein the set threshold voltage value is greater than 0V.

16. 15. The method of claim 14, wherein the at least one program state is a program state having a relatively low threshold voltage distribution among a plurality of program states.

17. checking the number of valid data stored in the selected memory block in which the background operation has been performed; determining, based on the number of valid data, that the selected memory block is an overwrite target memory block; performing a copy-back operation of moving and storing the valid data stored in the selected memory block determined as the overwrite target memory block in a target memory block; after the copyback operation, performing an overwrite operation to raise the threshold voltage of selected memory cells corresponding to an erased state or the erased state and at least one programmed state among the memory cells included in the selected memory block to a set threshold voltage value or higher.

18. 20. The method of claim 17, wherein the step of determining that the selected memory block is the memory block to be overwritten comprises determining that the selected memory block is the memory block to be overwritten if the number of valid data is smaller than a set value.

19. 20. The method of claim 17, wherein the overwrite operation applies an overwrite program voltage to a selected word line or all word lines of the selected memory block to raise the threshold voltage value of the selected memory cell above a set threshold voltage value.

20. 20. The method of claim 17, wherein the at least one program state is a program state having a relatively low threshold voltage distribution among a plurality of program states.

21. checking the number of valid data stored in a first memory block among the plurality of memory blocks; performing a copy-back operation to store the valid data stored in the first memory block in a second memory block among the plurality of memory blocks when the number of the checked valid data is less than a set data amount; and performing an overwrite operation to raise the threshold voltages of a number of memory cells included in the first memory block to a set threshold voltage value or higher based on the number of checked valid data in the first memory block.

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