Semiconductor package

Abstract

To improve the accuracy and efficiency of a semiconductor package manufacturing process, and prevent the curvature of a semiconductor package.SOLUTION: A semiconductor package 1 includes: a re-wiring layer 500, a first lower post 331 arranged on the re-wiring layer; a first upper connection post 311 on the first lower post; a second lower post 332 arranged on the re-wiring layer and laterally separated from the first lower post; a second upper connection pot 322 on the second lower post; a bridge structure 700 provided on the re-wiring layer and arranged between the first lower post and the second lower post; a semiconductor element 100 arranged on the first upper connection post and a first region of the bridge structure; a semiconductor chip 200 arranged on the second upper connection post and a second region of the bridge structure and laterally separated from the semiconductor element; and a lower molding film 420 provided on the re-wiring layer, covering side walls of the first and second lower posts and side walls of the second lower post and side walls of the first and second upper connection posts, and directly physically contacting with an underside of the semiconductor element and an underside of the semiconductor chip.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including a redistribution layer.

Background Art

[0002] A semiconductor package is a form in which an integrated circuit chip is embodied in a form suitable for use in an electronic product. Usually, a semiconductor package includes a semiconductor chip mounted on a printed circuit board. The semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. Recently, with the development of the electronics industry, the demand for improving the reliability of semiconductor packages has been increasing.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package with improved reliability.

Means for Solving the Problems

[0005] A semiconductor package according to one aspect of the present invention made to achieve the above object includes a redistribution layer, a first lower post disposed on the redistribution layer, a second lower post disposed on the redistribution layer and laterally spaced from the first lower post, a first upper connection post on the first lower post, a second upper connection post on the second lower post, a bridge structure provided on the redistribution layer and disposed between the first lower post and the second lower post, a semiconductor element disposed on the first upper connection post and a first region of the bridge structure, a semiconductor chip disposed on the second upper connection post and a second region of the bridge structure and laterally spaced from the semiconductor element, and a lower molding film provided on the redistribution layer and covering sidewalls of the first lower post and the second lower post and sidewalls of the first upper connection post and the second upper connection post. The lower molding film physically contacts directly the lower surfaces of the semiconductor element and the semiconductor chip.

[0006] A semiconductor package according to another aspect of the present invention made to achieve the above object includes a first semiconductor chip, a second semiconductor chip laterally spaced from the first semiconductor chip, a first upper connection post provided on a lower surface of the first semiconductor chip and connected to the first semiconductor chip, a second upper connection post provided on a lower surface of the second semiconductor chip and connected to the second semiconductor chip, a first lower post disposed on a lower surface of the first upper connection post, a second lower post disposed on a lower surface of the second upper connection post, a bridge structure provided on lower surfaces of the first semiconductor chip and the second semiconductor chip and laterally spaced from the first lower post and the second lower post, a first molding film covering sidewalls of the first semiconductor chip and the second semiconductor chip and spaced from the first upper connection post and the second upper connection post, and a second molding film provided on a lower surface of the first molding film. The second molding film covers the bridge structure, sidewalls of the first lower post and the second lower post, and sidewalls of the first upper connection post and the second upper connection post.

[0007] A semiconductor package according to still another aspect of the present invention made to achieve the above object includes a package substrate including a lower substrate pad, a substrate wiring, and an upper substrate pad, solder ball terminals disposed on the lower surface of the lower substrate pad, and a rewiring layer disposed on the upper surface of the package substrate and including an insulating layer, a rewiring pattern, a seed pattern, and a rewiring pad. A connecting solder ball provided between the package substrate and the rewiring layer to connect the upper substrate pad and the rewiring pad, a lower post provided on the upper surface of the rewiring layer and including a first lower post and a second lower post that are electrically connected to the rewiring pattern and spaced apart from each other laterally, a first upper connecting post disposed on the first lower post, a second upper connecting post disposed on the second lower post, a bridge structure provided on the upper surface of the rewiring layer and disposed between the first lower post and the second lower post, a chip stack package including a first lower semiconductor chip disposed on the upper surface of the first upper connecting post and a first region of the bridge structure and connected to the first upper connecting post and the bridge structure, a second semiconductor chip disposed on the upper surface of the second upper connecting post and a second region of the bridge structure and connected to the second upper connecting post and the bridge structure and spaced apart from the chip stack package laterally, a first molding film covering the side walls of the chip stack package and the second semiconductor chip, and a second molding film provided on the upper surface of the rewiring layer and covering the side walls of the first lower post and the second lower post and the side walls of the first upper connecting post and the second upper connecting post. The second molding film physically contacts the lower surface of the first molding film, the lower surface of the chip stack package, and the lower surface of the second semiconductor chip. [Effects of the Invention]

[0008] According to the present invention, in the semiconductor package manufacturing process, since the semiconductor element including the first semiconductor chip is stably fixed by the first upper post and the second semiconductor chip is stably fixed by the second upper post, the accuracy of the semiconductor package manufacturing process is improved. Further, since the semiconductor element and the second semiconductor chip are stably fixed, a bridge structure and a redistribution layer can be formed on the lower surface of the semiconductor element and the lower surface of the second semiconductor chip. Thereby, the efficiency of the semiconductor package manufacturing process is improved. Further, since the second molding film contains the same material as the first molding film, warpage of the semiconductor package is prevented.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0011] In this specification, the same reference numerals throughout refer to the same components. A semiconductor package and a method for manufacturing the same according to the concept of the present invention will be described.

[0012] FIG. 1A is a cross-sectional view showing a semiconductor package according to an embodiment. FIG. 1B is a cross-section of an example seen along the line I-I' of FIG. 1A. FIG. 1C is an enlarged view showing an example of the II region of FIG. 1B.

[0013] Referring to FIGS. 1A to 1C, the semiconductor package 1 includes a package substrate 600, solder ball terminals 675, a redistribution layer 500, a first lower post 331, a second lower post 332, a bridge structure 700, first upper posts (311, 317), second upper posts (322, 327), a semiconductor element 100 including a first lower semiconductor chip 110, a second semiconductor chip 200, a first molding film 410, and a second molding film 420.

[0014] The package substrate 600 includes lower substrate pads 620, substrate wirings 630, and upper substrate pads 610. For example, a printed circuit board is used as the package substrate 600. The upper substrate pads 610 and the lower substrate pads 620 are provided on the upper and lower surfaces of the package substrate 600, respectively. The substrate wirings 630 are provided in the package substrate 600 and are connected to the lower substrate pads 620 and the upper substrate pads 610. Thereby, the lower substrate pads 620 are connected to the upper substrate pads 610 through the substrate wirings 630. Being electrically connected to the package substrate 600 means being electrically connected to at least one of the substrate wirings 630. That two components are electrically connected to each other includes direct connection or indirect connection through other components. The lower substrate pads 620, the substrate wirings 630, and the upper substrate pads 610 include metals such as copper, aluminum, tungsten, and / or titanium.

[0015] The first direction D1 is parallel to the upper surface of the package substrate 600. The second direction D2 is parallel to the upper surface of the package substrate 600 and intersects the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1. The third direction D3 is perpendicular to the upper surface of the package substrate 600. The third direction D3 is the vertical direction. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0016] The solder ball terminals 675 are provided on the lower surface of the package substrate 600 and are electrically connected to the lower substrate pads 620. External electrical signals are transmitted to the package substrate 600 through the solder ball terminals 675. The solder ball terminals 675 contain a soldering material. The soldering material includes, for example, tin, silver, bismuth, or an alloy thereof.

[0017] The redistribution layer 500 is disposed on the package substrate 600. The redistribution layer 500 includes an insulating layer 510, a redistribution pattern 530, and a redistribution pad 550. Being electrically connected to the redistribution layer 500 means being electrically connected to any one of the redistribution patterns 530. The redistribution layer 500 includes a plurality of insulating layers 510. The plurality of insulating layers 510 are stacked vertically. "Vertically" means being arranged in the third direction D3. The number of stacked insulating layers 510 varies diversely. As an example, each of the insulating layers 510 contains the same material. The interface between adjacent insulating layers 510 may not be demarcated. The insulating layer 510 includes an organic material such as a photo-imageable dielectric (PID) material. The photosensitive polymer includes, for example, at least one of photosensitive polyimide (PSPI), polybenzoxazole, phenolic polymer, and benzocyclobutene-based polymer.

[0018] The redistribution pattern 530 is provided between the insulating layers 510 and further extends into the insulating layers 510. Some of the redistribution patterns 530 among the redistribution patterns 530 are stacked perpendicular to each other and are electrically connected to each other. The redistribution pattern 530 includes a metal such as, for example, copper and / or a copper alloy.

[0019] The redistribution pads 550 are provided on the lower surface of the redistribution layer 500 and are electrically connected to the redistribution pattern 530. The redistribution pads 550 are laterally spaced apart from each other.

[0020] The semiconductor package 1 further includes connection solder balls 650. The connection solder balls 650 are provided between the package substrate 600 and the redistribution layer 500, and connect the upper substrate pads 610 and the redistribution pads 550. The connection solder balls 650 contain a solder material. The redistribution layer 500 is electrically connected to the solder ball terminals 675 through the connection solder balls 650 and the package substrate 600.

[0021] The semiconductor element 100 is disposed on the redistribution layer 500. The semiconductor element 100 includes a chip stack package. For example, the chip stack package includes a first lower semiconductor chip 110 and a first upper semiconductor chip 120. The first upper semiconductor chip 120 is vertically stacked on the first lower semiconductor chip 110. The first lower semiconductor chip 110 is a logic chip or a controller chip. Being electrically connected to the semiconductor element 100 includes being electrically connected to the first lower semiconductor chip 110. The first upper semiconductor chip 120 is a memory chip. The memory chip includes a High Bandwidth Memory (HBM) chip. The chip stack package is a High Bandwidth Memory (HBM) package. The number of the first upper semiconductor chips 120 is not limited to what is shown and can be variously deformed. For example, the semiconductor element 100 includes a single first upper semiconductor chip 120 or five or more first upper semiconductor chips 120. The semiconductor element 100 further includes an internal molding film 140. The internal molding film 140 is disposed on the upper surface of the first lower semiconductor chip 110 and covers the sidewalls of the first upper semiconductor chip 120.

[0022] The sidewalls of the semiconductor element 100 include the sidewalls of the first lower semiconductor chip 110 and the sidewalls of the internal molding film 140. The lower surface 100b of the semiconductor element 100 corresponds to the lower surface of the first lower semiconductor chip 110. The first lower semiconductor chip 110 includes the first lower pads 105. The first lower pads 105 are provided on the lower surface of the first lower semiconductor chip 110. In this specification, the first lower pads 105 of the semiconductor element 100 correspond to the first lower pads 105 of the first lower semiconductor chip 110. In this specification, the first semiconductor chip refers to the first lower semiconductor chip 110. A specific example of the semiconductor element 100 will be described later with reference to FIG. 6. Hereinafter, in the drawings excluding FIGS. 1B and 6, for the sake of simplicity, the configuration of the semiconductor element 100 excluding the first lower pads 105 is omitted.

[0023] The second semiconductor chip 200 is provided on the redistribution layer 500 and is laterally separated from the semiconductor element 100. For example, the second semiconductor chip 200 is laterally separated from the first lower semiconductor chip 110. That two components are laterally separated means that they are horizontally separated. "Horizontally" means being arranged side by side on the upper surface of the package substrate 600. For example, the second semiconductor chip 200 is separated from the first lower semiconductor chip 110 in the first direction D1 or the opposite direction of the first direction D1.

[0024] The second semiconductor chip 200 is a different type of device from the semiconductor device 100. For example, the function of the second semiconductor chip 200 is different from the functions of the first lower semiconductor chip 110 and the first upper semiconductor chip 120. The second semiconductor chip 200 is a logic chip. The second semiconductor chip 200 is a different type of logic chip from the first lower semiconductor chip 110. For example, the second semiconductor chip 200 includes a Graphics Processing Unit (GPU) or a Central Processing Unit (CPU). The second semiconductor chip 200 includes an integrated circuit and chip pads 205. The integrated circuit is provided within the second semiconductor chip 200 and is disposed adjacent to the lower surface 200b of the second semiconductor chip 200. The chip pads 205 are disposed on the lower surface 200b of the second semiconductor chip 200 and are electrically connected to the integrated circuit. Being electrically connected to the second semiconductor chip 200 means being electrically connected to the integrated circuit through the chip pads 205.

[0025] The first molding film 410 covers the sidewalls of the semiconductor element 100 and the sidewalls of the second semiconductor chip 200. For example, the first molding film 410 covers the sidewalls of the first lower semiconductor chip 110 and the sidewalls of the second semiconductor chip 200. The lower surface 410b of the first molding film 410 is coplanar with the lower surface 100b of the semiconductor element 100 and the lower surface 200b of the second semiconductor chip 200. For example, the lower surface 410b of the first molding film 410 is disposed at substantially the same level as the lower surface 100b of the semiconductor element 100 and the lower surface 200b of the second semiconductor chip 200. The level of a certain component means the vertical level and is the level in the direction parallel to the third direction D3. The level difference between two components is measured in the direction parallel to the third direction D3. That the width, height, and level of a certain component are identical to each other means the identity within the error range that can occur in the process. The first molding film 410 exposes the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200. Different from what is shown, the first molding film 410 may further cover the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200. The first molding film 410 includes an insulating polymer such as an epoxy-based molding compound (EMC).

[0026] The first upper posts (311, 317) are disposed on the lower surface 100b of the semiconductor element 100 and are electrically connected to the semiconductor element 100. For example, the first upper posts (311, 317) are provided on the lower surface of the first lower pad 105 and are connected to the first lower pad 105. The first upper posts (311, 317) contain the same material as each other. The first upper posts (311, 317) contain a metallic material such as copper. The first upper posts (311, 317) further include, but are not limited to, nickel or gold (Au).

[0027] The first upper posts (311, 317) include a first upper connecting post 311 and a first upper bridge post 317. The height H1 of the first upper connecting post 311 is, for example, 5 μm to 10 μm. Since the height H1 of the first upper connecting post 311 is 10 μm or less, the semiconductor package 1 is miniaturized. The first upper bridge post 317 is disposed at a lateral distance from the first upper connecting post 311. The first upper bridge post 317 is disposed adjacent to the second semiconductor chip 200 in a plan view. The height of the first upper bridge post 317 is substantially the same as the height H1 of the first upper connecting post 311. The height of the first upper bridge post 317 is, for example, 5 μm to 10 μm.

[0028] The second upper posts (322, 327) are disposed on the lower surface 200b of the second semiconductor chip 200 and are electrically connected to the second semiconductor chip 200. For example, the second upper posts (322, 327) are provided on the lower surface of the chip pad 205 of the second semiconductor chip 200 and are connected to the chip pad 205. The second upper posts (322, 327) contain the same material as each other. The second upper posts (322, 327) contain a metallic material such as copper. As an example, the second upper posts (322, 327) further contain nickel or gold (Au). The second upper posts (322, 327) contain the same metal as the first upper posts (311, 317). In other examples, the second upper posts (322, 327) contain a metal different from that of the first upper posts (311, 317).

[0029] The second upper posts (322, 327) include a second upper connecting post 322 and a second upper bridge post 327. The height H2 of the second upper connecting post 322 is different from the height H1 of the first upper connecting post 311. In that case, the height H2 of the second upper connecting post 322 is different from the height of the first upper bridge post 317. On the other hand, the height H2 of the second upper connecting post 322 may be the same as or similar to the height H1 of the first upper connecting post 311 and the height of the first upper bridge post 317. The height H2 of the second upper connecting post 322 is, for example, 5 μm to 10 μm. Since the height H2 of the second upper connecting post 322 is 10 μm or less, the semiconductor package 1 is miniaturized.

[0030] The second upper bridge post 327 is disposed laterally spaced from the second upper connecting post 322. The height of the second upper bridge post 327 is substantially the same as the height H2 of the second upper connecting post 322. The height of the second upper bridge post 327 is different from the height H1 of the first upper connecting post 311 and the height of the first upper bridge post 317. On the other hand, the height of the second upper bridge post 327 may be the same as or similar to the height H1 of the first upper connecting post 311 and the height of the first upper bridge post 317. The height of the second upper bridge post 327 is 5 μm to 10 μm.

[0031] The first and second lower posts (331, 332) are provided on the upper surface of the redistribution layer 500 and are electrically connected to the redistribution pattern 530. The first and second lower posts (331, 332) are disposed laterally spaced from each other. The first and second lower posts (331, 332) include copper, titanium, and / or alloys thereof.

[0032] The first and second lower posts (331, 332) include the first lower post 331 and the second lower post 332. The first lower post 331 is disposed between the redistribution layer 500 and the first upper connecting post 311 and is connected to the first upper connecting post 311. The first lower post 331 is vertically overlapped with the semiconductor element 100. The semiconductor element 100 is electrically connected to the redistribution layer 500 via the first upper connecting post 311 and the first lower post 331. The first lower post 331 includes the same metal as the first upper posts (311, 317). For example, the first lower post 331 includes copper or a copper alloy. The height H3 of the first lower post 331 is higher than the height H1 of the first upper connecting post 311 and the height H2 of the second upper connecting post 322. For example, the height H3 of the first lower post 331 is 30 μm to 50 μm. Since the height H3 of the first lower post 331 is 50 μm or less, the semiconductor package 1 is miniaturized.

[0033] The second lower post 332 is disposed laterally spaced apart from the first lower post 331. The second lower post 332 is provided between the redistribution layer 500 and the second upper connection post 322 and is connected to the redistribution layer 500 and the second upper connection post 322. The second lower post 332 is vertically overlapped with the second semiconductor chip 200. The second semiconductor chip 200 is electrically connected to the redistribution layer 500 via the second lower post 332 and the second upper connection post 322.

[0034] The second lower post 332 includes the same metal as the second upper connection post 322 and the second upper bridge post 327. The second lower post 332 includes the same metal as the first lower post 331. For example, the second lower post 332 includes copper or a copper alloy.

[0035] The semiconductor package 1 includes a plurality of first lower posts 331, a plurality of second lower posts 332, a plurality of first upper connection posts 311, and a plurality of second upper connection posts 322. The first upper connection posts 311 are respectively connected to the first lower posts 331. The second upper connection posts 322 are respectively connected to the second lower posts 332.

[0036] Any one of the second lower posts 332 is electrically connected to any one of the first lower posts 331 through the redistribution pattern 530. Thereby, the second semiconductor chip 200 is electrically connected to the semiconductor element 100 through any one of the second lower posts 332, any one of the redistribution patterns 530, and any one of the first lower posts 331. Thereby, the length of the electrical path between the semiconductor element 100 and the second semiconductor chip 200 is reduced.

[0037] The semiconductor element 100 is electrically connected to the package substrate 600 through another first lower post 331 and another rewiring pattern 530. The second semiconductor chip 200 is electrically connected to the package substrate 600 through another second lower post 332 and yet another rewiring pattern 530. Hereinafter, for the sake of simplicity, a single first lower post 331, a single first upper connection post 311, a single second lower post 332, and a single second upper connection post 322 will be described.

[0038] The bridge structure 700 is disposed on the upper surface of the rewiring layer 500. The bridge structure 700 is disposed between the first lower post 331 and the second lower post 332. The bridge structure 700 is laterally spaced from the first lower post 331 and the second lower post 332.

[0039] The bridge structure 700 has a first region and a second region in a plan view. The semiconductor element 100 and the second semiconductor chip 200 are provided on the bridge structure 700. For example, the semiconductor element 100 is provided on the upper surface of the first region of the bridge structure 700. The second semiconductor chip 200 is provided on the upper surface of the second region of the bridge structure 700.

[0040] The bridge structure 700 includes a base substrate 710, bridge wirings 730, and vias 750. The bridge wirings 730 are provided in the bridge structure 700. The bridge wirings 730 are provided on the base substrate 710 and extend horizontally. For example, at least one of the bridge wirings 730 extends in a direction parallel to the first direction D1. The second semiconductor chip 200 is electrically connected to the semiconductor element 100 through the bridge wirings 730. The bridge wirings 730 are spaced apart from each other and insulated from each other. According to the present embodiment, since the bridge structure 700 is provided, the length of the electrical path between the semiconductor element 100 and the second semiconductor chip 200 is further reduced. Thereby, the performance of the semiconductor package 1 is improved. In this specification, a via is a configuration for vertical connection, and a wiring is a configuration for horizontal connection.

[0041] The through via 750 is provided within the bridge structure 700. The through via 750 vertically penetrates the base substrate 710. The through via 750 is separated from and insulated from the bridge wiring 730. When the number of bridge wirings 730 increases beyond a predetermined number, the design and manufacture of the bridge wiring 730 become difficult. According to the present embodiment, the semiconductor element 100 is electrically connected to any one of the redistribution patterns 530 via any one of the through vias 750. The second semiconductor chip 200 is electrically connected to any one of the redistribution patterns 530 through another one of the through vias 750. The second semiconductor chip 200 is electrically connected to the semiconductor element 100 through at least two through vias 750 and any one of the redistribution patterns 530. Thereby, the length of the electrical path between the semiconductor element 100 and the second semiconductor chip 200 is reduced. The second semiconductor chip 200 is electrically connected to the semiconductor element 100 not only through the bridge wiring 730 but also through the through vias 750. According to the present embodiment, even if the number of electrical paths between the semiconductor element 100 and the second semiconductor chip 200 increases, signal transmission between the semiconductor element 100 and the second semiconductor chip 200 is performed relatively quickly. Thereby, the semiconductor package 1 has improved performance and is miniaturized.

[0042] The lower surface of the first lower post 331 and the lower surface of the second lower post 332 are provided at a level lower than the lower surface of the bridge structure 700. Since the height H3 of the first lower post 331 and the height H30 of the second lower post 332 are 30 μm or more, the bridge structure 700 is disposed between the first lower post 331 and the second lower post 332. The height H3 of the first lower post 331 and the height H30 of the second lower post 332 satisfy the conditions, and the semiconductor element 100 and the second semiconductor chip 200 are electrically connected to each other through the bridge structure 700.

[0043] The second molding film 420 is provided between the upper surface of the rewiring layer 500 and the lower surface 410b of the first molding film 410. The second molding film 420 covers the side walls of the first and second lower posts (331, 332), the side walls of the first upper posts (311, 317), and the side walls of the second upper posts (322, 327). The second molding film 420 further covers the bridge structure 700. The second molding film 420 further extends into the gap regions between the bridge structure 700 and the semiconductor element 100, between the bridge structure 700 and the first molding film 410, and between the bridge structure 700 and the second semiconductor chip 200, and covers the side walls of the first and second upper bridge posts (317, 327). The second molding film 420 protects the first and second lower posts (331, 332), the first upper posts (311, 317), the second upper posts (322, 327), and the bridge structure 700. The second molding film 420 physically contacts directly the lower surface 410b of the first molding film 410, the lower surface 100b of the semiconductor element 100, and the lower surface 200b of the second semiconductor chip 200. That is, the semiconductor element 100 and the second semiconductor chip 200 are disposed directly on the upper surface of the second molding film 420.

[0044] According to this embodiment, the second molding film 420 contains the same material as the first molding film 410. For example, the second molding film 420 contains the same epoxy-based molding compound as the first molding film 410. As an example, the composition ratio of the epoxy-based molding compound contained in the second molding film 420 is substantially the same as the composition ratio of the epoxy-based molding compound contained in the first molding film 410. The coefficient of thermal expansion (CTE) of the second molding film 420 is substantially the same as the coefficient of thermal expansion of the first molding film 410. When the semiconductor package 1 operates, the temperature of the semiconductor package 1 changes. If the coefficients of thermal expansion of two components are different from each other, warpage of the semiconductor package 1 occurs due to the difference in the coefficients of thermal expansion between the components. For example, warpage of two components or other components adjacent to the components occurs. According to this embodiment, since the coefficient of thermal expansion of the second molding film 420 is substantially the same as the coefficient of thermal expansion of the first molding film 410, warpage of the semiconductor package 1 is prevented. Thereby, the semiconductor package 1 has improved operating reliability and thermal characteristics.

[0045] Hereinafter, with reference to FIG. 1C, the redistribution layer 500 and the bridge structure 700 will be described in more detail. Hereinafter, descriptions overlapping with the above-described portions will be omitted.

[0046] Referring to FIG. 1C together with FIG. 1B, the redistribution layer 500 is manufactured by a chip first process. Each of the redistribution patterns 530 includes a via portion 530V and a wiring portion 530W. Each wiring portion 530W of the redistribution patterns 530 is provided between the insulating layers 510. Each via portion 530V of the redistribution patterns 530 is provided within the corresponding insulating layer 510. Each via portion 530V of the redistribution patterns 530 is provided on the upper surface of the wiring portion 530W and is connected to the wiring portion 530W without a boundary surface. The width of each wiring portion 530W of the redistribution patterns 530 is wider than the width of the via portion 530V.

[0047] The redistribution layer 500 further includes a seed pattern 535. Each seed pattern 535 is disposed on the upper surface of the corresponding redistribution pattern 530. For example, each of the seed patterns 535 covers the upper surface and sidewalls of the via portion 530V of the corresponding redistribution pattern 530 and the upper surface of the wiring portion 530W. The uppermost seed pattern 535 is provided between the uppermost redistribution pattern 530 and the first and second lower posts (331, 332). The first and second lower posts (331, 332) are respectively disposed on the upper surface of the uppermost seed pattern 535. The seed pattern 535 includes a substance different from that of the redistribution pattern 530. For example, the seed pattern 535 includes a conductive seed substance. The conductive seed substance includes titanium, copper, and / or alloys thereof. The seed pattern 535 functions as a barrier layer to prevent the diffusion of substances contained in the redistribution pattern 530.

[0048] The redistribution pads 550 are provided on the lower surface of the lowermost insulating layer 510 and further extend into the lowermost insulating layer 510. Each lower portion of the redistribution pads 550 is disposed on the lower surface of the lowermost insulating layer 510. Each upper portion of the redistribution pads 550 is disposed within the lowermost insulating layer 510. Each lower portion of the redistribution pads 550 has a wider width than the upper portion, and each lower portion of the redistribution pads 550 is connected to the upper portion.

[0049] The rewiring layer 500 further includes a seed pad 555. The seed pad 555 is provided on the upper surface of the rewiring pad 550 and covers the upper surface of the rewiring pad 550. The seed pad 555 is provided between the lowermost rewiring pattern 530 and the rewiring pad 550 and extends between the lowermost insulating layer 510 and the rewiring pad 550. The seed pad 555 includes a metal material different from that of the rewiring pad 550. The seed pad 555 includes, for example, a conductive seed material.

[0050] The bridge structure 700 includes a base substrate 710, a bridge insulating layer 720, a conductive pad 715, bridge wirings 730, vias 750, and conductive connection portions 751. Being connected to the bridge structure 700 means being connected to at least one of the bridge wirings 730 and the vias 750. The base substrate 710 is, for example, a semiconductor substrate such as a silicon substrate. In other examples, the base substrate 710 includes an organic substrate. The organic substrate includes an insulating polymer. The bridge insulating layer 720 is laminated on the upper surface of the base substrate 710. The bridge insulating layer 720 includes a silicon-based insulating material or an organic insulating material. The silicon-based insulating material includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, and / or a combination thereof. The organic insulating material includes an insulating polymer. The upper surface of the bridge structure 700 includes the upper surface of the uppermost bridge insulating layer 720.

[0051] The conductive pads 715 are provided on the upper surface of the bridge structure 700. The upper surface of the bridge structure 700 further includes the upper surface of the uppermost bridge insulating layer 720. The upper surfaces of the conductive pads 715 are not covered by the bridge insulating layer 720. The conductive pads 715 are arranged laterally spaced apart from each other. For example, any one of the conductive pads 715 (for example, the first conductive pad) is provided on the first region of the bridge structure 700, and the other one of the conductive pads 715 (for example, the second conductive pad) is provided on the second region of the bridge structure 700. The conductive pads 715 include a metal such as copper, aluminum, and / or tungsten.

[0052] The bridge wiring 730 is disposed on the base substrate 710. The bridge wiring 730 is provided between one surface of the bridge insulating layer 720 and is connected to at least two conductive pads 715. For example, the bridge wiring 730 is connected to the first conductive pad and the second conductive pad among the conductive pads 715. The bridge structure 700 further includes a connecting via. The connecting via is disposed between the bridge wiring 730 and the conductive pad 715 and is connected to the bridge wiring 730 and the conductive pad 715. The bridge wiring 730 and the connecting via include a metal such as copper, titanium, and / or tungsten.

[0053] The through via 750 penetrates the base substrate 710. Although not shown, the through via 750 further penetrates the bridge insulating layer 720. The bridge structure 700 further includes a conductive connection portion 751. The conductive connection portion 751 penetrates at least one of the bridge insulating layers 720 and is interposed between the through via 750 and the conductive pad 715. Some of the conductive pads 715 are electrically connected to the through via 750 through the conductive connection portion 751.

[0054] The bridge structure 700 does not include an integrated circuit. Although not shown, the bridge structure 700 may further include passive elements such as capacitors, resistors, and / or inductors.

[0055] The semiconductor package 1 further includes bridge solder balls 670. The bridge solder balls 670 are respectively provided between the bridge structure 700 and the first and second upper bridge posts (317, 327). For example, the bridge solder balls 670 are provided between the conductive pads 715 and the first and second upper bridge posts (317, 327). The bridge solder balls 670 are directly connected to the upper surface of the conductive pads 715 and the lower surfaces of the first and second upper bridge posts (317, 327). The bridge solder balls 670 include a solder material. As an example, the bridge solder balls 670 include a eutectic solder material, but are not limited thereto.

[0056] When the gap fill film covers the side walls of the first and second upper bridge posts (317, 327) and the side wall of the bridge solder ball 670, stress is applied to the first and second upper bridge posts (317, 327) and the bridge solder ball 670. The stress is generated by the difference between the thermal expansion coefficients of the gap fill film and the second molding film 420.

[0057] According to the present embodiment, the second molding film 420 extends into the gap regions between the bridge structure 700 and the semiconductor element 100 and between the bridge structure 700 and the second semiconductor chip 200, and further covers the side walls of the first and second upper bridge posts (317, 327) and the side wall of the bridge solder ball 670. The second molding film 420 further extends into the gap region between the bridge structure 700 and the first molding film 410. The stress applied to the first and second upper bridge posts (317, 327) and the bridge solder ball 670 is prevented or reduced by the second molding film 420.

[0058] The semiconductor package 1 further includes a conductive pattern 755. The conductive pattern 755 is disposed between the redistribution layer 500 and the bridge structure 700. The conductive pattern 755 is disposed, for example, between the through via 750 and the uppermost seed pattern 535 corresponding thereto, and is electrically connected to the through via 750 and the uppermost seed pattern 535. For example, the conductive pattern 755 is in direct contact with the upper surface of the uppermost seed pattern 535. Thereby, the through via 750 is electrically connected to the redistribution pattern 530 via the conductive pattern 755 and the uppermost seed pattern 535. The conductive pattern 755 includes a metallic material such as copper, titanium, and / or an alloy thereof. The second molding film 420 further extends into the gap region between the redistribution layer 500 and the bridge structure 700 and covers the side wall of the conductive pattern 755 and the lower surface of the bridge structure 700. The lower surface of the conductive pattern 755 is provided at substantially the same level as the lower surfaces of the first lower post 331, the second lower post 332, and the second molding film 420.

[0059] Referring again to FIG. 1B, the semiconductor package 1 further includes a lower underfill film 460. The lower underfill film 460 is disposed between the package substrate 600 and the redistribution layer 500 and covers the sidewalls of the connecting solder balls 650. The lower underfill film 460 includes an insulating polymer such as an epoxy-based polymer.

[0060] FIG. 1D is a diagram for explaining a semiconductor package according to an embodiment, and corresponds to a diagram showing an enlarged view of another example of the II region in FIG. 1B.

[0061] Referring to FIG. 1D together with FIG. 1B, an underfill film 470 is further provided. The underfill film 470 is provided in the gap regions between the bridge structure 700 and the semiconductor element 100 and between the bridge structure 700 and the second semiconductor chip 200, and covers the sidewalls of the first and second upper bridge posts (317, 327) and the sidewalls of the bridge solder balls 670. The underfill film 470 further extends into the gap region between the bridge structure 700 and the first molding film 410.

[0062] The second molding film 420 is provided between the upper surface of the redistribution layer 500 and the lower surface 410b of the first molding film 410, and further covers the sidewalls of the underfill film 470. The underfill film 470 includes, but is not limited to, a different material from the second molding film 420. For example, the underfill film 470 includes an insulating polymer such as an epoxy polymer. According to this embodiment, since the underfill film 470 is provided, the space between the first upper bridge post 317 and the second upper bridge post 327 and the space between the bridge solder balls 670 are well filled by the underfill film 470. For example, the formation of voids between the first upper bridge post 317 and the second upper bridge post 327 and between the bridge solder balls 670 is prevented.

[0063] FIG. 2A is a cross-sectional view for explaining another example of a semiconductor package according to an embodiment, and corresponds to a cross-section taken along the line I-I' of FIG. 1A. FIG. 2B is a view showing an enlarged II region of FIG. 1B. Hereinafter, duplicate explanations of the above-described portions are omitted.

[0064] Referring to FIGS. 2A and 2B, the semiconductor package 1A includes a package substrate 600, solder ball terminals 675, a redistribution layer 500, a first lower post 331, a second lower post 332, a bridge structure 700, first upper posts (311, 317), second upper posts (322, 327), a semiconductor element 100, a second semiconductor chip 200, a first molding film 410, and a second molding film 420. The semiconductor element 100 includes a first lower semiconductor chip (110 in FIG. 1B).

[0065] The bridge structure 700 includes a base substrate 710, a bridge insulating layer 720, conductive pads 715, and bridge wirings 730 as described in the example of FIG. 1C. However, unlike FIG. 1C, the bridge structure 700 does not include through vias 750 and conductive connection portions 751. The semiconductor package 1A does not include the conductive pattern 755 described in the example of FIG. 1C. The lower surface of the bridge structure 700 is vertically separated from the redistribution layer 500. The second molding film 420 further fills the gap between the upper surface of the redistribution layer 500 and the lower surface of the bridge structure 700.

[0066] The second semiconductor chip 200 is electrically connected to the semiconductor element 100 via the bridge wiring 730. At this time, the electrical connection between the second semiconductor chip 200 and the semiconductor element 100 via the bridge wiring 730 passes through the first and second upper bridge posts (317, 327) and the bridge solder balls 670.

[0067] The second semiconductor chip 200 is electrically connected to the semiconductor element 100 via the redistribution layer 500. At this time, the electrical connection between the second semiconductor chip 200 and the semiconductor element 100 via the redistribution layer 500 passes through the first and second upper connection posts (311, 322) and the first and second lower posts (331, 332).

[0068] FIG. 3A is a diagram for explaining a first example of a first upper connecting post and a first lower post according to an embodiment, and is a diagram showing an enlarged view of region III in FIG. 2A. Hereinafter, duplicate explanations of the above-described portions are omitted.

[0069] Referring to FIG. 3A, the first lower post 331 contacts the lower surface of the first upper connecting post 311. The width W3 of the first lower post 331 is narrower than the width W1 of the first upper connecting post 311. As a result, the first lower post 331 is separated from a part 311b of the lower surface of the first upper connecting post 311. A part 311b of the lower surface of the first upper connecting post 311 is an edge region of the lower surface of the first upper connecting post 311, but is not limited thereto. The second molding film 420 further covers a part 311b of the lower surface of the first upper connecting post 311.

[0070] FIG. 3B is a diagram for explaining a first example of a second upper connecting post and a second lower post according to an embodiment, and is a diagram showing an enlarged view of region IV in FIG. 2A.

[0071] Referring to FIG. 3B, the second lower post 332 contacts the lower surface of the second upper connecting post 322. The width W30 of the second lower post 332 is narrower than the width W2 of the second upper connecting post 322. As a result, the second lower post 332 is separated from a part 322b of the lower surface of the second upper connecting post 322. A part 322b of the lower surface of the second upper connecting post 322 is an edge region of the lower surface of the second upper connecting post 322, but is not limited thereto. The second molding film 420 further covers a part 322b of the lower surface of the second upper connecting post 322.

[0072] FIG. 3C is a diagram for explaining a second example of a first upper connecting post and a first lower post according to an embodiment, and corresponds to a diagram showing an enlarged view of region III in FIG. 2A.

[0073] Referring to FIG. 3C, the first lower post 331 includes a first seed film 331S and a first metal post 331M. The first seed film 331S is provided between the first metal post 331M and the first upper connection post 311. For example, the first seed film 331S is provided on the lower surface of the first upper connection post 311. The first seed film 331S includes a metal material different from that of the first metal post 331M and the first upper connection post 311. For example, the first seed film 331S includes titanium or a copper-titanium alloy.

[0074] The first metal post 331M is disposed on the lower surface of the first seed film 331S. The first metal post 331M is disposed on the upper surface of the rewiring layer 500. For example, the first metal post 331M is in direct contact with the upper surface of the corresponding uppermost seed pattern 535. Forming the first metal post 331M includes performing a plating process using the first seed film 331S as an electrode. The width of the first metal post 331M is substantially the same as the width of the first seed film 331S. The side wall of the first upper connection post 311 is vertically aligned with the side wall of the first seed film 331S. The first metal post 331M includes the same metal as the first upper connection post 311.

[0075] The height H3 of the first lower post 331 is the same as the sum of the thickness of the first seed film 331S and the height of the first metal post 331M. The thickness of the first seed film 331S is smaller than the height of the first metal post 331M. The width W3 of the first lower post 331 is the same as or smaller than the width W1 of the first upper connection post 311.

[0076] FIG. 3D is a diagram for explaining a second example of a second upper connection post and a second lower post according to an embodiment, and corresponds to a diagram showing an enlarged view of the IV region in FIG. 2A.

[0077] Referring to FIG. 3D, the second lower post 332 includes a second seed film 332S and a second metal post 332M. The second seed film 332S is provided between the second metal post 332M and the second upper connecting post 322. For example, the second seed film 332S is provided on the lower surface of the second upper connecting post 322. The second seed film 332S includes a metal material different from that of the second metal post 332M and the second upper connecting post 322. For example, the second seed film 332S includes titanium or a copper-titanium alloy.

[0078] The second metal post 332M is disposed on the lower surface of the second seed film 332S. The second metal post 332M is disposed between the rewiring layer 500 and the second seed film 332S. For example, the second metal post 332M is in direct contact with the upper surface of the corresponding uppermost seed pattern 535. Forming the second metal post 332M includes performing a plating process using the second seed film 332S as an electrode. The width of the second metal post 332M is substantially the same as the width of the second seed film 332S. The side wall of the second upper connecting post 322 is vertically aligned with the side wall of the second seed film 332S. The width W30 of the second lower post 332 is the same as or smaller than the width W2 of the second upper connecting post 322. The second metal post 332M includes the same metal as the second upper connecting post 322.

[0079] The height H30 of the second lower post 332 is the same as the sum of the thickness of the second seed film 332S and the height of the second metal post 332M. The thickness of the second seed film 332S is smaller than the height of the second metal post 332M.

[0080] FIG. 3E is a diagram for explaining a third example of the first upper connecting post and the first lower post according to an embodiment, and corresponds to a diagram showing an enlarged view of region III in FIG. 2A.

[0081] Referring to FIG. 3E, the first lower post 331 is disposed on the lower surface of the first upper connecting post 311. The width W3' of the first lower post 331 is substantially the same as the width W1 of the first upper connecting post 311. The side walls of the first lower post 331 are vertically aligned with the side walls of the first upper connecting post 311.

[0082] FIG. 3F is a diagram for explaining a third example of a second upper connecting post and a second lower post according to an embodiment, and corresponds to a diagram showing an enlarged view of region IV in FIG. 2A.

[0083] Referring to FIG. 3F, the second lower post 332 is disposed on the lower surface of the second upper connecting post 322. The width W30' of the second lower post 332 is substantially the same as the width W2 of the second upper connecting post 322. The side walls of the second upper connecting post 322 are vertically aligned with the side walls of the second lower post 332.

[0084] FIG. 3G is a diagram for explaining a fourth example of a first upper connecting post and a first lower post according to an embodiment, and corresponds to a diagram showing an enlarged view of region III in FIG. 2A.

[0085] Referring to FIG. 3G, the first lower post 331 is disposed between the upper surface of the rewiring layer 500 and the lower surface of the first upper connecting post 311. The first upper connecting post 311 is offset from the first lower post 331 in the first direction D1 or the opposite direction of the first direction D1. The side walls of the first upper connecting post 311 are offset from the side walls of the first lower post 331 in the first direction D1 or the opposite direction of the first direction D1. The side walls of the first upper connecting post 311 are not vertically aligned with the side walls of the first lower post 331.

[0086] The width W3' of the first lower post 331 is narrower than the width W1 of the first upper connecting post 311. On the other hand, the width W3' of the first lower post 331 can be substantially the same as the width W1 of the first upper connecting post 311.

[0087] FIG. 3H is a diagram for explaining a fourth example of the second upper connection post and the second lower post according to an embodiment, and corresponds to a diagram showing an enlarged view of the IV region in FIG. 2A.

[0088] Referring to FIG. 3H, the second lower post 332 is disposed between the upper surface of the rewiring layer 500 and the lower surface of the second upper connection post 322. The second upper connection post 322 is offset from the second lower post 332 in the first direction D1 or the direction opposite to the first direction D1. The side wall of the second upper connection post 322 is offset from the side wall of the second lower post 332 in the first direction D1 or the direction opposite to the first direction D1. The side wall of the second upper connection post 322 is not aligned perpendicularly to the side wall of the second lower post 332.

[0089] The width W30' of the second lower post 332 is smaller than the width W2 of the second upper connection post 322. On the other hand, the width W30' of the second lower post 332 may be substantially the same as the width W2 of the second upper connection post 322.

[0090] FIG. 4 is a cross-sectional view for explaining still another example of a semiconductor package according to an embodiment, and corresponds to a cross-section taken along the line I-I' in FIG. 1A.

[0091] Referring to FIG. 4, the semiconductor package 1B further includes a heat dissipation structure 800 in the package substrate 600, the solder ball terminals 675, the rewiring layer 500, the first and second lower posts (331, 332), the bridge structure 700, the bridge solder balls 670, the first upper posts (311, 317), the second upper posts (322, 327), the semiconductor element 100, the second semiconductor chip 200, the first molding film 410, and the second molding film 420. The semiconductor element 100 includes a first lower semiconductor chip (110 in FIG. 1B).

[0092] The first molding film 410 does not extend over the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200, and is separated from the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200. For example, the upper surface of the first molding film 410 is coplanar with the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200.

[0093] The heat dissipation structure 800 is disposed over the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200 and physically contacts the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200. The heat dissipation structure 800 further extends over the upper surface of the first molding film 410. The heat dissipation structure 800 includes a material having a high thermal conductivity. Thereby, during the operation of the semiconductor package 1B, the heat generated in the semiconductor element 100 or the second semiconductor chip 200 is quickly released through the heat dissipation structure 800. The semiconductor package 1B exhibits improved thermal characteristics and operating characteristics. The heat dissipation structure 800 absorbs external physical impacts and protects the semiconductor element 100 and the second semiconductor chip 200.

[0094] The heat dissipation structure 800 includes a heat sink. The heat sink includes a heat slug or a heat sink. The heat sink includes a metal (e.g., copper and / or aluminum, etc.) or a carbon-containing material (e.g., graphene, graphite, and / or carbon nanotubes, etc.). As an example, a single metal layer or a plurality of stacked metal layers are used as the heat dissipation structure 800.

[0095] The heat dissipation structure 800 further includes a thermal interface material (TIM) layer. The thermal interface material layer is disposed between the semiconductor element 100 and the heat sink, and between the second semiconductor chip 200 and the heat sink. The thermal interface material layer further extends between the first molding film 410 and the heat sink. The thermal interface material layer includes, for example, a polymer and thermally conductive particles. The thermally conductive particles are dispersed in the polymer. The thermally conductive particles include a metal. The thermal interface material layer has a thermal conductivity greater than that of air. Due to the provision of the thermal interface material layer, the heat generated in the semiconductor element 100 and the second semiconductor chip 200 is more smoothly transmitted to the heat sink through the thermal interface material layer.

[0096] The heat dissipation structure 800 has conductivity and further functions as an electromagnetic wave shielding layer. For example, the heat dissipation structure 800 shields electromagnetic interference (EMI) of the semiconductor element 100 and the second semiconductor chip 200.

[0097] The heat dissipation structure 800 further extends on the sidewalls of the first molding film 410 and the sidewalls of the second molding film 420. The heat dissipation structure 800 is grounded through the redistribution layer 500 or the package substrate 600 to prevent electrical damage to the semiconductor element 100 or the second semiconductor chip 200 due to electrostatic discharge (ESD).

[0098] FIG. 5A is a diagram for explaining a first example of a first upper connection post and a first upper bridge post according to an embodiment, and corresponds to an enlarged view of the V region in FIG. 4. Hereinafter, redundant descriptions of the above-described portions are omitted. In the description of FIGS. 5A to 5F, for simplicity, a single bridge solder ball is described.

[0099] Referring to FIG. 5A in conjunction with FIG. 4, the first upper connecting post 311 includes a first connecting conductive post 311A. The first connecting conductive post 311A is disposed on the lower surface of any one of the first lower pads 105. The first connecting conductive post 311A is in direct contact with the lower surface of any one of the first lower pads 105. The first connecting conductive post 311A includes copper or a copper alloy. The first lower post 331 is in direct contact with the lower surface of the first connecting conductive post 311A. The height H1 of the first upper connecting post 311 is the same as the height of the first connecting conductive post 311A.

[0100] The first upper bridge post 317 includes a first bridge conductive post 317A. The first bridge conductive post 317A is disposed on the lower surface of another one of the first lower pads 105. The first bridge conductive post 317A is in direct contact with the lower surface of another one of the first lower pads 105. The bridge solder ball 670 is in direct contact with the lower surface of the first bridge conductive post 317A. The first bridge conductive post 317A is formed by a single process with the first connecting conductive post 311A. The height and material of the first bridge conductive post 317A are substantially the same as the height and material of the first connecting conductive post 311A.

[0101] FIG. 5B is a diagram for explaining a second example of the first upper connecting post and the first upper bridge post according to an embodiment, and corresponds to an enlarged view of the V region in FIG. 4.

[0102] Referring to FIG. 5B, the first upper connecting post 311 includes a first connecting conductive post 311A and a first connecting metal layer 311B. The first connecting conductive post 311A is in direct contact with the lower surface of any one of the first lower pads 105. The first connecting conductive post 311A includes the material described in the example of FIG. 5A.

[0103] The first connecting metal layer 311B is disposed on the lower surface of the first connecting conductive post 311A. The first connecting metal layer 311B contains a metal different from that of the first connecting conductive post 311A and the first lower post 331. For example, the first connecting metal layer 311B contains nickel or a nickel alloy. The first connecting metal layer 311B functions as a barrier film. The first connecting metal layer 311B prevents the metal contained in the first connecting conductive post 311A from moving. The first lower post 331 is in direct contact with the lower surface of the first connecting metal layer 311B.

[0104] The height H1 of the first upper connecting post 311 is the same as the sum of the thickness of the first connecting metal layer 311B and the height of the first connecting conductive post 311A. The thickness of the first connecting metal layer 311B is smaller than the height of the first connecting conductive post 311A.

[0105] The first upper bridge post 317 includes a first bridge conductive post 317A and a first bridge metal layer 317B. The first bridge conductive post 317A is in direct contact with the lower surface of another one of the first lower pads 105.

[0106] The first bridge metal layer 317B is disposed on the lower surface of the first bridge conductive post 317A. The first bridge metal layer 317B is formed in a single process with the first connecting metal layer 311B. The height and material of the first bridge metal layer 317B are substantially the same as the height and material of the first connecting metal layer 311B. For example, the first bridge metal layer 317B contains nickel or a nickel alloy. The first bridge metal layer 317B functions as a barrier film. The first bridge metal layer 317B prevents the movement of the metal contained in the first bridge conductive post 317A. For example, the first bridge metal layer 317B prevents the metal contained in the first bridge conductive post 317A from moving into the bridge solder ball 670. The first bridge conductive post 317A is separated from the bridge solder ball 670 by the first bridge metal layer 317B.

[0107] The height of the first upper bridge post 317 is the same as the sum of the thickness of the corresponding first bridge metal layer 317B and the height of the first bridge conductive post 317A. The thickness of the first bridge metal layer 317B is smaller than the height of the first bridge conductive post 317A.

[0108] FIG. 5C is a diagram for explaining a third example of the first upper connection post and the first upper bridge post according to an embodiment, and corresponds to an enlarged view of the V region in FIG. 4.

[0109] Referring to FIG. 5C, the first upper connection post 311 includes a first connection conductive post 311A, a first connection metal layer 311B, and a first connection bonding layer 311C. The first connection conductive post 311A and the first connection metal layer 311B are similar to those described in the example of FIG. 5B.

[0110] The first connection bonding layer 311C is disposed on the lower surface of the first connection metal layer 311B. The first connection bonding layer 311C includes a metal substance different from the first connection conductive post 311A, the first connection metal layer 311B, and the first lower post 331. For example, the first connection bonding layer 311C includes gold (Au) or a gold (Au) alloy. The first connection bonding layer 311C prevents oxidation of the first upper connection post 311. For example, the first connection bonding layer 311C prevents oxidation of the first connection metal layer 311B or the first connection conductive post 311A. The thickness of the first connection bonding layer 311C is smaller than the thickness of the first connection metal layer 311B and the height of the first connection conductive post 311A. The height H1 of the first upper connection post 311 is the same as the sum of the height of the first connection conductive post 311A, the thickness of the first connection metal layer 311B, and the thickness of the first connection bonding layer 311C. The first lower post 331 is in direct contact with the lower surface of the first connection bonding layer 311C.

[0111] The first upper bridge post 317 includes a first bridge conductive post 317A and a first bridge metal layer 317B, but does not include a first bridge bonding layer. The material and height of the first bridge conductive post 317A are substantially the same as the material and height of the first connecting conductive post 311A. The material and thickness of the first bridge metal layer 317B are substantially the same as the material and thickness of the first connecting metal layer 311B. For example, the lower surface of the first bridge metal layer 317B is disposed at substantially the same level as the lower surface of the first connecting metal layer 311B.

[0112] The bridge solder ball 670' is in direct contact with the lower surface of the first bridge metal layer 317B. The bridge solder ball 670' further includes the same metal as the first connecting bonding layer 311C in addition to the solder material. For example, the bridge solder ball 670' includes a solder material and gold (Au). In the reflow process of the bridge solder ball 670', the metal in the first bridge bonding layer (not shown) of the first upper bridge post 317 moves into the bridge solder ball 670' to form an intermetallic compound (IMC) with the solder material. As a result, after the reflow process, the first bridge bonding layer of the first upper bridge post 317 does not remain. The height of the first upper bridge post 317 is the same as the sum of the height of the first bridge conductive post 317A and the thickness of the first bridge metal layer 317B.

[0113] FIG. 5D is a diagram for explaining a first example of a second upper connecting post and a second upper bridge post according to an embodiment, and corresponds to an enlarged view of the VI region in FIG. 4.

[0114] Referring to FIG. 5D, the second upper connecting post 322 includes a second connecting conductive post 322A. The second connecting conductive post 322A is disposed on the lower surface of any one of the chip pads 205. The second connecting conductive post 322A is in direct contact with the lower surface of any one of the chip pads 205. The second connecting conductive post 322A includes copper or a copper alloy. The second lower post 332 is in direct contact with the lower surface of the second connecting conductive post 322A. The height H2 of the second upper connecting post 322 is the same as the height of the second connecting conductive post 322A.

[0115] The second upper bridge post 327 includes a second bridge conductive post 327A. The second bridge conductive post 327A is disposed on the lower surface of another one of the chip pads 205. The second bridge conductive post 327A is in direct contact with the lower surface of another one of the chip pads 205. The bridge solder ball 670 is in direct contact with the lower surface of the second bridge conductive post 327A. The second bridge conductive post 327A is formed in a single process with the second connecting conductive post 322A. The height and material of the second bridge conductive post 327A are substantially the same as the height and material of the second connecting conductive post 322A.

[0116] FIG. 5E is a diagram for explaining a second example of the second upper connecting post and the second upper bridge post according to an embodiment, and corresponds to an enlarged view of the VI region in FIG. 4.

[0117] Referring to FIG. 5E, the second upper connecting post 322 includes a second connecting conductive post 322A and a second connecting metal layer 322B. The second connecting conductive post 322A is in direct contact with the lower surface of the chip pad 205. The second connecting conductive post 322A includes the material described in the example of FIG. 5D.

[0118] The second connecting metal layer 322B is disposed on the lower surface of the second connecting conductive post 322A. The second connecting metal layer 322B includes a metal different from that of the second connecting conductive post 322A and the second lower post 332. For example, the second connecting metal layer 322B includes nickel or a nickel alloy. The second connecting metal layer 322B functions as a barrier film. The second connecting metal layer 322B prevents the metal contained in the second connecting conductive post 322A from moving. The second lower post 332 is in direct contact with the lower surface of the second connecting metal layer 322B.

[0119] The height H2 of the second upper connecting post 322 is the same as the sum of the thickness of the second connecting metal layer 322B and the height of the second connecting conductive post 322A. The thickness of the second connecting metal layer 322B is smaller than the height of the second connecting conductive post 322A.

[0120] The second upper bridge post 327 includes a second bridge conductive post 327A and a second bridge metal layer 327B. The second bridge conductive post 327A is in direct contact with the lower surface of another one chip pad 205.

[0121] The second bridge metal layer 327B is disposed on the lower surface of the second bridge conductive post 327A. The second bridge metal layer 327B is formed by a single process with the second connecting metal layer 322B. The height and material of the second bridge metal layer 327B are substantially the same as the height and material of the second connecting metal layer 322B. For example, the second bridge metal layer 327B includes nickel or a nickel alloy. The second bridge metal layer 327B functions as a barrier film. The second bridge metal layer 327B prevents the movement of the metal contained in the second bridge conductive post 327A. For example, the second bridge metal layer 327B prevents the metal contained in the second bridge conductive post 327A from moving into the bridge solder ball 670. The second bridge conductive post 327A is separated from the bridge solder ball 670 by the second bridge metal layer 327B.

[0122] The height of the second upper bridge post 327 is the same as the sum of the thickness of the corresponding second bridge metal layer 327B and the height of the second bridge conductive post 327A. The thickness of the second bridge metal layer 327B is smaller than the height of the second bridge conductive post 327A.

[0123] FIG. 5F is a diagram for explaining a third example of the second upper connection post and the second upper bridge post according to an embodiment, and corresponds to an enlarged view of the VI region in FIG. 4.

[0124] Referring to FIG. 5F, the second upper connection post 322 includes a second connection conductive post 322A, a second connection metal layer 322B, and a second connection bonding layer 322C. The second connection conductive post 322A and the second connection metal layer 322B are similar to those described in the example of FIG. 5E.

[0125] The second connection bonding layer 322C is disposed on the lower surface of the second connection metal layer 322B. The second connection bonding layer 322C includes a metal substance different from the second connection conductive post 322A, the second connection metal layer 322B, and the second lower post 332. For example, the second connection bonding layer 322C includes gold (Au) or a gold (Au) alloy. The second connection bonding layer 322C prevents oxidation of the second upper connection post 322. For example, the second connection bonding layer 322C prevents oxidation of the second connection metal layer 322B or the second connection conductive post 322A. The thickness of the second connection bonding layer 322C is smaller than the thickness of the second connection metal layer 322B and the height of the second connection conductive post 322A. The height H2 of the second upper connection post 322 is the same as the sum of the height of the second connection conductive post 322A, the thickness of the second connection metal layer 322B, and the thickness of the second connection bonding layer 322C. The second lower post 332 is in direct contact with the lower surface of the second connection bonding layer 322C.

[0126] The second upper bridge post 327 includes a second bridge conductive post 327A and a second bridge metal layer 327B, but does not include a second bridge bonding layer. The material and height of the second bridge conductive post 327A are substantially the same as the material and height of the second connecting conductive post 322A. The material and thickness of the second bridge metal layer 327B are substantially the same as the material and thickness of the second connecting metal layer 322B. For example, the lower surface of the second bridge metal layer 327B is disposed at substantially the same level as the lower surface of the second connecting metal layer 322B.

[0127] The bridge solder ball 670’ is in direct contact with the lower surface of the second bridge metal layer 327B. The bridge solder ball 670’ further includes the same metal as the second connecting bonding layer 322C in addition to the solder material. For example, the bridge solder ball 670’ includes a solder material and gold (Au). In the reflow process of the bridge solder ball 670’, the metal in the second bridge bonding layer (not shown) of the second upper bridge post 327 moves into the bridge solder ball 670’ to form an intermetallic compound (IMC) with the solder material. As a result, after the reflow process, the second bridge bonding layer of the second upper bridge post 327 does not remain. The height of the second upper bridge post 327 is the same as the sum of the height of the second bridge conductive post 327A and the thickness of the second bridge metal layer 327B.

[0128] Embodiments of the present invention are combined with each other. For example, at least two of the embodiments of FIGS. 1A to 1D, the embodiment of FIG. 1E, the embodiments of FIGS. 2A and 2B, the embodiment of FIG. 3A, the embodiment of FIG. 3B, the embodiment of FIG. 3D, the embodiment of FIG. 3E, the embodiment of FIG. 4, the embodiment of FIG. 5A, the embodiment of FIG. 5B, the embodiment of FIG. 5C, the embodiment of FIG. 5D, the embodiment of FIG. 5E, and the embodiment of FIG. 5F are combined with each other. For example, the first upper connection post 311 includes the first connection conductive post 311A as shown in FIG. 5A, and the second upper connection post 322 includes the first connection conductive post 311A and the first connection metal layer 311B as shown in FIG. 5E. In another example, the first upper connection post 311 includes the first connection conductive post 311A and the first connection metal layer 311B as shown in FIG. 5B, and the first lower post 331 includes the first metal post 311M and the first seed film 331S as shown in FIG. 3B. As yet another example, the semiconductor package 1B of FIG. 4 further includes an underfill film 470 as shown in FIG. 1D in the heat dissipation structure 800.

[0129] FIG. 6 is a cross-sectional view for explaining a semiconductor element according to an embodiment. Hereinafter, the content overlapping with the part described in FIG. 1B described above is omitted.

[0130] Referring to FIG. 6, the semiconductor element 100 includes a chip stack or a chip stack package. For example, the semiconductor element 100 includes a first lower semiconductor chip 110 and a first upper semiconductor chip 120. The semiconductor element 100 further includes an internal molding film 140.

[0131] The first lower semiconductor chip 110 includes a first integrated circuit (not shown), a first lower pad 105, a first through-structure 113, and a first upper pad 111. The first lower pad 105 and the first upper pad 111 are disposed on the lower surface and the upper surface of the first lower semiconductor chip 110, respectively. The first through-structure 113 penetrates the first lower semiconductor chip 110. The first upper pad 111 is electrically connected to the first lower pad 105 through the first through-structure 113. The first integrated circuit is provided within the first lower semiconductor chip 110 and is electrically connected to the first lower pad 105, the first through-structure 113, and the first upper pad 111. The first lower pad 105, the first through-structure 113, and the first upper pad 111 include metals such as copper, aluminum, tungsten, nickel, titanium, and their alloys. The width of the first lower semiconductor chip 110 is wider than the width of the first upper semiconductor chip 120.

[0132] Each of the first upper semiconductor chips 120 includes a second integrated circuit, a second lower pad 125, a second through-structure 123, and a second upper pad 121. However, the uppermost chip among the first upper semiconductor chips 120 includes the second lower pad 125 but does not include the second through-structure 123 and the second upper pad 121.

[0133] The second lower pad 125 is disposed on the lower surface of the first upper semiconductor chip 120. The second upper pad 121 is disposed on the upper surface of the first upper semiconductor chip 120. The second through-structure 123 penetrates the first upper semiconductor chip 120. In each of the first upper semiconductor chips 120, the second upper pad 121 is electrically connected to the second lower pad 125 through the second through-structure 123. The first upper semiconductor chip 120 includes the second integrated circuit therein. In each of the first upper semiconductor chips 120, the second integrated circuit is electrically connected to the second lower pad 125, the second through-structure 123, and the second upper pad 121. The second lower pad 125, the second through-structure 123, and the second upper pad 121 include metals such as copper, aluminum, tungsten, nickel, titanium, and their alloys.

[0134] The semiconductor device 100 further includes bumps 150. Some of the bumps 150 are disposed between the first lower semiconductor chip 110 and the lowermost first upper semiconductor chip 120 and are connected to the first upper pad 111 and the second lower pad 125. Some other bumps 150 are disposed between the first upper semiconductor chips 120 and are connected to the second upper pad 121 and the corresponding second lower pad 125. The bumps 150 contain a solder material. Although not shown, the bumps 150 further include a pillar pattern. The pillar pattern contains a metal such as copper, for example.

[0135] The semiconductor device 100 further includes an insulating film 160. The insulating film 160 is disposed between the first lower semiconductor chip 110 and the lowermost first upper semiconductor chip 120 and between the first upper semiconductor chips 120. The insulating film 160 covers the sidewalls of the corresponding bumps 150. The insulating film 160 includes, but is not limited to, a non-conductive film (NCF).

[0136] The internal molding film 140 is disposed on the upper surface of the first lower semiconductor chip 110 and covers the sidewalls of the first upper semiconductor chips 120. The internal molding film 140 includes an insulating polymer such as an epoxy-based molding compound. Different from what is shown, if the insulating film 160 is omitted, the internal molding film 140 can further extend between the first lower semiconductor chip 110 and the lowermost first upper semiconductor chip 120 and between the first upper semiconductor chips 120 to further cover the sidewalls of the bumps 150.

[0137] As another example, the semiconductor device 100 does not include the bumps 150 and the insulating film 160. The first lower and upper semiconductor chips (110, 120) are directly bonded to each other. For example, the first lower semiconductor chip 110 and the lowermost first upper semiconductor chip 120 are directly bonded to each other. The adjacent first upper semiconductor chips 120 are directly bonded to each other.

[0138] Figures 7A to 7K are diagrams for explaining the manufacturing process of a semiconductor package according to an embodiment. Hereinafter, descriptions overlapping with the above-described parts are omitted. In some steps, the semiconductor element and the second semiconductor chip may be inverted so that the upper surfaces of the semiconductor element and the second semiconductor chip face downward, but for the sake of uniformity, they are illustrated so that the upper surfaces of the semiconductor element and the second semiconductor chip face upward. Some steps will be described later. Although it corresponds to FIGS. 7D to 7J, it is not limited thereto.

[0139] Referring to FIG. 7A, a semiconductor element 100 provided with first upper posts (311, 317) is prepared. The first upper posts (311, 317) are formed on the lower surface of the first lower pads 105 of the semiconductor element 100. The first upper posts (311, 317) include a first upper connection post 311 and a first upper bridge post 317. The first upper bridge post 317 is formed in a single process with the first upper connection post 311. The material and height of the first upper bridge post 317 are substantially the same as the material and height H1 of the first upper connection post 311, respectively. The height H1 of the first upper connection post 311 is, for example, 5 μm to 10 μm. The height of the first upper bridge post 317 is 5 μm to 10 μm.

[0140] A second semiconductor chip 200 provided with second upper posts (322, 327) is prepared. The second upper posts (322, 327) are formed on the lower surface of the chip pads 205 of the second semiconductor chip 200. The second upper posts (322, 327) include a second upper connection post 322 and a second upper bridge post 327. The second upper bridge post 327 is formed in a single process with the second upper connection post 322. The material and height of the second upper bridge post 327 are substantially the same as the material and height H2 of the second upper connection post 322, respectively. The height H2 of the second upper connection post 322 and the height of the second upper bridge post 327 are, for example, 5 μm to 10 μm.

[0141] A carrier substrate 900 is prepared. The carrier substrate 900 is a temporary substrate. A carrier adhesive layer 990 is attached onto the upper surface of the carrier substrate 900. The carrier adhesive layer 990 includes, but is not limited to, an insulating polymer.

[0142] The semiconductor element 100 and the second semiconductor chip 200 are disposed on the carrier adhesive layer 990. The semiconductor element 100 and the second semiconductor chip 200 are attached onto the carrier substrate 900 using the carrier adhesive layer 990. At this time, the lower surface 100b of the semiconductor element 100 and the lower surface 200b of the second semiconductor chip 200 physically contact the carrier adhesive layer 990. The carrier adhesive layer 990 is relatively soft, and the first upper posts (311, 317) and the second upper posts (322, 327) are inserted into the carrier adhesive layer 990. Thereby, the first upper posts (311, 317) and the second upper posts (322, 327) are provided within the carrier adhesive layer 990. The upper surface of the carrier adhesive layer 990 is provided at a level higher than the lower surfaces of the first upper posts (311, 317) and the second upper posts (322, 327). The thickness of the carrier adhesive layer 990 is greater than the height H1 of the first upper connecting post 311, the height of the first upper bridge post 317, the height H2 of the second upper connecting post 322, and the height of the second upper bridge post 327. Thereby, the lower surfaces of the first upper posts (311, 317) and the second upper posts (322, 327) are separated from the carrier substrate 900.

[0143] Referring to FIG. 7B, a first molding film 410 is formed on the carrier adhesive layer 990 to cover the sidewalls of the semiconductor element 100 and the second semiconductor chip 200. The first molding film 410 exposes, but is not limited to, the upper surfaces of the semiconductor element 100 and the second semiconductor chip 200. The lower surface 410b of the first molding film 410 directly contacts the upper surface of the carrier adhesive layer 990. Thereby, the lower surface 410b of the first molding film 410 is coplanar with the lower surface 100b of the semiconductor element 100 and the lower surface 200b of the second semiconductor chip 200.

[0144] Since the first upper posts (311, 317) are provided in the carrier adhesive layer 990, the semiconductor element 100 is firmly fixed to the carrier adhesive layer 990 by the first upper posts (311, 317) during the formation process of the first molding film 410. Since the second upper posts (322, 327) are provided in the carrier adhesive layer 990, the second semiconductor chip 200 is firmly fixed to the carrier adhesive layer 990 by the second upper posts (322, 327) during the formation process of the first molding film 410. Thereby, unwanted movement of the semiconductor element 100 and the second semiconductor chip 200 is prevented. The accuracy of the manufacturing process of the semiconductor package is improved, and the yield of the semiconductor package is improved.

[0145] Since the height H1 of the first upper connecting post 311 and the height of the first upper bridge post 317 are 5 μm or more, the semiconductor element 100 is stably fixed to the carrier adhesive layer 990 during the formation process of the first molding film 410. Since the height H2 of the second upper connecting post 322 and the height of the second upper bridge post 327 are 5 μm or more, the second semiconductor chip 200 is stably fixed to the carrier adhesive layer 990 during the formation process of the first molding film 410. Thereby, the accuracy and efficiency of the manufacturing process of the semiconductor package are further improved.

[0146] Referring to FIG. 7C, the carrier adhesive layer 990 and the carrier substrate 900 are removed, and the lower surface 410b of the first molding film 410, the lower surface 100b of the semiconductor element 100, and the lower surface 200b of the second semiconductor chip 200 are exposed. For example, the carrier adhesive layer 990 and the carrier substrate 900 are separated from the first molding film 410, the semiconductor element 100, and the second semiconductor chip 200. Thereby, the first upper posts (311, 317) and the second upper posts (322, 327) are exposed. For example, the lower surface and side walls of the first upper posts (311, 317) and the lower surface and side walls of the second upper posts (322, 327) are exposed. The lower surface 410b of the first molding film 410 is provided at a level higher than the lower surfaces of the first upper posts (311, 317) and the second upper posts (322, 327).

[0147] Referring to FIG. 7D, the first lower post 331 and the second lower post 332 are respectively formed on the lower surfaces of the first upper connecting post 311 and the second upper connecting post 322. The forming process of the first and second lower posts (331, 332) is performed by a plating process. At this time, the second lower post 332 is formed with the first lower post 331 in a single plating process. The second lower post 332 contains the same metal as the first lower post 331. The first and second lower posts (331, 332) contain the same metal as the first and second upper connecting posts (311, 322).

[0148] The width W3 of the first lower post 331 is smaller than the width W1 of the first upper connecting post 311. Thereby, in the manufacturing process of the first lower post 331, even if a process error occurs, the first lower post 331 is prevented from being misaligned vertically with respect to the first upper connecting post 311. For example, the upper surface of the first lower post 331 is well connected to the lower surface of the first upper connecting post 311. On the other hand, the width W3 of the first lower post 331 may be substantially the same as the width W1 of the first upper connecting post 311.

[0149] The height H3' of the first lower post 331 is higher than the height H1 of the first upper connecting post 311. The height H30' of the second lower post 332 is higher than the height H2 of the second upper connecting post 322. The height H30' of the second lower post 332 is the same as or similar to the height H3' of the first lower post 331. On the other hand, the height H30' of the second lower post 332 may be different from the height H3' of the first lower post 331.

[0150] The width W30 of the second lower post 332 is narrower than the width W2 of the second upper connecting post 322. Thereby, in the manufacturing process of the second lower post 332, even if a process error occurs, the second lower post 332 is prevented from being misaligned vertically with respect to the second upper connecting post 322. For example, the upper surface of the second lower post 332 is well connected to the lower surface of the second upper connecting post 322. On the other hand, the width W30 of the second lower post 332 may be substantially the same as the width W2 of the second upper connecting post 322.

[0151] The first and second lower posts (331, 332) are not formed on the lower surfaces of the first upper bridge post 317 and the second upper bridge post 327. The first and second lower posts (331, 332) are separated from the first and second upper bridge posts (317, 327).

[0152] Referring to FIG. 7E, the bridge structure 700 is disposed on the lower surface 100b of the semiconductor element 100 and the lower surface 200b of the second semiconductor chip 200. For example, the bridge structure 700 is disposed on the lower surfaces of the first upper bridge post 317 and the second upper bridge post 327.

[0153] The bridge structure 700 includes a base substrate 710, a bridge insulating layer 720, bridge wirings 730, conductive pads 715, conductive connection portions 751, and vias 750 as described in the example of FIG. 1C above. On the other hand, the bridge structure 700 may not include the conductive connection portions 751 and the vias 750 as in the examples of FIGS. 2A and 2B. In the process of arranging the bridge structure 700, the arrangement of the bridge structure 700 is adjusted so that the conductive pads 715 are vertically aligned with the first and second upper bridge posts (317, 327).

[0154] Bridge solder balls 670 are formed between the bridge structure 700 and the first and second upper bridge posts (317, 327), and the conductive pads 715 and the first and second upper bridge posts (317, 327) are connected. For example, the bridge solder balls 670 bond the upper surface of the conductive pads 715 and the lower surfaces of the first and second upper bridge posts (317, 327) by a reflow process of the bridge solder balls 670. Thereby, the second semiconductor chip 200 and the semiconductor element 100 are electrically connected to each other via the bridge structure 700.

[0155] The conductive pattern 755 is formed on the lower surface of the bridge structure 700 and is connected to the through-via 750. The formation of the conductive pattern 755 is performed before or after the placement of the bridge structure 700. The lower surface of the conductive pattern 755 is provided at the same level as or a different level from the lower surface of the first lower post 331. The lower surface of the conductive pattern 755 is provided at the same level as or a different level from the lower surface of the second lower post 332.

[0156] Referring to FIG. 7F, the second molding film 420 is formed on the lower surface 410b of the first molding film 410, the lower surface 100b of the semiconductor element 100, and the lower surface 200b of the second semiconductor chip 200, and covers the first upper posts (311, 317), the second upper posts (322, 327), the first and second lower posts (331, 332), and the bridge structure 700. For example, the second molding film 420 covers the side walls of the first upper posts (311, 317), the side walls of the second upper posts (322, 327), and the side walls of the first and second lower posts (331, 332). The second molding film 420 further covers the lower surface of the bridge structure 700, the lower surface of the conductive pattern 755, and the lower surfaces of the first and second lower posts (331, 332).

[0157] The second molding film 420 is formed directly on the lower surface 410b of the first molding film 410 and physically contacts the lower surface 410b of the first molding film 410. For example, no other components are interposed between the first molding film 410 and the second molding film 420. The formation of the second molding film 420 is performed using the same epoxy-based molding compound as the first molding film 410. Thereby, the difference in the coefficient of thermal expansion between the first molding film 410 and the second molding film 420 is reduced, and the occurrence of warpage of the semiconductor package is prevented in the manufacturing process of the semiconductor package.

[0158] The second molding film 420 further extends into the gap regions between the bridge structure 700 and the semiconductor element 100, between the bridge structure 700 and the first molding film 410, and between the bridge structure 700 and the second semiconductor chip 200, and further covers the sidewalls of the first and second upper bridge posts (317, 327) and the sidewall of the bridge solder ball 670. On the other hand, an underfill film 470 as described in the example of FIG. 1D can be formed in the gap regions between the bridge structure 700 and the semiconductor element 100, between the bridge structure 700 and the first molding film 410, and between the bridge structure 700 and the second semiconductor chip 200.

[0159] Referring to FIG. 7G, a polishing process is performed on the lower surface of the second molding film 420, and the lower surfaces of the conductive pattern 755, the first lower post 331, and the second lower post 332 are exposed. The polishing process includes, but is not limited to, a chemical mechanical polishing process.

[0160] In the polishing process, the lower part of the second molding film 420 is removed. Further, a part of the conductive pattern 755, a part of the first lower post 331, and a part of the second lower post 332 are further removed together with the second molding film 420. The height H3 of the first lower post 331 after the polishing process is the same as or lower than the height of the first lower post 331 before the polishing process (H3' in FIG. 7F). The height H30 of the second lower post 332 after the polishing process is the same as or lower than the height of the second lower post 332 before the polishing process (H30' in FIG. 7F). In FIG. 7F, even if the lower surfaces of the first lower post 331, the second lower post 332, or the conductive pattern 755 are provided at different levels, the lower surfaces of the first lower post 331, the second lower post 332, and the conductive pattern 755 are provided at substantially the same level by the polishing process. After the polishing process, the lower surfaces of the second molding film 420, the first lower post 331, the second lower post 332, and the conductive pattern 755 are coplanar.

[0161] Referring to FIG. 7H, an insulating layer 510, a seed pattern 535, and a rewiring pattern 530 are formed on the lower surface of the second molding film 420. Forming the insulating layer 510 includes coating a photosensitive polymer PID on the lower surface of the second molding film 420. The insulating layer 510 has openings. The openings penetrate the insulating layer 510. The openings expose the lower surfaces of the first lower post 331, the second lower post 332, and the conductive pattern 755.

[0162] The seed pattern 535 is formed in the openings and on the lower surface of the insulating layer 510. The rewiring pattern 530 is formed by a plating process using the seed pattern 535 as an electrode. The plating process includes an electroplating process.

[0163] As an example, forming the seed pattern 535 and the rewiring pattern 530 includes forming a seed layer in the openings and on the lower surface of the insulating layer 510, forming a resist pattern on the seed layer, performing a plating process using the seed layer as an electrode, removing the resist pattern to expose a part of the seed layer, and etching the exposed part of the exposed seed layer. The rewiring pattern 530 is formed in the openings and on top of the resist pattern by the plating process. Each of the rewiring patterns 530 includes a via portion and a wiring portion. The via portion is formed in the corresponding opening, and the wiring portion is formed on the lower surface of the via portion and on the lower surface of the insulating layer 510. By etching the seed layer, the seed pattern 535 is formed on the lower surface of each of the rewiring patterns 530.

[0164] Referring to FIG. 7I, the process of forming the insulating layer 510, the seed pattern 535, and the rewiring pattern 530 is repeatedly performed. Thereby, a stacked insulating layer 510, a stacked seed pattern 535, and a stacked rewiring pattern 530 are formed.

[0165] Thereafter, a seed pad 555 and a redistribution pad 550 are formed. The redistribution pad 550 and the seed pad 555 are formed on the lower surface of the bottommost insulating layer 510 and within the bottommost insulating layer 510. Forming the redistribution pad 550 includes performing an electroplating process using the seed pad 555 as an electrode. The redistribution layer 500 is manufactured according to the example described above. The redistribution layer 500 includes the insulating layer 510, the seed pattern 535, the redistribution pattern 530, the seed pad 555, and the redistribution pad 550.

[0166] According to the present embodiment, the redistribution layer 500 is manufactured by a chip first process. Thereby, the number of manufacturing steps of the redistribution layer 500 is reduced, and the redistribution layer 500 is manufactured more simply and efficiently. Since the redistribution layer 500 is manufactured by the chip first process, solder balls are not used for the electrical connection between the semiconductor element 100 and the redistribution layer 500 and the electrical connection between the second semiconductor chip 200 and the redistribution layer 500. For example, the semiconductor element 100 is electrically connected to the redistribution layer 500 via the first upper connection post 311 and the first lower post 331. The second semiconductor chip 200 is electrically connected to the redistribution layer 500 via the second upper connection post 322 and the second lower post 332. The manufacturing process of the semiconductor package is further simplified, and the efficiency of the manufacturing process of the semiconductor package is further improved. Hereinafter, for simplicity, the illustration of the seed pattern 535 and the seed pad 555 is omitted.

[0167] Referring to FIG. 7J, a connecting solder ball 650 is formed on the lower surface of the redistribution layer 500. For example, the connecting solder ball 650 is formed on the lower surface of the redistribution pad 550 and is connected to the redistribution pad 550. Although not shown, a connecting pillar is further interposed between the redistribution pad 550 and the connecting solder ball 650. The connecting pillar contains a metal such as copper. Thereby, a preliminary package is manufactured. The preliminary package includes a redistribution layer 500, a connecting solder ball 650, first and second lower posts (331, 332), first upper posts (311, 317), a semiconductor element 100, second upper posts (322, 327), a second semiconductor chip 200, a bridge structure 700, a first molding film 410, and a second molding film 420.

[0168] Referring to FIG. 7K, a package substrate 600 is prepared. The package substrate 600 includes an upper substrate pad 610, a substrate wiring 630, and a lower substrate pad 620. The preliminary package is disposed on the package substrate 600 such that the connecting solder balls 650 are vertically aligned with the upper substrate pads 610. A reflow process of the connecting solder balls 650 is performed, and the connecting solder balls 650 are bonded to the upper substrate pads 610. Thereby, the redistribution layer 500 is electrically connected to the package substrate 600 via the connecting solder balls 650.

[0169] Referring again to FIG. 1B, a lower underfill film 460 is formed between the package substrate 600 and the redistribution layer 500 to cover the sidewalls of the connecting solder balls 650. Solder ball terminals 675 are formed on the lower surface of the package substrate 600 and are connected to the lower substrate pads 620. The manufacturing of the semiconductor package 1 is completed according to the above-described example.

[0170] As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical idea of the present invention.

Description of Reference Numerals

[0171] 1, 1A, 1B Semiconductor Packages 100 Semiconductor Element (Chip Stack Package) 100b, 200b, 410b Bottom Surface 105, 125 First and Second Lower Pads 110 First Lower Semiconductor Chip (First Semiconductor Chip) 111, 121 First and Second Upper Pads 113, 123 First and Second Through-Structures 120 First Upper Semiconductor Chip 140 Internal Molding Film 150 Bump 160 Insulating Film 200 Second Semiconductor Chip 205 Chip Pad 311, 322 First and Second Upper Connection Posts (First and Second Upper Posts) 317, 327 First and Second Upper Bridge Posts (First and Second Upper Posts) 311A, 322A First and Second Connecting Conductive Posts 311B, 322B First and Second Connecting Metal Layers 311C, 322C First and Second Connecting Bonding Layers 317A, 327A First and Second Bridge Conductive Posts 317B, 327B First and Second Bridge Metal Layers 331, 332 First and Second Lower Posts (Lower Posts) 331M, 332M First and Second Metal Posts 331S, 332S First and Second Seed Films 410, 420 First and Second Molding Films (Upper and Lower Molding Films) 460 Lower Underfill Film 470 Underfill Film 500 Redistribution Layer 510 Insulating Layer 530 Redistribution Pattern 530V Via Portion 530W Wiring Portion 535 Seed Pattern 550 Redistribution Pad 555 Seed Pad 600 Package Substrate 610 Upper Substrate Pad 620 Lower Substrate Pad 630 Substrate Wiring 650 Connecting Solder Ball 670, 670’ Bridge Solder Ball 675 Solder Ball Terminal 700 Bridge Structure 710 Base Substrate 715 Conductive Pad 720 Bridge Insulating Layer 730 Bridge Wiring 750 Through Via 751 Conductive Connection Part 755 Conductive Pattern 800 Heat Dissipation Structure 900 Carrier Substrate 990 Carrier Adhesive Layer D1 First Direction D2 Second Direction D3 Third Direction

Claims

1. A redistribution layer; a first lower post disposed on the redistribution layer; a second lower post disposed on the redistribution layer and spaced laterally from the first lower post; a first upper connecting post on the first lower post; a second upper connecting post on the second lower post; a bridge structure provided on the redistribution layer and disposed between the first lower post and the second lower post; a semiconductor device disposed on the first upper connecting post and a first region of the bridge structure; a semiconductor chip disposed on the second upper connecting post and the second region of the bridge structure and spaced laterally from the semiconductor device; a lower molding layer provided on the redistribution layer to cover sidewalls of the first lower post and the second lower post and sidewalls of the first upper connecting post and the second upper connecting post, The lower molding film is in direct physical contact with a lower surface of the semiconductor device and a lower surface of the semiconductor chip.

2. an upper molding layer covering a sidewall of the semiconductor device and a sidewall of the semiconductor chip; 2. The semiconductor package of claim 1, wherein the lower molding film is in direct physical contact with a lower surface of the upper molding film.

3. 3. The semiconductor package of claim 2, wherein a lower surface of the upper molding film is coplanar with a lower surface of the semiconductor device and a lower surface of the semiconductor chip.

4. 3. The semiconductor package of claim 2, wherein the lower molding film includes the same epoxy-based molding compound as the upper molding film.

5. a first upper bridge post between the bridge structure and the semiconductor device; a second upper bridge post between the bridge structure and the semiconductor chip; 3. The semiconductor package of claim 2, wherein the upper molding layer is spaced apart from the first upper bridge post and the second upper bridge post.

6. 6. The semiconductor package of claim 5, wherein the lower molding film extends between the bridge structure and the semiconductor chip and between the bridge structure and the semiconductor element, and covers sidewalls of the first upper bridge post and the second upper bridge post.

7. The bridge structure includes: Bridge wiring, a through via spaced apart from the bridge wiring, the semiconductor chip is electrically connected to the semiconductor device through the bridge wiring, The semiconductor package of claim 1 , wherein the semiconductor chip and the semiconductor device are electrically connected to the redistribution layer through the through vias.

8. The semiconductor device is a first lower semiconductor chip; 2. The semiconductor package of claim 1, further comprising: a plurality of first upper semiconductor chips stacked on the first lower semiconductor chip.

9. 1. A semiconductor package comprising: A first semiconductor chip; a second semiconductor chip spaced laterally from the first semiconductor chip; a first upper connection post provided on a lower surface of the first semiconductor chip and connected to the first semiconductor chip; a second upper connection post provided on a lower surface of the second semiconductor chip and connected to the second semiconductor chip; a first lower post disposed on a lower surface of the first upper connecting post; a second lower post disposed on a lower surface of the second upper connecting post; a bridge structure provided on a lower surface of the first semiconductor chip and a lower surface of the second semiconductor chip and spaced laterally from the first lower post and the second lower post; a first molding film covering sidewalls of the first and second semiconductor chips and spaced apart from the first and second upper connecting posts; a second molding film provided on a lower surface of the first molding film; the second molding film covers the bridge structure, sidewalls of the first and second lower posts, and sidewalls of the first and second upper connecting posts.

10. 10. The semiconductor package of claim 9, wherein the second molding film is in direct physical contact with a bottom surface of the first molding film, a bottom surface of the first semiconductor chip, and a bottom surface of the second semiconductor chip.

11. a first upper bridge post between the bridge structure and the first semiconductor chip; a second upper bridge post between the bridge structure and the second semiconductor chip; 10. The semiconductor package of claim 9, wherein the second molding film extends onto an upper surface of the bridge structure to cover sidewalls of the first upper bridge post and the second upper bridge post.

12. a bridge solder ball provided between the bridge structure and the first upper bridge post and between the bridge structure and the second upper bridge post, the bridge solder ball directly contacts a lower surface of the first upper bridge post and the second upper bridge post; The semiconductor package of claim 11 , wherein the second molding film covers a sidewall of the bridge solder ball.

13. a redistribution layer disposed on a lower surface of the second molding film, The redistribution layer is Rewiring patterns, a seed pattern on an upper surface of the rewiring pattern; The semiconductor package of claim 9 , wherein at least one of the seed patterns directly contacts a lower surface of the first lower post.

14. a conductive pattern disposed between the redistribution layer and the bridge structure and electrically connected to the redistribution pattern; The bridge structure includes: A base substrate; A bridge wiring on the base substrate; a through via that penetrates the base substrate and is electrically isolated from the bridge wiring, The semiconductor package of claim 13 , wherein the through via is electrically connected to the conductive pattern.

15. The semiconductor package of claim 14 , wherein the second molding film further extends into a gap region between the redistribution layer and the bridge structure to further cover a sidewall of the conductive pattern.

16. the first semiconductor chip is a first lower semiconductor chip, The semiconductor package includes: a plurality of first upper semiconductor chips stacked on the first lower semiconductor chip; an inner molding layer disposed on an upper surface of the first lower semiconductor chip and covering sidewalls of the first upper semiconductor chips; The semiconductor package of claim 9 , wherein the second semiconductor chip is a different type from the first lower semiconductor chip and the first upper semiconductor chip.

17. a package substrate including a lower substrate pad, a substrate trace, and an upper substrate pad; a solder ball terminal disposed on a lower surface of the lower substrate pad; a redistribution layer disposed on an upper surface of the package substrate, the redistribution layer including an insulating layer, a redistribution pattern, a seed pattern, and a redistribution pad; a connecting solder ball provided between the package substrate and the redistribution layer to connect the upper substrate pad and the redistribution pad; a lower post including a first lower post and a second lower post provided on an upper surface of the redistribution layer, electrically connected to the redistribution pattern and laterally spaced apart from each other; a first upper connecting post disposed on the first lower post; a second upper connecting post disposed on the second lower post; a bridge structure provided on an upper surface of the redistribution layer and disposed between the first lower post and the second lower post; a chip stack package including a first lower semiconductor chip disposed on an upper surface of the first upper connecting post and a first region of the bridge structure and connected to the first upper connecting post and the bridge structure; a second semiconductor chip disposed on an upper surface of the second upper connecting post and on a second region of the bridge structure, connected to the second upper connecting post and the bridge structure, and spaced laterally from the chip stack package; a first molding film covering a sidewall of the chip stack package and a sidewall of the second semiconductor chip; a second molding layer provided on an upper surface of the redistribution layer to cover sidewalls of the first and second lower posts and sidewalls of the first and second upper connecting posts, The second molding film is in physical contact with a bottom surface of the first molding film, a bottom surface of the chip stack package, and a bottom surface of the second semiconductor chip.

18. a first upper bridge post between the bridge structure and the chip stack package; a second upper bridge post between the bridge structure and the second semiconductor chip; bridge solder balls provided between the bridge structure and the first upper bridge post and between the bridge structure and the second upper bridge post; 20. The semiconductor package of claim 17, wherein the first molding film is spaced apart from the first upper bridge post, the second upper bridge post, and the bridge solder ball.

19. The height of the first upper connection post is 5 μm to 10 μm; the height of the first upper bridge post is between 5 μm and 10 μm; The height of the second upper connection post is 5 μm to 10 μm; 20. The semiconductor package of claim 18, wherein the second upper bridge post has a height of 5 μm to 10 μm.

20. a lower surface of the bridge structure is spaced from the redistribution layer; The semiconductor package of claim 17 , wherein the second molding film extends between a lower surface of the bridge structure and the redistribution layer to cover the lower surface of the bridge structure.

Images