Serial communication device, delay adjustment device, and serial communication method

Abstract

To provide a serial communication device capable of complying with a timing specification on serial communication even if signal delay resulting from bit error during data transfer occurs.SOLUTION: A serial communication device for transferring a plurality of packets indicating a state of a control signal at a change point of the control signal, includes: a delay amount calculation part for calculating a delay amount for start timing of the received control signal; a buffer control part for storing received transfer data in a buffer; and a timing adjustment part for delaying the transfer data stored in the buffer with aligning with the delay amount and output them.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a serial communication device, a delay adjustment device, and a serial communication method.

Background Art

[0002] There is a serial communication device that serially transfers data from a transmission device to a reception device using one or more serial communication channels. Further, in order to reduce misdetection of a control signal due to bit error during data transfer in the serial communication device, a technique of transferring a specific packet a predetermined number of times at a change point of the control signal to be transferred is known (see, for example, Patent Document 1).

Summary of the Invention

Problems to be Solved by the Invention

[0003] With the technique disclosed in Patent Document 1, it is possible to reduce misdetection of a control signal due to bit error during data transfer in the serial communication device. However, with this method alone, when a delay of the control signal due to bit error occurs, the timing specification of the serial communication may not be maintained.

[0004] One embodiment of the present invention has been made in view of the above problems, and enables the serial communication timing specification to be maintained even when a signal delay due to bit error occurs during data transfer in the serial communication device.

Means for Solving the Problems

[0005] In order to solve the above problems, a serial communication device according to an embodiment of the present invention is a serial communication device that transfers a plurality of packets indicating a state of a control signal at a change point of the control signal, and includes a delay amount calculation unit that calculates a delay amount of a start timing of the received control signal, a buffer control unit that stores the received transfer data in a buffer, and a timing adjustment unit that delays and outputs the transfer data stored in the buffer in accordance with the delay amount.

Advantages of the Invention

[0006] According to one embodiment of the present invention, in a serial communication device, even when a signal delay due to bit error occurs during data transfer, the timing specification of serial communication can be maintained.

Brief Description of the Drawings

[0007]

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Modes for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention (the present embodiment) will be described in detail with reference to the drawings. <Configuration of Serial Communication Device> FIG. 1 is a diagram showing a configuration example of a serial communication device according to an embodiment. The serial communication device 1 is a device that serially transfers a plurality of data from a transmission device 10 to a reception device 30 using a plurality of serial communication cables 120a, 120b,.... Further, the serial communication device 1 according to the present embodiment includes a delay adjustment device 40 downstream of the reception device 30. Note that the delay adjustment device 40 may be a delay adjustment circuit or the like provided in the reception device 30. In the following description, when indicating an arbitrary serial communication cable among the plurality of serial communication cables 120a, 120b,...., "serial communication cable 120" is used.

[0009] The transmission device 10 includes a transmission control unit 110 and a serial transmission unit 121. The transmission control unit 110 includes a transmission determination unit 111, a packet generation unit 112, and a packet transmission unit 113. The transmission determination unit 111 monitors input signals such as control signals A to D, records the changed signals, and generates a "corresponding signal flag" and a "transmission pulse". The packet generation unit 112 generates packet data (DATA) in a specific data format of the corresponding signal based on the corresponding signal flag. The packet transmission unit 113 transfers the same packet data (DATA) to the serial transmission unit 121, for example, three times (continuously) based on the transmission pulse supplied from the transmission determination unit 111 at the rising edge and falling edge timings of the input signal.

[0010] The serial transmission unit 121, which is a serial interface, includes a plurality of lanes (LANE1, LANE2,...), and transmits packet data (DATA) to the reception device 30 using LANE1 and the serial communication cable 120a. Further, the serial transmission unit 121 transmits image data (data) and an image data enable signal de to the reception device 30 using LANE2 and the serial communication cable 120b.

[0011] The receiving device 30 includes a serial receiving unit 122 and a reception control unit 130. The serial receiving unit 122, which is a serial interface, receives the same packet data (DATA) transferred from the transmitting device 10 at the timings of the rising edge and falling edge of the input signal.

[0012] The reception control unit 130 includes a packet reception unit 131, a packet comparison unit 132, and a restoration unit 133. The packet reception unit 131 records the packet data (DATA) received by the serial receiving unit 122 and sequentially supplies it to the packet comparison unit 132. The packet comparison unit 132 compares the supplied packet data (DATA) with "comparison data" in a predetermined data format and performs detection processing of the received signal.

[0013] When the comparison result of the packet comparison unit 132 matches, the corresponding signal flag and value are supplied to the restoration unit 133. The restoration unit 133 updates and holds the value of the corresponding signal based on the corresponding signal flag and value supplied from the packet comparison unit 132. When the comparison result does not match, the packet comparison unit 132 regards that a bit error has occurred in the received packet data (DATA), ignores the received packet data (DATA), and notifies the reception control unit 130 of a reception error.

[0014] In the following description, it is assumed that the serial communication device 1 converts 1-bit control signals A to D into packet data (DATA[15:0]) from a predetermined data format and transfers the packet data continuously three times using LANE1 of the serial transmission unit 121. Also, it is assumed that the serial communication device 1 transfers a 1-bit image enable signal de and 16-bit image data (data[15:0]) as they are using LANE2 of the serial transmission unit 121. Further, the following description is made assuming that the control signal A is an lgate signal indicating the period of one line of the image data. Note that the control signals C to D are, for example, spare signals.

[0015] Incidentally, the configurations and processing contents of the transmission device 10 and the reception device 30 described above may be the same as those of the serial communication transmission device 4 and the serial communication reception device 7 disclosed in Patent Document 1, for example.

[0016] The delay adjustment device 40 includes, for example, a delay determination unit 141, a delay amount calculation unit 142, a buffer control unit 143, a buffer 144, a timing adjustment unit 145, a quality monitoring unit 146, and the like.

[0017] The delay determination unit 141 executes a delay determination process for determining whether a delay has occurred based on the timing of the control signal restored by the reception device 30.

[0018] The delay amount calculation unit 142 executes a delay amount calculation process for calculating the delay amount of the control signal (for example, lgate) received by the reception device 30. For example, when a delay occurs, the delay amount calculation unit 142 calculates the signal delay amount based on the timing of a predetermined start signal (for example, the rising edge of lgate) and a key signal for delay amount calculation (for example, data[15:0] or de), and the timing specifications of the serial communication device 1.

[0019] The buffer control unit 143 executes a buffer control process for storing the restored control signal (lgate), the received image data (data[15:0]), the image data enable signal (de), and the like in the buffer 144. Note that the image data is an example of transfer data. Preferably, the buffer control unit 143 stores only the valid image data among the received image data in the buffer 144.

[0020] The buffer 144 is a buffer for delay adjustment that stores the restored control signal, the received image data, the image data enable signal, and the like.

[0021] The timing adjustment unit 145 executes a timing adjustment process of delaying and outputting the image data, image data enable signal, control signal, etc. stored in the buffer 144 in accordance with the delay amount calculated by the delay amount calculation unit 142. Preferably, the timing adjustment unit 145 adjusts the end timing of the control signal in accordance with the end timing of the transfer data to be delayed and output.

[0022] The quality monitoring unit 146 executes a quality monitoring process of, for example, counting the number of received packets (DATA[15:0]) and evaluating the quality of serial communication.

[0023] (Example when there is no delay adjustment unit) FIG. 2 is a diagram showing an example when there is no delay adjustment unit according to an embodiment. In serial communication, when transferring a 1-bit signal as it is, when a bit error occurs, the value of the signal may become a random value and the subsequent circuit may malfunction. Note that bit errors occur, for example, in the serial communication cables 120a and 120b, the serial transmitter 121, and the serial receiver 122 of FIG. 1.

[0024] Therefore, in order to prevent the subsequent circuit from malfunctioning due to the occurrence of a bit error, the transmission device 10 transmits packet data indicating whether the signal is H or L a plurality of times at the signal change point.

[0025] In the example of FIG. 2, when lgate201, which is an example of a control signal, rises, the transmission device 10 transmits DATA203 including the packet "0x33FF" indicating that lgate201 is in the H state three times. Further, when lgate201 falls, the transmission device 10 transmits DATA203 including the packet "0x3300" indicating that lgate201 is in the L state three times. Note that when the transmission device 10 transmits a packet with DATA203, it sets the data enable signal DE202 of the control signal to H.

[0026] Also, when the receiving device 30 receives the packet "0x33FF" from the DE204 received from the transmitting device 10 and the DATA205, it sets lgate to the H state, and when it receives the packet "0X3300", it sets lgate to the L state.

[0027] Thus, when the received DE204 and DATA205 are not bit-corrupted, the receiving device 30 can restore the correct lgate206. In this case, as shown in Fig. 2(A), lgate206 satisfies T1, T2, and T3 which are the timing specifications of the serial communication device 1. Therefore, the serial communication device 1 can correctly transfer the image data by lgate206, de211, and data212.

[0028] Here, the control signal lgate is used as a line signal flag. For example, during the period when lgate is H, it represents the transfer period of one line, and during the period when lgate is L, it represents the blanking period between lines. Also, the lowercase de is the data enable signal of the image data, and the uppercase DE is the data enable signal for the control signal. Similarly, the lowercase data is the image data, and the uppercase DATA is the packet data indicating the state of the control signal.

[0029] Also, T1, T2, and T2 are the times defined by the timing specifications of the serial communication device 1. T1 is the time from the rising edge of lgate to the rising edge of de. T2 is the time from the falling edge of de of the last data of the line to the falling edge of lgate. T3 is the time from the falling edge of lgate of one line to the rising edge of lgate of the next line.

[0030] On the other hand, when the received DE204 and DATA205 are bit - corrupted, the receiving device 30 cannot restore the correct lgate206. For example, as shown in FIG. 2, when the receiving device 30 cannot correctly receive the packets (1) and (2) due to bit - corruption, the restored lgate207 has a delayed rise. In this case, as shown in FIG. 2(B), the restored lgate207 cannot satisfy T1, T2, and T3 which are the timing specifications of the serial communication device 1.

[0031] In the example of FIG. 2(B), the rise of lgate207 is delayed by T1 + T5 compared to the timing specifications of the serial communication device 1. In this case, the serial communication device 1 cannot correctly transfer the image data due to lgate207, de211, and data212.

[0032] Thus, according to the technology disclosed in Patent Document 1, it is possible to reduce the misdetection of control signals due to bit - corruption during data transfer in the serial communication device 1. However, with only this method, there is a problem that when a delay of the control signal due to bit - corruption occurs, the timing specifications of serial transfer cannot be maintained.

[0033] Therefore, the serial communication device 1 according to the present embodiment has a delay adjustment unit 140 (or a delay adjustment device 40) that adjusts the delay amount of the signal received by the receiving device 30 so as to satisfy the timing specifications of the serial communication device 1 even when bit - corruption occurs.

[0034] [Example 1] FIG. 3 is a diagram for explaining the outline of the processing of the delay adjustment unit according to Example 1. FIG. 3(A) shows the relationship between lgate311, de312, and data313 when no bit - corruption occurs. In this case, for example, at time t0, when lgate311 rises, according to the timing specifications of the serial communication device 1, at time t1 after the elapse of time T1, de312 rises and starts the transfer of data313 for one line.

[0035] Also, for example, when the transfer of data313 is completed at time t4, lgate311 falls at time t5 after the elapse of time T2 from time t4. Further, at time t6 after the elapse of time T3 from time t5, lgate311 rises again for the next one line.

[0036] FIG. 3(B) shows the relationship among lgate321, de322, and data323 when bit error occurs and the rising of lgate321 is delayed by T1 + T5 and there is no delay adjustment unit 140. In this case, lgate321 which should rise at time t0 rises at time t2 after starting the transfer of data323 for one line at time t1. Therefore, the serial communication device 1 cannot correctly transfer data323 for one line.

[0037] Therefore, as shown in FIG. 3(C), the delay adjustment unit 140 according to the first embodiment has a function of calculating the delay amount (T1 + T5) of lgate331 and delaying and outputting lgate331, de332, and data333 by the calculated delay amount.

[0038] Thereby, as shown in FIG. 3(C), when lgate331 rises at time t2, de332 rises at time t3 after the elapse of time T1 and starts the transfer of data333 for one line.

[0039] Also, for example, when the transfer of data333 is completed at time t7, lgate331 falls at time t8 after the elapse of time T2. In this way, even when the delay adjustment unit 140 cannot receive the packet "0x33FF" indicating the H state of lgate one or two times, it can output lgate331, de332, and data333 according to the timing specification of the serial communication device 1.

[0040] (Processing of the delay adjustment unit) FIG. 4 is a flowchart showing an example of the processing of the delay adjustment unit according to the first embodiment. This processing shows an example of the processing executed by the delay adjustment unit 140 having a functional block as shown in FIG. 1, for example. Here, the following description will be given on the assumption that no bit error has occurred in the image data (data) and the image data enable signal (de).

[0041] In step S401, the buffer control unit 143 prepares a buffer 144 for the maximum signal delay amount of the serial communication device 1.

[0042] In step S402, the delay determination unit 141 determines the start timing of the control signal. For example, in FIG. 3(B), the delay determination unit 141 determines the time t2 when lgate321 rises.

[0043] In step S403, the delay determination unit 141 determines the start timing of the transfer data. For example, in FIG. 3(B), the delay determination unit 141 determines the time t1 when de322 first rises.

[0044] In step S404, the delay amount calculation unit 142 calculates the delay amount of the control signal based on the start timing of the control signal, the start timing of the transfer data, and the timing specification of the serial communication device 1. For example, in FIG. 3(B), in the timing specification of the serial communication device 1, lgate321 is supposed to rise T1 time before the time t1 when de322 first rises, but actually, it rises T5 time later than the time t1. In this case, the delay amount calculation unit 142 can calculate the delay time of lgate321 (an example of the control signal) as T1 + T5.

[0045] In step S405, the timing adjustment unit 145 delays and outputs signals such as transfer data by the calculated signal delay amount based on the start timing of the control signal. For example, as shown in FIG. 3(C), the timing adjustment unit 145 delays de332 and data333 by the calculated delay amount T1 + T5 and outputs them based on the rising time t2 of lgate331 (the start timing of the control signal).

[0046] Further, the timing adjustment unit 145 turns off lgate331 in accordance with the delayed de332 and data333. For example, the timing adjustment unit 145 may delay and output lgate331 in the same manner as de332 and data333, or may turn off lgate331 at time t8 after time T2 has elapsed from time t7 when the transfer of data333 is completed.

[0047] By the process of FIG. 4, the serial communication device 1 can comply with the timing specifications of serial communication even when a signal delay due to bit error occurs during data transfer.

[0048] [Example 2] FIG. 5 is a diagram for explaining the outline of the processing of the delay adjustment unit according to the second embodiment. FIG. 5(A) shows lgate511, de512, and data513 of the first embodiment when lgate511 is delayed by time T1 + T5 due to bit error. In this case, the buffer control unit 143 stores all the states of de512 and data513 in the buffer 144.

[0049] However, when de512 is in the L state, there is no valid data in data513. Therefore, the buffer control unit 143 according to the second embodiment stores data513 in the buffer 144 only when de512 is in the H state. As a result, as shown in FIG. 5(B), unnecessary line data delay can be eliminated.

[0050] FIG. 5(C) shows an image of the data range 501 stored in the buffer 144 in Example 2 and the data range 502 stored in the buffer 144 in Example 1. In Example 1, since all the data in the data range 502 is stored in the buffer 144, for example, when the line data delay is large, it is necessary to increase the usage amount of the buffer 144.

[0051] On the other hand, in Example 2, even when the line data delay is large, the usage amount of the buffer 144 can be saved and the line data delay can be absorbed. Note that Example 2 can be applied in combination with Example 1. (Processing of Buffer Control Unit) FIG. 6 is a diagram showing an example of the processing of the buffer control unit according to Example 2. This processing shows an example of the processing executed by the buffer control unit 143 of the delay adjustment unit 140 from the start of reception of transfer data to the end of reception.

[0052] In step S601, when the buffer control unit 143 receives transfer data from the receiving device 30, it executes the processing after step S602.

[0053] In step S602, the buffer control unit 143 determines whether the data enable signal (for example, the image data enable signal de) of the transfer data is H. When the data enable is H, the buffer control unit 143 shifts the processing to step S603. On the other hand, when the enable is L, the buffer control unit 143 ends the processing of FIG. 6.

[0054] When shifting to step S603, the buffer control unit 143 stores the transfer data in the buffer 144. Thereby, the buffer control unit 143 can store only the data 513 during the period when de512 is H during the period from time t11 to t12 in FIG. 5(A) in the buffer 144, for example. From this, the serial communication device 1 can reduce the data range stored in the buffer 144 and absorb the line data delay as shown in FIG. 5(C), for example.

[0055] [Embodiment 3] FIG. 7 is a diagram for explaining an outline of the processing of the delay adjustment unit according to Embodiment 3. In Embodiment 3, an example in the case where the fall of a control signal such as lgate is delayed will be described. FIG. 7(A) shows the relationship between lgate311, de312, and data313 when bit error does not occur. Note that since this figure is the same as FIG. 3(A) already described, the description is omitted here.

[0056] FIG. 7(B) shows the relationship between lgate711, de712, and data713 when bit error occurs, the fall of lgate711 is delayed from T2 to T4, and there is no delay adjustment unit 140. In this case, since the time T6 from the fall of lgate711 in Line1 to the rise of the next Line2 does not satisfy T3 which is one of the timing specifications of the serial communication device 1, it is considered that the subsequent circuit may malfunction.

[0057] Therefore, as shown in FIG. 7(C), the timing adjustment unit 145 according to Embodiment 3 has a function of reconstructing lgate721 so that lgate721 falls when the time T2 has elapsed from the time t4 when data transfer is completed. Thereby, lgate721, de722, and data723 in FIG. 7(C) satisfy the timing specifications of the serial communication device 1, so that the subsequent circuit can suppress malfunction and transfer data correctly.

[0058] (Processing of the Timing Adjustment Unit) FIG. 8 is a flowchart showing an example of the processing of the timing adjustment unit according to Embodiment 3. This processing shows an example of the processing executed by the timing adjustment unit 145 of the delay adjustment unit 140.

[0059] In step S801, the timing adjustment unit 145 determines whether a predetermined time has elapsed since receiving the last data of one line. For example, in FIG. 7(C), the timing adjustment unit 145 determines whether the time T2 defined by the timing specification of the serial communication device 1 has elapsed since the time t4 when the last data was received. If the predetermined time has elapsed, the timing adjustment unit 145 causes the process to proceed to step S802. On the other hand, if the predetermined time has not elapsed, the timing adjustment unit 145 repeatedly executes the process of step S801 until the predetermined time elapses.

[0060] When the process proceeds to step S802, the timing adjustment unit 145 determines whether the control signal is H. For example, in FIG. 7(B), the timing adjustment unit 145 determines whether lgate711 is H after the time T2 has elapsed from the time t4. If the control signal is H, the timing adjustment unit 145 causes the process to proceed to step S803. On the other hand, if the control signal is not H, the timing adjustment unit 145 ends the process of FIG. 8.

[0061] When the process proceeds to step S803, the timing adjustment unit 145 drops the control signal. For example, as shown in FIG. 7(C), the timing adjustment unit 145 sets lgate721 to L when the time T2 has elapsed from the time t4.

[0062] Note that the process shown in FIG. 8 is an example. For example, in FIG. 7(C), if lgate721 does not drop within a predetermined time after rising, lgate721 may be forcibly dropped. Note that Example 3 can be applied in combination with Examples 1 and 2. and can be applied in combination.

[0063] [Example 4] FIG. 9 is a diagram for explaining the process of the quality monitoring unit according to Example 4. The delay adjustment unit 140 can monitor or evaluate the serial transfer quality using the quality monitoring unit 146.

[0064] For example, as shown in FIG. 9(A), when lgate901 rises, the transmission device 10 transmits the packet "0x33FF" indicating that lgate901 is in the H state three times. Also, when lgate901 falls, the transmission device 10 transmits the packet "0x3300" indicating that lgate901 is in the L state three times.

[0065] As a result, the receiving device 30 receives the six packets transmitted by the transmitting device 10 and the data enable signal DE902 corresponding to the six packets. The quality monitoring unit 146 includes counters cnt1 to cnt6 corresponding to the timings (1) to (6) of the six packets received by the receiving device 30.

[0066] For example, at the timing of (1), when the quality monitoring unit 146 receives the packet "0x33FF" and can restore the value of lgate, it adds 1 to cnt1. Similarly, at the timing of (2), when the quality monitoring unit 146 can restore the value of lgate, it adds 1 to cnt2, and at the timing of (3), when the quality monitoring unit 146 can restore the value of lgate, it adds 1 to cnt3.

[0067] Also, at the timing of (4), when the quality monitoring unit 146 receives the packet "0x3300" and can restore the value of lgate, it adds 1 to cnt4. Similarly, at the timing of (5), when the quality monitoring unit 146 can restore the value of lgate, it adds 1 to cnt5, and at the timing of (6), when the quality monitoring unit 146 can restore the value of lgate, it adds 1 to cnt6.

[0068] Also, at a predetermined timing (for example, page end, or job end, etc.), the quality monitoring unit 146 reflects the values of cnt1 to cnt6 in a register or the like and then initializes cnt1 to cnt6 to 0.

[0069] Note that the quality monitoring unit 146 may count the counter values at the timings (1) to (3) together like cnt7, or may count the counter values at the timings (4) to (6) together like cnt8. Further, the quality monitoring unit 146 may count the counter values at the timings (1) to (6) together like cnt9.

[0070] Note that in the above description, the quality monitoring unit 146 counts the number of times the packet has been correctly received, but it is not limited to this. The quality monitoring unit 146 may count the number of times the packet has not been correctly received.

[0071] FIG. 9(B) shows an example where the packets (1), (2), (4), and (6) are incorrect. Thus, when the quality of the serial communication is poor, the count values of the counters cnt1 to cnt9 decrease. Therefore, the quality monitoring unit 146 can monitor the frequency of bit errors and the signal restoration status based on the count values of one or more of the counters cnt1 to cnt9. In other words, the quality monitoring unit 146 can monitor or evaluate the quality of the serial communication. Note that Example 4 can be applied in combination with Examples 1 to 3.

[0072] <Hardware Configuration of Delay Adjustment Device> The delay adjustment device 40 is realized, for example, by hardware, a program executed by a computer, or a combination of hardware and a program executed by a computer.

[0073] FIG. 10 is a diagram showing an example of the hardware configuration of a computer according to an embodiment. The computer 1000 includes, for example, a CPU (Central Processing Unit) 1001, a memory 1002, a storage device 1003, an input device 1004, an output device 1005, a communication I / F 1006, and a bus 1007.

[0074] The CPU 1001 is an arithmetic unit that realizes each function of the computer 1000 by executing a predetermined program stored in a storage medium such as a storage device 1003 and a memory 1002. The memory 1002 includes, for example, a RAM (Random Access Memory) used as a work area of the CPU 1001, a ROM (Read Only Memory) storing a startup program of the CPU 1001, and the like. The storage device 1003 is a non-volatile and large-capacity storage device that stores programs, data, and the like.

[0075] The input device 1004 includes various devices that receive external input to the computer 1000. The output device 1005 includes various devices that output to the outside from the computer 1000. The communication I / F 1006 is an interface for communicating with an external device. The bus 1007 is commonly connected to each of the above-described components and transmits, for example, an address signal, a data signal, and various control signals.

[0076] Note that the hardware configuration of the computer 1000 shown in FIG. 10 is an example. The computer 1000 may further include various signal processing devices such as a DSP (Digital Signal Processor) or an ASIC (Application Specific Integrated Circuit).

[0077] As described above, according to the present embodiment, in the serial communication device, even when a signal delay due to bit error occurs during data transfer, the timing specification of the serial communication can be observed.

[0078] <Supplementary Note> Each function of each of the embodiments described above can be realized by one or more processing circuits. Here, the "processing circuit" in this specification refers to a processor programmed to execute each function by software, such as a processor implemented by an electronic circuit, an ASIC (Application Specific Integrated Circuit) designed to execute each function described above, a DSP (digital signal processor), an FPGA (field programmable gate array), and devices such as conventional circuit modules.

[0079] <Appendix> This specification discloses serial communication devices, delay adjustment devices, and serial communication methods in the following respective items. (Item 1) A serial communication device that transfers a plurality of packets indicating the state of the control signal at a change point of the control signal, a delay amount calculation unit that calculates a delay amount of the start timing of the received control signal, a buffer control unit that stores the received transfer data in a buffer, a timing adjustment unit that delays and outputs the transfer data stored in the buffer in accordance with the delay amount, A serial communication device having the above. (Item 2) The serial communication device according to Item 1, wherein the timing adjustment unit adjusts the end timing of the control signal in accordance with the end timing of the transfer data to be delayed and output. (Item 3) The serial communication device according to Item 3, wherein the timing adjustment unit determines the end timing of the control signal based on the end timing of the transfer data to be delayed and output and the timing specification of the serial communication device. (Item 4) The serial communication device according to any one of Items 1 to 3, wherein the buffer control unit stores only valid transfer data among the received transfer data in the buffer. (Item 5) The buffer control unit further stores the data enable signal of the received transfer data in the buffer, and based on the data enable signal, stores valid transfer data among the received transfer data in the buffer, the serial communication device according to claim 4. (Item 6) The delay amount calculation unit calculates the delay amount based on the start timing of the control signal, the start timing of the transfer data, and the timing specification of the serial communication device, the serial communication device according to any one of claims 1 to 5. (Item 7) The serial communication device according to any one of claims 1 to 6, comprising a quality monitoring unit that counts the number of the received plurality of packets and evaluates the quality of serial communication. (Item 8) A delay amount calculation unit that calculates a delay amount of a start timing of the control signal received by serial communication that transfers a plurality of packets indicating a state of the control signal at a change point of the control signal; A buffer control unit that stores received transfer data in a buffer; A timing adjustment unit that delays and outputs the transfer data stored in the buffer in accordance with the delay amount; A delay adjustment device having the above. (Item 9) At a change point of a control signal, a serial communication device that transfers a plurality of packets indicating a state of the control signal executes a delay amount calculation process for calculating a delay amount of a start timing of the received control signal; executes a buffer control process for storing received transfer data in a buffer; executes a timing adjustment process for delaying and outputting the transfer data stored in the buffer in accordance with the delay amount; A serial communication method for performing the above.

[0080] As described above, the embodiments of the present invention have been explained. However, the present invention is not limited to such specific embodiments, and various modifications and applications are possible within the scope of the gist of the present invention described in the claims.

Explanation of Signs

[0081] 1 Serial communication device 40 Delay adjustment device 140 Delay adjustment unit 142 Delay amount calculation unit 143 Buffer control unit 144 Buffer 145 Timing adjustment unit 146 Quality monitoring unit 1000 Computer

Prior Art Documents

Patent Documents

[0082]

Patent Document 1

Claims

1. A serial communication device that transfers a plurality of packets indicating the state of the control signal at a change point of the control signal, comprising: a delay amount calculation unit that calculates a delay amount of the start timing of the received control signal; a buffer control unit that stores the received transfer data in a buffer; a timing adjustment unit that delays and outputs the transfer data stored in the buffer in accordance with the delay amount; A serial communication device having the above.

2. The serial communication device according to claim 1, wherein the timing adjustment unit adjusts the end timing of the control signal in accordance with the end timing of the transfer data to be delayed and output.

3. The serial communication device according to claim 2, wherein the timing adjustment unit determines the end timing of the control signal based on the end timing of the transfer data to be delayed and output and the timing specification of the serial communication device.

4. The serial communication device according to claim 1, wherein the buffer control unit stores only valid transfer data among the received transfer data in the buffer.

5. The buffer control unit further stores the data enable signal of the received transfer data in the buffer, and stores only valid transfer data among the received transfer data in the buffer based on the data enable signal. The serial communication device according to claim 4.

6. The serial communication device according to any one of claims 1 to 5, wherein the delay amount calculation unit calculates the delay amount based on the start timing of the control signal, the start timing of the transfer data, and the timing specification of the serial communication device.

7. The serial communication device according to any one of claims 1 to 5, further comprising a quality monitoring unit that counts the number of the received plurality of packets and evaluates the quality of the serial communication.

8. A delay amount calculation unit that calculates a delay amount of the start timing of the control signal received in serial communication that transfers a plurality of packets indicating the state of the control signal at a change point of the control signal; a buffer control unit that stores the received transfer data in a buffer; a timing adjustment unit that delays and outputs the transfer data stored in the buffer in accordance with the delay amount; A delay adjustment device having the above.

9. At a change point of a control signal, a serial communication device that transfers a plurality of packets indicating the state of the control signal A delay amount calculation process for calculating a delay amount of the start timing of the received control signal, A buffer control process for storing the received transfer data in a buffer, A timing adjustment process for delaying and outputting the transfer data stored in the buffer in accordance with the delay amount, A serial communication method that executes the above processes.

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