Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device that can be miniaturized while suppressing degradation of breakdown voltage of a capacitor and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises: a substrate that has a first principal surface and a second principal surface being opposite to the first principal surface; an organic stopper layer that is provided above the first principal surface; a first electrode that is provided above the organic stopper layer; an insulation film that is provided above the first electrode; a second electrode that is provided above the insulation film; a first through-hole that penetrates through the substrate and the organic stopper layer to reach the first electrode; and a metal layer that covers the second principal surface and a first inner wall surface of the first through-hole and is electrically connected to the first electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] In a semiconductor integrated circuit such as a monolithic microwave integrated circuit (MMIC), a metal-insulator-metal (MIM) capacitor in which a lower electrode, an insulating film, and an upper electrode are stacked may be formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to miniaturize a semiconductor device, it is conceivable to form a through hole that penetrates a substrate and reaches a lower electrode, and provide a metal layer connected to the lower electrode through the through hole on the back surface of the substrate. However, damage is caused to the lower electrode or the insulating film between the lower electrode and the upper electrode when the through hole is formed. Damage to the lower electrode and the insulating film leads to a decrease in the breakdown voltage of the capacitor. By providing a thick film between the substrate and the lower electrode, damage to the lower electrode and the like can be suppressed. However, in this case, a long time is required for etching the thick film, resulting in a decrease in throughput.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can be miniaturized while suppressing a decrease in the breakdown voltage of a capacitor.

Means for Solving the Problems

[0006] The semiconductor device of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, an organic stopper layer provided above the first main surface, a first electrode provided above the organic stopper layer, an insulating film provided on the first electrode, a second electrode provided on the insulating film, a first through hole that penetrates the substrate and the organic stopper layer and reaches the first electrode, and a metal layer that covers the second main surface and a first inner wall surface of the first through hole and is electrically connected to the first electrode.

Effects of the Invention

[0007] According to the present disclosure, it is possible to miniaturize while suppressing a decrease in the breakdown voltage of a capacitor.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to an aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, an organic stopper layer provided above the first main surface, a first electrode provided above the organic stopper layer, an insulating film provided on the first electrode, a second electrode provided on the insulating film, a first through hole that penetrates the substrate and the organic stopper layer and reaches the first electrode, and a metal layer that covers the second main surface and a first inner wall surface of the first through hole and is electrically connected to the first electrode.

[0011] An organic stopper layer is provided between the substrate and the first electrode, and the organic stopper layer functions as an etching stopper when forming the first through hole in the substrate. Therefore, damage to the first electrode and the insulating film when forming the first through hole in the substrate can be suppressed. For this reason, the semiconductor device can be miniaturized while suppressing a decrease in the breakdown voltage of the MIM capacitor including the first electrode, the insulating film, and the second electrode.

[0012] [2] In [1], it has a semiconductor layer provided on the first main surface, a third electrode provided on the semiconductor layer, and a second through hole that penetrates the substrate and the semiconductor layer and reaches the third electrode. The organic stopper layer is provided on the semiconductor layer. The first through hole penetrates the semiconductor layer. The metal layer may cover the second inner wall surface of the second through hole and be electrically connected to the third electrode. In this case, a semiconductor element such as a transistor including the semiconductor layer and the third electrode and an MMIC including a MIM type capacitor can be configured.

[0013] [3] In [1] or [2], the organic stopper layer may contain at least one selected from the group consisting of polyimide and benzocyclobutene. In this case, it is easy to obtain a desired thickness for the organic stopper layer.

[0014] [4] In any one of [1] to [3], the thickness of the organic stopper layer may be 1 μm or more and 10 μm or less. In this case, while suppressing the time required for etching the organic stopper layer to be short, it is easy for the organic stopper layer to function as an etching stopper during processing of the substrate or the like.

[0015] [5] In any one of [1] to [4], it has an inorganic stopper layer provided between the organic stopper layer and the first electrode, and the first through hole may penetrate the inorganic stopper layer. In this case, good adhesion can be obtained between the organic stopper layer and the first electrode by the inorganic stopper layer. Also, the inorganic stopper layer functions as an etching stopper when the first through hole penetrates the organic stopper layer.

[0016] [6] In [5], the thickness of the inorganic stopper layer may be 20 nm or more and 500 nm or less. In this case, while suppressing the time required for etching the inorganic stopper layer to be short, it is easy for the inorganic stopper layer to function as an etching stopper during processing of the organic stopper layer.

[0017] 〔7〕A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, an organic stopper layer provided above the first main surface, a first electrode provided above the organic stopper layer, an insulating film provided on the first electrode, and a second electrode provided on the insulating film. A step of preparing a structure including the above, a step of forming a first through hole that overlaps the first electrode in a plan view perpendicular to the first main surface, penetrates the substrate, and reaches the organic stopper layer by performing first reactive ion etching, and a step of performing second reactive ion etching to extend the first through hole so as to penetrate the organic stopper layer and reach the first electrode, and a step of forming a metal layer that covers the second main surface and the first inner wall surface of the first through hole and is electrically connected to the first electrode.

[0018] During the first reactive ion etching, the organic stopper layer functions as an etching stopper. Therefore, damage to the first electrode and the insulating film due to the first reactive ion etching can be suppressed. Further, the second reactive ion etching for extending the first through hole can be performed under conditions where damage to the first electrode and the insulating film is less likely to occur. For this reason, the semiconductor device can be miniaturized while suppressing a decrease in the breakdown voltage of the MIM capacitor including the first electrode, the insulating film, and the second electrode.

[0019] [8] In [7], the structure has a semiconductor layer provided on the first main surface and a third electrode provided on the semiconductor layer. The organic stopper layer is provided on the semiconductor layer. The step of performing the first reactive ion etching forms, by performing a third reactive ion etching, a portion that penetrates the substrate of the first through hole and reaches the semiconductor layer, and forms a second through hole that overlaps the third electrode in plan view, penetrates the substrate, and reaches the semiconductor layer. The step of performing the fourth reactive ion etching extends the first through hole so as to penetrate the semiconductor layer and reach the organic stopper layer, and extends the second through hole so as to penetrate the semiconductor layer and reach the third electrode. The metal layer may cover the second inner wall surface of the second through hole and be electrically connected to the third electrode. In this case, a semiconductor device such as a transistor including a semiconductor layer and a third electrode and a MMIC including a MIM type capacitor can be configured.

[0020] [9] In [7] or [8], the structure has an inorganic stopper layer provided between the organic stopper layer and the first electrode. The step of performing the second reactive ion etching may include a step of extending the first through hole so as to penetrate the organic stopper layer and reach the inorganic stopper layer by performing a fifth reactive ion etching, and a step of extending the first through hole so as to penetrate the inorganic stopper layer and reach the first electrode by performing a sixth reactive ion etching. In this case, a good adhesion can be obtained between the organic stopper layer and the first electrode by the inorganic stopper layer. Further, the inorganic stopper layer functions as an etching stopper when the first through hole penetrates the organic stopper layer. Since the inorganic stopper layer may be thin, the sixth reactive ion etching can be performed under conditions where damage to the first electrode and the insulating film is less likely to occur.

[0021]

[10] In [9], in the fifth reactive ion etching, a reactive gas containing oxygen may be used. In this case, the organic stopper layer can be easily etched.

[0022] [Details of Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In the present specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant descriptions. In the following description, an XYZ orthogonal coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the posture of the semiconductor device. Also, depending on the viewing point, the +Z side may be referred to as upward, upper side, or top, and the -Z side may be referred to as downward, lower side, or bottom.

[0023] (Configuration of Semiconductor Device) The embodiment relates to a semiconductor device including a field effect transistor (FET) such as a GaN-based high electron mobility transistor (HEMT) and a MIM capacitor. FIG. 1 is a cross-sectional view showing the semiconductor device according to the embodiment.

[0024] As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a substrate 11, a semiconductor layer 12, a gate electrode 22G, a source electrode 22S, a drain electrode 22D, a lower electrode 41, an insulating film 42, an upper electrode 43, and a back electrode 72.

[0025] The substrate 11 is, for example, a silicon carbide (SiC) substrate. The substrate 11 has a first main surface 11A and a second main surface 11B opposite to the first main surface 11A. The first main surface 11A is above the second main surface 11B (+Z side).

[0026] The semiconductor layer 12 is provided on the first main surface 11A. The semiconductor layer 12 is, for example, a nitride semiconductor layer containing gallium (Ga). The nitride semiconductor layer includes an electron traveling layer (channel layer) and an electron supply layer (barrier layer) that constitute the HEMT.

[0027] The source electrode 22S and the drain electrode 22D are provided on the semiconductor layer 12. The source electrode 22S and the drain electrode 22D are in ohmic contact with the semiconductor layer 12. The semiconductor layer 12 may include a plurality of regrown layers, and the source electrode 22S and the drain electrode 22D may be provided on the regrown layers. The source electrode 22S is an example of a third electrode.

[0028] The semiconductor device 100 has an insulating film 21. The insulating film 21 is provided on the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12, and covers the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12. Note that the insulating film 21 may have an opening above the source electrode 22S and the drain electrode 22D. The insulating film 21 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The insulating film 21 may have a laminate of two or more of these.

[0029] An opening 21G for a gate is formed in the insulating film 21. The opening 21G is between the source electrode 22S and the drain electrode 22D in a plan view perpendicular to the first main surface 11A. Hereinafter, "plan view" means "plan view perpendicular to the first main surface 11A". The gate electrode 22G is provided on the insulating film 21 between the source electrode 22S and the drain electrode 22D in a plan view, and makes a Schottky contact with the semiconductor layer 12 through the opening 21G.

[0030] The semiconductor device 100 has an FET 20 including a semiconductor layer 12, a gate electrode 22G, a source electrode 22S, and a drain electrode 22D. The FET 20 is, for example, a HEMT.

[0031] The semiconductor device 100 further has an insulating film 51, an organic stopper layer 52, an inorganic stopper layer 53, and an interlayer insulating film 54.

[0032] The insulating film 51 is provided on the gate electrode 22G and the insulating film 21, and covers the gate electrode 22G and the insulating film 21. The insulating film 51 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The insulating film 51 may have a laminate of two or more of these. The insulating films 21 and 51 provide good adhesion between the semiconductor layer 12 and the organic stopper layer 52.

[0033] The organic stopper layer 52 is provided on the insulating film 51 away from the FET 20. In other words, the organic stopper layer 52 is provided above the first main surface 11A. The organic stopper layer 52 includes at least one selected from the group consisting of, for example, polyimide and benzocyclobutene (BCB). The thickness of the organic stopper layer 52 is, for example, 1 μm or more and 10 μm or less. The thickness of the organic stopper layer 52 can be measured by observation using a scanning electron microscope (SEM).

[0034] The inorganic stopper layer 53 is provided on the organic stopper layer 52 and the insulating film 51, and covers the organic stopper layer 52 and the insulating film 51. The inorganic stopper layer 53 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The inorganic stopper layer 53 may have a laminate of two or more of these. The thickness of the inorganic stopper layer 53 is, for example, 20 nm or more and 500 nm or less. The thickness of the inorganic stopper layer 53 can be measured by observation using SEM.

[0035] The lower electrode 41 is provided on the inorganic stopper layer 53 above the organic stopper layer 52. In other words, the inorganic stopper layer 53 is provided between the organic stopper layer 52 and the lower electrode 41. For example, in plan view, the contour of the lower electrode 41 is inside the contour of the organic stopper layer 52. The lower electrode 41 has, for example, a titanium (Ti) film and a gold (Au) film thereon. The lower electrode 41 is an example of the first electrode.

[0036] The insulating film 42 is provided on the lower electrode 41 and the inorganic stopper layer 53 and covers the lower electrode 41 and the inorganic stopper layer 53. The insulating film 42 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The insulating film 42 may have a laminate of two or more of these.

[0037] The upper electrode 43 is provided on the insulating film 42 above the organic stopper layer 52. In other words, the insulating film 42 is provided between the lower electrode 41 and the upper electrode 43. For example, in plan view, the contour of the upper electrode 43 is inside the contour of the organic stopper layer 52. The upper electrode 43 has, for example, a titanium (Ti) film and a gold (Au) film thereon. The upper electrode 43 is an example of the second electrode.

[0038] The semiconductor device 100 has a MIM capacitor 40 including the lower electrode 41, the insulating film 42, and the upper electrode 43.

[0039] The interlayer insulating film 54 is provided on the upper electrode 43 and the insulating film 42, and covers the upper electrode 43 and the insulating film 42. For example, the upper surface of the interlayer insulating film 54 may be flattened. An opening 61C that penetrates the interlayer insulating film 54 is formed in the interlayer insulating film 54. The opening 61C reaches the upper electrode 43. An opening 61D that penetrates the interlayer insulating film 54, the insulating film 42, the inorganic stopper layer 53, the insulating film 51, and the insulating film 21 is formed in the interlayer insulating film 54, the insulating film 42, the inorganic stopper layer 53, the insulating film 51, and the insulating film 21. The opening 61D reaches the drain electrode 22D. Note that another opening may be formed in the same manner as the opening 61D, and the opening may reach the source electrode 22S.

[0040] The semiconductor device 100 has wirings 62C and 62D. The wiring 62C is provided on the interlayer insulating film 54 and is in contact with the upper electrode 43 through the opening 61C. The wiring 62D is provided on the interlayer insulating film 54 and is in contact with the drain electrode 22D through the opening 61D.

[0041] A through hole 71S that penetrates the substrate 11 and the semiconductor layer 12 is formed in the substrate 11 and the semiconductor layer 12. The through hole 71S reaches the source electrode 22S. A through hole 71C that penetrates the substrate 11, the semiconductor layer 12, the insulating film 21, the insulating film 51, the organic stopper layer 52, and the inorganic stopper layer 53 is formed in the substrate 11, the semiconductor layer 12, the insulating film 21, the insulating film 51, the organic stopper layer 52, and the inorganic stopper layer 53. The through hole 71C reaches the lower electrode 41. The through hole 71C is an example of a first through hole, and the through hole 71S is an example of a second through hole.

[0042] The back electrode 72 is formed on the second main surface 11B of the substrate 11, the inner wall surface of the through hole 71C, the lower surface of the lower electrode 41, the inner wall surface of the through hole 71S, and the lower surface of the source electrode 22S. The back electrode 72 is in contact with the lower electrode 41 and the source electrode 22S, and covers the second main surface 11B, the inner wall surface of the through hole 71C, and the inner wall surface of the through hole 71S. For example, the back electrode 72 is composed of a gold (Au) layer. The back electrode 72 has, for example, a seed layer and a plating layer. For example, the back electrode 72 is grounded, and a ground potential is applied to the lower electrode 41 and the source electrode 22S. The back electrode 72 is an example of a metal layer.

[0043] (Method of manufacturing a semiconductor device) Next, a method of manufacturing the semiconductor device 100 according to the embodiment will be described. FIGS. 2 to 10 are cross-sectional views showing the method of manufacturing the semiconductor device 100 according to the embodiment.

[0044] First, as shown in FIG. 2, for example, by a metal organic chemical vapor deposition (MOCVD) method, a semiconductor layer 12 is formed on the substrate 11. The substrate 11 has a first main surface 11A and a second main surface 11B opposite to the first main surface 11A.

[0045] Next, a source electrode 22S and a drain electrode 22D are formed on the semiconductor layer 12. In the formation of the source electrode 22S and the drain electrode 22D, growth of a metal film is performed by a vapor deposition method using a growth mask, and then the growth mask is removed. That is, the source electrode 22S and the drain electrode 22D can be formed, for example, by vapor deposition and lift-off. Next, an insulating film 21 is formed on the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12. The insulating film 21 can be formed, for example, by a plasma CVD method or a sputtering method. The insulating film 21 covers the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12.

[0046] Next, an opening 21G is formed in the insulating film 21. In forming the opening 21G, for example, reactive ion etching (RIE) using a resist pattern as a mask is performed. For etching the insulating film 21, a reactive gas containing fluorine (F) or chlorine (Cl) is used. Next, a gate electrode 22G is formed on the insulating film 21. In forming the gate electrode 22G, growth of a metal film is performed by a vapor deposition method using a growth mask, and then the growth mask is removed. That is, the gate electrode 22G can be formed, for example, by vapor deposition and lift-off. The gate electrode 22G makes a Schottky contact with the semiconductor layer 12 through the opening 21G.

[0047] Next, as shown in FIG. 3, an insulating film 51 is formed on the gate electrode 22G and the insulating film 21. The insulating film 51 can be formed, for example, by plasma CVD method or sputtering method. The insulating film 51 covers the gate electrode 22G and the insulating film 21. Next, an organic stopper layer 52 is formed on the insulating film 51. In other words, the organic stopper layer 52 is formed above the first main surface 11A. The organic stopper layer 52 is formed on the insulating film 51 away from the FET 20. The organic stopper layer 52 contains at least one selected from the group consisting of, for example, polyimide or benzocyclobutene. The organic stopper layer 52 can be formed, for example, by spin coating, exposure, development, and baking of photosensitive polyimide or photosensitive benzocyclobutene. The organic stopper layer 52 may be formed by spin coating, baking, and etching of non-photosensitive polyimide or non-photosensitive benzocyclobutene.

[0048] Next, as shown in FIG. 4, an inorganic stopper layer 53 is formed on the organic stopper layer 52 and the insulating film 51. The inorganic stopper layer 53 can be formed, for example, by plasma CVD method or sputtering method. The inorganic stopper layer 53 covers the organic stopper layer 52 and the insulating film 51.

[0049] Next, as shown in FIG. 5, above the organic stopper layer 52, the lower electrode 41 is formed on the inorganic stopper layer 53. In other words, the inorganic stopper layer 53 is formed between the organic stopper layer 52 and the lower electrode 41. In forming the lower electrode 41, for example, a metal film is formed over the entire surface, and then the metal film is etched. The etching may be either dry etching or wet etching. The lower electrode 41 may be formed by vapor deposition and lift-off of the metal film. Next, an insulating film 42 is formed on the lower electrode 41 and the inorganic stopper layer 53. The insulating film 42 can be formed, for example, by plasma CVD method or sputtering method. The insulating film 42 covers the lower electrode 41 and the inorganic stopper layer 53. Next, above the organic stopper layer 52, the upper electrode 43 is formed on the insulating film 42. In other words, the insulating film 42 is formed between the lower electrode 41 and the upper electrode 43. In forming the upper electrode 43, for example, a metal film is formed over the entire surface, and then the metal film is etched. The etching may be either dry etching or wet etching. The upper electrode 43 may be formed by vapor deposition and lift-off of the metal film.

[0050] Next, as shown in FIG. 6, an interlayer insulating film 54 is formed on the upper electrode 43 and the insulating film 42. The interlayer insulating film 54 can be formed, for example, by plasma CVD method or sputtering method. The interlayer insulating film 54 covers the upper electrode 43 and the insulating film 42. The upper surface of the interlayer insulating film 54 may be planarized. Next, openings 61C and 61D are formed. The opening 61C penetrates the interlayer insulating film 54 and reaches the upper electrode 43. The opening 61D penetrates the interlayer insulating film 54, the insulating film 42, the inorganic stopper layer 53, the insulating film 51, and the insulating film 21 and reaches the drain electrode 22D. Note that another opening may be formed in the same manner as the opening 61D, and the opening may reach the source electrode 22S.

[0051] Next, wirings 62C and 62D are formed on the interlayer insulating film 54. The wiring 62C contacts the upper electrode 43 through the opening 61C, and the wiring 62D contacts the drain electrode 22D through the opening 61D. Note that, similar to the opening 61D, another opening reaching the source electrode 22S may be provided, and a wiring contacting the source electrode 22S through the opening may be formed on the interlayer insulating film 54 in the same manner as the wiring 62D. That is, another opening similar to the opening 61D may be provided above the source electrode 22S, and a wiring may be formed on the interlayer insulating film 54 in the same manner as the wiring 62D through the opening.

[0052] In this way, a structure 80 including the FET 20 and the MIM capacitor 40 is prepared.

[0053] Next, as shown in FIG. 7, by performing RIE, through holes 71C and 71S penetrating the substrate 11 are formed in the substrate 11. The through hole 71C is formed such that the contour of the through hole 71C is located inside the contour of the organic stopper layer 52 in plan view, and the through hole 71S is formed such that the contour of the through hole 71S is located inside the contour of the source electrode 22S in plan view. The through hole 71C overlaps the lower electrode 41 in plan view and reaches the semiconductor layer 12. The through hole 71S overlaps the source electrode 22S in plan view and reaches the semiconductor layer 12. In forming the through holes 71C and 71S, RIE of the substrate 11 is performed using a resist pattern as a mask. For etching the substrate 11, reactive gases containing fluorine (F) such as carbon tetrafluoride (CF 4 ) sulfur hexafluoride (SF 6 ), fluoromethane (CH x F y ) are used. As a result of this RIE, the semiconductor layer 12 is exposed from the through holes 71C and 71S. The through holes 71C and 71S may penetrate into the semiconductor layer 12. The RIE of the substrate 11 is an example of the third reactive ion etching.

[0054] Next, as shown in FIG. 8, by performing RIE, the through-hole 71C is extended to penetrate the semiconductor layer 12, the insulating film 21, and the insulating film 51 and reach the organic stopper layer 52, and the through-hole 71S is extended to penetrate the semiconductor layer 12 and reach the source electrode 22S. For the etching of the semiconductor layer 12, the insulating film 21, and the insulating film 51, reactive gases containing chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ), etc. are used. This reactive gas does not contain oxygen (O 2 ). As a result of this RIE, the organic stopper layer 52 is exposed from the through-hole 71C, and the source electrode 22S is exposed from the through-hole 71S. In this RIE, the etching rate of the organic stopper layer 52 is about 1 / 3 times the etching rate of the semiconductor layer 12, the insulating film 21, and the insulating film 51. That is, the organic stopper layer 52 shows an etching selectivity of about 3 with respect to the insulating film 21 and the insulating film 51. The through-hole 71C may enter the organic stopper layer 52. In this RIE, the organic stopper layer 52 functions as an etching stopper. Although the source electrode 22S is also exposed to the etching atmosphere, the source electrode 22S is not etched in the RIE using a reactive gas containing chlorine (Cl). The RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51 is an example of the fourth reactive ion etching. The third reactive ion etching and the fourth reactive ion etching are included in the first reactive ion etching.

[0055] Note that when the semiconductor layer 12 is sufficiently thin or the like, the RIE of the substrate 11 and the RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51 may be continuously performed without changing the reactive gas from the etching of the substrate 11.

[0056] Next, as shown in FIG. 9, by performing RIE, the through-hole 71C is extended to penetrate the organic stopper layer 52 and reach the inorganic stopper layer 53. For the etching of the organic stopper layer 52, oxygen (O 2) A reactive gas containing is used. As a result of this RIE, the inorganic stopper layer 53 is exposed from the through hole 71C. In this RIE, the etching rate of the inorganic stopper layer 53 is about 1 / 100 to 1 / 50 times the etching rate of the organic stopper layer 52. That is, the inorganic stopper layer 53 shows an etching selectivity of about 50 to 100 with respect to the organic stopper layer 52. The through hole 71C may penetrate into the inorganic stopper layer 53. In this RIE, the inorganic stopper layer 53 functions as an etching stopper. Note that the source electrode 22S is also exposed to the etching atmosphere, but in the RIE using a reactive gas containing oxygen (O 2 ) the source electrode 22S is not etched. The RIE of the organic stopper layer 52 is an example of the fifth reactive ion etching.

[0057] Next, as shown in FIG. 10, by performing RIE, the through hole 71C is extended so as to penetrate the inorganic stopper layer 53 and reach the lower electrode 41. For the etching of the inorganic stopper layer 53, a reactive gas containing fluorine (F) such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), fluoromethane (CH x F y ), or a reactive gas containing chlorine (Cl) such as chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ) is used. A reactive gas containing fluorine (F) and chlorine (Cl) may be used for the etching of the inorganic stopper layer 53. This reactive gas is oxygen (O 2It does not include ). In the RIE of the inorganic stopper layer 53, the voltage for generating plasma and the voltage for attracting plasma are made lower than those in the RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51. As a result of this RIE, the lower electrode 41 is exposed from the through hole 71C. The through hole 71C may penetrate into the lower electrode 41. Although the source electrode 22S is also exposed to the etching atmosphere, the source electrode 22S is not etched in the RIE using a reactive gas containing fluorine (F), a reactive gas containing chlorine (Cl), or a reactive gas containing fluorine (F) and chlorine (Cl). The RIE of the inorganic stopper layer 53 is an example of the sixth reactive ion etching. The fifth reactive ion etching and the sixth reactive ion etching are included in the second reactive ion etching.

[0058] Next, a back surface electrode 72 is formed (see FIG. 1). The back surface electrode 72 is formed on the second main surface 11B of the substrate 11, the inner wall surface of the through hole 71C, the lower surface of the lower electrode 41, the inner wall surface of the through hole 71S, and the lower surface of the source electrode 22S.

[0059] In this way, the semiconductor device 100 according to the embodiment can be manufactured.

[0060] In the semiconductor device 100 according to the embodiment, an organic stopper layer 52 is provided between the substrate 11 and the lower electrode 41, and the organic stopper layer 52 functions as an etching stopper when the through hole 71C is formed in the substrate 11 and the semiconductor layer 12. Therefore, even if the RIE when forming the through hole 71C in the substrate 11 and the semiconductor layer 12 is performed at high power, damage to the lower electrode 41 and the insulating film 42 can be suppressed. For this reason, miniaturization is possible by forming the through hole 71C so as to overlap the lower electrode 41 in plan view while suppressing a decrease in the breakdown voltage of the MIM capacitor 40.

[0061] Since the MIM capacitor 40 and the FET 20 are provided on the substrate 11, an MMIC can be configured. Also, a part of the through hole 71C can be formed simultaneously with the through hole 71S.

[0062] Since the organic stopper layer 52 contains at least one selected from the group consisting of polyimide and benzocyclobutene, it is easy to obtain a desired thickness for the organic stopper layer 52. That is, such an organic stopper layer 52 can be easily formed thick and can be easily patterned. Further, since internal stress hardly remains in the organic stopper layer 52, the organic stopper layer 52 is hardly peeled off, and stress from the organic stopper layer 52 hardly acts on the FET 20. When the thickness of the organic stopper layer 52 is 1 μm or more and 10 μm or less, it is easy to make the organic stopper layer 52 function as an etching stopper while suppressing the time required for etching the organic stopper layer 52. The organic stopper layer 52 having a thickness of 1 μm or more and 10 μm or less can be penetrated by etching in a short time. Depending on the RIE conditions during the formation of the through hole 71C, the thickness of the organic stopper layer 52 may be 1 μm or more and 5 μm or less, or may be 1 μm or more and 3 μm or less. Further, by using a reactive gas containing oxygen, the organic stopper layer 52 can be easily etched.

[0063] By providing the inorganic stopper layer 53, good adhesion between the organic stopper layer 52 and the lower electrode 41 can be obtained. Further, by providing the inorganic stopper layer 53, it is easy to suppress damage to the lower electrode 41 during RIE of the organic stopper layer 52. When the thickness of the inorganic stopper layer 53 is 20 nm or more and 500 nm or less, it is easy to make the inorganic stopper layer 53 function as an etching stopper while suppressing the time required for etching the inorganic stopper layer 53. The inorganic stopper layer 53 having a thickness of 20 nm or more and 500 nm or less can be penetrated in a short time even by low-power etching that hardly causes damage to the lower electrode 41. Further, stress from such an inorganic stopper layer 53 can be made hardly act on the FET 20. The thickness of the inorganic stopper layer 53 may be 30 nm or more and 400 nm or less, or may be 50 nm or more and 350 nm or less.

[0064] Note that the reactive gas used for RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51, and the reactive gas used for RIE of the inorganic stopper layer 53 are oxygen (O 2By not including ), etching of the organic stopper layer 52 in these RIEs can be suppressed.

[0065] The FET 20 may be of the MIS (metal insulator semiconductor) type instead of the Schottky type. The present disclosure can also be applied to a semiconductor device that does not include the FET 20. That is, the semiconductor layer 12, the insulating film 21, etc. that constitute the FET 20 may not be present. Further, the insulating film 51 and the inorganic stopper layer 53 are not essential either, and even when the insulating film 51 or the inorganic stopper layer 53 or both of them are not provided, the semiconductor device can be miniaturized while suppressing a decrease in the breakdown voltage of the capacitor.

[0066] Although the embodiments have been described in detail above, the present disclosure is not limited to specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Explanation of Reference Numerals

[0067] 11: Substrate 11A: First main surface 11B: Second main surface 12: Semiconductor layer 20: FET 21: Insulating film 21G: Opening 22D: Drain electrode 22G: Gate electrode 22S: Source electrode 40: MIM type capacitor 41: Lower electrode 42: Insulating film 43: Upper electrode 51: Insulating film 52: Organic stopper layer 53: Inorganic stopper layer 54: Interlayer insulating film 61C, 61D: Openings 62C, 62D: Wires 71C, 71S: Through holes 72: Back surface electrode 80: Structure 100: Semiconductor device

Claims

1. A substrate having a first main surface and a second main surface opposite to the first main surface; An organic stopper layer provided above the first main surface; A first electrode provided above the organic stopper layer; An insulating film provided on the first electrode; A second electrode provided on the insulating film; A first through hole that penetrates the substrate and the organic stopper layer and reaches the first electrode; A metal layer that covers the second main surface and the first inner wall surface of the first through hole and is electrically connected to the first electrode; A semiconductor device having the above.

2. A semiconductor layer provided on the first main surface; A third electrode provided on the semiconductor layer; A second through hole that penetrates the substrate and the semiconductor layer and reaches the third electrode; Having The organic stopper layer is provided above the semiconductor layer, The first through hole penetrates the semiconductor layer, The semiconductor device according to claim 1, wherein the metal layer covers the second inner wall surface of the second through hole and is electrically connected to the third electrode.

3. The semiconductor device according to claim 1 or claim 2, wherein the organic stopper layer contains at least one selected from the group consisting of polyimide and benzocyclobutene.

4. The semiconductor device according to claim 1 or claim 2, wherein the thickness of the organic stopper layer is 1 μm or more and 10 μm or less.

5. Having an inorganic stopper layer provided between the organic stopper layer and the first electrode, The semiconductor device according to claim 1 or claim 2, wherein the first through hole penetrates the inorganic stopper layer.

6. The semiconductor device according to claim 5, wherein the thickness of the inorganic stopper layer is 20 nm or more and 500 nm or less.

7. A step of preparing a structure including a substrate having a first main surface and a second main surface opposite to the first main surface, an organic stopper layer provided above the first main surface, a first electrode provided above the organic stopper layer, an insulating film provided on the first electrode, and a second electrode provided on the insulating film; A step of forming a first through hole that overlaps the first electrode in a plan view perpendicular to the first main surface, penetrates the substrate, and reaches the organic stopper layer by performing first reactive ion etching; A step of extending the first through hole so as to penetrate the organic stopper layer and reach the first electrode by performing second reactive ion etching; A step of forming a metal layer that covers the second main surface and the first inner wall surface of the first through hole and is electrically connected to the first electrode; A method of manufacturing a semiconductor device having the same. **Claim 8** The structure includes a semiconductor layer provided on the first main surface and a third electrode provided on the semiconductor layer, and the organic stopper layer is provided on the semiconductor layer. The step of performing the first reactive ion etching is as follows: By performing a third reactive ion etching, a portion that penetrates the substrate of the first through hole and reaches the semiconductor layer is formed, and in a plan view, a second through hole that overlaps the third electrode, penetrates the substrate, and reaches the semiconductor layer is formed. By performing a fourth reactive ion etching, the first through hole is extended to penetrate the semiconductor layer and reach the organic stopper layer, and the second through hole is extended to penetrate the semiconductor layer and reach the third electrode. having The method of manufacturing a semiconductor device according to claim 7, wherein the metal layer covers a second inner wall surface of the second through hole and is electrically connected to the third electrode. **Claim 9** The structure has an inorganic stopper layer provided between the organic stopper layer and the first electrode. The step of performing the second reactive ion etching is as follows: By performing a fifth reactive ion etching, the first through hole is extended to penetrate the organic stopper layer and reach the inorganic stopper layer. The method of manufacturing a semiconductor device according to claim 7 or claim 8, further comprising a step of performing a sixth reactive ion etching to extend the first through hole to penetrate the inorganic stopper layer and reach the first electrode. **Claim 10** The method of manufacturing a semiconductor device according to claim 9, wherein a reactive gas containing oxygen is used in the fifth reactive ion etching.

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