Image sensor

Abstract

To provide an image sensor capable of realizing clear image quality.SOLUTION: An image sensor is provided, including: a substrate having a first surface and a second surface opposite to the first surface; and a pixel separation structure disposed in the substrate, the pixel separation structure separating pixels from each other. The pixels include first and second pixels spaced apart from each other along a first direction. The pixel separation structure includes: first silicon-containing patterns surrounding each of the first and second pixels when viewed in a plan view and being spaced apart from each other; and a second silicon-containing pattern extending between the first and second pixels and connecting the first silicon-containing patterns to each other. The second silicon-containing pattern includes side portions adjoining the first silicon-containing patterns, and a connecting portion spaced apart from the first silicon-containing patterns and connecting the side portions.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001] The present invention relates to an image sensor.

Background Art

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor can be classified into a CCD (Charge coupled device) type and a CMOS (Complementary metal oxide semiconductor) type. The CMOS type image sensor is abbreviated as CIS (CMOS image sensor). The CIS includes a plurality of pixels two-dimensionally arranged. Each of the pixels includes a photodiode PD (photodiode). The photodiode serves to convert incident light into an electrical signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide an image sensor capable of realizing a clear image quality.

[0005] The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned should be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0006] An image sensor according to an embodiment of the present invention for achieving the above object includes a substrate having a first surface and a second surface opposite to the first surface, and a pixel separation portion disposed in the substrate for separating pixels from each other. The pixels include a first pixel and a second pixel spaced apart from each other along a first direction. The pixel separation portion surrounds each of the first pixel and the second pixel in a plan view, and includes a first silicon-containing pattern spaced apart from each other, and a second silicon-containing pattern disposed between the first pixel and the second pixel for connecting the first silicon-containing patterns. The second silicon-containing pattern includes a side wall portion in contact with the first silicon-containing pattern, and a connection portion spaced apart from the first silicon-containing pattern for connecting the side wall portions.

[0007] An image sensor according to an embodiment of the present invention includes a substrate having a first surface and a second surface opposite to the first surface, a transistor disposed on the first surface, and a pixel separation portion disposed in the substrate for separating pixels from each other. The pixels include a first pixel to a fourth pixel arranged along a clockwise direction. The pixel separation portion includes a first silicon-containing pattern surrounding each of the first pixel and the second pixel in a plan view and spaced apart from each other, a second silicon-containing pattern for connecting the adjacent first silicon-containing patterns, and a first embedded insulating pattern spaced apart from the first silicon-containing pattern via the second silicon-containing pattern. Between a corner of the third pixel adjacent to the first pixel and a corner of the first pixel, the first embedded insulating pattern penetrates the second silicon-containing pattern.

[0008] An image sensor according to another embodiment of the present invention includes a substrate having a first surface and a second surface opposite to the first surface, and a pixel separation portion disposed within the substrate for separating pixels from each other. The pixels include first and second pixels spaced apart from each other along a first direction. The pixel separation portion is an embedded insulating pattern having a first empty space therein, which is interposed between the first and second pixels and is vertically elongated, and a silicon-containing pattern conformally covering the inner wall of the embedded insulating pattern in the first empty space and having a 'U'-shaped cross-section and having a second empty space therein, and a second embedded insulating pattern disposed in the second empty space.

Advantages of the Invention

[0009] In the image sensor of the present invention, a first silicon-containing pattern and / or a second silicon-containing pattern serving as a common bias exist in a liner form within the pixel separation portion. Therefore, the portion occupied by silicon in the pixel separation portion can be relatively small. Also, at the intersection between four pixels, the second silicon-containing pattern is penetrated by the second embedded insulating pattern, and the second silicon-containing pattern does not exist at this point. Therefore, light absorption and light loss due to silicon can be reduced, and a high-sensitivity image sensor with a clear image quality can be realized.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0012] FIG. 1 is a block diagram for explaining an image sensor according to an embodiment of the present invention.

[0013] Referring to FIG. 1, the image sensor can include an Active Pixel Sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a Correlated Double Sampler (CDS) 1006, an Analog to Digital Converter (ADC) 1007, and an input / output buffer (I / O buffer) 1008.

[0014] The Active Pixel Sensor array 1001 includes a plurality of unit pixels arranged two-dimensionally and can convert an optical signal into an electrical signal. The Active Pixel Sensor array 1001 can be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal from the row driver 1003. Also, the converted electrical signal can be provided to the Correlated Double Sampler 1006.

[0015] The row driver 1003 can provide a plurality of driving signals for driving a number of unit pixels to the Active Pixel Sensor array 1001 according to the result decoded by the row decoder 1002. When the unit pixels are arranged in a matrix shape, the driving signals can be provided for each row.

[0016] The timing generator 1005 can provide a timing signal and a control signal to the row decoder 1002 and the column decoder 1004.

[0017] The correlated double sampler (CDS) 1006 can receive and hold and sample the electrical signals generated by the active pixel sensor array 1001. The correlated double sampler 1006 can double sample a specific noise level and a signal level by an electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0018] The analog-to-digital converter (ADC) 1007 can convert an analog signal corresponding to the difference level output from the correlated double sampler 1006 into a digital signal and output it.

[0019] The input / output buffer 1008 can latch a digital signal, and the latched signal can sequentially output the digital signal to a video signal processing unit (not shown) according to the decoding result in the column decoder 1004.

[0020] FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention.

[0021] Referring to FIGS. 1 and 2, the active pixel sensor array 1001 includes a plurality of unit pixels PX, and the unit pixels PX can be arranged in a matrix shape. Each unit pixel PX can include a transmission transistor TX. Each unit pixel PX can further include logic transistors RX, SX, DX. The logic transistor can be a reset transistor RX, a selection transistor SX, or a source follower transistor DX. The transmission transistor TX can include a transmission gate TG. Each unit pixel PX can further include a photoelectric conversion unit PD and a floating diffusion region FD. The logic transistors RX, SX, DX can be shared among a plurality of unit pixels PX with each other.

[0022] The photoelectric conversion unit PD can generate and accumulate photo charges in proportion to the amount of light incident from the outside. The photoelectric conversion unit PD can include a photodiode, a phototransistor, a photogate, a PIN diode, and combinations thereof. The transmission transistor TX can transmit the charges generated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD can cumulatively store the charges transmitted from the photoelectric conversion unit PD. The source follower transistor DX can be controlled according to the amount of photo charges accumulated in the floating diffusion region FD.

[0023] The reset transistor RX can periodically reset the charges accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX can be connected to the floating diffusion region FD, and the source electrode can be connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX can be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD can be discharged and the floating diffusion region FD can be reset.

[0024] The source follower transistor DX including the source follower gate electrode SF can serve as a source follower buffer amplifier. The source follower transistor DX can amplify the potential change in the floating diffusion region FD and output it to the output line Vout.

[0025] The selection transistor SX including the selection gate electrode SEL can select the unit pixel PX to be read out in row units. When the selection transistor SX is turned on, the power supply voltage VDD can be applied to the drain electrode of the source follower transistor DX.

[0026] FIG. 3A is a top plan view of an image sensor according to an embodiment of the present invention. FIG. 3B is a cross-sectional view of the image sensor cut along lines A-A', B-B', and C-C' in FIG. 3A according to an embodiment of the present invention. FIG. 4 is an enlarged view of 'P4' in FIG. 3B.

[0027] Referring to FIGS. 3A, 3B, and 4, an image sensor 500 according to an embodiment of the present invention includes a first substrate 1. The first substrate 1 can be, for example, a single-crystalline silicon wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. The first substrate 1 can be doped, for example, with impurities of a first conductivity type. For example, the first conductivity type can be P-type. The first substrate 1 includes a front surface 1a and a back surface 1b on opposite sides of each other. In this specification, the front surface 1a can be referred to as the first surface 1a, and the back surface 1b can also be referred to as the second surface 1b. The first substrate 1 can include a plurality of unit pixels PX.

[0028] The unit pixel PX can include first to fourth pixels PX(1) to PX(4) along the clockwise direction. The first and second pixels PX(1), PX(2) can be arranged in parallel along a first direction X. The fourth and first pixels PX(4), PX(1) can be arranged in parallel along a second direction Y intersecting the first direction X. The first and third pixels PX(1), PX(3) can be arranged in parallel along a third direction Z intersecting both the first direction X and the second direction Y.

[0029] A pixel isolation part DTI is arranged on the first substrate 1 to separate / limit the unit pixel PX. The pixel isolation part DTI can have a mesh shape in a plan view. The pixel isolation part DTI can penetrate the first substrate 1. The aspect ratio of the pixel isolation part DTI can be 50 to 300.

[0030] Referring to FIGS. 3A and 3B, the pixel isolation portion DTI can include first to third isolation portions P1 to P3 in a plan view. The first isolation portion P1 is interposed between the first and second pixels PX(1) and PX(2) and can be adjacent to the edges (or corners) of the first and second pixels PX(1) and PX(2). The second isolation portion P2 is interposed between the corners of the first and third pixels PX(1) and PX(3) adjacent in the third direction (Z). The third isolation portion P3 is interposed between the centers of the first and second pixels PX(1) and PX(2). The first isolation portion P1 can have a first width W1 in the first direction X. The second isolation portion P2 can have a second width W2 in the third direction Z. The third isolation portion P3 can have a third width W3 in the first direction X. The third width W3 can be larger than the first width W1 and smaller than the second width W2. The side walls of the pixel isolation portion DTI can have a concavo-convex structure.

[0031] Referring to FIGS. 3A and 3B, the pixel isolation portion DTI is located in a deep trench 22 formed from the front surface 1a to the back surface 1b of the first substrate 1. The deep trench 22 includes first to third deep trenches 22(1) to 22(3). The first separation portion P1 is disposed in the first deep trench 22(1). The second separation portion P2 is disposed in the second deep trench 22(2). The third separation portion P3 is disposed in the third deep trench 22(3).

[0032] Referring to FIGS. 3A, 3B, and 4, the first to third separation portions P1 to P3 each include an insulating liner pattern 12 covering the inner wall of the deep trench 22 and a first silicon-containing pattern 13 covering its side wall. The insulating liner pattern 12 and the first silicon-containing pattern 13 can each surround the unit pixel PX in a planar manner. The first silicon-containing pattern 13 is formed in a liner form. The first silicon-containing pattern 13 can be formed of a boron-doped silicon film. Alternatively, the first silicon-containing pattern 13 can be formed of B-doped Silicon germanium, SiC, or SiGe:C. The insulating liner pattern 12 is SiO2 , Si 3 N 4 It can have at least one single-layer or multi-layer structure among SiCN, SiOCN, and SiON. The insulating liner pattern 12 can have a thickness of 10 Å to 2000 Å.

[0033] The first to third separation parts P1 to P3 can further include a first embedded insulating pattern 14, a second silicon-containing pattern 15, a second embedded insulating pattern 21, and a third embedded insulating pattern 16. The second silicon-containing pattern 15 can be formed of a silicon film doped or undoped with boron. Alternatively, the second silicon-containing pattern 15 can be formed of Silicon germanium, SiC, or SiGe:C doped or undoped with boron.

[0034] The insulating liner pattern 12, the first embedded insulating pattern 14, the second embedded insulating pattern 21, and the third embedded insulating pattern 16 can be formed of an insulating material having a refractive index different from that of the first silicon-containing pattern 13. The first embedded insulating pattern 14 and the second embedded insulating pattern 21 can each independently have at least one single-layer or multi-layer structure among HARP (High Aspect Ratio Process) oxide (i.e., Thermal non-plasam-based CVD oxide), HDP (High density plasma) oxide, PTEOS (Plasma Tetraethyloxysilane), LTO (Low temperature oxide), MTO (Medium temperature oxide), and HTO (High temperature oxide). The third embedded insulating pattern 16 can have at least one single-layer or multi-layer structure among ALD oxide, FCVD (flowable chemical vapor deposition) oxide, TOSZ (Tonen SilaZene), HDP oxide, HARP oxide, and PTEOS.

[0035] Referring to FIGS. 3A, 3B, and 4, the first embedded insulating pattern 14 covers the upper sidewalls and the lower sidewalls of the first silicon-containing pattern 13. Alternatively, the first embedded insulating pattern 14 can cover only the lower sidewalls of the first silicon-containing pattern 13. The first embedded insulating pattern 14 can have a first empty space 311 inside. The sidewalls of the middle portion of the first silicon-containing pattern 13 can be exposed to the first empty space 311 of the first embedded insulating pattern 14. That is, the first embedded insulating pattern 14 can expose the sidewalls of the middle portion of the first silicon-containing pattern 13 without covering them. In the first deep trench 22(1) and the third deep trench 22(3), the first embedded insulating pattern 14 can be separated into a plurality of parts. The upper surface of the first embedded insulating pattern 14 adjacent to the front surface 1a of the first substrate 1 can be recessed.

[0036] Referring to FIGS. 3A, 3B, and 4, the second silicon-containing pattern 15 is located in the first empty space 311 of the first embedded insulating pattern 14. The second silicon-containing pattern 15 can have a 'U'-shaped cross-section. The second silicon-containing pattern 15 can connect the first silicon-containing patterns 13 facing each other in the first deep trench 22(1) and the third deep trench 22(3). The second silicon-containing pattern 15 can be formed in a liner form (linearly). The second silicon-containing pattern 15 can include a side part (15(a)) in contact with the first silicon-containing pattern 13 and a connecting part (15(b)) spaced apart from the first silicon-containing pattern 13 and connecting the side part 15(a). Each of the side parts 15(a) can be bent so as to protrude toward the side surface of the substrate and have an arc shape. The connecting part 15(b) is in contact with the first embedded insulating pattern 14. The first embedded insulating pattern 14 is interposed between the connecting part 15(b) and the first silicon-containing pattern 13. The lower surface of the connecting part 15(b) can protrude toward the front surface 1a of the first substrate 1 and be rounded.

[0037] A negative bias voltage can be applied to the first silicon-containing pattern 13 and the second silicon-containing pattern 15. The first silicon-containing pattern 13 can serve as a common bias line. Therefore, holes that can exist on the surface of the first substrate 1 in contact with the pixel isolation part DTI can be captured to improve dark current characteristics.

[0038] In the C-C’ cross-section of FIG. 3B, within the second deep trench 22(2), the second silicon-containing pattern 15 does not connect the first silicon-containing patterns 13 facing each other.

[0039] Referring to FIGS. 3A, 3B, and 4, within the first deep trench 22(1) and the third deep trench 22(3), the second silicon-containing pattern 15 can have a hollow shell shape. That is, the second silicon-containing pattern 15 can have a second empty space 331. A second embedded insulating pattern 21 is disposed within the second empty space 331 of the second silicon-containing pattern 15. In the C-C’ cross-section of FIG. 3B, within the second deep trench 22(2), the second embedded insulating pattern 21 can penetrate the second silicon-containing pattern 15. A void region VD can be disposed inside the second embedded insulating pattern 21.

[0040] In the image sensor 500 according to the present invention, the second silicon-containing pattern 15 does not exist at the center of the second deep trench 22(2) having the widest width, and instead, the second embedded insulating pattern 21 and the void region VD can be disposed. Therefore, light absorption by the second silicon-containing pattern 15 can be minimized to reduce light loss.

[0041] The third embedded insulating pattern 16 is located between the front surface 1a of the first substrate 1 and the first embedded insulating pattern 14. The third embedded insulating pattern 16 can be separated from the first and second silicon-containing patterns 13, 15.

[0042] FIG. 5A is a plan view of the image sensor at the first level LV1 of FIG. 3B. The cross-sectional view of the image sensor cut along line A-A', B-B', and C-C' of FIG. 5A may be the same as that of FIG. 3B. FIG. 5B is an enlarged view of the 'P5' portion of FIG. 3B.

[0043] Referring to FIGS. 3B, 5A, and 5B, at the first level LV1, the void region VD exists in all of the first to third portions P1 to P3 of the pixel isolation part DTI and can be connected to each other. In this example, the upper end of the void region VD can be separated from the back surface 1b of the first substrate 1. The thickness of the second embedded insulating pattern 21 in the second deep trench 22(2) is thicker than the thickness of the second embedded insulating pattern 21 in the first deep trench 22(1) and the third deep trench 22(3).

[0044] FIGS. 6A to 6C are enlarged views of 'P6' of FIG. 3B according to an embodiment of the present invention.

[0045] Referring to FIG. 6A, the first silicon-containing pattern 13 can have a first thickness T1. The second silicon-containing pattern 15 can have a second thickness T2. The second thickness T2 can be the same as or different from the first thickness T1. For example, the second thickness T2 can be larger than the first thickness T1. The first silicon-containing pattern 13 can be doped with a first impurity (e.g., boron) at a first concentration. The second silicon-containing pattern 15 can be doped with a first impurity (e.g., boron) at a second concentration or may not be doped at all. The second concentration can be the same as or smaller than the first concentration. Inside the second silicon-containing pattern 15, the concentration of the first impurity (e.g., boron) can decrease as it approaches the second embedded insulating pattern 21. The smaller the doping concentration of boron in the second silicon-containing pattern 15, the more the light absorption amount by the second silicon-containing pattern 15 can be reduced. Therefore, light loss can be reduced, the light reception rate can be improved, and a clear image can be realized.

[0046] Alternatively, referring to FIG. 6B, a native oxide film 11 can be disposed between the first silicon-containing pattern 13 and the second silicon-containing pattern 15. The native oxide film 11 can have a third thickness T3. The third thickness T3 can preferably be 1 Å to 5 Å. Since the third thickness T3 is as thin as 5 Å or less, the first silicon-containing pattern 13 and the second silicon-containing pattern 15 can be electrically connected to each other.

[0047] Alternatively, referring to FIG. 6C, the first silicon-containing pattern 13 can include first silicon grains G1 having a first average diameter DA1. The second silicon-containing pattern 15 can include second silicon grains G2 having a second average diameter DA2. The second average diameter DA2 can be larger than the first average diameter DA1. The density of the first silicon grains G1 in the first silicon-containing pattern 13 can be larger than the density of the second silicon grains G2 in the second silicon-containing pattern 15.

[0048] In the first substrate 1 of the unit pixel PX, a photoelectric conversion unit PD can be disposed respectively. The photoelectric conversion unit PD can be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type can be, for example, N-type. The N-type impurities doped in the photoelectric conversion unit PD can form a PN junction with the P-type impurities doped in the surrounding first substrate 1 to provide a photodiode.

[0049] In the first substrate 1, an element isolation portion STI adjacent to the front surface 1a can be disposed. The element isolation portion STI can have a single film or a multiple film structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The element isolation portion STI can be penetrated by a pixel isolation portion DTI. The element isolation portion STI can limit an active region ACT adjacent to the front surface 1a in each unit pixel PX. The active region ACT can be provided for the transistors TX, RX, DX, SX in FIG. 2.

[0050] A transmission gate TG can be arranged on the front surface 1a of the first substrate 1 in each unit pixel PX. A part of the transmission gate TG can extend into the first substrate 1. The transmission gate TG is of the Vertical type. Alternatively, the transmission gate TG may be of the Planar type which does not extend into the first substrate 1 and has a flat shape. A gate insulating film Gox can be interposed between the transmission gate TG and the first substrate 1. A floating diffusion region FD can be arranged in the first substrate 1 on one side of the transmission gate TG. For example, impurities of the second conductivity type can be doped into the floating diffusion region FD.

[0051] The image sensor 500 can be a back-illuminated image sensor. Light can be incident into the first substrate 1 through the back surface 1b of the first substrate 1. Electron-hole pairs can be generated at the PN junction by the incident light. The electrons thus generated can be moved to the photoelectric conversion part PD. When a voltage is applied to the transmission gate TG, the electrons can be moved to the floating diffusion region FD.

[0052] The front surface 1a can be covered with a first interlayer insulating film IL. The first interlayer insulating film IL can be formed of a multilayer film of at least one film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous low-dielectric film. A first wiring 17 can be arranged in the first interlayer insulating film IL. The floating diffusion region FD can be connected to the first wiring 17.

[0053] A fixed charge film 24 is disposed on the back surface 1b of the first substrate 1. The fixed charge film 24 can be in contact with the back surface 1b of the first substrate 1. The fixed charge film 24 can be formed of a single film or a multiple film of a metal oxide film or a metal fluoride film containing an amount of oxygen or fluorine less than the stoichiometric ratio. Therefore, the fixed charge film can have a negative fixed charge. The fixed charge film 24 can be formed of a single film or a multiple film of a metal oxide or a metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanoids. As a specific example, the fixed charge film 24 can include a hafnium oxide film and / or an aluminum oxide film. The fixed charge film 24 can improve dark current and white spots.

[0054] A first protective film 44 can be laminated on the fixed charge film 24. The first protective film 44 can include at least one of PETEOS, SiOC, SiO 2 , and SiN. The first protective film 44 can function as an antireflection film and / or a planarizing film.

[0055] A light-shielding grid pattern 48a can be disposed on the first protective film 44. Low refractive index patterns 50a can be respectively disposed on the light-shielding grid pattern 48a. The light-shielding grid pattern 48a and the low refractive index patterns 50a are superimposed on the pixel isolation portion DTI and can have a planar grid shape. The light-shielding grid pattern 48a can contain, for example, titanium. The low refractive index patterns 50a can have the same thickness as each other and can contain the same organic substance as each other. The low refractive index patterns 50a can have a refractive index smaller than that of the color filters CF1 and CF2. For example, the low refractive index patterns 50a can have a refractive index of about 1.3 or less. The light-shielding grid pattern 48a and the low refractive index patterns 50a can prevent crosstalk between adjacent unit pixels PX.

[0056] Color filters CF1 and CF2 can be arranged between the low-refractive-index patterns 50a. The color filters CF1 and CF2 can each have one color among blue, green, and red. As another example, the color filters CF1 and CF2 may include other colors such as cyan, magenta, or yellow.

[0057] In the image sensor according to this example, the color filters CF1 and CF2 can be arranged in a bayer pattern shape. In other examples, the color filters CF1 and CF2 can be arranged in the shape of a 2x2 Tetra pattern, a 3x3 nona pattern, or a 4x4 hexadeca pattern.

[0058] Micro-lenses ML can be respectively arranged on the color filters CF1 and CF2. Alternatively, one micro-lens ML can cover a plurality of color filters CF1 and CF2 at the same time. The edges of the micro-lenses ML can be in contact with each other and connected.

[0059] In the image sensor 500 according to this example, the first silicon-containing pattern 13 exists in a liner form within the pixel isolation part DTI. Also, the second silicon-containing pattern 15 is in contact with a part of the first silicon-containing pattern 13 and can connect the first silicon-containing pattern 13. Therefore, the portion occupied by silicon in the pixel isolation part DTI can be relatively small. Therefore, the absorption and loss of light by silicon can be reduced, and the light sensitivity can be improved to implement an image sensor with a clear image quality.

[0060] FIG. 7 is a cross-sectional view of an image sensor obtained by cutting FIG. 3A along lines A-A', B-B', and C-C' according to an embodiment of the present invention.

[0061] Referring to FIG. 7, in the image sensor 501 according to this example, a first void region VD1 is disposed within the second embedded insulating pattern 21, and the upper end of the first void region VD1 can be located at the same level as the back surface 1b of the first substrate 1. The upper end of the first void region VD1 can be defined by the fixed charge film 24. The other structure can be the same / similar to that described with reference to FIG. 3B.

[0062] FIG. 8 is a cross-sectional view of an image sensor cut along line A-A', line B-B', and line C-C' of FIG. 3A according to an embodiment of the present invention.

[0063] Referring to FIG. 8, in the structure of FIG. 7, the remaining pattern 19 is disposed within the first void region VD1. That is, in the image sensor 502 according to this example, the remaining pattern 19 is disposed within the second embedded insulating pattern 21. The remaining pattern 19 can be made of a material different from that of the second embedded insulating pattern 21. The upper end of the remaining pattern 19 can be in contact with the fixed charge film 24. The remaining pattern 19 can include the same material as the fixed charge film 24. In this case, there may be no interface between the remaining pattern 19 and the fixed charge film 24. Although not shown, an antireflection film can be disposed on the back surface 1b of the first substrate 1, and the remaining pattern 19 can include the same material as the antireflection film. Or, the remaining pattern 19 can include a metal. Therefore, the pixel isolation portion DTI can be effective in preventing crosstalk between adjacent unit pixels PX. According to an example, the remaining pattern 19 is Al 2 O 3 、TiO 2 、HfOx, Al, W, Cu, Ag, Si 3 N 4 and can have at least one single film or multilayer structure among them. Within the second deepest trench 22(2) and the third deepest trench 22(3), a second void region VD2 can be formed inside the remaining pattern 19.

[0064] FIG. 9 is a top plan view of an image sensor according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of the image sensor cut along lines A-A', B-B', and C-C' according to an embodiment of the present invention.

[0065] Referring to FIGS. 9 and 10, in the image sensor 503 according to this example, the pixel isolation part DTI can have cross-sections of different structures depending on the position. The second separation part P2 of the pixel isolation part DTI can be the same / similar to FIG. 3B. The second separation part P2 of the pixel isolation part DTI can include an insulating liner pattern 12, a first silicon-containing pattern 13, a first embedded insulating pattern 14, a second silicon-containing pattern 15, a second embedded insulating pattern 21, and a third void region VD3. The first separation part P1 of the pixel isolation part DTI can exclude the second embedded insulating pattern 21 and the third void region VD3 of the second separation part P2. The first separation part P1 of the pixel isolation part DTI can include the first silicon-containing pattern 13 and the second silicon-containing pattern 15 connecting these. However, in the first separation part P1 of the pixel isolation part DTI, the second silicon-containing pattern 15 can have an elliptical cross-section instead of a shell form. In the plan view of FIG. 9, the second silicon-containing pattern 15 can have a hollow rhombus shape.

[0066] The third separation part P3 of the pixel isolation part DTI includes the first silicon-containing pattern 13 and the first embedded insulating pattern 14, and can exclude the second silicon-containing pattern 15 and the second embedded insulating pattern 21. In the third separation part P3 of the pixel isolation part DTI, the first embedded insulating pattern 14 can include a fourth void region VD4. The fourth void region VD4 is not connected to the third void region VD3 and can be separated. The other structure can be the same / similar to that described with reference to FIGS. 3A to 6C.

[0067] FIG. 11 is a cross-sectional view of the image sensor cut along lines A-A', B-B', and C-C' according to an embodiment of the present invention.

[0068] Referring to FIG. 11, in the image sensor 504 according to this example, in the structure of FIG. 10, the heights of the upper ends of the third void region VD3 and the fourth void region VD4 are located at the level of the back surface 1b of the first substrate 1, and the remaining pattern 19 is inserted into the third void region VD3 and the fourth void region VD4. The remaining pattern 19 can be the same / similar as that described with reference to FIG. 8. The fifth void region VD5 can be arranged in the remaining pattern 19 at the third separation part P3 of the pixel separation part DTI. The other structure can be the same / similar as that described with reference to FIGS. 9 and 10.

[0069] FIGS. 12A, 13A, 14A, 15A, 16A, and 19A are plan views sequentially showing the process of manufacturing an image sensor having the plan views of FIGS. 3A and 5A. FIGS. 12B, 13B, 14B, 15B, 16B, 18B, and 19B, and FIGS. 20A to 20F are cross-sectional views sequentially showing the process of manufacturing the image sensor of FIG. 3B. FIG. 17 is a plan view of the image sensor at the first level of FIG. 16B. FIGS. 16C, 18B, and 19C are cross-sectional views showing the process of manufacturing an image sensor according to an embodiment of the present invention. FIGS. 12B, 13B, 14B, 15B, 16B, and 19B are cross-sectional views obtained by cutting FIGS. 12A, 13A, 14A, 15A, 16A, and 19A along lines A-A', B-B', and C-C'. FIG. 16C is a cross-sectional view obtained by cutting FIG. 16A along line D-D'. FIG. 19C is a cross-sectional view obtained by cutting FIG. 19A along line D-D'.

[0070] Referring to FIGS. 12A and 12B, the first substrate 1 is prepared. The first substrate 1 can be, for example, a single-crystalline silicon wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. The first substrate 1 can be doped with impurities of, for example, the first conductivity type. For example, the first conductivity type can be P-type. The first substrate 1 includes a front surface 1a and a back surface 1b on opposite sides of each other.

[0071] Referring to FIGS. 13A and 13B, a first mask pattern 9 is formed on the front surface 1a of the first substrate 1. The first mask pattern 9 can include, for example, at least one single film or a multilayer structure among silicon oxide, silicon nitride, and silicon oxynitride. The first mask pattern 9 can limit the position of the active region ACT in FIG. 3A on the front surface 1a. Using the first mask pattern 9 as an etching mask, the front surface 1a of the first substrate 1 is etched to form a shallow trench 5.

[0072] Referring to FIGS. 14A and 14B, a second mask pattern 6 is formed on the front surface 1a of the first substrate 1. The second mask pattern 7 can cover the first mask pattern 9 and fill a part of the shallow trench 5. The second mask pattern 6 can limit the position of the pixel isolation portion. The second mask pattern 7 can expose a part of the lower surface of the shallow trench 5. The second mask pattern 7 can have at least one single film or a multilayer structure among silicon oxide, SiN, SiCN, and SiOCN. Using the second mask pattern 7 as an etching mask, the first substrate 1 is etched to form a deep trench 22.

[0073] When forming the deep trench 22, due to the interference effect between the etchants, the deep trench 22 can be formed planar as shown in FIG. 14A. That is, the deep trench 22 is formed to include first to third deep trenches 22(1) to 22(3). The first deep trench 22(1) is located between the first and second pixels PX(1), PX(2) and can be adjacent to the edges of the first and second pixels PX(1), PX(2). The second deep trench 22(2) is located between the first and third pixels PX(1), PX(3). The third deep trench 22(3) is interposed between the centers of the first and second pixels PX(1), PX(2). The first deep trench 22(1) can be formed to have a first width W1 in the first direction (X). The second deep trench 22(2) can be formed to have a second width W2 in the third direction (Z). The third deep trench 22(3) can be formed to have a third width W3 in the first direction (X). The third width W3 can be larger than the first width W1 and smaller than the second width W2.

[0074] Referring to FIGS. 15A and 15B, an insulating liner film 12a is conformally formed on the front surface 1a of the first substrate 1 on which the deep trench 22 is formed by an ALD (Atomic Layer Deposition) method. The insulating liner film 12a can have a constant thickness regardless of the position. The insulating liner film 12a can be formed of at least one single film or a multi-film structure among silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

[0075] The first silicon-containing film is conformally deposited on the insulating liner film 12a and etched to form a first silicon-containing pattern 13 in the deep trench 22. The deposition and etching of the first silicon-containing film can be sequentially performed in one process chamber. When forming the first silicon-containing film, a first impurity (for example, boron) can be doped in situ. The upper end of the first silicon-containing pattern 13 can be formed lower than the bottom surface of the shallow trench 5. The first silicon-containing film can be an amorphous polysilicon film, a polycrystalline silicon film, a single-crystalline silicon film, SiGe, SiC, or SiGe:C. The first silicon-containing film can be formed by ALD, CVD, or Epitaxial Deposition method.

[0076] Referring to FIGS. 16A to 16C and FIG. 17, a first buried insulating film 14a is laminated on the front surface 1a of the first substrate 1. The first buried insulating film 14a can be formed by a vapor deposition process in which the step coverage characteristics are deteriorated from an ALD process. For example, the first buried insulating film 14a can be formed by a CVD (Chemical Vapor Deposition) process such as LPCVD (Low pressure CVD) or PECVD (Plasma enhanced CVD). The first buried insulating film 14a can cover the inner wall and the bottom surface of the deep trench 22. Alternatively, the first buried insulating film 14a may cover only the upper inner wall of the deep trench 22 to prevent only the entrance of the deep trench 22 and may not cover the bottom surface of the deep trench 22. The thickness of the first buried insulating film 14a can vary depending on the position. That is, at the entrance and the bottom of the deep trench 22, the first buried insulating film 14a can be formed relatively thick, and on the side wall of the deep trench 22, the first buried insulating film 14a can be formed relatively thin. The first buried insulating film 14a can block the entrances of the first deep trench 22(1) and the third deep trench 22(3) having a relatively narrow width, and a first empty space 311 can be formed in the first buried insulating film 14a. However, the entrance of the second deep trench 22(2) having the widest width can be opened without being blocked by the first buried insulating film 14a. Therefore, a first hole (HL) can be formed in the first buried insulating film 14a in the second deep trench 22(2). As shown in FIGS. 16C and 17, the first hole HL can be connected to the first empty space 311.

[0077] Referring to FIGS. 18A and 18B, an isotropic etching process is performed on the first buried insulating film 14a. Therefore, the surface of the first buried insulating film 14a can be etched as a whole and the thickness of the first buried insulating film 14a can be reduced. Therefore, a part of the side wall of the first silicon-containing pattern 13 can be exposed.

[0078] If, during the process of depositing the first embedded insulating film 14a in FIGS. 16A to 16C, the thickness is reduced or the process time is shortened, a part of the sidewall of the first silicon-containing pattern 13 may not be covered by the first embedded insulating film 14a and may be exposed. In this case, the isotropic etching process for the first embedded insulating film 14a in FIGS. 18A and 18B can be omitted.

[0079] Referring to FIGS. 19A to 19C, a second silicon-containing film 15a can be conformally deposited on the first embedded insulating film 14a. The second silicon-containing film 15a can be formed by ALD. The second silicon-containing film 15a can be formed to contact the first silicon-containing pattern 13 within the deep trench 22. The second silicon-containing film 15a can conformally cover the inner wall of the first hole HL and also conformally cover the inner wall of the first embedded insulating pattern 14 within the first empty space 311 through the first hole HL. The second silicon-containing film 15a can be an amorphous polysilicon film, a polycrystalline silicon film, or a single-crystalline silicon film. Boron can be doped in situ when depositing the second silicon-containing film 15a. The second silicon-containing film 15a is formed in a liner form (linearly) without filling the first empty space 311. Accordingly, a second empty space 331 defined by the second silicon-containing film 15a is formed.

[0080] Referring to FIG. 20A, an anisotropic etching process is performed on the second silicon-containing film 15a. Accordingly, the second silicon-containing film 15a on the upper surface of the first embedded insulating film 14a is removed, exposing the upper surface of the first embedded insulating film 14a, while a second silicon-containing pattern 15 can be formed. The second silicon-containing pattern 15 is formed on the inner wall of the first hole HL and the inner wall of the second empty space 331.

[0081] Referring to FIGS. 5B and 20B, a second embedded insulating film 21a is deposited on the first embedded insulating film 14a. The second embedded insulating film 21a can be formed in a process with lower step coverage characteristics than ALD, for example, a CVD process. The second embedded insulating film 21a is also formed on the inner wall of the first hole HL and can also be formed in the second empty space 331 through the first hole HL. At this time, void regions VD can be formed in the second embedded insulating film 21a in the relatively narrow first deep trench 22(1) and the third deep trench 22(3). The void regions VD can be connected to the first hole HL as shown in FIG. 5B.

[0082] Referring to FIG. 20C, an etch-back process is performed on the second embedded insulating film 21a, the first embedded insulating film 14a, and the insulating liner film 12a to remove the second embedded insulating film 21a, the first embedded insulating film 14a, and the insulating liner film 12a on the upper surface and side walls of the second mask pattern 7, and form an insulating liner pattern 12, a first silicon-containing pattern 13, a first embedded insulating pattern 14, a second silicon-containing pattern 15, and a second embedded insulating pattern 21 in the deep trench 22. A third embedded insulating film 16a is formed on the second mask pattern 7 to fill the upper part of the deep trench 22. The third embedded insulating film 16a can be formed in a single film or a multi-layer film structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

[0083] An annealing process can be additionally performed for the crystallization of the first and second silicon-containing patterns 13 and 15. At this time, the first impurity (for example, boron) doped inside the first silicon-containing pattern 13 can diffuse into the second silicon-containing pattern 15.

[0084] Referring to FIG. 20D, the CMP (Chemical Mechanical Polishing) process is carried out to remove the second mask pattern 7 and the third embedded insulating film 16a on the first mask pattern 9, and form a pixel isolation portion DTI in the deep trench 22. In the CMP process, the first mask pattern 9 can function as a polishing stop film. A part of the second mask pattern 7 can remain and become an element isolation portion STI. Then, the first mask pattern 9 is removed to expose the front surface 1a of the first substrate 1.

[0085] Referring to FIG. 20E, an ion implantation process or the like is carried out on the first substrate 1 to form a photoelectric conversion portion PD. A transmission gate TG, a gate insulating film Gox, and a floating diffusion region FD are formed on the front surface 1a of the first substrate 1. A first interlayer insulating film IL and a first wiring 17 are formed on the front surface 1a of the first substrate 1.

[0086] Referring to FIG. 20F, a back grinding process is carried out on the back surface 1b of the first substrate 1 to remove a part of the first substrate 1 and a part of the pixel isolation portion DTI. Therefore, the first and second silicon-containing patterns 13, 15 and the first and second embedded insulating patterns 14, 21 of the pixel isolation portion DTI can be exposed. At this time, depending on the progress of the back grinding process, the void region VD of the pixel isolation portion DTI may be exposed. Also, the first embedded insulating pattern 14 adjacent to the back surface 1b may be removed so that only the first embedded insulating pattern 14 remains at the lower part of the deep trench 22.

[0087] Subsequently, referring to FIG. 3B, through normal processes, a fixed charge film 24, a first protective film 44, a light-shielding grid pattern 48a, a low refractive index pattern 50a, color filters CF1, CF2, and a microlens ML are formed on the back surface 1b of the first substrate 1.

[0088] FIG. 21A is a top plan view of an image sensor according to an embodiment of the present invention. FIG. 21B is a cross-sectional view of the image sensor taken along lines A-A', B-B', and C-C' of FIG. 21A according to an embodiment of the present invention. FIG. 21C is an enlarged view of 'P7' in FIG. 21B. FIG. 21D is a top plan view of the image sensor at the first level of FIG. 21B.

[0089] Referring to FIGS. 21A to 21D, in the image sensor 505 according to this example, the pixel isolation portion DTI can exclude the first silicon-containing pattern 13 of FIG. 3B. Specifically, the pixel isolation portion DTI according to this example can include an insulating liner pattern 12, a first embedded insulating pattern 14, a second silicon-containing pattern 15, a second embedded insulating pattern 21, and a third embedded insulating pattern 16.

[0090] The insulating liner pattern 12 contacts the side wall of the first substrate 1 in the deep trench 22. The first embedded insulating pattern 14 can contact the insulating liner pattern 12. When the first embedded insulating pattern 14 and the insulating liner pattern 12 are made of the same material, the interface between them cannot be observed, and the first embedded insulating pattern 14 and the insulating liner pattern 12 can be integrally formed. The first embedded insulating pattern 14 has a first empty space 311 inside. The first empty space 311 may be elongated in the vertical direction.

[0091] The second silicon-containing pattern 15 is disposed in the first empty space 311 of the first embedded insulating pattern 14 and conformally covers the inner wall of the first embedded insulating pattern 14. The second silicon-containing pattern 15 can be formed of a boron-doped silicon film. Alternatively, the second silicon-containing pattern 15 can be formed of boron-doped Silicon germanium, SiC, or SiGe:C. A negative bias voltage can be applied to the second silicon-containing pattern 15. The second silicon-containing pattern 15 can serve as a common bias line.

[0092] The second silicon-containing pattern 15 can have a 'U'-shaped cross-section. The second silicon-containing pattern 15 can include a side part (15(a)) and a connecting part (15(b)). In this example, the side wall part 15(a) of the second silicon-containing pattern 15 is adjacent to the side wall of the first substrate 1 and can surround each of the pixels PX as shown in FIG. 21B. The side wall part 15(a) of the second silicon-containing pattern 15 can be bent so as to protrude toward the side wall of the first substrate 1 and have an arc shape. A first embedded insulating pattern 14 can be interposed between the side wall part 15(a) of the second silicon-containing pattern 15 and the insulating liner pattern 12. Alternatively, the side wall part 15(a) of the second silicon-containing pattern 15 can be in contact with the insulating liner pattern 12. The connecting part 15(b) of the second silicon-containing pattern 15 can connect the side wall part 15(a) and be adjacent to the front surface 1a of the substrate 1. The lower surface of the connecting part 15(b) can protrude toward the front surface 1a of the first substrate 1 and be rounded.

[0093] The second silicon-containing pattern 15 can have a second empty space 331 inside. The second empty space 331 can be elongated in the vertical direction. A second embedded insulating pattern 21 is disposed in the second empty space 331 of the second silicon-containing pattern 15. The second embedded insulating pattern 21 can include a void region VD.

[0094] At the intersection point that is the center of four adjacent pixels PX(1) to PX(4) (that is, between the first pixel PX(1) and the third pixel PX(3), or in the third deep trench 22(2) having the widest width W2), the second embedded insulating pattern 21 can penetrate the second silicon-containing pattern 15 and be adjacent to the first surface 1a. At this position, the second silicon-containing pattern 15 includes only the side wall part 15(a) and does not include the connecting part 15(b). The other configurations are the same / similar to those described above.

[0095] The image sensors 505 in FIGS. 21A to 21D can be manufactured by omitting the manufacturing process of the first silicon-containing pattern 13 in FIGS. 15A and 15B during the manufacturing process of FIGS. 12A to 20F and proceeding with the remaining processes. At this time, since the manufacturing process of the first silicon-containing pattern 13 is omitted, the process can be simplified.

[0096] FIG. 22 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0097] Referring to FIG. 22, an image sensor 506 according to this example can include a first substrate 1 having a pixel array region APS, an optical black region OB, and a pad region PAD, a wiring layer 200 on the front surface 1a of the first substrate 1, and a second substrate 400 on the wiring layer 200. The wiring layer 200 can include an upper wiring layer 221 and a lower wiring layer 223. The pixel array region APS can include a plurality of pixels PX. The pixels PX arranged in the pixel array region APS can be substantially the same as those described above with reference to FIGS. 3A to 11 and FIGS. 21A to 21D.

[0098] A light-shielding pattern WG, a first connection structure 120, a first conductive pad 81, and a bulk color filter 90 can be provided on the first substrate 1 in the optical black region OB. The first connection structure 120 can include a first connection line 121, an insulating pattern 123, and a first capping pattern 125.

[0099] A part of the first connection line 121 can be provided on the back surface 1b of the first substrate 1. The light-shielding pattern WG can cover the back surface 1b and conformally cover the inner walls of the third trench TR3 and the fourth trench TR4. The first connection line 121 can penetrate through the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 and the wiring layer 200. More specifically, the first connection line 121 can contact the wirings in the upper wiring layer 221 and the lower wiring layer 223 and the first and second silicon patterns 13, 15 of the pixel isolation part DTI in the photoelectric conversion layer 150. Therefore, the first connection structure 120 can be electrically connected to the wirings in the wiring layer 200. The first connection line 121 can contain a metal substance, such as tungsten. The light-shielding pattern WG can block the light incident in the optical black region OB.

[0100] The first conductive pad 81 can be provided inside the third trench TR3 and fill the remaining part of the third trench TR3. The first conductive pad 81 can contain a metal substance, such as aluminum. The first conductive pad 81 can be connected to the first and second silicon-containing patterns 13, 15 in FIG. 3B. A negative bias voltage can be applied to the first and second silicon-containing patterns 13, 15 in FIG. 3B through the first conductive pad 81. Therefore, problems such as white spots and dark current can be prevented / reduced.

[0101] The insulating pattern 123 can fill the remaining part of the fourth trench TR4. The insulating pattern 123 can penetrate through all or part of the photoelectric conversion layer 150 and the wiring layer 200. The first capping pattern 125 can be provided on the upper surface of the insulating pattern 123. The first capping pattern 125 can be provided on the insulating pattern 123.

[0102] The bulk color filter 90 can be provided on the first conductive pad 81, the light-shielding pattern WG, and the first capping pattern 125. The bulk color filter 90 can cover the first conductive pad 81, the light-shielding pattern WG, and the first capping pattern 125. The first protective film 71 can be provided on the bulk color filter 90 to seal the bulk color filter 90.

[0103] A photoelectric conversion region PD' and a dummy region PD'' can be provided in the optical black region OB of the first substrate 1. The photoelectric conversion region PD' can be doped with impurities of a second conductivity type different from the first conductivity type, for example. The second conductivity type can be, for example, an n-type. The photoelectric conversion region PD' has a structure similar to that of the photoelectric conversion region PD, but may not perform the same operation as the photoelectric conversion region PD (i.e., the operation of generating an electrical signal upon receiving light). The dummy region PD'' does not have to be doped with impurities. The signal generated in the dummy region PD'' can be used as information for removing subsequent process noise.

[0104] In the pad region PAD, a second connection structure 130, a second conductive pad 83, and a second protective film 73 can be provided on the first substrate 1. The second connection structure 130 can include a second connection line 131, an insulating pattern 133, and a second capping pattern 135.

[0105] The second connection line 131 can be provided on the back surface 1b of the first substrate 1. More specifically, the second connection line 131 can cover the back surface 1b and conformally cover the inner walls of the fifth trench TR5 and the sixth trench TR6. The second connection line 131 can penetrate the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 and the wiring layer 200. More specifically, the second connection line 131 can contact the wiring in the lower wiring layer 223. Therefore, the second connection structure 130 can be electrically connected to the wiring in the wiring layer 200. The second connection line 131 can include a metallic substance, for example, tungsten.

[0106] The second conductive pad 83 can be provided inside the fifth trench TR5 to fill the remaining portion of the fifth trench TR5. The second conductive pad 83 can include a metallic substance, such as aluminum. The second conductive pad 83 can serve as an electrical connection path to the outside of the image sensor element. The insulating pattern 133 can fill the remaining portion of the sixth trench TR6. The insulating pattern 133 can penetrate all or part of the photoelectric conversion layer 150 and the wiring layer 200. The second capping pattern 135 can be provided on the insulating pattern 133.

[0107] FIG. 23 is a cross-sectional view of an image sensor according to an embodiment of the present invention.

[0108] Referring to FIG. 23, an image sensor 507 according to this example can have a structure in which first to third sub-chips CH1 to CH3 are bonded in order. The first sub-chip CH1 can preferably perform an image sensing function. The first sub-chip CH1 can be the same / similar as that described with reference to FIGS. 3A to 11.

[0109] The first sub-chip CH1 can include a transmission gate TG and a first interlayer insulating film IL1 covering the same on the front surface 1a of the first substrate 1. The first substrate 1 can include a pixel array region APS and an edge region EG. The pixel array region APS can include a plurality of unit pixels PX. The edge region EG can correspond to a part of the optical black region OB in FIG. 22.

[0110] A first element isolation part STI1 is arranged on the first substrate 1 to define an active region. A pixel isolation part DTI is arranged on the first substrate 1 to separate / limit the unit pixel PX in the pixel array region APS. The pixel isolation part DTI can extend to the edge region EG. The pixel isolation part DTI can be the same / similar as that described with reference to FIGS. 3A to 11 and FIGS. 21A to 21D.

[0111] The front surface 1a of the first substrate 1 can be covered with the first interlayer insulating film IL1. The first wiring 17 can be disposed between or within the first interlayer insulating film IL1. The floating diffusion region FD can be connected to the first wiring 17 by the first contact plug 115. The first conductive pad CP1 can be disposed within the lowermost first interlayer insulating film IL1. The first conductive pad CP1 can contain copper.

[0112] In the edge region EG, the connection contact BCA can penetrate through the first protective film 44, the fixed charge film 24, and a part of the first substrate 1 and contact the first and second silicon patterns 13 and 15. The connection contact BCA can be located within the third trench 46. The connection contact BCA can include an anti-diffusion pattern 48g that conformally covers the inner sidewalls and bottom surface of the third trench 46, a first metal pattern 52 on the anti-diffusion pattern 48g, and a second metal pattern 54 that fills the third trench 36. The anti-diffusion pattern 48g can contain, for example, titanium. The first metal pattern 52 can contain, for example, tungsten. The second metal pattern 54 can contain, for example, aluminum. The anti-diffusion pattern 48g and the first metal pattern 52 can extend on the first protective film 44 and be electrically connected to other wirings and vias / contacts. The connection contact BCA can contact the second silicon-containing pattern 15 of the pixel isolation portion DTI in FIGS. 3A to 11 and FIGS. 21A to 21D. A part of the connection contact BCA can be inserted into the void region VD of the pixel isolation portion DTI in FIGS. 3A to 11 and FIGS. 21A to 21D.

[0113] A second protective film 56 is laminated on the first protective film 44. The second protective film 56 can conformally cover the light-shielding grid pattern 48a, the low-refractive-index pattern 50a, and the connection contact BCA.

[0114] In the edge region EG, a first optical black pattern CFB can be disposed on the second protective film 56. The first optical black pattern CFB can include, for example, the same material as a blue color filter.

[0115] In the edge region EG, a remaining lens layer MLR can be disposed on the first optical black pattern CFB. The remaining lens layer MLR can include the same material as the microlens ML.

[0116] The second sub-chip CH2 can include a second substrate SB2, a select gate SEL disposed thereon, a source follower gate SF, and a reset gate (not shown), and a second interlayer insulating film IL2 covering them. A second element isolation portion STI2 is disposed on the second substrate SB2 to define an active region. A second contact 217 and a second wiring 215 can be disposed in the second interlayer insulating film IL2. A second conductive pad CP2 can be disposed in the uppermost second interlayer insulating film IL2. The second conductive pad CP2 can include copper. The second conductive pad CP2 can be in contact with the first conductive pad CP1. The source follower gate SF can be respectively connected to the floating diffusion region FD of the first sub-chip CH1.

[0117] The third sub-chip CH3 can include a third substrate SB3, peripheral transistors PTR disposed thereon, and a third interlayer insulating film IL3 covering them. A third element isolation portion STI3 is disposed on the third substrate SB3 to define an active region. A third contact 317 and a third wiring 315 can be disposed within the third interlayer insulating film IL3. The uppermost third interlayer insulating film IL3 is in contact with the second substrate SB2. The through electrode TSV can penetrate the second interlayer insulating film IL2, the second element isolation portion STI2, the second substrate SB2, and the third interlayer insulating film IL3 to connect the second wiring 215 and the third wiring 315. The sidewall of the through electrode TSV can be surrounded by a via insulating film TVL. The third sub-chip CH3 can include a circuit for driving the first and / or second sub-chips CH1, CH2 or storing electrical signals generated by the first and / or second sub-chips CH1, CH2.

[0118] As described above, the embodiments of the present invention have been described with reference to the attached drawings. However, those having ordinary knowledge in the technical field to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing its technical idea and essential features. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive. The embodiments in FIGS. 3A to 23 can be combined with each other.

Explanation of Reference Numerals

[0119] 1 Substrate 11 Native Oxide Film 12 Insulating Liner Pattern 13 First Silicon-Containing Pattern 14 First Embedded Insulating Pattern 15 Second Silicon-Containing Pattern 16 Third Embedded Insulating Pattern 21 Second Embedded Insulating Pattern 22 Deep Trench 24 Fixed Charge Film 311 First Empty Space 331 Second Empty Space 5000 Image Sensor ACT Active Region DTI Pixel Separation Section FD Floating Diffusion Region IL First Interlayer Insulation Film P1~P3 Separation Portion PD Photoelectric Conversion Section PX Unit Pixel PX(1)~PX(4) Pixel STI Element Isolation Section TG Transmission Gate VD Void Region

Claims

1. An image sensor comprising: a substrate having a first surface and a second surface opposite the first surface; a pixel separator disposed within the substrate and separating pixels from each other; The pixels include a first pixel and a second pixel spaced apart from each other along a first direction, The pixel separation unit includes: a first silicon-containing pattern surrounding each of the first pixel and the second pixel and spaced apart from each other in a plan view; a second silicon-containing pattern disposed between the first pixel and the second pixel and connecting the first silicon-containing pattern; the second silicon-containing pattern includes a sidewall portion adjacent to the first silicon-containing pattern, and a connection portion spaced apart from the first silicon-containing pattern and connecting the sidewall portion, Image sensor.

2. further comprising a transistor disposed over the first surface; The image sensor of claim 1 , wherein the connection portion protrudes toward the first surface and has a rounded lower surface.

3. The image sensor of claim 1 , wherein the pixel separator further comprises a first buried insulating pattern interposed between the connection portion and the first silicon-containing pattern.

4. the second silicon-containing pattern has a hollow shell shape; The image sensor of claim 3 , wherein the pixel separator further comprises a second buried insulating pattern disposed within the second silicon-containing pattern.

5. The image sensor of claim 4 , wherein the pixel separator further comprises a void region disposed in the second buried insulating pattern.

6. the pixel separating portion further includes a remaining pattern disposed in the second buried insulating pattern, The image sensor of claim 4 , wherein the remaining pattern is made of a different material than the second buried insulating pattern.

7. a fixed charge film covering the second surface; The image sensor of claim 6 , wherein the remaining pattern comprises the same material as the fixed charge film.

8. the first silicon-containing pattern comprises a first concentration of boron; 2. The image sensor of claim 1, wherein the second silicon-containing feature comprises a second concentration of boron that is the same as or less than the first concentration.

9. An image sensor comprising: a substrate having a first surface and a second surface opposite the first surface; a transistor disposed over the first surface; a pixel separator disposed in the substrate and separating pixels from each other; The pixels include a first pixel to a fourth pixel arranged along a clockwise direction, The pixel separation unit includes: a first silicon-containing pattern surrounding each of the first pixel and the second pixel and spaced apart from each other in a plan view; a second silicon-containing pattern connecting adjacent first silicon-containing patterns; a first buried insulating pattern separated from the first silicon-containing pattern by the second silicon-containing pattern, the first buried insulating pattern penetrates the second silicon-containing pattern between a corner of a third pixel adjacent to the first pixel and a corner of the first pixel; Image sensor.

10. An image sensor comprising: a substrate having a first surface and a second surface opposite the first surface; a pixel separator disposed in the substrate and separating pixels from each other; The pixels include a first pixel and a second pixel spaced apart from each other along a first direction, The pixel separation unit includes: a first buried insulating pattern interposed between the first pixel and the second pixel and having a first empty space therein, the first empty space being elongated in a vertical direction; a silicon-containing pattern covering an inner wall of the first buried insulating pattern in the first empty space, the silicon-containing pattern having a U-shaped cross section and a second empty space therein; a second buried insulating pattern disposed in the second empty space. Image sensor.

Images