Inductor of microelectronic die

Abstract

To provide a micro electron device for achieving a desire Q value without unnecessary increasing a size and a cost, and provide a formation method of them.SOLUTION: A micro electron device 100 includes: a bump bond 130 and an inductor 140 onto a die 102, and contains a first lateral direction conductor 108 to be extended along the die 102, and some of the first lateral direction conductor 108 is contacted to some of terminals 104 of the die. The micro electron device contains a conductive column 114 onto the first lateral direction conductor, and contains a second lateral direction conductor 120 to be extended to a lateral direction in a certain surface on the conductive column on the side opposite to the first lateral direction conductor. A first set 128 of the first lateral direction conductor 108, the conductive column, and the second lateral direction conductor provides a bump pond of a device. A second set 138 of the first lateral direction conductor, the conductive column, and the second lateral direction conductor is electrically coupled serially in order to from the inductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application relates to the field of microelectronic devices, and more particularly, to inductors on microelectronic devices.

Background Art

[0002] Microelectronic devices often include circuits with inductors that typically range from about 0.5 to 5 nanohenries (nH). Inductors in this range tend to utilize hundreds of square microns or more, unnecessarily increasing the size and cost of the microelectronic device. Achieving a desirable Q value in these inductors has been difficult heretofore.

Summary of the Invention

[0003] This description introduces a microelectronic device having a die, bump bonds on the die, and an inductor. The die includes terminals that extend to a terminal surface of the die. The microelectronic device includes a first lateral conductor that extends along the terminal surface, with at least a portion of the first lateral conductor in contact with at least a portion of the terminal. The microelectronic device also includes a conductive column that extends vertically away from the terminal surface on the first lateral conductor, and a second lateral conductor that extends laterally in a plane parallel to the terminal surface on a conductive column opposite the first lateral conductor. The second lateral conductor has a die attachment surface located on the side opposite the conductive column. A first set of the first lateral conductor, the conductive column, and the second lateral conductor provides the bump bonds of the microelectronic device. A second set of the first lateral conductor, the conductive column, and the second lateral conductor are electrically coupled in series to form an inductor. A method of forming the microelectronic device is also described.

Brief Description of the Drawings

[0004]

Figure 1

[0005]

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 2I

Figure 2J

Figure 2K

Figure 2L

[0006]

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 3F

[0007]

Figure 4

[0008]

Figure 5

[0009]

Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0010] Some examples will be described with reference to the accompanying drawings. The drawings may not be drawn to scale. This description is not limited by the order in which acts or events are illustrated, and not all illustrated acts or events are necessary to implement the techniques described herein. This description is illustrated by examples directed to active devices, but these illustrations are not limitations on the scope or applicability of these examples, and the devices are not limited to the physical structures illustrated.

[0011] The microelectronic device includes a die having bump bonds and inductors on the die. The die includes terminals, such as bond pads, that extend to a terminal surface of the die. The terminal surface is not necessarily flat. The microelectronic device includes a first lateral conductor that extends along the terminal surface outside the die. Some of the first lateral conductors are in contact with some of the terminals.

[0012] The microelectronic device includes conductive columns that extend vertically from the terminal surface on the first lateral conductor. Some of the conductive columns can be in contact with the corresponding first lateral conductors at positions laterally offset from the terminals with which the corresponding first lateral conductors are in contact. Thus, some of the conductive columns are not located directly above the terminals to which they are electrically coupled via the corresponding first lateral conductors.

[0013] The microelectronic device includes a second lateral conductor that extends laterally in a plane parallel to the terminal surface on a conductive column opposite the first lateral conductor. The second lateral conductor has a die attachment surface located opposite the conductive column. Solder or a conductive adhesive may be disposed on the die attachment surface of at least a portion of the second lateral conductor.

[0014] A first set of the first lateral conductor, the conductive column, and the second lateral conductor provides a bump bond of the microelectronic device. A second set of the first lateral conductor, the conductive column, and the second lateral conductor are electrically coupled in series to form an inductor. The inductor may have a linear configuration, a loop configuration, or other configuration. One or more nodes of the inductor may contact a terminal at the terminal surface. One or more nodes of the inductor may extend to the second lateral conductor for electrical connection with an external lead of the package. The inductor may be part of a transformer.

[0015] "Lateral" refers to a direction parallel to the plane of the terminal surface of the die. Terms such as "over" and "under" are used to provide a spatial relationship between structures or elements. An element referred to as being "connected" or "coupled" to another element may be directly connected or directly coupled to the other element, or intervening elements may be present.

[0016] FIG. 1 is a cross-sectional view of an exemplary microelectronic device having a die and bump bonds and inductors on the die. The microelectronic device 100 includes a die 102, which can be, for example, a discrete semiconductor device, an integrated circuit, or a microelectromechanical systems (MEMS) device. The die 102 has terminals 104 that extend to a terminal surface 106 of the die 102. The terminals 104 can mainly include, for example, aluminum or copper. The terminals 104 can be bond pads above the top interconnect level of the die 102 or a part of the top interconnect level. The terminals 104 can include an under-bump metal (UBM) layer at the terminal surface 106. The UBM layer can include metals such as nickel, palladium, platinum, gold, copper, titanium, tungsten, chromium, etc. Although not shown in FIG. 1, the die 102 can have a protective overcoat (PO) layer of an electrically insulating material that extends between the terminals 104 to the terminal surface 106. The PO layer can include silicon dioxide, silicon nitride, silicon oxynitride, polyimide, etc.

[0017] The microelectronic device 100 includes a first lateral conductor 108 that extends along the terminal surface 106. Some and optionally all of the first lateral conductors 108 contact some and optionally all of the terminals 104. An individual first lateral conductor 108 can contact one or more of the terminals 104. In this example, the first lateral conductor 108 is the first conductor seed layer 110 on the terminal surface 106 and the first main conductor 112 on the first conductor seed layer 110. The first main conductor 112 extends laterally to the lateral boundary of the first lateral conductor 108. The first main conductor 112 can extend in a straight line or can have one or more lateral bends. The first conductor seed layer 110 can include, on the terminal surface 106, an adhesion layer containing a metal such as titanium, tungsten, chromium, or nickel, and a copper plating layer on this adhesion layer. The first conductor seed layer 110 can have a thickness of, for example, from 10 nanometers to 1 micron. The first main conductor 112 is conductive and can include plated copper, optionally together with other metals such as gold, silver, or nickel. The first main conductor 112 can have a thickness of, for example, from 3 microns to 30 microns.

[0018] The microelectronic device 100 includes a conductive column 114 disposed on a first lateral conductor 108. The conductive column 114 extends perpendicularly to the terminal surface 106 from the first lateral conductor 108. "Perpendicularly" includes an orientation that is substantially perpendicular within the manufacturing and measurement tolerances that occur when forming the microelectronic device 100. Some of the conductive columns 114 may contact the corresponding first lateral conductor 108 at positions that are laterally offset from the terminal 104 with which the corresponding first lateral conductor 108 is in contact. Another portion of the conductive column 114 may contact the corresponding first lateral conductor 108 directly above the terminal 104 with which the corresponding first lateral conductor 108 is in contact. Examples of both portions of the conductive column 114 are shown in FIG. 1. In this example, the conductive column 114 is a column seed layer 116 on the first lateral conductor 108 and a main column 118 on the column seed layer 116. The main column 118 is conductive and extends to the top of the conductive column 114 on the side opposite the first lateral conductor 108. The column seed layer 116 may include an adhesive layer containing a metal such as titanium, chromium, or nickel on the terminal surface 106 and a copper plating layer on this adhesive layer. The column seed layer 116 may have a thickness of, for example, from 10 nanometers to 1 micron. The main column 118 may include plated copper, optionally with other metals such as gold, silver, or nickel, and may have a composition similar to that of the first main conductor 112. The main column 118 may have a height of, for example, from 30 microns to 100 microns, measured perpendicularly to the terminal surface 106. The conductive column 114 may have various cross-sectional shapes. Some examples of the conductive column 114 may have a circular cross-sectional shape or a square cross-sectional shape with rounded corners. Other examples of the conductive column 114 may have an elliptical or rectangular cross-sectional shape. Other cross-sectional shapes for the conductive column 114 are within the scope of this example. The main column 118 may have a width of, for example, from 25 microns to 50 microns, measured parallel to the terminal surface 106, and may also have a length of, for example, from 25 microns to 300 microns, measured parallel to the terminal surface 106.

[0019] The microelectronic device 100 further includes a second lateral conductor 120 disposed on the conductive column 114. The second lateral conductor 120 and the first lateral conductor 108 are located at opposite ends of the conductive column 114. Some of the second lateral conductors 120 extend laterally beyond the corresponding conductive columns 114 on which they are disposed in a plane parallel to the terminal surface. In this example, the second lateral conductor 120 includes a second conductor seed layer 122 on the conductive column 114 and a second main conductor 124 on the second conductor seed layer 122. The second main conductor 124 extends laterally to the lateral boundary of the second lateral conductor 120. The second main conductor 124 may extend in a straight line or may have one or more lateral bends. The second conductor seed layer 122 may include an adhesion layer containing a metal such as titanium, chromium, or nickel on the conductive column 114 and a copper plating layer on this adhesion layer. The second conductor seed layer 122 may have a thickness of, for example, from 10 nanometers to 1 micron. The second main conductor 124 may include plated copper, optionally with other metals such as gold, silver, or nickel, and may have a composition similar to that of the first main conductor 112. The second main conductor 124 may have a thickness of, for example, from 3 microns to 30 microns. The second lateral conductor 120 has a die attachment surface 126 located on the side opposite the first lateral conductor 108.

[0020] A first set 128 of a first lateral conductor 108, a conductive column 114, and a second lateral conductor 120 provides a bump bond 130 of the microelectronic device 100. A die attach material 132 is disposed on a die attach surface 126 of the bump bond 130. The die attach material 132 can include solder, for example, in the form of a solder paste or a solder layer formed using a molten solder bath. Alternatively, the die attach material 132 can include a conductive adhesive, such as an epoxy with metal particles. Other compositions for the die attach material 132 are within the scope of this example. One or more of the bump bonds 130 can include an insulating layer 134 on the die attach surface 126 to define an area for the die attach material 132. The insulating layer 134 can include a polymeric insulating material, such as polyimide or polyester, or can include an inorganic insulating material, such as ceramic or glass frit.

[0021] FIG. 1 shows a microelectronic device 100 attached to an external lead 136. The external lead 136 can be part of a package that includes the microelectronic device 100, or can be part of a carrier or circuit board on which the microelectronic device 100 is mounted. The external lead 136 is electrically coupled to the bump bond 130 via the die attach material 132. By having the first lateral conductor 108 and the second lateral conductor 120 in the bump bond 130, it can be possible to have a desired arrangement of the terminals 104 on the die 102 and to connect the terminals 104 to a desired arrangement of the external leads 136. Although not shown in FIG. 1, an encapsulating material, such as epoxy, can be disposed on the terminal surface 106 while covering the first lateral conductor 108 and surrounding the conductive column 114.

[0022] A second set 138 of a first lateral conductor 108, a conductive column 114, and a second lateral conductor 120 are electrically configured in series to provide an inductor 140. The inductor 140 may have a linear configuration as shown in FIG. 1, in which the first lateral conductor 108, the conductive column 114, and the second lateral conductor 120 of the inductor 140 are arranged in a linear array. Alternatively, the inductor 140 may have an annular configuration or other configuration. The inductor 140 may have a desirably high quality factor, generally referred to as a Q value, due to the low electrical resistance in the first lateral conductor 108, the conductive column 114, and the second lateral conductor 120. By having a first lateral conductor 108 with a thickness from 3 microns to 30 microns including copper, a Q value greater than 1 can be provided at a frequency of 100 megahertz (MHz). This may be difficult to achieve using a thinner redistribution layer (RDL) or interconnect in die 102. The low electrical resistance of the inductor 140 may enable use in power circuits and signal circuits that may reduce the reliability of an inductor formed with a thinner RDL layer. The inductor 140 may include additional conductive elements in parallel with the first lateral conductor 108 or the second lateral conductor 120 to further improve the Q value. For example, an interconnect of die 102 may be electrically coupled in parallel with the first lateral conductor 108 in the second set 138. An example of an external lead 136 may be electrically coupled in parallel with the second lateral conductor 120 in the second set 138. One or more nodes of the inductor 140 may contact one or more of the terminals 104 as shown in FIG. 1. One or more nodes of the inductor 140 may extend to the die attachment surface 126 for electrical connection to an external lead of the package. The inductor 140 may be part of a transformer.

[0023] Figures 2A - 2L are cross - sectional views of a die and a microelectronic device having bump bonds and inductors on this die, shown at certain stages of an exemplary formation method. Referring to Figure 2A, the microelectronic device 200 includes a die 202 that can be implemented as a discrete semiconductor device, an integrated circuit, a MEMS device, or other such microelectronic die. The die 202 can be a part of a semiconductor wafer that includes additional dies. The die 202 has terminals 204 that extend to a terminal surface 206 of the die 202. The terminals 204 can be formed mainly of aluminum or copper, for example, and can have a UBM layer formed on the terminal surface 206 to protect the terminals 204 during manufacturing and thus provide a low - electrical - connection to the terminals 204. The UBM layer can be formed, for example, by a sputtering process or an electroless plating process. The die 202 can have a PO layer that extends between the terminals 204 to the terminal surface 206. The PO layer can include any of the electrical insulating materials described with respect to the PO layer of Figure 1 and can be formed, for example, by a plasma - enhanced chemical vapor deposition (PECVD) process or a photolithography process.

[0024] A first conductor seed layer 210 is formed on the terminal surface 206 in contact with the terminals 204. The first conductor seed layer 210 can include an adhesion layer that is formed on the terminal surface 206 in contact with the terminals 204 and a plating layer on this adhesion layer. The adhesion layer can include one or more metals having a desired adhesion to the terminals 204 and to the material of the die 202, such as the PO layer at the adjacent terminal surface 206 of the terminals 204. For example, the adhesion layer can include titanium, titanium - tungsten, chromium, or nickel and can be formed by one or more sputtering processes. The plating layer can mainly include copper and can be formed by a sputtering process.

[0025] The first conductor plating mask 242 exposes the first conductor seed layer 210 in the area for the later-formed first lateral conductor 208 shown in FIG. 2B and is formed on the first conductor seed layer 210. In one version of this example, the first conductor plating mask 242 may include a photoresist or other photosensitive polymer and may be formed by a photolithography process. In another version, the first conductor plating mask 242 may include a polymer material and may be formed by an additive process such as a material jetting process. In a further version, the first conductor plating mask 242 may include a thermally erodible material such as polyimide, polyester, or polymethyl methacrylate (PMMA) and may be formed by a laser ablation process. Other materials for the first conductor plating mask 242 and methods for forming the first conductor plating mask 242 are also within the scope of this example.

[0026] Referring to FIG. 2B, the first main conductor 212 is formed on the first conductor seed layer 210 at the location exposed by the first conductor plating mask 242. The first main conductor 212 may have the composition described with respect to the first main conductor 112 of FIG. 1. The first main conductor 212 may be formed by an electroplating process of copper or, optionally, by an electroless copper plating process. The first conductor seed layer 210 and the first main conductor 212 provide the first lateral conductor 208 of the microelectronic device 200.

[0027] Referring to FIG. 2C, the column seed layer 216 is on the first lateral conductor 208 and is formed on the first conductor plating mask 242. The column seed layer 216 may include an adhesion layer in contact with the first lateral conductor 208, which is on the first lateral conductor 208 and is formed on the first conductor plating mask 242, and a plating layer on this adhesion layer. The adhesion layer may include one or more metals having a desired adhesion to the metal in the first lateral conductor 208 and to the material of the first conductor plating mask 242. For example, the adhesion layer may include titanium, chromium, or nickel and may be formed by one or more sputtering processes. The plating layer may mainly include copper and may be formed by a sputtering process.

[0028] Referring to FIG. 2D, the column plating mask 244 is formed on the column seed layer 216, exposing the column seed layer 216 in the area for the later-formed conductive column 214 shown in FIG. 2E. The column plating mask 244 may be formed by any of the methods described with respect to the first conductor plating mask 242. Other materials for the column plating mask 244 and methods for forming the column plating mask 244 are also within the scope of this example.

[0029] Referring to FIG. 2E, the main column 218 is formed on the column seed layer 216 at the location exposed by the column plating mask 244. The main column 218 may have the composition described with respect to the main column 118 of FIG. 1. The main column 218 may be formed by an electroplating process of copper or, optionally, by an electroless copper plating process. The column seed layer 216 and the main column 218 provide the conductive column 214 of the microelectronic device 200.

[0030] Referring to FIG. 2F, a second conductor seed layer 222 is formed on the conductive column 214 and on the column plating mask 244. The second conductor seed layer 222 may include an adhesive layer in contact with the conductive column 214, which is on the conductive column 214 and formed on the column plating mask 244, and a plating layer on this adhesive layer. The adhesive layer may include one or more metals having a desired adhesion to the metal in the conductive column 214 and to the material of the column plating mask 244. For example, the adhesive layer may include any of the metals described with respect to the adhesive layer of the column seed layer 216 and may be formed by one or more sputtering processes. The plating layer may mainly include copper and may be formed by a sputtering process.

[0031] Referring to FIG. 2G, a second conductor plating mask 246 is formed on the second conductor seed layer 222, exposing the second conductor seed layer 222 in the area for the later-formed second lateral conductor 220 shown in FIG. 2G. The second conductor plating mask 246 may be formed by any of the methods described with respect to the first conductor plating mask 242. Other materials for the second conductor plating mask 246 and methods for forming the second conductor plating mask 246 are also within the scope of this example.

[0032] Referring to FIG. 2G, a second main conductor 224 is formed on the second conductor seed layer 222 at the location exposed by the second conductor plating mask 246. The second main conductor 224 may have the composition described with respect to the second main conductor 124 in FIG. 1. The second main conductor 224 may be formed by an electroplating process of copper or, optionally, by an electroless copper plating process. The second conductor seed layer 222 and the second main conductor 224 provide the second lateral conductor 220 of the microelectronic device 200.

[0033] Referring to FIG. 2H, the second conductor plating mask 246 of FIG. 2G is removed, leaving the second lateral conductor 220 in place. The second conductor plating mask 246 can be removed by a dry process using oxygen radicals, such as an asher process or an ozone process. Alternatively, the second conductor plating mask 246 can be removed by a wet process using a solvent such as N-methyl-2-pyrrolidine (NMP) or dimethyl sulfoxide (DMSO). Proprietary formulations of resist removal chemicals for removing the second conductor plating mask 246 are commercially available from several suppliers.

[0034] Referring to FIG. 2I, the second conductor seed layer 222 at the location exposed by the second main conductor 224 is removed, leaving the second conductor seed layer 222 in place under the second main conductor 224. The second conductor seed layer 222 can be removed by a wet etching process using an acid bath. During the removal of the second conductor seed layer 222, a small portion of the second main conductor 224 can be removed.

[0035] Referring to FIG. 2J, the column plating mask 244 of FIG. 2I is removed, leaving the main column 218 in place. The column plating mask 244 can be removed by a process similar to the process used to remove the second conductor plating mask 246 of FIG. 2G. Other methods for removing the column plating mask 244 are also within the scope of this example.

[0036] The column seed layer 216 at the location exposed by the main column 218 is removed. The column seed layer 216 can be removed by a process similar to the process used to remove the second conductor seed layer 222. Other methods for removing the column seed layer 216 are also within the scope of this example. As a result of the removal of the column seed layer 216, the second conductor seed layer 222 on the second main conductor 224 at the location exposed by the main column 218 can be removed, as shown in FIG. 2J.

[0037] Thereafter, the first conductor plating mask 242 is removed, leaving the first main conductor 212 in place. The first conductor plating mask 242 can be removed by a process similar to the process used to remove the second conductor plating mask 246. Other methods for removing the first conductor plating mask 242 are also within the scope of this example.

[0038] The first conductor seed layer 210 at the location exposed by the first main conductor 212 is removed, leaving the first conductor seed layer 210 in place between the first main conductor 212 and the terminal surface 206. The first conductor seed layer 210 can be removed by a process similar to the process used to remove the second conductor seed layer 222. Other methods for removing the first conductor seed layer 210 are also within the scope of this example.

[0039] The second lateral conductor 220 has a die attachment surface 226 located on the side opposite the first lateral conductor 208. A first set 228 of the first lateral conductor 208, the conductive column 214, and the second lateral conductor 220 provides the bump bond 230 of the microelectronic device 200. A second set 238 of the first lateral conductor 208, the conductive column 214, and the second lateral conductor 220 are electrically configured in series to provide the inductor 240. Forming the first set 228 and the second set 238 of the first lateral conductor 208, the conductive column 214, and the second lateral conductor 220 simultaneously can reduce manufacturing cost and complexity compared to forming the inductor 240 separately from the bump bond 230.

[0040] Referring to FIG. 2K, the encapsulation material 248 can surround the first lateral conductor 208 and the conductive column 214 and extend to the second lateral conductor 220 to be formed on the die 202. The encapsulation material 248 can include epoxy and can be formed, for example, by injection molding or press molding. The encapsulation material 248 can include magnetic particles 250, such as ferrite particles or ferromagnetic particles containing iron, nickel, or cobalt. The magnetic particles 250 can provide an average relative permeability of the encapsulation material 248 greater than 1 (the relative permeability of vacuum is 1), thereby increasing the inductance of the inductor 240.

[0041] Referring to FIG. 2L, the insulating layer 234 can be formed on the second main conductor 224 to define an area for the die attachment material 232 to be disposed later and to insulate the second main conductor 224 in the second set 238. The insulating layer 234 can include any of the materials described with respect to the insulating layer 134 of FIG. 1. The insulating layer 234 can be formed by any of several methods. In one version of this example, the insulating layer 234 can be formed by spin coating the microelectronic device 200 with a photosensitive polymer material such as polyimide, exposing the photosensitive polymer material to patterned ultraviolet (UV) light, and then growing the photosensitive polymer material. In another version, the insulating layer 234 can be formed by a screen printing process. In a further version, the insulating layer 234 can be formed by an additive process such as a material extrusion process. Other methods for forming the insulating layer 234 are also within the scope of this example.

[0042] The die attachment material 232 is formed on the die attachment surface 226 of the bump bond 230. The die attachment material 232 may include solder in the form of a solder paste, which is formed by a screen printing process or a material extrusion process. The die attachment material 232 may include solder in the form of a solder layer, which is formed using a molten solder bath. The die attachment material 232 may include a conductive adhesive, which is formed by a screen printing process or a material extrusion process. Other compositions for the die attachment material 232 and methods for its formation are also within the scope of this example. The insulating layer 234 may be used to define an area for the die attachment material 232.

[0043] The microelectronic device 200 is attached to the external lead 236 by electrically coupling the bump bond 230 to the external lead 236 via the die attachment material 232. The external lead 236 may be part of a package that includes the microelectronic device 200, such as a lead frame or a chip carrier. Alternatively, the external lead 236 may be part of a circuit board on which the microelectronic device 200 is mounted, such as a printed circuit board (PCB). In this example version where the die attachment material 232 includes solder, the microelectronic device 200 may be attached to the external lead 236 by a solder reflow process. In this example version where the die attachment material 232 includes an adhesive, the microelectronic device 200 may be attached to the external lead 236 by an adhesive curing process. The inductor 240 formed from the first lateral conductor 208, the conductive column 214, and the second lateral conductor 220 may be sufficiently robust to withstand the process of attaching the microelectronic device 200 to the external lead 236 without significant degradation.

[0044] Figures 3A through 3F are cross-sectional views of a microelectronic device having a die, bump bonds on the die, and inductors, shown at certain stages of another exemplary method of formation. Referring to FIG. 3A, the microelectronic device 300 includes a die 302 that may be implemented as a discrete semiconductor device, an integrated circuit, a MEMS device, or other such microelectronic die. The die 302 has terminals 304 of conductive material that extend to a terminal surface 306 of the die 302.

[0045] In this example, the terminals 304 may include one or more extended terminals 304a that span the length of the lower winding in the area for the inductor 340. Also, one or more interconnects 352 of the die 302 may span the length of the lower winding and may be electrically coupled to the extended terminals 304a by vias 354 of the die 302. The interconnects 352 and vias 354 may be part of the interconnect network of the die 302.

[0046] A first conductor seed layer 310 is formed on the die 302 in contact with the terminals 304. The first conductor seed layer 310 may have a layer structure and composition as described with respect to the first conductor seed layer 210 of FIG. 2A and may be formed as described with respect to the first conductor seed layer 210.

[0047] A first conductor plating mask 342 is formed over the first conductor seed layer 310, exposing an area for a first lateral conductor 308. The first conductor plating mask 342 may have a composition as described with respect to the first conductor plating mask 242 of FIG. 2A and may be formed as described with respect to the first conductor plating mask 242.

[0048] The first main conductor 312 is formed on the first conductor seed layer 310 at the location exposed by the first conductor plating mask 342 using the first copper plating bath 356. The first copper plating bath 356 can be implemented in an electroplating process or an electroless plating process. In this example, after the first main conductor 312 is formed, the first conductor plating mask 342 is left in place. A portion of the first conductor seed layer 310 between the first main conductor 312 and the terminal surface 306 is combined with the first main conductor 312 to provide the first lateral conductor 308 of the microelectronic device 300.

[0049] Referring to FIG. 3B, a column plating mask 344 is formed on the first conductor plating mask 342 and the first lateral conductor 308, exposing an area for the conductive column 314 on the first lateral conductor 308. The column plating mask 344 can have a composition as described for the column plating mask 244 of FIG. 2D and can be formed by any of the methods described for the column plating mask 244.

[0050] The second conductor seed layer 358 is formed on the column plating mask 344 in contact with the first lateral conductor 308 at the location exposed by the column plating mask 344. The second conductor seed layer 358 can have a layer structure and composition as described for the column seed layer 216 of FIG. 2C or the second conductor seed layer 222 of FIG. 2F and can be formed as described for the column seed layer 216 or the first conductor seed layer 210.

[0051] The second conductor plating mask 346 is formed on the second conductor seed layer 358, exposing an area for the second lateral conductor 320. The second conductor plating mask 346 can have a composition as described for the second conductor plating mask 246 of FIG. 2F and can be formed by any of the methods described for the second conductor plating mask 246.

[0052] The second main conductor 360 is formed using a second copper plating bath 362 on a second conductor seed layer 358 at a location exposed by the second conductor plating mask 346. The second copper plating bath 362 can be implemented in an electroplating process or an electroless plating process, and can be implemented using the equipment and plating solution of the first copper plating bath 356 in FIG. 3A. A portion of the second conductor seed layer 358 laterally surrounded by the column plating mask 344 is combined with a portion of the second main conductor 360 laterally surrounded by the column plating mask 344 to provide a conductive column 314 of the microelectronic device 300. A portion of the second conductor seed layer 358 laterally surrounded by the second conductor plating mask 346 is combined with a portion of the second main conductor 360 laterally surrounded by the second conductor plating mask 346 to provide a second lateral conductor 320 of the microelectronic device 300. By providing the conductive column 314 and the second lateral conductor 320 from a portion of the second main conductor 360 formed using one plating bath, the manufacturing cost and complexity can be reduced compared to forming the conductive column 314 and the second lateral conductor 320 using separate plating baths.

[0053] Referring to FIG. 3C, the second lateral conductor 320 has a die attachment surface 326 located on the opposite side of the first lateral conductor 308. Optionally, a barrier layer 364 can be formed on the second lateral conductor 320 covering the die attachment surface 326. The barrier layer 364 can include one or more metals that reduce the diffusion of copper and tin to suppress the formation of a copper-tin intermetallic compound. The barrier layer 364 can include, for example, nickel, cobalt, or molybdenum. The barrier layer 364 can be particularly advantageous when a tin-containing solder, such as a silver-tin solder, is placed on the second lateral conductor 320. The barrier layer 364 can be formed by an electroplating process, such as a reverse pulse electroplating process. Such an electroplating process can enable a desired ratio of metals in the barrier layer 364 that is difficult to achieve using direct current (DC) plating.

[0054] Thereafter, the second conductor plating mask 346 is removed. The second conductor plating mask 346 can be removed by any of the methods described for removing the second conductor plating mask 246 with respect to FIG. 2H.

[0055] The second conductor seed layer 358 at the location exposed by the removal of the second conductor plating mask 346 is removed. The second conductor seed layer 358 can be removed by any of the methods described for removing the second conductor seed layer 222 with respect to FIG. 2I.

[0056] The column plating mask 344 is removed. The column plating mask 344 can be removed by any of the methods described for removing the column plating mask 244 with respect to FIG. 2J.

[0057] The first conductor seed layer 310 at the location exposed by the removal of the column plating mask 344 is removed. The first conductor seed layer 310 can be removed by any of the methods described for removing the first conductor seed layer 210 with respect to FIG. 2J. As a result of the removal of the first conductor seed layer 310, a portion of the second conductor seed layer 358 exposed by the removal of the column plating mask 344 can be removed.

[0058] Referring to FIG. 3D, a first set 328 of the first lateral conductor 308, the conductive column 314, and the second lateral conductor 320 provides the bump bond 330 of the microelectronic device 300. A second set 338 of the first lateral conductor 308, the conductive column 314, and the second lateral conductor 320 are electrically configured in series to provide the inductor 340. The extended terminal 304a and the interconnect 352 are electrically coupled in parallel with the first lateral conductor 308 of the inductor 340 to reduce the electrical resistance of the inductor 340 and, therefore, increase the Q value of the inductor 340.

[0059] The die attachment material 332 is formed on the die attachment surface 326 and, if present, on the barrier layer 364. The die attachment material 332 can have any of the compositions described for the die attachment material 232 of FIG. 2L. The die attachment material 332 can be formed by any of the methods described with respect to the die attachment material 232.

[0060] A magnetic material 366 having a relative permeability greater than 1 can be formed between the conductive columns 314 of the inductor 340, which can increase the inductance of the inductor 340. The magnetic material 366 can include, in a polymer binder such as an epoxy, for example, ferrite particles or ferromagnetic particles including iron, nickel, or cobalt. The magnetic material 366 can be formed within the inductor 340 using an additive process such as the material extrusion process 368 shown in FIG. 3D.

[0061] Referring to FIG. 3E, the microelectronic device 300 is attached to the external lead 336 by electrically coupling the bump bond 330 and the inductor 340 to the external lead 336 via the die attachment material 332. The external lead 336 can be part of a package including the microelectronic device 300 or can be part of a circuit board on which the microelectronic device 300 is mounted. The microelectronic device 300 can be attached to the external lead 336 as described with respect to FIG. 2L. In this example, the external lead 336 electrically coupled to the inductor 340 can further reduce the electrical resistance of the inductor 340 and, therefore, can increase the Q value of the inductor 340. The inductor 340 and the bump bond 330 formed from the first lateral conductor 308, the conductive columns 314, and the second lateral conductor 320 can be robust enough to withstand the process of attaching the microelectronic device 300 to the external lead 336 without compromising mechanical integrity even when the inductor 340 and the bump bond 330 are not mechanically supported by an encapsulation material.

[0062] Referring to FIG. 3F, an encapsulating material 348, sometimes referred to as an underfill material, can surround the first lateral conductor 308, the conductive column 314, the second lateral conductor 320, and the die attachment material 332, extend to the external lead 336, and be formed on the die 302. The encapsulating material 348 can include epoxy and can be formed by injection molding. The encapsulating material 348 can provide mechanical support for the first lateral conductor 308, the conductive column 314, and the second lateral conductor 320.

[0063] FIG. 4 is a top view of an exemplary microelectronic device having a die and an inductor on the die. The microelectronic device 400 includes a die 402, and the die 402 has a terminal surface 406. The microelectronic device 400 includes a first lateral conductor 408, a conductive column 414, and a second lateral conductor 420 on the terminal surface 406. A first set of the first lateral conductor 408, the conductive column 414, and the second lateral conductor 420 (not shown in FIG. 4) provides a bump bond (not shown in FIG. 4) of the microelectronic device 400. A second set 438 of the first lateral conductor 408, the conductive column 414, and the second lateral conductor 420 is electrically configured in series to provide an inductor 440. In this example, the inductor 440 has an annular configuration such that the first lateral conductor 408, the conductive column 414, and the second lateral conductor 420 of the inductor 440 are arranged on a closed loop array. A magnetic material 466 having a relative permeability greater than 1 can be located on the first lateral conductor 408 and under the second lateral conductor 420 in the inductor 440. The annular configuration can provide a desired inductance for the inductor 440 in a compact space on the terminal surface 406. One or more nodes of the inductor 440 can be electrically coupled to components in the die 402 or to external leads (not shown in FIG. 4).

[0064] FIG. 5 is a top view of another exemplary microelectronic device having a die and a transformer including two inductors on this die. The microelectronic device 500 includes a die 502, and the die 502 has a terminal surface 506. The microelectronic device 500 includes a first lateral conductor 508, a conductive column 514, and a second lateral conductor 520 on the terminal surface 506. A first set (not shown in FIG. 5) of the first lateral conductor 508, the conductive column 514, and the second lateral conductor 520 provides bump bonding (not shown in FIG. 5) of the microelectronic device 500. A first second set 538a of the first lateral conductor 508, the conductive column 514, and the second lateral conductor 520 is electrically configured in series to provide a first inductor 540a. A second second set 538b of the first lateral conductor 508, the conductive column 514, and the second lateral conductor 520 is electrically configured in series to provide a second inductor 540b. A magnetic material 566 having a relative permeability greater than 1 is located above the first lateral conductor 508 and below the second lateral conductor 520 in the first inductor 540a and the second inductor 540b. In this example, the first inductor 540a has a linear configuration such that the first lateral conductor 508, the conductive column 514, and the second lateral conductor 520 are arranged on the surface of a cylinder around the magnetic material 566. Similarly, the second inductor 540b has a linear configuration around the magnetic material 566. The first inductor 540a and the second inductor 540b are elements of a transformer 570. FIG. 5 shows the first inductor 540a and the second inductor 540b with the same number of turns around the magnetic material 566, but other configurations of the transformer 570 having different numbers of turns are within the scope of this example. The transformer 570 can enable transmission of signals or power between the first inductor 540a and the second inductor 540b without consuming space in the die 502.

[0065] FIG. 6 is a top view of another exemplary microelectronic device having a die and a transformer including two inductors on this die. The microelectronic device 600 includes a die 602, and the die 602 has a terminal surface 606. The microelectronic device 600 includes a first lateral conductor 608, a conductive column 614, and a second lateral conductor 620 on the terminal surface 606. A first set of the first lateral conductor 608, the conductive column 614, and the second lateral conductor 620 (not shown in FIG. 6) provides a bump bond (not shown in FIG. 6) of the microelectronic device 600. A first second set 638a of the first lateral conductor 608, the conductive column 614, and the second lateral conductor 620 is electrically configured in series to provide a first inductor 640a. A second second set 638b of the first lateral conductor 608, the conductive column 614, and the second lateral conductor 620 is electrically configured in series to provide a second inductor 640b. In this example, the first inductor 640a and the second inductor 640b have a linear configuration and are interdigitated to form a transformer 670. Due to the interdigitated configuration of the transformer 670, signal or power transmission between the first inductor 640a and the second inductor 640b may be possible without disposing a magnetic material in the first inductor 640a or the second inductor 640b.

[0066] The various features of the examples described in this application can be combined in other embodiments of the exemplary microelectronic devices. For example, the microelectronic device 100 of FIG. 1 may be formed by the processes described with respect to the methods of FIGS. 2A-2L, by the processes described with respect to the methods of FIGS. 3A-3F, or by another method. The microelectronic devices described in this application can be formed using any method, such as the method described in the patent application filed on Jul. 9, 2018, patent application Ser. No. 16 / 030,371, attorney docket number TI-78661, which is assigned to the assignee of the present invention. The above application is incorporated herein by reference, but is not admitted to be prior art to the present description. The bump bond 130 of FIG. 1 may have the barrier layer 364 of FIG. 3C. The microelectronic device 100 of FIG. 1 may include an encapsulating material 248 comprising magnetic particles 250, as described with respect to FIG. 2K, or may include a magnetic material 366, as described with respect to FIG. 3D.

[0067] Although the various embodiments of this description have been described above, they are presented merely as examples and not as limitations. Without departing from the spirit or scope of this description, numerous changes can be made to the described embodiments in the context of this application. Thus, the breadth and scope of this description should not be limited by any of the above-described embodiments. Rather, the scope of this description should be defined in the following claims and their equivalents.

Claims

1. 1. A microelectronic device comprising: a die having terminals extending to a terminal surface of the die; a first lateral conductor extending along a surface of the terminal, at least a portion of the first lateral conductor being electrically coupled to at least a portion of the terminal; a conductive column on the first horizontal conductor extending perpendicularly away from the terminal surface; and a second lateral conductor on the conductive column opposite the first lateral conductor and extending laterally in a plane parallel to the terminal surface; Including, a first set of the first lateral conductors, the conductive columns, and the second lateral conductors providing bump bonds of the microelectronic device; a second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form an inductor of the microelectronic device.

2. 10. The microelectronic device of claim 1, The microelectronic device, wherein the first lateral conductor comprises copper.

3. 3. The microelectronic device of claim 2, each of the first lateral conductors includes a first conductive seed layer on the terminal surface, the first conductive seed layer including at least one metal selected from the group consisting of titanium, tungsten, chromium, and nickel.

4. 10. The microelectronic device of claim 1, The microelectronic device, wherein the first lateral conductor has a thickness of between 3 microns and 30 microns.

5. 10. The microelectronic device of claim 1, 1. A microelectronic device, wherein the conductive columns comprise copper, the conductive columns having a width, measured parallel to the terminal surface, of 25 microns to 50 microns, a length, measured parallel to the terminal surface, of 25 microns to 300 microns, and a height, measured perpendicular to the terminal surface, of 30 microns to 100 microns.

6. 10. The microelectronic device of claim 1, A microelectronic device, wherein each of the conductive columns includes a column seed layer on the first lateral conductor, the column seed layer including at least one metal selected from the group consisting of titanium, chromium, and nickel.

7. 10. The microelectronic device of claim 1, the second lateral conductor comprises copper; each of the second lateral conductors includes a second conductor seed layer on the conductive columns, the second conductor seed layer including at least one metal selected from the group consisting of titanium, chromium, and nickel.

8. 10. The microelectronic device of claim 1, The second lateral conductor has a thickness of between 3 microns and 30 microns.

9. 10. The microelectronic device of claim 1, A microelectronic device comprising a die attach material on at least a portion of the second lateral conductors, the die attach material being selected from the group consisting of solder and adhesive.

10. 10. The microelectronic device of claim 1, A microelectronic device comprising a magnetic material located in the inductor, the magnetic material having an average relative magnetic permeability greater than 1, where the relative magnetic permeability of a vacuum is 1.

11. 11. The microelectronic device of claim 10, The microelectronic device, wherein the magnetic material includes an encapsulant comprising magnetic particles located on the die.

12. 11. The microelectronic device of claim 10, A microelectronic device, wherein the inductor has a linear configuration in which the first lateral conductors, the conductive columns, and the second lateral conductors of the inductor are arranged in a linear array.

13. 11. The microelectronic device of claim 10, A microelectronic device, wherein the inductor has an annular configuration in which the first lateral conductor, the conductive columns, and the second lateral conductor of the inductor are arranged in a closed loop array.

14. 1. A method of forming a microelectronic device, comprising: obtaining a die having terminals extending to a terminal surface of the die; forming a first lateral conductor extending along a surface of the terminal such that at least a portion of the first lateral conductor contacts at least a portion of the terminal; forming a conductive column on the first horizontal conductor so as to extend vertically away from the terminal surface; and forming a second lateral conductor on the conductive column opposite the first lateral conductor so as to extend laterally in a plane parallel to the terminal surface; Including, a first set of the first lateral conductors, the conductive columns, and the second lateral conductors providing bump bonds of the microelectronic device; a second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form an inductor of the microelectronic device.

15. 15. The method of claim 14, forming the first lateral conductor; forming a first conductive seed layer on a surface of the terminal such that the first conductive seed layer contacts the terminal; forming a first conductor plating mask over the first conductor seed layer such that the first conductor plating mask exposes the first conductor seed layer in areas intended for the first lateral conductors; forming a first main conductor on the first conductor seed layer at locations exposed by the first conductor plating mask using a plating process; removing the first conductor plating mask; and removing the first conductor seed layer where exposed by the first main conductor, such that the first main conductor and the first conductor seed layer between the first main conductor and the terminal surface provide the first lateral conductor; Including, The method, wherein the first conductive seed layer comprises at least one metal selected from the group consisting of titanium, tungsten, chromium, and nickel.

16. 15. The method of claim 14, forming the conductive columns forming a column seed layer adjacent the first lateral conductor; forming a column plating mask over the column seed layer such that the column plating mask exposes the column seed layer in areas intended for the conductive columns; forming main columns on the column seed layer at locations exposed by the column plating mask using a plating process; removing the column plating mask; and removing the column seed layer where exposed by the main columns, such that the main columns and the column seed layer between the main columns and the first lateral conductor provide the conductive columns; Including, the column seed layer comprises at least one metal selected from the group consisting of titanium, chromium, and nickel; method.

17. 15. The method of claim 14, forming the second lateral conductor; forming a second conductive seed layer contacting the conductive columns; forming a second conductor plating mask over the second conductor seed layer such that the second conductor plating mask exposes the second conductor seed layer in areas intended for the second lateral conductors; forming a second main conductor on the second conductor seed layer at locations exposed by the second conductor plating mask using a plating process; removing the second conductor plating mask; and removing the second conductor seed layer where exposed by the second main conductor, such that the second main conductor and the second conductor seed layer between the second main conductor and the conductive columns provide the second lateral conductor; Including, The method, wherein the second conductive seed layer comprises at least one metal selected from the group consisting of titanium, tungsten, chromium, and nickel.

18. 15. The method of claim 14, forming the conductive columns and forming the second lateral conductor; forming a column plating mask over the first lateral conductors such that the column plating mask exposes the first lateral conductors in areas intended for the conductive columns; forming a second conductor seed layer over the column plating mask such that the second conductor seed layer contacts the first lateral conductors at locations exposed by the column plating mask; forming a second conductor plating mask over the second conductor seed layer such that the second conductor plating mask exposes the second conductor seed layer in areas intended for the second lateral conductors; forming a second main conductor on the second conductor seed layer at locations exposed by the second conductor plating mask using a plating process, whereby a portion of the second conductor seed layer laterally surrounded by the column plating mask combines with a portion of the second main conductor laterally surrounded by the column plating mask to provide the conductive column; forming the second main conductor such that a portion of the second conductor seed layer laterally surrounded by the second conductor plating mask combines with a portion of the second main conductor laterally surrounded by the second conductor plating mask to provide the second lateral conductor; removing the second conductor plating mask; removing the second conductor seed layer where exposed by the second main conductor; and removing the column plating mask; A method comprising:

19. 15. The method of claim 14, forming a magnetic material in the inductor, the magnetic material having an average relative permeability greater than 1, where the relative permeability of a vacuum is 1.

20. 15. The method of claim 14, forming a die attach material over at least a portion of the second lateral conductor; and electrically coupling the bump bonds to external leads through the die attach material; Including, The method, wherein the die attach material is selected from the group consisting of solder and adhesive.

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