Packaging substrate and method for manufacturing packaging substrate

Abstract

To provide a packaging substrate capable of reducing an undulation phenomenon that may occur due to a gap between electronic elements and / or a gap between a cavity portion and the electronic element, etc., and a method for manufacturing the same.SOLUTION: A packaging substrate includes a core layer 22 including a glass substrate 21 having first and second surfaces opposite each other and a cavity portion penetrating the glass substrate. A cavity module is disposed in the cavity portion. The cavity module includes a plurality of electronic elements 40 that are arranged, a first insulating layer 61 covering each of the electronic elements, and a third insulating layer 71 containing a molding material and disposed such that the molding material covers the electronic elements. The first insulating layer is disposed on an entire surface or an entire surface excluding one surface of each of the electronic elements, and a second insulating layer 62 is embedded in a portion of the cavity portion excluding the cavity module. Dielectric constants of the first insulating layer, the second insulating layer and the third insulating layer are mutually different.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] Embodiments relate to a substrate for packaging, a semiconductor package, a method for manufacturing a substrate for packaging, a method for manufacturing a semiconductor package, and the like.

Background Art

[0002] In fabricating electronic components, forming a circuit on a semiconductor wafer is referred to as the front-end (FE) process, and assembling the wafer into a state where it can be used as an actual product is referred to as the back-end (BE) process. This back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron line widths in nanometer units, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, relatively, there is no technology to perfectly package this. Therefore, the electrical performance of a semiconductor may sometimes be determined by the packaging technology and the electrical connections thereby, rather than the performance of the semiconductor technology itself.

[0004] As materials for substrates for packaging, ceramics or resins are applied. In the case of a ceramic substrate such as a silicon substrate, it is not easy to mount high-performance high-frequency semiconductor elements because of its high resistance value or high dielectric constant. In the case of a resin substrate, it is relatively possible to mount high-performance high-frequency semiconductor elements. However, there is a limit to reducing the pitch of wiring.

[0005] Recently, silicon or glass can be applied to substrates for high-end packaging. By forming through-holes in a silicon or glass substrate and applying a conductive substance to these through-holes, the wiring length between the element and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

[0006] In addition, heat may be generated during operation of the semiconductor package, and heat dissipation means for dissipating such heat may further be included.

[0007] As related prior arts, there are Korean Registered Patent No. 10-2543188, US Registered Patent US11676942B2, etc.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] An object of the embodiment is to provide a method for manufacturing a packaging substrate capable of improving an undulation phenomenon that may occur due to a gap between electronic elements and / or a gap between a cavity portion and an electronic element in a packaging substrate using a glass substrate, and a packaging substrate using the same.

MEANS FOR SOLVING THE PROBLEMS

[0009] To achieve the above object, a packaging substrate according to one or more embodiments includes a glass core having a first surface and a second surface facing each other; and a core layer including a cavity portion penetrating the glass core.

[0010] A cavity module and a second insulating layer are disposed in the cavity portion.

[0011] The cavity module includes a plurality of electronic elements, a first insulating layer, and a third insulating layer.

[0012] The first insulating layer is a layer that covers each of the electronic elements with a coating material.

[0013] The third insulating layer is a layer that covers the plurality of disposed electronic elements with a molding material.

[0014] The first insulating layer may be disposed on the entire surface or the entire surface except one surface of each of the electronic elements.

[0015] The second insulating layer may be embedded in a portion of the internal space of the cavity portion excluding the cavity module.

[0016] The first insulating layer and the third insulating layer may have different dielectric constants from each other.

[0017] The coating material can have a lower dielectric constant than the molding material of the third insulating layer.

[0018] The high-frequency relative dielectric constant Dk is the relative dielectric constant at a high frequency of 5.8 GHz.

[0019] Dk1 is the high-frequency relative dielectric constant of the first insulating layer, and Dk3 is the high-frequency relative dielectric constant of the third insulating layer.

[0020] The difference between the Dk1 and the Dk3 may be 0.1 or more.

[0021] Df1 is the dielectric loss rate of the first insulating layer, and Df3 is the dielectric loss rate of the third insulating layer.

[0022] The difference between the Df1 and the Df3 may be 0.0001 or more.

[0023] The first insulating layer can have a lower dielectric constant than the second insulating layer.

[0024] Df1 is the dielectric loss rate of the first insulating layer, and Df2 is the dielectric loss rate of the second insulating layer.

[0025] The difference between the Df1 and the Df2 may be 0.1 or more.

[0026] The first insulating layer may include an inorganic vapor deposition layer, LCP (liquid crystal polymer), EMC (Epoxy Molding Compound), ABF (Ajinomoto Build-up Film), or MPI (Modified Polyimide).

[0027] An electronic element connection electrode may be arranged on the electronic element.

[0028] The cavity module may include a cavity connection electrode.

[0029] The cavity connection electrode is an electrode that is electrically connected to the electronic element connection electrode and exposed on the surface of the cavity module.

[0030] The electronic element may include a passive element, an active element, or both of them.

[0031] A first insulating layer via penetrating the first insulating layer may be further arranged in the first insulating layer.

[0032] A third insulating layer via penetrating at least a part of the third insulating layer may be further arranged in the third insulating layer.

[0033] Part or all of the interior of the first insulating layer via and the third insulating layer via may be filled with an electrode material.

[0034] To achieve the above object, a manufacturing method of a packaging substrate according to one or more embodiments includes a preparation step of preparing a glass substrate with a cavity portion and a cavity module; and a lamination step of arranging the cavity module in the cavity portion and providing a second insulating layer on the glass substrate.

[0035] The cavity module includes a plurality of electronic elements, a first insulating layer, and a third insulating layer.

[0036] The first insulating layer is a layer that covers each of the electronic elements with a coating material.

[0037] The first insulating layer may be disposed on the entire surface or the entire surface excluding one surface of each of the electronic elements.

[0038] The third insulating layer is a layer that covers the plurality of disposed electronic elements with a molding material.

[0039] The second insulating layer may be embedded in a portion of the internal space of the cavity portion excluding the cavity module.

[0040] The first insulating layer and the third insulating layer may have different dielectric constants from each other.

[0041] The cavity module may be manufactured by a cavity module manufacturing step.

[0042] The cavity module manufacturing step includes an arranging process of arranging adjacent electronic elements; a primary insulating process of providing a first insulating layer on the surface of the arranged electronic elements; and a molding process of molding the electronic elements provided with the first insulating layer with a molding material to provide a cavity module including a third insulating layer.

[0043] The molding material may include EMC (Epoxy Molding Compound), ABF (Ajinomoto Build-up Film), or MPI (Modified Polyimide).

[0044] The cavity module manufacturing step may further include a cavity electrode forming process after the molding process.

[0045] The cavity electrode formation process is a process of removing a part of the molding material, forming an electrode connected to the connection electrode of the electronic element, and arranging a cavity module connection electrode connected to the electrode.

Advantages of the Invention

[0046] The packaging substrate and the method for manufacturing the packaging substrate according to the embodiment can prevent the occurrence of the angulation phenomenon in the cavity portion in which the electronic element is embedded, and can improve the quality of the packaging substrate.

[0047] The embodiment can improve the angulation phenomenon in the cavity portion and prevent the occurrence of leakage current in the electronic element including the passive element and / or the active element.

[0048] The embodiment can prevent a short circuit due to contact between adjacent electronic elements. Exemplarily, the embodiment can prevent a short circuit that may occur unintentionally in the manufacturing process of forming an electrically conductive layer on the side surface of the cavity portion.

[0049] The embodiment can prevent the position of the electronic element from being changed by forming the third insulating layer, which can prevent contact between the electronic elements and prevent a short circuit phenomenon that may occur unintentionally between them.

Brief Description of the Drawings

[0050]

Figure 1

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

BEST MODE FOR CARRYING OUT THE INVENTION

[0051] To assist in a comprehensive understanding of the methods, apparatuses, and / or systems described in this specification, the following detailed description is provided. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described in this specification will become apparent after understanding the content presented in this application. For example, the order of operations described in this specification is merely illustrative and is not limited to the operations described herein. Except for steps that must proceed in a certain order, the order of operations may be changed according to the understanding of the content presented in this application. Also, the description of known features may be omitted to enhance clarity and conciseness after understanding the disclosure of this application. However, the omission of such features and their descriptions is not intended to be recognized as general knowledge.

[0052] The features described in this specification can be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided to illustrate some of the ways, apparatuses, and / or systems for embodying many of the possible embodiments that will become apparent after understanding the disclosure of this application.

[0053] In this specification, terms such as "first," "second," "third," etc. can be used to describe various members, components, regions, layers, or cross-sections, but these members, components, regions, layers, or cross-sections are not limited to these words. Instead, such terms are used for the purpose of distinguishing one member, component, region, layer, or section from another member, component, region, layer, or section. Therefore, the first member, component, region, layer, or section referred to in the examples described in this specification can also be referred to as the second member, component, region, layer, or section without departing from the teachings of the examples.

[0054] Throughout the specification, when an element such as a layer, region, or substrate is described as "on," "connected to," or "coupled to" another element, it can be described as being directly "on," "connected to," or "coupled to" the other element, or one or more other elements can intervene therebetween. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to," no other element can intervene therebetween. Similarly, expressions such as "between" and "directly between," and "contact" and "directly contact" can also be interpreted as described above.

[0055] The terms used in this specification are for illustrative purposes only and are not used to limit the disclosure. The singular forms used in this specification are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and / or" used in this specification includes any one or more combinations of the related listed items. The terms "comprising", "consisting of" and "including" in this specification specify the presence of the stated features, numbers, operations, elements, components and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components and / or combinations thereof. In this specification, the use of the term "can" in relation to an illustration or example (e.g., what an illustration or example includes or can embody) means that there is at least one illustration or example in which such a feature is included or embodied, but not all examples are limited to this.

[0056] In this application, "B is located on A" means that B is in direct contact with A or is arranged on A with another layer or structure intervening therebetween, and thus should not be construed as B being in direct contact with A.

[0057] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be construed to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0058] In the above one or more examples, the description of "A and / or B" means "A, B, or A and B".

[0059] In the above one or more examples, terms such as "first", "second", "A" or "B" are used to distinguish the same terms from each other.

[0060] In the above one or more examples, unless otherwise specified, the singular form is to be construed contextually as including not only the singular form but also the plural forms.

[0061] In the above one or more examples, the coefficient of thermal expansion described without specific reference to temperature means the coefficient of thermal expansion at normal temperature or room temperature.

[0062] FIG. 1 is a conceptual diagram for explaining a cross-sectional structure of a packaging substrate according to an embodiment. FIGS. 2A and 2B respectively show conceptual diagrams for explaining in cross-section the structures of packaging substrates according to other embodiments. FIG. 3A is a conceptual diagram for explaining the process of generating the cross-sectional structure of the packaging substrate of FIG. 2A. Further, FIG. 3B is a conceptual diagram for explaining the process of generating the cross-sectional structure of FIG. 2B.

[0063] To achieve the above object, a semiconductor device 100 according to an embodiment includes a semiconductor element portion 30 in which one or more semiconductor elements (first semiconductor element: 32, second semiconductor element: 34, third semiconductor element: 36) are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20 and transmitting external electrical signals to and connecting the semiconductor elements (first semiconductor element: 32, second semiconductor element: 34, third semiconductor element: 36) to each other.

[0064] A packaging substrate 20 according to an embodiment includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity portion 28 where a cavity element 40 can be located. The cavity element 40 is illustrated as being disposed at the lower end of the packaging substrate 20 in FIG. 1, but is not limited to being disposed at the lower end.

[0065] The semiconductor element portion 30 refers to an element to be mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, as the semiconductor element portion 30, for example, arithmetic elements such as a CPU and a GPU (first semiconductor element: 32, second semiconductor element: 34), memory elements such as memory chips (third semiconductor element: 36), etc. may be applied, but any semiconductor element to be mounted on a semiconductor device can be applied without limitation.

[0066] As the motherboard 10, a motherboard such as a printed circuit board or a printed wiring board may be applied.

[0067] The packaging substrate 20 can further include a lower layer 29 selectively located under the core layer.

[0068] The core layer 22 includes a glass substrate 21 having a first region 221 with a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness or has a thickness of 0, a plurality of core vias 23 penetrating the glass substrate 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting the first surface 213 of the glass substrate 21 and the second surface 214 facing the first surface through the core vias 23.

[0069] The second region 222 of the core layer 22 can serve as a cavity structure.

[0070] Within the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and these two surfaces are generally parallel to each other, so the glass substrate 21 has a constant thickness throughout.

[0071] The internal space 281 formed by the difference in thickness between the first region 221 and the second region 222 serves to accommodate part or all of the cavity element 40. FIGS. 2B and 3B illustrate a full cavity from which the glass substrate of the second region has been removed. However, the embodiment is not limited thereto, and a half cavity is also applicable. An illustration of the half cavity is presented in FIGS. 2A and 3A.

[0072] The glass substrate 21 may include a core via 23 that penetrates the first surface 213 and the second surface 214. When the second thickness is not zero, the core via 23 may be formed in both the first region 221 and the second region 222 and may be formed with an intended pitch and pattern. Also, when the second thickness is zero, the core via 23 may be formed in the first region 221 and may be formed with an intended pitch and pattern.

[0073] Conventionally, as a packaging substrate for a semiconductor device, a form in which a silicon substrate and an organic substrate are laminated has been applied. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements occurring when applied to a high-speed circuit, and there is a drawback that power loss is relatively large. Also, in the case of an organic substrate, in order to form a more complex distribution pattern, a larger area is required, which does not conform to the manufacturing process of miniaturized electronic devices. In order to form a complex distribution pattern within a defined size, substantial pattern miniaturization is required, but due to the characteristics of materials such as polymers applied to organic substrates, there is a substantial limit to pattern miniaturization.

[0074] In an embodiment, as a method of solving such problems, the glass substrate 21 is applied as a support for the core layer 22. Also, by applying a core via 23 formed through the glass substrate 21 together with the glass substrate 21, the length of the electrical flow is further shortened, providing a packaging substrate 20 that is further miniaturized, has a faster reaction, and has less loss characteristics.

[0075] The glass substrate 21 is preferably a glass substrate applied to semiconductors. For example, a borosilicate glass substrate, a non-alkali glass substrate, etc. may be applied, but it is not limited thereto.

[0076] The core via 23 penetrates the glass substrate 21. The core via 23 can be formed by a method of removing a predetermined area of the glass substrate 21. Specifically, it can be formed by etching plate-shaped glass by physical and / or chemical methods.

[0077] Specifically, for the formation of the core via 23, after forming a defect (scratch) on the surface of the glass substrate by a method such as laser, a method of chemically etching, laser etching, etc. may be applied, but it is not limited thereto.

[0078] Based on the unit area (1 cm × 1 cm) of the glass substrate 21, the number of the core vias 23 may be 100 to 3,000, may be 100 to 2,500, or may be 225 to 1,024. When such pitch conditions are satisfied, the formation of an electrically conductive layer, etc. and the performance of the packaging substrate can be improved.

[0079] The core distribution layer 24 includes a core distribution pattern 241 which is an electrically conductive layer that electrically connects the first surface and the second surface of the glass substrate via a through-via, and a core insulating layer 223 that covers the core distribution pattern. The core layer 22 serves as an electrical path across the glass substrate 21 by forming an electrically conductive layer therein via a core via, and can connect the upper and lower portions of the glass substrate at a relatively short distance, thereby enabling faster electrical signal transmission and having low-loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but it is not limited thereto.

[0080] The cavity portion 28 is substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, etc., and there is no limitation on its shape.

[0081] The cavity element 40 may have a shape that is generally cylindrical, cuboid, or polygonal.

[0082] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that covers the cavity distribution pattern.

[0083] On the other hand, the cavity portion according to another embodiment may be embodied in a form that penetrates the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by a process similar to the process of forming the core via 23, and the area and shape penetrating the glass substrate 21 may be different from those of the core via 23.

[0084] In such an embodiment, after the cavity element 40 is arranged in the cavity portion, an insulating layer may be generated. That is, an insulating layer may also be generated in the cavity portion through the process of generating the core insulating layer 223 described above.

[0085] The core distribution pattern 241 may be patterned so as to be electrically connectable to the cavity element 40.

[0086] The cavity element 40 may include an active element such as a transistor or a power transmission element such as a multilayer ceramic capacitor (MLCC), that is, a passive element.

[0087] When an element such as a transistor that serves to convert an electrical signal between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, transistors and the like are applied to the passages of the packaging substrate 20, so that a semiconductor device 100 that is more efficient and has a high speed can be provided.

[0088] In addition, power transmission elements such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor elements. Passive power transmission elements are generally applied to at least 200 or more semiconductor elements. In transmitting power, their performance is also affected by the characteristics of the electrical conductive layers around the elements. In one embodiment, non-circular core vias can be applied where a low-resistance electrical conductive layer is required, such as for such power transmission elements.

[0089] On the other hand, passive elements such as capacitors may be individually inserted and applied as the cavity element 40, or an element group including a large number of passive elements in a form embedded between insulator layers (cavity element insulator layers) may be inserted into the cavity element after being formed such that the electrodes are exposed. In the latter case, the workability of manufacturing the packaging substrate can be made smoother, and it is more advantageous for the insulator layer to be positioned in the space between complex elements sufficiently and with high reliability.

[0090] The glass substrate 21 serves as an intermediate role connecting the semiconductor element portion 30 and the mother board 10 to the upper and lower parts respectively, and the core via 23 serves as a path for transmitting these electrical signals, so as to perform smooth signal transmission. For the purpose of distinguishing from the core vias in the second region 222 described later, the core vias arranged in the first region 221 are referred to as first region core vias.

[0091] An upper layer 26 is located on the first surface 213.

[0092] The upper layer 26 can include an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25. The uppermost surface of the upper layer 26 can be protected by a cover layer 60 in which an opening is formed where the connection electrodes of the semiconductor element portion can directly abut.

[0093] The upper distribution layer 25 may include an upper insulating layer 253 located on the first surface, and an electrically conductive layer having a predetermined pattern and being electrically connected to at least a part of the core distribution layer 24, the upper distribution pattern 251 being built in the upper insulating layer 253. The upper distribution layers 25 arranged one above the other may be connected to each other via blind vias 252.

[0094] The upper insulating layer 253 can be applied as an insulator layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing fillers may be applied, but it is not limited thereto.

[0095] The insulator layer may be formed by a method of forming and curing an insulating coating layer. Alternatively, it may be formed by laminating an insulator film formed into a film in an uncured or semi-cured state on the core layer 22 and then curing it. At this time, if a vacuum lamination method or the like is applied, the insulator can be embedded into the space inside the core via 23, enabling efficient progress of the process.

[0096] According to one embodiment, even when a multi-layer insulator layer is laminated and applied, it may be difficult to substantially distinguish between the insulator layers, and a plurality of insulator layers are collectively referred to as an upper insulating layer. Also, the same insulating material may be applied to the core insulating layer 223 and the upper insulating layer 253. In such a case, their boundaries are not substantially distinguished. Alternatively, according to another embodiment, by setting different pressures and temperatures for curing the multi-layer insulator layer, boundaries of the insulator layer can also be generated.

[0097] The upper distribution pattern 251 refers to an electrically conductive layer located in the upper insulating layer 253 in a preset form, and may be formed, for example, by a build-up layer method. Specifically, after forming an insulator layer and removing unnecessary portions of the insulator layer, an electrically conductive layer is formed by a method such as copper plating. After selectively removing unnecessary portions of the electrically conductive layer, an insulator layer is formed again on this electrically conductive layer. After removing unnecessary portions again, the method of forming an electrically conductive layer by a method such as plating is repeated to form the upper distribution pattern 251 in which the electrically conductive layer is formed in a vertical or horizontal direction in the intended pattern.

[0098] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, electrical signal transmission between the semiconductor element portion 30 is smoothly performed, and at least a part thereof is formed to include a fine pattern so that an intended complex pattern can be sufficiently accommodated. At this time, the fine pattern may have a width and a pitch each less than 4 μm, may be 3.5 μm or less, may be 3 μm or less, may be 2.5 μm or less, or may be 2.3 μm or less. The width and the pitch may be 1 μm or more (hereinafter, the description of the fine pattern is the same).

[0099] The upper surface connection layer 27 includes an upper surface connection pattern 272 located in the upper insulating layer 253, which is at least partially electrically connected to the upper distribution pattern 251, and an upper surface connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper surface connection pattern 272.

[0100] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a part thereof may be embedded while being exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating. When the upper surface connection pattern is embedded while a part thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a part of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching.

[0101] The upper surface connection pattern 272 can include a fine pattern in at least a part thereof, like the upper part distribution pattern 251 described above. The upper surface connection pattern 272 including such a fine pattern enables more elements to be electrically connected under a narrow area, making the connection of electrical signals between elements or with the outside smoother and enabling more integrated packaging.

[0102] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 with a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball.

[0103] In the case of the half cavity substrate, the cavity portion 28 is located above and / or below the second region 222, and can include a cavity distribution layer 282 and an internal space 281 where the cavity element 40 is located, which is electrically connected to the core distribution pattern 241. The cavity distribution layer 282 can be formed via the second region core via 232 (see FIG. 3A).

[0104] Specifically, the thickness of the glass substrate 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in the internal space 281 formed by the difference in thickness. Further, the core via 23 and the core distribution layer 24 formed on the glass substrate 21 serve as an electrical connection structure for connecting the cavity element 40 and external elements.

[0105] Alternatively, instead of the second region 222, a cavity portion in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 1, i.e., the first region 221, may be generated, and the cavity elements 40 may be arranged in the cavity portion.

[0106] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the core distribution pattern 241 located on at least a part of the second surface 214 of the core layer 22, or may be electrically connected through a board connection portion 52 such as a solder ball. Further, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 through a lower layer (not shown) located below the core layer 22. The element connection portion 51 and the board connection portion 52 are collectively referred to as the connection portion 50.

[0107] According to an example, in addition to the glass substrate 21, substantially no other additional substrates can be applied to the packaging substrate 20 located between the semiconductor element portion 30 and the motherboard 10.

[0108] Conventionally, when connecting an element and a motherboard, an interposer and an organic substrate were laminated and applied together therebetween. This is understood to be applied in such a multi-stage form for at least two reasons. One is that there is a problem in scale in directly bonding the fine pattern of the element to the motherboard, and the other is that there is a possibility of wiring damage due to the difference in the coefficient of thermal expansion during the bonding process or the driving process of the semiconductor device. In an embodiment, a glass substrate having a coefficient of thermal expansion similar to that of the semiconductor element is applied, and a fine pattern having a fine scale sufficient for mounting the element is formed on the first surface of the glass substrate and its upper layer, thereby solving such problems.

[0109] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0110] Figures 4 and 5 are flowcharts for explaining the manufacturing process of a packaging substrate according to an embodiment in cross-section.

[0111] First, as shown in Fig. 4(a), a glass substrate 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass substrate may be a glass substrate applied to a substrate of an electronic device or the like. For example, a non-alkali glass substrate or the like may be applied, but is not limited thereto. As a commercially available product, products manufactured by manufacturing companies such as Corning, Schott, and AGC may be applied. For forming the defect (groove), methods such as mechanical etching and laser irradiation may be applied.

[0112] As shown in Fig. 4(b), the glass substrate 21a on which the defect (groove) 21b is formed is subjected to an etching step of forming a core via 23 through a physical or chemical etching process. In the etching process, vias may be formed in the defective portions of the glass substrate, and at the same time, the surface of the glass substrate 21a may also be etched. In order to prevent such etching of the glass surface, a masking film or the like may be applied. However, considering the annoyance of applying and removing the masking film, the defective glass substrate itself can be etched. In such a case, the thickness of the glass substrate having the core via may be slightly thinner than the thickness of the original glass substrate.

[0113] Thereafter, as shown in Figs. 4(c) and 4(d), a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate. The electrically conductive layer may typically be a metal layer containing copper metal, but is not limited thereto.

[0114] Since the properties of the glass surface (including the surface of the glass substrate and the surface of the core via) and the surface of the copper metal are different, the adhesion may be poor. In the embodiment, the adhesion between the glass surface and the metal can be improved by two methods: a dry method and a wet method.

[0115] The dry method is a method that applies sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel can be sputtered together with copper or the like. In such a case, the adhesion between the glass and the metal can be improved by the anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0116] The wet method is a method of performing a primer treatment, that is, a method of forming a primer layer 21c by pretreating with a compound substance having a functional group such as an amine. After pretreatment with a silane coupling agent according to the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group. As mentioned above, the support substrate of the embodiment needs to be highly performant enough to form a fine pattern, and this must be maintained even after the primer treatment. Therefore, when such a primer contains nanoparticles, it is preferable to apply nanoparticles having an average diameter of 150 nm or less. For example, particles having an amine group preferably have nanoparticles applied thereto. The primer layer may be formed by applying a bonding improver manufactured by, for example, the CZ series of MEC.

[0117] The seed layer / primer layer 21c can selectively form a metal layer for the electrical conductive layer in a state where the portion where the formation of the electrical conductive layer is unnecessary is removed or in a state where it is not removed. Further, the seed layer / primer layer 21c can selectively process the portion where the formation of the electrical conductive layer is necessary or unnecessary in an activated state or an inactivated state selectively activated for metal plating, and subsequent steps can be performed. For example, for the activation or inactivation treatment, light irradiation treatment such as laser light of a certain wavelength, chemical treatment, or the like may be applied. For the formation of the metal layer, a copper plating method or the like applied to the manufacture of semiconductor elements may be applied, but is not limited thereto.

[0118] As shown in FIG. 4(e), when a part of the core distribution layer is unnecessary, it may be removed, or after a part of the seed layer is removed or inactivated, metal plating is performed to form an electrically conductive layer in a predetermined pattern, so that an etching layer 21e of the core distribution layer may be formed.

[0119] FIG. 5 illustrates the manufacturing steps of forming an insulating layer and an upper distribution pattern according to an embodiment.

[0120] As shown in FIG. 5(a), after the formation of the core distribution layer which is the electrically conductive layer, the core via can go through an insulating layer forming step of filling the empty space with an insulating layer. At this time, the applied insulating layer can be one manufactured in the form of a film. For example, a method such as vacuum laminating an insulating layer in the form of a film may be applied. By performing vacuum lamination in this way, the insulating layer can be sufficiently embedded into the empty space inside the core via, so that a core insulating layer without void formation can be formed.

[0121] FIGS. 5(b) to (e) illustrate the upper layer manufacturing steps.

[0122] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition for forming the insulating layer 23a or by laminating an insulating film. For simplicity, it is preferable to apply the method of laminating an insulating film. The lamination of the insulating film can be performed by a process of laminating and curing the insulating film. At this time, if the vacuum lamination method is applied, the insulating resin can be sufficiently embedded even in a layer where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts at least a part of the glass substrate, so an insulating layer having sufficient adhesion is applied. Specifically, it is preferable that the glass substrate and the upper insulating layer have a characteristic that the adhesion test value according to ASTM D3359 satisfies 4B or more.

[0123] The upper distribution pattern can be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form the etched layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with an insulating layer therebetween, it can be formed by a method in which a blind via 23b is formed in the insulating layer and then a plating process is performed. The formation of the blind via may employ a dry etching method such as laser etching or plasma etching, or a wet etching method using a masking layer and an etching solution.

[0124] Thereafter, although not shown, an upper surface connection layer and a cover layer may be formed.

[0125] The upper surface connection pattern and the upper surface connection electrode can also be formed by a process similar to the formation of the upper distribution layer. Specifically, it may be formed by a method such as forming an etched layer of the insulating layer in the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etched layer of the electrically conductive layer. However, a method of selectively forming only the electrically conductive layer without applying an etching method may also be applied. The cover layer can be formed such that an opening (not shown) is formed at a position corresponding to the upper surface connection electrode to expose the upper surface connection electrode and enable direct connection to an element connection portion or a terminal of the element.

[0126] When the upper layer is generated, a step of forming a lower surface connection layer and a cover layer to generate a lower layer can be performed. The lower distribution layer and / or the lower surface connection layer, and optionally the cover layer, can be formed in a manner similar to the above-described upper surface connection layer and cover layer formation steps.

[0127] The electronic device mainly applies a method of forming an insulating layer by laminating an insulating film [e.g., ABF (Ajinomoto Build-up Film)]. In this case, an undulation phenomenon may occur. In particular, in the cavity portion where the embedding element is disposed, a severe undulation phenomenon may occur due to the gap between the elements and / or the gap between the side surface of the cavity portion and the element. Due to the severe undulation phenomenon, leakage current may occur in the cavity portion. Such leakage current can be fatal to active elements and the like.

[0128] When the electronic device is disposed in the cavity portion, particularly when a large number of electronic devices are disposed in the cavity portion, the accuracy of the arrangement position of the electronic device may be unintentionally reduced, or phenomena such as warping of the glass core that occur unintentionally in the manufacturing process may occur, which may lead to defects in the packaging substrate. Exemplarily, when elements and elements and / or elements and electrodes are disposed adjacent to each other, due to the characteristics of the elements where the electrodes are exposed, a short circuit or the like may occur due to their contact with each other, which may cause defects in the packaging substrate.

[0129] Therefore, the embodiment proposes an invention that can substantially prevent the occurrence of the undulation phenomenon in the cavity portion in which the electronic device is embedded. Through this, the purpose of preventing the occurrence of leakage current in the packaging substrate, reducing defects in the packaging substrate, and the like can be achieved. The embodiment proposes performing the process of forming the insulating layer not once but multiple times, or utilizing a cavity module in which two or more electronic devices are modularized.

[0130] FIG. 6 is an example of a cross-sectional structure of the core layer of the packaging substrate generated according to the embodiment. The packaging substrate of FIG. 6 is a diagram conceptually simplified for explaining the core layer generated according to the embodiment, and the content described with reference to FIGS. 1 to 3 can be applied.

[0131] The packaging substrate may have a core layer 22 including a glass core 21 having a first surface and a second surface facing each other, and a core via penetrating the glass core 21. An electrode 63 may be formed on the surface of the glass core 21. Further, for example, the cavity portion according to FIG. 6 may be formed to penetrate both the first surface and the second surface of the glass core 21, and an electronic element 40 is disposed inside the cavity portion.

[0132] As described above, the electronic element 40 can include either a passive element or an active element. The cavity portion may be formed through etching or the like together with the core via. Further, the cavity portion may be formed independently after the core via is formed or before the core via is formed.

[0133] The electronic element 40 disposed inside the cavity portion may be covered on the entire surface except one surface or on the entire surface by a first insulating layer 61. For example, although the electronic element 40 is disposed in the cavity portion, it may be disposed in a form in which the entire surface except i) one surface of the electronic element 40 or ii) the entire surface is covered with the first insulating layer as a coating material. What includes the electronic element and the first insulating layer can be referred to as a cavity module. That is, the cavity module can include i) a plurality of arranged electronic elements and ii) a first insulating layer covering each of the electronic elements.

[0134] For example, when the electronic element 40 has a hexahedral shape, five surfaces except one surface (e.g., the bottom surface) of the electronic element 40 may be covered with the first insulating layer 61. Or, the edge of the upper surface of the electronic element 40 may be covered with the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the upper surface of the electronic element 40.

[0135] For example, when the electronic element 40 has a cylindrical shape, the side surface and / or the upper surface excluding the bottom surface of the electronic element 40 may be covered with the first insulating layer 61. Alternatively, the edge of the upper surface of the electronic element 40 may be covered with the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the upper surface of the electronic element 40.

[0136] For example, one or more connection electrodes may be formed in the bottom surface direction of the electronic element 40. Alternatively, for example, five surfaces excluding the upper surface of the electronic element 40 may be covered with the first insulating layer 61. Alternatively, for example, the edge of the bottom surface of the electronic element 40 may be covered with the first insulating layer 61. That is, the first insulating layer 61 may be formed on the edge of the bottom surface of the electronic element 40. In this case, for example, one or more connection electrodes may be formed in the upper surface direction of the electronic element 40.

[0137] By forming the first insulating layer 61 on the entire surface or the entire surface excluding one surface of the electronic element 40, it is possible to prevent a short circuit due to contact between the arranged electronic elements. Further, a short circuit that may occur unintentionally in the manufacturing process of forming an electrically conductive layer on the side surface of the cavity portion 28 can be prevented by the first insulating layer 61 formed on the entire surface or the entire surface excluding one surface of the electronic element 40.

[0138] Further, the core layer 22 according to FIG. 6 may include a second insulating layer 62 laminated on the first surface and the second surface. The remaining portion of the cavity portion 28 according to FIG. 6 excluding the electronic element 40 and the first insulating layer 61 may be filled with the second insulating layer 62. That is, after arranging the cavity module in the cavity portion 28, there may be a remaining space inside the cavity portion, and the second insulating layer 62 can be formed here. For example, the core layer 22 according to FIG. 6 may include a second insulating layer 62 embedded in the remaining portion of the cavity portion 28 excluding the cavity module. For example, the second insulating layer 62 can be laminated and cured on the upper part (for example, the first surface) and the lower part (for example, the second surface) of the glass core 21, and the second insulating layer can be generated through this.

[0139] A connection electrode may be connected to the electronic element 40.

[0140] A connection electrode may be disposed on an exposed surface of the electronic element 40 where the first insulating layer 61 is not disposed.

[0141] A connection electrode may be disposed through the first insulating layer 61 of the electronic element 40. The connection electrode may be in the form of a blind via.

[0142] A first insulating layer via (not shown) penetrating the first insulating layer may be further disposed in the first insulating layer. Part or all of the inside of the first insulating layer via may be filled with an electrode material.

[0143] One end of the first insulating layer via is in contact with the electronic element 40, and the other end of the first insulating layer via can be exposed outside the cavity portion 28.

[0144] The first insulating layer via may be disposed in a form that penetrates the cavity portion 28 vertically without directly contacting the electronic element 40.

[0145] As the electrode material, an electrically conductive material can be applied, and for example, an electrically conductive metal may be applied. Specifically, copper, copper alloy, silver, etc. may be applied, but it is not limited thereto.

[0146] The same material as that of the material (coating material) of the first insulating layer 61 and the second insulating layer 62 may be applied, or different materials may be applied to each other. In the latter case, materials having different dielectric constants can be applied.

[0147] For example, the first insulating layer 61 and the second insulating layer 62 may have different dielectric constants from each other. For example, the first insulating layer 61 can have the same or a lower dielectric constant than the second insulating layer 62. In this case, there is an advantage that the occurrence of the undulation phenomenon in the cavity portion can be substantially suppressed, and a sufficient insulating effect can be expected for each of the electronic elements.

[0148] The first insulating layer 61 and the second insulating layer 62 can each contain an insulating material.

[0149] Exemplarily, as the insulating material, a polymer resin, a mixed material of a polymer resin and a filler (such as inorganic particles, organic particles, organic-inorganic composite particles), an inorganic vapor deposition layer, etc. may be applied.

[0150] Exemplarily, as the polymer resin, an acrylic resin, an epoxy resin, a modified resin thereof, etc. may be applied, and a material applicable for purposes such as molding in an electronic device may be applied. Exemplarily, LCP (liquid crystal polymer), etc. may be applied.

[0151] Exemplarily, as the mixed material, a mixture of an acrylic resin and a filler, a mixture of a mixture of an acrylic resin and an epoxy resin and a filler, a mixture of an epoxy resin and a filler, etc. may be applied. As the filler, inorganic particles may be applied, and exemplarily, silica particles may be applied. As commercially available products, ABF (Ajinomoto Build-up Film), EMC (Epoxy Molding Compound), MPI (Modified Polyimide), etc. may be applied, but are not limited thereto.

[0152] As the inorganic vapor deposition layer, exemplarily, a silicon oxide vapor deposition layer, a silicon nitride vapor deposition layer, etc. may be applied, but are not limited thereto.

[0153] For the first insulating layer 61 and the second insulating layer 62, materials with the same or different coefficients of thermal expansion (CTE) may be applied. Preferably, materials with a small difference between the coefficient of thermal expansion of the first insulating layer 61 and the coefficient of thermal expansion of the second insulating layer 62 can be applied.

[0154] The difference in the coefficient of thermal expansion between the material of the first insulating layer and the material of the second insulating layer may be 2 ppm / °C or less, 1.5 ppm / °C or less, 1 ppm / °C or less, or 0.5 ppm / °C or less. The difference in the coefficient of thermal expansion may be 0 ppm / °C or more, 0.1 ppm / °C or more, or 0.2 ppm / °C or more.

[0155] The coefficient of thermal expansion of the first insulating layer 61 may be 8 ppm / °C or more, 10 ppm / °C or more, 12 ppm / °C or more, or 14 ppm / °C or more. The coefficient of thermal expansion may be 20 ppm / °C or less, 18 ppm / °C or less, or 17 ppm / °C or less.

[0156] The coefficient of thermal expansion of the second insulating layer 62 may be 8 ppm / °C or more, 10 ppm / °C or more, or 12 ppm / °C or more. The coefficient of thermal expansion may be 20 ppm / °C or less, 18 ppm / °C or less, 16 ppm / °C or less, or 14 ppm / °C or less.

[0157] For the first insulating layer 61 and the second insulating layer 62, materials with different dielectric constants may be applied. Preferably, the material of the insulating layer can be selected and applied such that the dielectric constant of the first insulating layer 61 is lower than the dielectric constant of the second insulating layer 62.

[0158] For the first insulating layer 61 and the second insulating layer 62, materials with different relative dielectric constants Dk at a high frequency of 5.8 GHz may be applied. Exemplarily, the difference between the Dk of the first insulating layer 61 and the Dk of the second insulating layer 62 may be 0.1 or more. The difference in Dk may be 0.1 or more, 0.13 or more, 0.16 or more, or 0.2 or more. The difference in Dk may be 1 or less, 0.8 or less, 0.6 or less, 0.5 or less, 0.4 or less, 0.3 or less, or 0.25 or less.

[0159] The Dk of the first insulating layer 61 may be 2.3 or more, 2.5 or more, 2.7 or more, or 2.9 or more. The Dk may be 3.4 or less, 3.2 or less, or 3.1 or less.

[0160] The Dk of the second insulating layer 62 may be 3.0 or more, 3.1 or more, or 3.2 or more. The Dk may be 3.6 or less, 3.5 or less, or 3.4 or less.

[0161] The Dk of the first insulating layer 61 may be smaller than the Dk of the second insulating layer 62.

[0162] For the first insulating layer 61 and the second insulating layer 62, materials with the same or different dielectric loss factors Df may be applied. Preferably, materials with a difference in Df between the first insulating layer 61 and the second insulating layer 62 of 0.0001 or more can be applied. The difference in Df may be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df may be 0.02 or less.

[0163] The Df of the first insulating layer 61 may be 0.004 or less, 0.0038 or less, or 0.0036 or less. The Df may be 0.001 or more, 0.0015 or more, 0.0018 or more, or 0.002 or more.

[0164] The Df of the second insulating layer 62 may be 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0165] The Df of the first insulating layer 61 may be smaller than the Df of the second insulating layer 62.

[0166] For example, the second insulating layer 62 may be applied with ABF, and the first insulating layer 61 may be applied with LCP. For example, the second insulating layer 62 may be applied with EMC, and the first insulating layer 61 may be applied with LCP. For example, ABP with different dielectric constants may be applied to the second insulating layer 62 and the first insulating layer 61.

[0167] As an example, the formation of the first insulating layer 61 can form an insulating layer on the surface of the electronic element 40 by using methods such as a varnish type method, a selective lamination method, and vapor deposition.

[0168] For the second insulating layer 62, a normal method of forming an insulating layer in the cavity of the packaging substrate can be applied, and the method applied to the formation of the first insulating layer 61 may also be applied.

[0169] FIG. 7 is an example of a cross-sectional structure of a core layer of a packaging substrate generated by another embodiment. The packaging substrate of FIG. 7 is a diagram conceptually simplified for explaining the core layer generated by the embodiment, and the content described with reference to FIGS. 1 to 3 can be applied.

[0170] The packaging substrate can include a core layer 22 including a glass core 21 having a first surface and a second surface facing each other, and a core via penetrating the glass core 21. An electrode 63 can be formed on the surface of the glass core 21. The cavity portion is formed to penetrate both the first surface and the second surface of the glass core 21, and a cavity module is disposed inside the cavity portion. That is, a cavity module can be disposed in the cavity portion.

[0171] As described above, the electronic element 40 can include passive elements, active elements, or both. The cavity portion may be formed simultaneously with the core via, such as by etching, or may be formed independently after or before the core via is formed.

[0172] Also, the cavity module disposed inside the cavity portion 28 according to FIG. 7 can include: i) a plurality of arranged electronic elements; ii) a first insulating layer 61 covering each of the electronic elements 40; and iii) a molding material, and the molding material can include a third insulating layer 71 disposed to cover the electronic elements. The electronic element 40 may be covered on the entire surface or the entire surface except for one surface by the first insulating layer 61. That is, for example, in the cavity portion according to FIG. 7, although the electronic element 40 is disposed, a first insulating layer may be formed on the entire surface or the entire surface except for one surface of the electronic element 40, and the third insulating layer 71 may be formed to cover the electronic element on which the first insulating layer is formed and that includes the molding material.

[0173] The electronic element, the first insulating layer covering the electronic element, and the third insulating layer covering the electronic element on which the first insulating layer is formed are collectively referred to as a cavity module. That is, the cavity module can include: i) a plurality of arranged electronic elements; ii) a first insulating layer covering each of the electronic elements; and iii) a molding material, and the molding material can include a third insulating layer 71 disposed to cover the electronic elements.

[0174] The third insulating layer fixes the relative positions of the electronic elements covered by the first insulating layer in an arranged state and modularizes them into a cavity module.

[0175] The descriptions of the electronic element 40, the first insulating layer 61, the second insulating layer 62, etc. are repetitive with the above descriptions, so detailed descriptions are omitted. The molding material of the third insulating layer 71 will be described later.

[0176] The remaining portion of the cavity portion 28 excluding the electronic element 40, the first insulating layer 61, and the third insulating layer 71 according to FIG. 7 may be filled with the second insulating layer 62. That is, after arranging the cavity module in the cavity portion 28, a remaining space may exist inside the cavity portion, and the second insulating layer 62 can be formed here with an insulating material. For example, the core layer 22 according to FIG. 7 can embed an insulating material in the remaining portion of the cavity portion 28 excluding the cavity module and cure it to form the second insulating layer 62. For example, the second insulating layer 62 can be laminated and cured on the upper part (e.g., the first surface) and the lower part (e.g., the second surface) of the glass core 21, and the second insulating layer can be generated through this.

[0177] When there are two or more electronic elements included in the cavity module, the interval between adjacent electronic elements 40 may be 30 μm or more, 50 μm or more, or 80 μm or more. Also, the interval may be 300 μm or less, 250 μm or less, or 200 μm or less. By having such an interval, the occurrence of interference between electronic elements in the cavity can be minimized, and the space utilization rate can be increased.

[0178] The thickness of the cavity module may be 335 μm or more, 370 μm or more, or 400 μm or more. Also, the thickness may be 1,000 μm or less, 900 μm or less, 800 μm or less, 700 μm or less, 665 μm or less, 620 μm or less, or 600 μm or less. The thickness may be substantially the same as the thickness of the glass substrate 21, or the difference in thickness may be 1 μm or more and 30 μm or less.

[0179] The molding material of the third insulating layer 71 can include a substance that can properly fix the element and prevent electrical short circuits. Exemplarily, it can include any one or more selected from the group consisting of epoxy resins, polyimide resins, polyurethane resins, polyester resins, acrylate resins, and polyamide resins. Exemplarily, the molding material can include epoxy molding compound (EMC), glass fiber reinforced epoxy (FR-4), etc. The molding material can include other additives, phenolic resins, carbon black, flame retardants, fillers, etc. The filler that can be included in the molding material may be a particulate filler, and the particle size of the filler may be 1 μm to 20 μm, or may be 2 μm to 15 μm.

[0180] A connection electrode can be connected to the electronic element 40.

[0181] A connection electrode may be disposed on the exposed surface of the electronic element 40 where the first insulating layer 61 is not disposed. A connection electrode may be disposed on the exposed surface of the electronic element 40 where the first insulating layer 61 and the third insulating layer 71 are not disposed.

[0182] A connection electrode may be disposed through the first insulating layer 61 of the electronic element 40. A connection electrode may be disposed through the first insulating layer 61 and the third insulating layer 71 of the electronic element 40. The connection electrode may be in the form of a blind via. Specifically, in the electronic element 40, a part of each of the first insulating layer 61 and the third insulating layer 71 may be removed in the form of a via or the like, and an electrically conductive substance may be embedded therein to be connection-electroded.

[0183] A first insulating layer via (not shown) penetrating the first insulating layer may be further disposed in the first insulating layer. A part or all of the inside of the first insulating layer via may be filled with an electrode material.

[0184] A third insulating layer via (not shown) penetrating the third insulating layer may be further disposed in the third insulating layer. Part or all of the interior of the third insulating layer via may be filled with an electrode material.

[0185] One end of the first insulating layer via is in contact with the electronic element 40, and the other end of the first insulating layer via can be exposed outside the first insulating layer.

[0186] One end of the first insulating layer via is in contact with the electronic element 40, the other end of the first insulating layer via is in contact with one end of the third insulating layer via, and the other end of the third insulating layer via can be exposed outside the cavity portion 28.

[0187] The third insulating layer via may be arranged in a form that penetrates the cavity portion 28 vertically without directly contacting the electronic element 40.

[0188] An electrically conductive material may be applied to the electrode material, and for example, an electrically conductive metal may be applied. Specifically, copper, copper alloy, silver, etc. may be applied, but it is not limited thereto.

[0189] The same material may be applied to the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71. Alternatively, different materials may be applied to each other, and this case is more preferable. In the latter case, materials having different dielectric constants may be applied.

[0190] The first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 may have different dielectric constants from each other. For example, the first insulating layer 61 can have the same or lower dielectric constant than the second insulating layer 62 and the third insulating layer 71. In this case, there is an advantage that the occurrence of an undulation phenomenon in the cavity portion can be substantially suppressed, and a sufficient insulating effect can be expected for each of the electronic elements.

[0191] The first insulating layer 61 and the second insulating layer 62 can each contain an insulating material, and the third insulating layer 71 can contain a molding material.

[0192] As the insulating material and the molding material, a polymer resin, a mixed material of a polymer resin and a filler (such as inorganic particles, organic particles, organic-inorganic composite particles), an inorganic vapor deposition layer, etc. may be applied.

[0193] As the polymer resin, an acrylic resin, an epoxy resin, a modified resin thereof, etc. may be applied, and a material applicable for the purpose of molding etc. to an electronic device may be applied. Exemplarily, LCP (liquid crystal polymer) etc. may be applied.

[0194] As the mixed material, a mixture of an acrylic resin and a filler, a mixture of a mixture of an acrylic resin and an epoxy resin and a filler, a mixture of an epoxy resin and a filler, etc. may be applied. As the filler, inorganic particles may be applied, and exemplarily, silica particles may be applied. As commercially available products, ABF (Ajinomoto Build-up Film), EMC (Epoxy Molding Compound), MPI (Modified Polyimide), etc. may be applied, but are not limited thereto.

[0195] As the inorganic vapor deposition layer, exemplarily, a silicon oxide vapor deposition layer, a silicon nitride vapor deposition layer, etc. may be applied, but are not limited thereto.

[0196] Exemplarily, the first insulating layer 61 can contain an inorganic vapor deposition layer, LCP (liquid crystal polymer), EMC (Epoxy Molding Compound), ABF (Ajinomoto Build-up Film), or MPI (Modified Polyimide).

[0197] Exemplarily, the second insulating layer 62 can include, but is not limited to, an organic-inorganic composite material, specifically ABF (Ajinomoto Build-up Film).

[0198] Exemplarily, the third insulating layer 71 can include a molding material that is EMC (Epoxy Molding Compound), ABF (Ajinomoto Build-up Film), or MPI (Modified Polyimide).

[0199] The ABF of the second insulating layer and the ABF of the third insulating layer can have different characteristics from each other. Specifically, even if they are materials commonly referred to as ABF, physical properties such as the coefficient of thermal expansion and dielectric constant can vary slightly depending on the specific type of resin applied and the content of inorganic particles applied.

[0200] For the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71, materials with the same or different coefficients of thermal expansion (CTE) can be applied. Preferably, materials with a small difference in the coefficient of thermal expansion between the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 can be applied.

[0201] The difference in the coefficient of thermal expansion between the material of the first insulating layer and the material of the third insulating layer may be 2 ppm / °C or less, 1.5 ppm / °C or less, 1 ppm / °C or less, or 0.5 ppm / °C or less. The difference in the coefficient of thermal expansion may also be 0 ppm / °C or more, 0.1 ppm / °C or more, or 0.2 ppm / °C or more.

[0202] The coefficient of thermal expansion of the first insulating layer 61 may be 8 ppm / °C or more, 10 ppm / °C or more, 12 ppm / °C or more, or 14 ppm / °C or more. The coefficient of thermal expansion may also be 20 ppm / °C or less, 18 ppm / °C or less, or 17 ppm / °C or less.

[0203] The coefficient of thermal expansion of the second insulating layer 62 may be 8 ppm / °C or more, 10 ppm / °C or more, or 12 ppm / °C or more. The coefficient of thermal expansion may be 20 ppm / °C or less, 18 ppm / °C or less, 16 ppm / °C or less, or 14 ppm / °C or less.

[0204] The coefficient of thermal expansion of the third insulating layer 71 may be 8 ppm / °C or more, 10 ppm / °C or more, or 12 ppm / °C or more. The coefficient of thermal expansion may be 20 ppm / °C or less, 18 ppm / °C or less, 16 ppm / °C or less, or 16 ppm / °C or less.

[0205] For the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71, materials having different dielectric constants may be applied. Preferably, the material of the insulating layer can be selected and applied such that the dielectric constant of the first insulating layer 61 is lower than the dielectric constants of the second insulating layer 62 and the third insulating layer 71. Also, the material of the insulating layer can be selected and applied such that the dielectric constant of the second insulating layer 62 is lower than the dielectric constant of the third insulating layer 71.

[0206] For the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71, materials having different relative dielectric constants Dk at a high frequency of 5.8 GHz may be applied. Exemplarily, the difference between the Dk of the first insulating layer 61 and the Dk of the third insulating layer 71 may be 0.1 or more. The difference in Dk may be 0.1 or more, 0.13 or more, 0.16 or more, or 0.2 or more. The difference in Dk may be 1 or less, 0.8 or less, 0.6 or less, 0.5 or less, 0.4 or less, 0.3 or less, or 0.25 or less.

[0207] The Dk of the first insulating layer 61 may be 2.3 or more, 2.5 or more, 2.7 or more, or 2.9 or more. The Dk may be 3.4 or less, 3.2 or less, or 3.1 or less.

[0208] The Dk of the second insulating layer 62 may be 3.0 or more, 3.1 or more, or 3.2 or more. The Dk may be 3.6 or less, 3.5 or less, or 3.4 or less.

[0209] The Dk of the third insulating layer 71 may be 3.0 or more, 3.1 or more, or 3.2 or more. The Dk may be 3.6 or less, 3.5 or less, or 3.4 or less.

[0210] The Dk of the first insulating layer 61 may be smaller than the Dk of the third insulating layer 71.

[0211] For the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71, materials with the same or different dielectric loss factors Df may be applied. Preferably, materials with a difference in Df between the first insulating layer 61 and the third insulating layer 71 of 0.0001 or more can be applied. The difference in Df may be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df may be 0.02 or less.

[0212] The Df of the first insulating layer 61 may be 0.004 or less, 0.0038 or less, or 0.0036 or less. The Df may be 0.001 or more, 0.0015 or more, 0.0018 or more, or 0.002 or more.

[0213] The Df of the second insulating layer 62 may be 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0214] The Df of the third insulating layer 71 may be 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0215] The Df of the first insulating layer 61 may be smaller than the Df of the third insulating layer 71.

[0216] The Df of the first insulating layer 61 may be smaller than the Df of the second insulating layer 62 and the Df of the third insulating layer 71.

[0217] The third insulating layer 71 has a flexural strength at 25 °C of 5 kg / mm 2 or more, 7 kg / mm 2 or more, or even 10 kg / mm 2 or more. Also, the flexural strength may be 25 kg / mm 2 or less, 20 kg / mm 2 or less, or even 18 kg / mm 2 or less.

[0218] The third insulating layer 71 has a flexural modulus at 25 °C of 1,200 kg / mm 2 or more, 1,300 kg / mm 2 , or even 1,400 kg / mm 2 or more. The flexural modulus may be 2,500 kg / mm 2 or less, 2,300 kg / mm 2 or less, or even 2,100 kg / mm 2 or less.

[0219] The third insulating layer 71 may have an elongation at 23 °C of 0.3% to 7%.

[0220] The third insulating layer 71 may have a thermal conductivity of 0.3 W / m·K or more, 0.5 W / m·K or more, or even 0.7 W / m·K or more. Also, the thermal conductivity may be 2.3 W / m·K or less, 2.0 W / m·K or less, or even 1.8 W / m·K or less.

[0221] By having such physical properties, the third insulating layer 71 can stably fix and insulate the electronic element.

[0222] For example, the third insulating layer 71 may be applied with EMC, the second insulating layer 62 may be applied with ABF, and the first insulating layer 61 may be applied with LCP. For example, the third insulating layer 71 may be applied with EMC, the second insulating layer 62 may be applied with EMC, and the first insulating layer 61 may be applied with LCP. The EMC of the third insulating layer and the EMC of the second insulating layer may have different dielectric constants from each other. For example, the third insulating layer 71 may be applied with ABF, the second insulating layer 62 may be applied with ABF, and the first insulating layer 61 may be applied with LCP. The ABF of the third insulating layer and the ABF of the second insulating layer may have different dielectric constants from each other. For example, the third insulating layer 71, the second insulating layer 62, and the first insulating layer 61 may be applied with EMPs having different dielectric constants from each other. For example, the third insulating layer 71, the second insulating layer 62, and the first insulating layer 61 may be applied with ABP having different dielectric constants from each other.

[0223] In terms of controlling the dielectric constant, it is preferable that the third insulating layer 71 is applied with EMC, the second insulating layer 62 is applied with ABF, and the first insulating layer 61 is applied with LCP.

[0224] As an example, the first insulating layer 61 can be formed on the surface of the electronic element 40 by using methods such as the varnish type method, the selective lamination method, and vapor deposition to form an insulating layer.

[0225] For the second insulating layer 62, a normal method of forming an insulating layer in the cavity of the packaging substrate can be applied, and the method applied to form the first insulating layer 61 may also be applied.

[0226] For the third insulating layer 71, a method of forming a molding part can be applied. Exemplarily, a mold frame can be placed on the electronic element on which the first insulating layer is formed in the above arrangement, and after injecting a molding material into the mold frame, a method of curing the molding material may also be applied.

[0227] A manufacturing method for generating a packaging substrate according to the embodiments disclosed in FIGS. 6 and 7 is proposed.

[0228] The packaging substrate according to FIG. 6 can be manufactured by preparing a glass core 21 in which a cavity portion is disposed and an electronic element 40 on which a first insulating layer 61 is formed, arranging the electronic element 40 in the cavity portion, and laminating a second insulating layer 62 on the glass substrate.

[0229] The packaging substrate according to FIG. 7 can be manufactured by preparing a glass core 21 in which a cavity portion is disposed and a cavity module, arranging the cavity module in the cavity portion, and laminating a second insulating layer 62 on the glass substrate.

[0230] Specifically, this specification proposes an embodiment for generating a packaging substrate according to the following embodiments.

[0231] As one embodiment, an electronic element can be selected and placed in a mold, and then a first insulating layer can be coated (or sputtered) on each of the electronic elements. Thereafter, if necessary, at least a part of the first insulating layer coated on a specific surface (for example, the upper surface or the bottom surface) of the electronic element can be removed, and then electrodes or the like can be formed. Thereafter, if necessary, a molding material can be placed in the mold in which the electronic element is disposed and cured to provide a cavity module. Optionally, a part of the molding material can be removed to form a cavity electrode.

[0232] The cavity module can be placed on a glass substrate in which a cavity portion is disposed, and a second insulating layer can be provided here. The second insulating layer can be formed by a process of forming an RDL (Re-Distribution Layer).

[0233] FIG. 8 is a flowchart for explaining, in cross-section, a method for manufacturing a packaging substrate according to an embodiment.

[0234] Through FIG. 8, the steps of forming the first insulating layer and the second insulating layer in the packaging substrate will be described in more detail as follows.

[0235] For example, as shown in FIG. 8(a), an electronic element 40 can be attached to an adhesive film 33 (support) such as a PI tape (Polyimide Tape).

[0236] Thereafter, as shown in FIG. 8(b), for example, a first insulating layer 61 can be formed on a part of the surface of the electronic element 40 disposed in the cavity portion 28, excluding the upper surface or the lower surface. For example, a sputter, coating, or molding process may be performed on the electronic element 40 in the cavity portion 28 to form the first insulating layer 61 on a part of the surface of the electronic element 40 excluding the upper surface or the lower surface. For example, one or more connection electrodes may be formed in the direction of the bottom surface of the electronic element 40. For example, one or more connection electrodes may be formed in the upper direction or the lower direction of the electronic element 40. Here, the glass core 21 may be disposed such that the electronic element is disposed in the cavity portion. At this time, the glass core 21 may be the one in which the same electrode 63 as the core distribution layer is disposed.

[0237] Next, as shown in FIG. 8(c), a process of laminating the second insulating layer 62 on the first surface (Lamination on top) can be performed. The second insulating layer 62 can be laminated on the entire first surface of the glass core 21, and when pre-cure is performed, as shown in FIG. 8(d), the second insulating layer 62 can be embedded into the internal space of the cavity portion. For example, the second insulating layer 62 can contain an insulating mixture, and the insulating mixture can contain inorganic particles and a polymer resin. For example, the second insulating layer 62 can contain the aforementioned ABF (Ajinomoto Build-up Film).

[0238] Optionally, the adhesive film may be removed during subsequent processes. Exemplarily, an adhesive film whose adhesive force can be reduced by ultraviolet irradiation or the like may be applied as the adhesive film. The adhesive film may reduce the adhesive force of the adhesive film by irradiating ultraviolet rays directly on the adhesive film or passing through the glass core, and the adhesive film can be easily removed from the glass core. Further, the electronic element can be positioned by the second insulating layer pre-cured by curing, and when the degree of warpage is controlled below a certain level, subsequent processes can be applied without fixing the adhesive film.

[0239] Next, as shown in FIG. 8(e), a step of laminating the second insulating layer 62 on the second surface (Lamination on bottom) may be performed. The second insulating layer 62 may be laminated on the entire second surface of the glass core 21, and when pre-cure is performed, as shown in FIG. 8(f), the second insulating layer 62 may be embedded into the internal space of the cavity portion 28.

[0240] Therefore, according to FIG. 8, as an example, a core via can be generated in the glass core 21 including the first surface and the second surface facing each other, and a cavity portion penetrating the first surface and the second surface of the glass core 21 can be generated. Alternatively, a glass core 21 in which such a process has been performed is prepared; an electronic element 40 is arranged in the cavity portion 28, and a first insulating layer 61 is formed on a part of the surfaces of the arranged electronic element 40 except for the bottom surface; and a second insulating layer 62 is laminated on the first surface and the second surface, and a method for manufacturing a packaging substrate may be proposed.

[0241] Another method for manufacturing a packaging substrate as another embodiment includes a preparation step of preparing a glass substrate in which a cavity portion is arranged and a cavity module; and a lamination step of arranging the cavity module in the cavity portion and providing a second insulating layer on the glass substrate.

[0242] The descriptions of the glass substrate, the cavity module, etc. are repetitive with the above descriptions, so the descriptions thereof are omitted.

[0243] The cavity module can be manufactured by a cavity module manufacturing step.

[0244] The cavity module manufacturing step can include an arranging process of arranging electronic elements adjacent to each other; a primary insulation process of providing a first insulating layer on the surface of the arranged electronic elements; and a molding process of molding the electronic elements provided with the first insulating layer with a molding material to provide a cavity module including a third insulating layer.

[0245] The cavity module manufacturing step may further include a cavity electrode forming process after the molding process.

[0246] The cavity electrode forming process can be a process of removing a part of the molding material, forming an electrode connected to the connection electrode of the electronic element, and arranging a cavity module connection electrode connected to the electrode.

[0247] FIG. 9 is a flowchart for explaining, in cross-section, a method of manufacturing a packaging substrate according to another embodiment. A more specific explanation will be given with reference to FIG. 9.

[0248] (a), (b), and (c) of FIG. 9 illustrate the cavity module manufacturing step.

[0249] Exemplarily, as shown in FIG. 9(a), an electronic element 40 is arranged on a support (e.g., an adhesive film such as a PI tape (Polyimide Tape)) that can fix the position of the electronic element.

[0250] Thereafter, as shown in FIG. 9(b), the first insulating layer 61 may be formed on a part of the surfaces of the arranged electronic elements 40 excluding the upper or lower surfaces. For example, the first insulating layer 61 may be formed on the electronic elements 40 by a method such as sputtering or coating. For example, one or more connection electrodes may be formed in the bottom direction of the electronic elements 40. For example, one or more connection electrodes may be formed in the upper surface direction of the electronic elements 40.

[0251] Next, as shown in FIG. 9(c), a third insulating layer 71 containing a molding material and arranged to cover the electronic elements 40 on which the first insulating layer is formed may be formed. For example, a molding material may be injected into a molding structure including side walls so as to cover the electronic elements 40 on which the first insulating layer is formed, and the molding material may be cured to form the third insulating layer 71.

[0252] The cavity module manufactured in this way can further selectively include cavity connection electrodes.

[0253] FIGS. 9(d), (e), and (f) illustrate the manufacturing steps of a packaging substrate.

[0254] As shown in FIG. 9(d), a process of arranging a cavity module in the cavity portion 28 of a glass substrate 21 and laminating a second insulating layer 62 on the first surface (Lamination on top) may be performed. The second insulating layer 62 may be laminated on the entire first surface of the glass core 21, and when pre-cure is performed, the second insulating layer 62 may be embedded into the internal space of the cavity portion 28.

[0255] If necessary, the process of FIG. 9(d) can be performed with an adhesive film disposed at the lower end of the glass substrate. The adhesive film may help to fix the position of the cavity module when the glass substrate has a full cavity.

[0256] The adhesive film can be removed during the subsequent process. Exemplarily, an adhesive film whose adhesive force can be reduced by ultraviolet irradiation or the like may be applied. The adhesive film can reduce the adhesive force of the adhesive film by irradiating the adhesive film directly or passing ultraviolet rays through the glass core, etc., and the adhesive film can be easily removed from the glass core. Further, the electronic element can be fixed in position by the second insulating layer pre-cured by curing.

[0257] Next, as shown in FIG. 9(e), a step of laminating the second insulating layer 62 on the second surface (Lamination on bottom) can be performed. The second insulating layer 62 can be laminated on the entire second surface of the glass core 21, and when pre-cure is performed, as shown in FIG. 9(f), the second insulating layer 62 can be embedded into the internal space of the cavity portion 28. In the second insulating layer 62, a boundary with the third insulating layer can be observed. The boundary can be observed as a boundary of color difference as a line in the cross section. In the cross section, the boundary can be observed in a band shape (exemplarily, a color change such as a gradation) where the color has a relatively constant thickness and the color changes. Exemplarily, the constant interval may be 2 to 30 μm, or may be 3 to 10 μm.

[0258] The packaging substrate and the method for manufacturing the packaging substrate according to the embodiments described above can prevent the angulation phenomenon generated by the gap between elements and / or the gap between the cavity portion and the element, and can prevent leakage current from occurring in the cavity portion.

[0259] Further, by forming the second insulating layer and the third insulating layer having different dielectric constants arranged to cover the electronic element formed with the first insulating layer, it is possible to prevent a short circuit due to contact between the arranged electronic elements, and to prevent the position of the electronic element from being changed. Through this, it is possible to prevent contact between the electronic elements and prevent a short circuit that may occur unintentionally in the manufacturing process of forming the electrically conductive layer.

[0260] The present specification described above has been described with reference to the embodiments shown in the drawings, but this is merely exemplary, and those having ordinary knowledge in the art will understand that various modifications and variations of the embodiments are possible from now on. That is, the scope of rights of the present specification is not limited to the above-described embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the appended claims also belong to the scope of rights of the embodiments. Therefore, the true technical protection scope of the present specification must be determined by the technical idea of the appended claims.

Description of Reference Numerals

[0261] 100 Semiconductor device 10 Motherboard 30 Semiconductor element section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging substrate 21, 21a Glass substrate 22 Core layer 223 Core insulating layer 26 Upper layer 213 First surface 214 Second surface 23 Core via 24 Core distribution layer 241 Core distribution pattern 29 Lower layer 25 Upper distribution layer 251 Upper distribution pattern 252 Blind via 253 Upper insulating layer 27 Upper surface connection layer 271 Upper surface connection electrode 272 Upper surface connection pattern 28 Cavity section 281 Internal space 282 Cavity distribution layer 40 Electronic element 50 Connection section 51 Element connection section 52 Board connection part 60 Cover layer 61 First insulating layer 62 Second insulating layer 63 Electrode 71 Third insulating layer 33 Support

Claims

1. a core layer including a glass core having a first surface and a second surface opposed to each other, and a cavity portion penetrating the glass core; a cavity module and a second insulating layer are disposed in the cavity portion; the cavity module includes a plurality of electronic elements, a first insulating layer, and a third insulating layer; the first insulating layer is a layer that covers each of the electronic elements with a coating material; The first insulating layer is disposed on the entire surface or the entire surface except for one surface of each of the electronic elements; the third insulating layer is a layer that covers the arranged electronic elements with a molding material; the second insulating layer is embedded in a portion of the internal space of the cavity portion excluding the cavity module; The first insulating layer and the third insulating layer have different dielectric constants.

2. The packaging substrate of claim 1 , wherein the coating material has a lower dielectric constant than the molding material.

3. The high frequency dielectric constant Dk is the dielectric constant at a high frequency of 5.8 GHz, Dk1 is the high frequency dielectric constant of the first insulating layer, Dk3 is the high frequency dielectric constant of the third insulating layer, The packaging substrate according to claim 1 , wherein the difference between Dk1 and Dk3 is 0.1 or more.

4. Df1 is the dielectric loss factor of the first insulating layer, Df3 is the dielectric loss factor of the third insulating layer, The packaging substrate according to claim 1 , wherein the difference between Df1 and Df3 is 0.0001 or more.

5. the first insulating layer has a lower dielectric constant than the second insulating layer; Df1 is the dielectric loss factor of the first insulating layer, Df2 is the dielectric loss factor of the second insulating layer, The packaging substrate according to claim 1 , wherein a difference between Df1 and Df2 is 0.1 or more.

6. 2. The packaging substrate of claim 1, wherein the first insulating layer comprises an inorganic deposition layer, a liquid crystal polymer (LCP), an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), or a modified polyimide (MPI).

7. an electronic element connection electrode is disposed on the electronic element; The cavity module includes a cavity connecting electrode; The packaging substrate according to claim 1 , wherein the cavity connection electrodes are connection electrodes that are electrically connected to the electronic element connection electrodes and are exposed on a surface of the cavity module.

8. The packaging substrate of claim 1 , wherein the electronic elements include passive elements, active elements, or both.

9. A first insulating layer via penetrating the first insulating layer is further disposed in the first insulating layer; A third insulating layer via is further disposed in the third insulating layer, the third insulating layer penetrating at least a portion of the third insulating layer; The packaging substrate of claim 1 , wherein the first insulating layer via and the third insulating layer via are partially or entirely filled with an electrode material.

10. A method for manufacturing a packaging substrate, comprising: A preparation step of preparing a glass substrate on which a cavity portion is arranged and a cavity module; and a lamination step of arranging the cavity module in the cavity portion and providing a second insulating layer on the glass substrate; the cavity module includes a plurality of electronic elements, a first insulating layer, and a third insulating layer; the first insulating layer is a layer that covers each of the electronic elements with a coating material; The first insulating layer is disposed on the entire surface or the entire surface except for one surface of each of the electronic elements; the third insulating layer is a layer that covers the arranged electronic elements with a molding material; the second insulating layer is embedded in a portion of the internal space of the cavity portion excluding the cavity module; The first insulating layer and the third insulating layer have different dielectric constants.

11. The cavity module is manufactured by a cavity module manufacturing step, 11. The method for manufacturing a packaging substrate according to claim 10, wherein the cavity module manufacturing step includes an arrangement process for arranging electronic elements adjacent to each other, a primary insulation process for providing a first insulating layer on a surface of the arranged electronic elements, and a molding process for molding the electronic elements provided with the first insulating layer with a molding material to provide a cavity module including a third insulating layer.

12. The method for manufacturing a packaging substrate according to claim 10, wherein the molding material comprises an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), or a modified polyimide (MPI).

13. The cavity module manufacturing step further includes a cavity electrode forming process after the molding process, 12. The method for manufacturing a packaging substrate according to claim 11, wherein the cavity electrode forming process is a process of removing a portion of the molding material, forming an electrode connected to a connection electrode of the electronic element, and arranging a cavity module connection electrode connected to the electrode.

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