Detector pixel and energy-resolving photon counting detector

Abstract

To accurately compensate a dark current of a photodetector in detector pixels to improve measurement accuracy.SOLUTION: A pixel comprises: a photodetector configured to convert an incident photon into a first signal indicative of energy of the incident photon; a charge sensitive amplifier (CSA) configured to convert the first signal into a CSA output signal at output of the CSA; and a dark current compensation unit (DCCU) for the photodetector. The DCCU comprises a signal following unit configured to provide an intermediate signal, and the intermediate signal is configured to follow a signal indicative of the CSA output signal, with a first maximum signal change rate in a first direction and a second maximum signal change rate lower than the first maximum signal change rate in a second direction opposite to the first direction. The second direction is a direction in which the signal indicative of the CSA output signal is configured to change when a photon is incident on the photodetector. The DCCU further comprises a signal generation unit configured to generate a dark current compensation signal on the basis of the intermediate signal and to provide the dark current compensation signal to the CSA.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Aspects of the present disclosure generally relate to detector pixels for energy-resolving photon counting detectors and energy-resolving photon counting detectors including the same. Aspects of the present disclosure relate in particular to X-ray applications such as mammography, fluoroscopy, surgery, and tomography, extraoral dentistry, intraoral dentistry, and non-medical non-destructive inspection applications such as pipeline inspection and security.

Background Art

[0002] Photon counting detectors capable of discriminating photon energy are known in the art. Compared to energy integrating detectors operating in continuous mode, energy-resolving photon counting detectors operate in pulse mode. These detectors can process and record individual absorption events when photons such as X-ray photons are absorbed by the detector material. Energy-resolving photon counting detectors can potentially provide superior noise characteristics compared to energy integrating detectors because they count photons individually. For this reason, it has become an attractive candidate for use in computed tomography (CT) applications. For example, using an energy-resolving photon counting detector, contrast agents can be more accurately identified during a CT scan.

[0003] An energy-resolving photon counting detector typically consists of a plurality of detector pixels. Each pixel includes a photodetector configured to convert an incident photon into a first signal indicative of the energy of the incident photon, a charge sensitive amplifier (CSA) configured to convert the first signal into a CSA output signal, and a processing circuit for processing the CSA output signal.

[0004] A photodetector may be associated with a leakage current. This leakage current may exist even when no photons are incident on the photodetector and is therefore generally referred to as the dark current. The dark current is integrated by the CSA and as a result may appear as a cause of error in the second signal output by the processing circuit. In particular, the dark current is added to the charge generated by the incident photons and causes an error in the energy level detected by the detector pixel. Further, if no additional measures are taken, the dark current is integrated by the CSA and the potential of the entire feedback network of the CSA continues to increase until it is large enough to generate a current sufficient to cancel the dark current flowing through the feedback network. In practice, if the output voltage required to achieve this exceeds the supply voltage of the CSA, the CSA may saturate, potentially preventing proper operation of the detector pixel.

[0005] To account for the effect of the dark current on the second signal, dark current compensation can be implemented. Conventionally, this involves estimating the dark current of the photodetector and providing a dark current compensation signal that compensates for or at least mitigates the effect of the dark current to the input of the CSA. The dark current of the photodetector can depend on various conditions such as the applied bias voltage, temperature, and the rate at which photons are incident on the photodetector. As a result, dynamic compensation of the dark current is usually preferred. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] Known dynamic dark current compensation techniques are described in "Pixel Detectors with Local Intelligence: The View of an IC Designer" by F. Krummenacher, and a low-pass filter architecture is used in this technique. In particular, in the prior art, the output of the CSA is low-pass filtered to estimate the dark current, and a dark current compensation signal is generated accordingly. However, such a circuit may not operate optimally when the photon incidence rate is high. When the photon incidence rate is high, the average of the signal output by the CSA is further away from the "baseline" value corresponding to the output voltage after the CSA is reset, and a discrepancy occurs between the estimated dark current and the actual dark current.

[0007] As shown in FIG. 1A, due to the discrepancy between the dark current compensation signal and the actual dark current, the output voltage Vcsa of the CSA may droop between photon incidences with respect to the baseline B at which the output voltage of the CSA is reset. Since the discriminator bank also compares a second signal with respect to the baseline B, there may be a measurement error due to the low maximum value of the second signal.

[0008] Therefore, especially in the case of an energy-resolving photon counting detector, it is necessary to accurately compensate the dark current of the photodetector in the detector pixel to improve the measurement accuracy.

[0009] An object of the present invention is to provide a detector pixel and an energy-resolving photon counting detector in which the above problems do not occur or hardly occur.

Means for Solving the Problems

[0010] According to one aspect of the present disclosure, a detector pixel for an energy-resolved photon counting detector is provided. The pixel includes a photodetector configured to convert an incident photon into a first signal indicative of the energy of the incident photon, a CSA configured to convert the first signal at the input of the CSA into a CSA output signal at the output of the CSA, and a DCCU for compensating the dark current of the photodetector. The DCCU includes a signal tracking unit configured to provide an intermediate signal, the intermediate signal being configured to track a signal indicative of the CSA output signal at a first maximum signal change rate in a first direction and at a second maximum signal change rate lower than the first maximum signal change rate in a second direction opposite to the first direction. The second direction is a direction configured such that a signal indicative of the CSA output signal changes when a photon is incident on the photodetector. The DCCU further includes a signal generation unit configured to generate a dark current compensation signal based on the intermediate signal and provide the dark current compensation signal to the CSA.

[0011] Note that the signal indicative of the CSA output signal may be the CSA output signal itself. Alternatively, it may be a converted version such as a level-shifted and / or scaled version of the CSA output signal. In the latter case, the signal indicative of the CSA output signal may be the actual signal provided to the signal tracking unit, or it may be a dummy signal or "virtual" signal that the intermediate signal follows. In that case, the operation of the intermediate signal indicates the operation of the CSA output signal.

[0012] The applicant has found that errors are likely to occur in the conventional approach of applying a low-pass filter to the output voltage of the CSA to estimate the dark current. That is, this approach may be sufficient for a low photon count rate where the signal averaging at the output of the CSA mainly depends on the baseline of the CSA and the dark current, but it does not apply to a high photon count rate where the signal pulses due to incident photons contribute significantly to the signal averaging.

[0013] This is shown, for example, in FIG. 1B, where a signal SL with a low photon count rate and another signal SH with a high photon count rate are shown. Further, in FIG. 1B, a solid line representing the signal average of both signals SL and SH is shown. As can be seen from FIG. 1B, the difference between the signal average of signal SH and the "base level" (i.e., the signal level when there are no pulses) is much larger than the difference between the signal average of signal SL and the base level. Dark current compensation ideally uses feedback to control the CSA so that when there are no incident photons, the baseline voltage is kept constant and equal to the expected baseline level of the CSA. However, since low-pass filtering tends towards the average, in this conventional approach, the dark current can be significantly overestimated, especially when the photon count rate is high. Here, the baseline level of the CSA can correspond to the level at which the CSA is configured to be reset, and thus represents the signal level that the CSA output signal should have when there are no incident photons and no dark current.

[0014] In contrast, according to the present disclosure, the DCCU provides an asymmetric response to the output of the CSA. In particular, the signal tracking unit can remove or at least reduce the influence of signal pulses in the CSA output signal caused by incident photons on dark current compensation by tracking the signal indicating the CSA output signal in a state where the maximum rate of change in the direction of its pulse is lower than the rate of change in the opposite direction.

[0015] For example, during normal operation, when the signal level of the intermediate signal is closer to the baseline level of the CSA than the signal level of the CSA output signal, the rate of change of the intermediate signal can be relatively low. On the other hand, the signal tracking unit can track the signal indicating the CSA output signal at a relatively high speed when the signal level of the intermediate signal is further away from the baseline level than the signal level of the CSA output signal during normal operation.

[0016] Since the dark current is usually at a low frequency, even when there are no incident photons in both directions of the signal change, the change in the dark current can be sufficiently tracked, and the response of the DCCU to the (high-frequency) signal pulse in one direction due to the incident photons can be mitigated. The pulse usually has a time width in the range of 10 to 100 ns, but the present disclosure is not limited thereto. Therefore, the dark current can be estimated and compensated more accurately, leading to a more accurate decomposition of the photon energy by the detector pixel.

[0017] The signal generation unit may further include a comparison circuit configured to compare the intermediate signal with a reference signal based on the baseline level and output a result representing the comparison for generating a dark current compensation signal. Further, the output of the comparison circuit may be a dark current compensation signal or a control signal for controlling a signal generator to generate a dark current compensation signal. Here, the baseline level may mean a level (e.g., voltage) at which the CSA is reset passively or actively after processing photons.

[0018] The signal tracking unit may include a first signal changing element configured to change the signal level in a first direction in response to a signal indicating the CSA output signal, and a second signal changing element configured to change the signal level of the intermediate signal in a second direction in response to a signal indicating the CSA output signal.

[0019] The second signal changing element may include a current source such as a transistor-implemented current source. The current source of the second signal changing element is intentionally selected to be relatively small, thereby limiting the pull-up strength of the second signal changing element.

[0020] The first signal changing element may include a source follower transistor, and its control terminal is connected directly or indirectly to the output of the CSA. The source follower transistor can follow the voltage of its control terminal (such as the gate terminal) with its source voltage. By appropriately setting the dimensions of the transistor, its response speed (i.e., the maximum rate of change) can be intentionally set much higher than that of the second signal changing element. Another advantage of this embodiment is that the source follower does not or hardly loads the output of the CSA.

[0021] The signal generation unit may further include a reference transistor configured to level shift the baseline voltage to provide a reference signal, thereby taking into account the level shift of the intermediate signal with respect to the output voltage signal of the CSA caused by the source follower transistor. The reference transistor is configured in the same way as the source follower transistor and can, for example, use the same dimensions to replicate the level shift caused by the source follower transistor, for example, making it equal to its gate-source voltage. In practice, the reference transistor may be configured as a source follower with respect to the baseline voltage rather than the output voltage signal of the CSA.

[0022] The second signal changing element may include a further source follower transistor whose channel is arranged in series with a current source. Further, the signal following unit may further include a buffer connected between the output of the CSA and each of the source follower and the further source follower, and the buffer is configured to provide each of the level-shifted signals to the source follower transistor and the further source follower transistor, thereby taking into account the level shift caused by each of the source follower transistor and the further source follower transistor.

[0023] With the above configuration, an intermediate signal that is not level-shifted or hardly level-shifted with respect to the output voltage signal of the CSA can be provided. Therefore, the baseline voltage does not need to be level-shifted before being compared with the intermediate signal. The buffer may include a diode-connected buffer transistor.

[0024] The first signal changing element may be composed of a series connection of a first diode and a first resistive element, and the second signal changing element may be composed of a series connection of a second diode and a second resistive element. The second signal changing element may be connected in parallel with the first signal changing element, and the second diode may be anti-parallel to the first diode. Further, the resistance of the first resistive element may be smaller than the resistance of the second resistive element. In this embodiment, combining the second diode and the second resistive element results in a lower maximum rate of change of the signal level of the intermediate signal compared to the case of combining the first diode and the first resistive element. In a preferred further embodiment, the first diode and the second diode are Schottky diodes, with a relatively low forward voltage required to operate in the forward mode, reducing the dead zone where neither the first diode nor the second diode is forward-biased. However, the present disclosure is not limited thereto.

[0025] This can be achieved, for example, by using resistors with different resistance values, or by appropriately setting the dimensions of the first and second diodes to effectively realize the first and second resistive elements respectively, or by both.

[0026] In a further embodiment, the signal following unit may further include an amplifier coupled to its first input between the output of the CSA and the first and second signal changing elements. The first and second signal changing elements are coupled between the output of the amplifier and the output of the signal following unit, and the output of the signal following unit is coupled to the second input of the amplifier, thereby forming a negative feedback loop including the amplifier and the first and second signal changing elements. By doing so, the dead zone where neither the first diode nor the second diode is forward-biased can be reduced.

[0027] The first signal change element can include a diode connected to the output of the CSA. In a further embodiment, the second signal change element can include a current source such as a transistor-implemented current source. In this embodiment, the current source may have a lower maximum change rate of the intermediate signal compared to the diode.

[0028] The signal generation unit can further include a reference diode configured to provide a reference signal by biasing with a reference current source and shifting the baseline voltage, thereby taking into account the level shift of the intermediate signal with respect to the output voltage signal of the CSA generated by the diode, or the corresponding one of the first diode and / or the second diode. Therefore, the level shift caused by the diode, or the first diode and / or the second diode, can be considered by providing a reference signal for comparing with the intermediate signal level-shifted with respect to the baseline voltage of the CSA. For this purpose, the reference diode can have the same dimensions as the diode, the first diode, and / or the second diode and provide a similar level shift.

[0029] The signal generation unit can further include a first capacitor connected between the output of the comparison circuit and the reference terminal. The output signal of the comparison unit is defined as the voltage across the first capacitor and can then be used to generate a dark current compensation signal. For example, the dark current compensation signal can be generated by a signal generator such as a transistor having a control terminal connected to the output of the comparison circuit, configured to convert the voltage across the first capacitor into a current and supply the current to the input of the CSA. The reference terminal to which the first capacitor is connected may be the power supply voltage or ground.

[0030] The signal tracking unit may further include a second capacitor to which an intermediate signal is supplied as a voltage. The intermediate signal may be defined as a voltage signal applied to the second capacitor. The first terminal of the second capacitor is connected to the input of the comparison circuit, and the second terminal of the second capacitor may be connected to a reference terminal such as a power supply voltage or ground.

[0031] The CSA may include an amplifier, a reset element configured to reset the CSA, and a feedback network including a parallel connection of a feedback capacitor. In a further embodiment, the reset element may include a feedback resistor. Alternatively, the reset element may include a feedback transistor. In this case, the pixel may further include a trigger circuit configured to generate a reset signal for the feedback transistor in response to the output voltage signal of the CSA.

[0032] The pixel may further include a shaper configured to shape the output voltage signal of the CSA into a second signal indicating the energy of incident photons. In another embodiment, the shaper may include a differentiator and an integrator.

[0033] The pixel may further include a bank of discriminators including a plurality of comparison units. Each comparison unit may be configured to compare the maximum value of the second signal with a respective threshold value and output the result of the comparison.

[0034] The pixel may further include a counter array including a plurality of counters respectively connected to the plurality of comparison units. Each counter may be configured to cumulatively store the result of the comparison.

[0035] The photodetector may include a light-absorbing material such as cadmium zinc telluride (CZT) or cadmium telluride (CdTe). In a further embodiment, the photodetector may be a photodiode or a phototransistor.

[0036] The CSA output signal can be a voltage signal, the intermediate signal is a voltage signal, and the baseline level can be a baseline voltage. In other words, the CSA can be configured to convert a first signal (e.g., a charge signal) into an output voltage signal.

[0037] According to another aspect of the present disclosure, an energy-resolving photon-counting detector is provided. The photon-counting detector includes a plurality of detector pixels that can be arranged in a matrix of rows and columns. At least one, preferably each pixel, is configured as a detector pixel defined in any of the embodiments of the foregoing previous aspects.

Advantages of the Invention

[0038] The present invention is particularly useful for the conversion of X-ray photons, but is not limited thereto, and can be similarly used for other applications such as detectors for visible light, infrared light, etc.

[0039] Further aspects and / or embodiments of the present disclosure will become apparent from the detailed description set forth below.

[0040] Next, the present invention will be described in more detail with reference to the accompanying drawings.

Brief Description of the Drawings

[0041]

Figure 1A

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DETAILED DESCRIPTION OF THE INVENTION

[0042] In the accompanying drawings, for the sake of convenience of explanation, the same or similar components and / or functions may be assigned the same reference numerals. Further, if a first component is described with reference to a previous drawing and the same reference numeral is assigned to a second component in another drawing, unless otherwise explicitly stated, the description of the first component described with reference to the previous drawing may be applied identically or similarly to the second component described with reference to other drawings. For the sake of brevity, the description of the first component may be omitted for the second component described with reference to other drawings.

[0043] Unless the context clearly dictates otherwise, throughout the description and claims, words such as "comprising," "including," and the like are to be construed in an inclusive sense, i.e., in the sense of "including, but not limited to," rather than in an exclusive or exhaustive sense. As used herein, the terms "connected," "coupled," or variations thereof mean either a direct or indirect connection or coupling between two or more elements. The coupling or connection between elements may be physical, logical, electromagnetic, or any combination thereof. Further, terms such as "herein," "above," "below," and words of similar import used in this application refer to the entire application and not to specific parts of the application. Wherever context permits, words used in the detailed description in the singular or plural may also include the plural or singular, respectively. The word "or" with respect to a list of two or more items covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0044] The teachings of the technology provided herein are not necessarily limited to the systems described below and can also be applied to other systems. Further implementations of the technology can be provided by combining the elements and operations of the various examples described below. Alternative implementations of the technology may include not only additional elements but also fewer elements than the implementations described below.

[0045] These changes and other changes can be made to the technology in light of the following detailed description. The description explains specific examples of the technology and describes the best mode contemplated, but no matter how detailed the description may appear, the technology can be practiced in various ways. The details of the system may vary significantly in a particular implementation, but nevertheless are included in the technology disclosed herein. As noted above, the specific terms used when describing a particular feature or aspect of the technology should not be construed as meaning that the term is redefined herein so as to be limited to a particular characteristic, feature, or aspect of the technology with which the term is associated. In general, unless such terms are explicitly defined in the detailed description section, the terms used in the appended claims should not be construed as limiting the technology to the specific examples disclosed in the specification. Thus, the actual scope of this technology includes not only the disclosed examples, but also all equivalent ways of practicing or implementing this technology based on the appended claims.

[0046] In the following description, reference is made to various transistors. Such reference can be construed as referring to the same or different types of transistor technologies, such as bipolar junction transistors (BJTs), field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), etc. Subtypes include, for example, junction FETs (JFETs), metal oxide semiconductor FETs (MOSFETs), particularly complementary MOS (CMOS) transistors, and the like. Similarly, when reference is made to a diode, this may refer to various types of diodes, such as PN diodes, PiN diodes, Schottky diodes, merged pin Schottky (MPS) diodes, and the like. One of ordinary skill in the art will understand that various combinations are possible and that the present disclosure is not limited to all transistors and / or diodes being of the same type or subtype. Although not limited to this, the exemplary examples in the detailed description of the present disclosure are described using CMOS technology.

[0047] FIG. 2 shows a schematic example of detector pixel 1 of an energy-resolved photon counting detector.

[0048] Pixel 1 includes a photodetector 2 configured to output a first signal as a result of absorbing incident photons, and a detection unit 3 configured to receive and process the first signal from the photodetector 2. The photodetector 2 can take the form of a photodiode as shown in FIG. 2, for example, but it is not necessarily so. For example, the photodetector 2 includes a piece of light-absorbing material such as cadmium zinc telluride (CZT) disposed between electrodes. The first electrode can be negatively biased using a voltage source -Vb, and the second electrode is connected to the detection unit 3. The photodetector 2 outputs a first signal as a result of absorbing photons. This first signal includes or is formed by free electrons generated by the absorption of photons and repelled towards the second electrode by a large negative bias present on the first electrode.

[0049] Of course, it is also possible to use a photodetector of the opposite polarity and apply a positive bias instead of a negative bias. In that case, the first signal includes or is formed by free holes generated by photon absorption and repelled towards the detection unit 3 instead of free electrons. Hereinafter, unless explicitly stated otherwise, Pixel 1 operating based on the first signal including free electrons will be referred to.

[0050] The detection unit 3 generates a second signal in response to the first signal. This second signal is then provided to a discriminator bank 7 including a plurality of comparison units 7a. Each comparison unit 7a compares the second signal with a respective (different) threshold TH. The output of the comparison unit 7a is connected to a respective counter 8a included in a counter array 8. After processing a large number of incident photons, the energy spectrum of the incident radiation can be determined by the values stored in the counter 8a.

[0051] In the above, the detection unit 3, discriminator bank 7, and counter array 8 are part of a processing circuit configured to process the electrical signal from the photodetector 2. Further, the photodetector 2 is an example of a photon conversion assembly that directly converts incident photons (e.g., X-ray photons) into an electrical signal. However, the present disclosure is not limited thereto, and is similarly applicable to an indirect conversion detector that uses, for example, a scintillator to convert incident photons into respective secondary photons that can be processed by the photodetector 2.

[0052] The detection unit 3 includes a charge sensitivity amplifier (CSA) 4 configured to convert an input charge into an output voltage. In particular, the CSA 4 includes an amplification unit 5 and a feedback network including a parallel connection of a feedback capacitor Cf and a feedback transistor Mf. In this example, the feedback transistor Mf can be inactive (i.e., open or high impedance) during measurement. After measurement, the feedback transistor Mf is activated for a short time (i.e., closed or low impedance), the feedback capacitor Cf is discharged, and the CSA 4 is prepared for the next measurement. For this purpose, the detection unit 3 may further include a trigger circuit 9 configured to detect the incidence of photons based on the output voltage signal of the CSA 4 and supply a reset signal rst to the feedback transistor Mf after the measurement is completed. For example, the reset signal rst is supplied to the feedback transistor Mf after a predetermined time from when a signal is detected at the output of the CSA 4, taking into account the time required for the pixel 1 to process the second signal supplied by the detection unit 3.

[0053] In the above description, CSA4 has been described as having active reset using a feedback transistor Mf. However, CSA4 with passive reset is also envisioned by the present disclosure. For example, the feedback transistor Mf may be replaced with a resistive element having a relatively high resistance (not shown in FIG. 2), such as a resistor or a transistor-mounted resistive element. In that case, the trigger circuit 9 may be omitted. When using passive reset, the time constant of the feedback network needs to be small enough to sufficiently reset CSA4 between measurements, but not too small so as not to affect the measurement itself. Instead of replacing the feedback transistor Mf with a resistive element, a resistive element connected in parallel to the feedback transistor Mf may be added to the feedback network.

[0054] The detection unit 3 may further include a shaper 6. In this example, the shaper 6 includes a combination of a differentiator 6a and an integrator 6b. The shaper 6 is configured to shape (i.e., prepare) the signal output by the CSA4 into a shaper output signal (i.e., the second signal), and this is done in a manner suitable for the comparison unit 7a of the discriminator bank 7 to determine its maximum value.

[0055] As shown by the corresponding signal shapes shown under the various components, the first signal output by the photodetector 2 corresponds to a spike signal representing the electrons - Qin generated as a result of the absorption of photons. This signal is processed by the CSA4 and converted into a signal Vcsa whose step height is determined according to the energy of the absorbed photons. The signal Vcsa is then differentiated by the differentiator 6a of the shaper 6 to become the signal Vdif. The DC component of the signal Vcsa is removed by the differentiation. Next, the signal Vdif is integrated by the integrator 6b of the shaper 6 to become the signal Vshp that appears as the second signal at the output of the detection unit 3. The maximum value of the second signal Vshp indicates the energy of the absorbed photons. This maximum value is detected by the discriminator bank 7 using the comparison unit 7a, and the result of the detection is then stored in the counter 8a of the counter array 8.

[0056] Pixel 1 further includes a dark current compensation unit (DCCU) 10 that forms part of a feedback control loop around CSA4. In practice, the DC loop gain of this feedback control loop is finite because there are resistance elements such as the feedback resistance (not shown) of feedback transistor Mf in the feedback network of CSA4. For example, feedback transistor Mf is weakly biased in its "inactive" state for the purpose of stabilizing the feedback control loop and forms a high impedance between the input and output of CSA4.

[0057] DCCU 10 is configured to estimate the dark current of photodetector 2 and provide a dark current compensation signal to CSA4 that compensates for or at least reduces the impact of the dark current on the operation of Pixel 1. DCCU 10 will be described in more detail below with reference to FIGS. 3 to 15.

[0058] FIG. 3 shows a part of Pixel 1 according to an embodiment of the present disclosure. In particular, FIG. 3 shows photodetector 2, CSA4, and DCCU 10. For convenience of explanation, the remaining components of Pixel 1 such as shaper 6, discriminator bank 7, counter 8, and trigger circuit 9 shown in FIG. 2 are omitted from the illustration and corresponding description of FIG. 3.

[0059] In the following description, the description of FIG. 2 can be applied identically or similarly to any of the embodiments described with reference to FIGS. 3 and later, including the omitted components, unless otherwise explicitly stated. However, the present disclosure is not limited to this, and various alternative implementations and / or modifications of the remaining components not shown in FIGS. 3 and later are equally applicable. The shaper 6, discriminator bank 7, and counter array 8 of Pixel 1 may be collectively referred to as a signal processing circuit for processing the output signal of the CSA.

[0060] Referring to FIG. 3, the photodetector 2 provides a first signal to the input of the CSA 4, and the CSA 4 converts the first signal into a CSA output signal. The DCCU 10 is connected between the input and output of the CSA 4. In particular, the DCCU 10 is composed of a signal tracking unit 11 and a signal generating unit 12. The signal tracking unit 11 provides an intermediate signal to the signal generating unit 12. Next, the signal generating unit 12 generates a dark current compensation signal based on the intermediate signal and provides it to the CSA 4 to compensate for the dark current from the photodetector 2. Although FIG. 3 shows a subtraction element at the input of the CSA 4, this can also be an addition element, for example, by inverting the polarity of the dark current compensation signal provided by the signal generating unit 12 to make it an addition element.

[0061] According to the present disclosure, the intermediate signal is configured to follow, at its signal level, the CSA output signal or its scaled and / or level-shifted version representing the CSA output signal. However, the maximum signal change rate of the intermediate signal provided by the signal tracking unit 11, i.e., the tracking ability, depends on the direction in which the intermediate signal changes to follow the CSA output signal. In particular, the signal tracking unit 11 can change the intermediate signal at a change rate up to a first maximum signal change rate in a first direction and at a change rate up to a second maximum signal change rate in a second direction opposite to the first direction. The signal tracking unit 11 may be configured such that the second maximum signal change rate is lower than the first maximum signal change rate. The second direction is defined by the direction in which the signal indicating the CSA output signal is configured to change when photons are incident for the purpose of removing the influence of the signal pulse on the dark current compensation.

[0062] The signal indicating the CSA output signal can be the CSA output signal itself or a modified version thereof. For example, additional components such as an amplifier or a buffer can be connected between CSA4 and DCCU10. These components are configured to modify the CSA output signal before providing the modified CSA output signal to DCCU10. Such a modified CSA output signal can still be the CSA output signal, particularly indicating its signal operation. DCCU10 can be configured to consider the difference between the signal indicating the CSA output signal and the actual CSA output signal (if present) by processing the intermediate signal accordingly.

[0063] Here, when the intermediate signal "follows" the signal indicating the CSA output signal, it may mean that the signal level of the intermediate signal represents the behavior of the signal indicating the CSA output signal, considering the maximum signal change rate of the intermediate signal. For example, the signal level of the intermediate signal can converge to the exact signal level of the signal indicating the CSA output signal over time or "follow" the signal indicating the CSA output signal in terms of "distance" based on the first and second maximum signal change rates defined above, and can be level-shifted and / or scaled accordingly.

[0064] The concept described with reference to FIG. 3 is illustrated using FIG. 4, which shows the CSA output signal as the output voltage signal Vcsa over time and also as the intermediate signal Vsf. In particular, the example shown in FIG. 4 shows the influence of the signal pulse due to incident photons on the CSA output signal Vcsa and the intermediate signal Vsf according to the present disclosure. In this example, the signal indicating the CSA output signal corresponds to the output voltage signal Vcsa.

[0065] Before the first time instance t1, there are no incident photons, and the output voltage signal Vcsa approximately corresponds to the baseline level at which it is normally reset. Here, for the sake of convenience, it is assumed that there is no dark current or it has already been compensated by DCCU10, and as a result, the output voltage signal Vcsa of CSA4 remains approximately at the baseline level in the absence of incident photons.

[0066] At time instance t1, photons are incident on the photodetector, and a signal pulse appears at the output of CSA4. The intermediate signal Vsf of the signal tracking unit 11 follows or tracks the output voltage signal Vcsa. According to the present disclosure, the maximum rate of change in this polarity direction is more restricted compared to the opposite polarity direction. In particular, at this stage, the intermediate signal Vsf is closer to the baseline level than the output voltage signal Vcsa. As a result, the rate of signal change for the intermediate signal Vsf to follow the output voltage signal Vcsa is more restricted.

[0067] At the second time instance t2, CSA4 is reset to the baseline level again, and the output voltage signal Vcsa decreases. When the output voltage signal Vcsa falls below the signal level of the intermediate signal Vsf, the polarity direction in which the signal tracking unit 11 follows the output voltage signal Vcsa changes. Due to the high maximum rate of change in this polarity direction, the intermediate signal Vsf can respond very quickly to the change in the output voltage signal Vcsa. In particular, at this stage, the intermediate signal Vsf is further away from the baseline level than the output voltage signal Vcsa. Therefore, the rate of signal change for the intermediate signal Vsf to follow the output voltage signal Vcsa is high. In this way, DCCU10 hardly reacts to relatively high-frequency signal pulses but can react to low-frequency changes in the output voltage signal Vcsa. This is particularly advantageous because the dark current is not necessarily static and may change over time due to various factors such as temperature changes in the photodetector 2.

[0068] FIG. 5 shows a more detailed schematic diagram of a part of pixel 1 of FIG. 3 according to an embodiment of the present disclosure.

[0069] The photodetector 2 can be connected to the input of CSA4 and can be biased negatively using a negative high voltage -HV. In this implementation, when photons are incident, free electrons are generated by the absorption of the incident photons and can be repelled towards CSA4. Therefore, the first signal output by the photodetector 2 has a negative polarity, and the output voltage signal Vcsa of CSA4 can consequently have a positive polarity.

[0070] CSA4 includes an amplifier 5 and a feedback network including a feedback capacitor Cf and a feedback resistor Rf. In this implementation, a passive reset using the feedback resistor Rf is shown, but as shown in FIG. 2, it can be replaced with an active reset using a transistor such as a feedback transistor Mf. In all embodiments shown hereinafter from FIG. 5, the feedback resistor Rf can be replaced with a feedback transistor Mf combined with a trigger circuit 9 as described with reference to FIG. 2. The feedback transistor Mf can be biased to form a high impedance (i.e., in the “non-active” case) or a low impedance (i.e., in the “active” case).

[0071] In this embodiment, the signal following unit 11 includes a first signal changing element that changes the signal level of the intermediate signal Vsf in the direction of the first polarity, and a second signal changing element that changes the signal level of the intermediate signal Vsf in the direction of the second polarity. In particular, the first signal changing element includes a source follower transistor Msf, while the second signal changing element includes a current source Isf, which may be a transistor implementation current source as will be understood by those skilled in the art.

[0072] The strength of the signal change of the current source Isf is configured to be smaller than the strength of the signal change of the source follower transistor Msf by making the current supplied by the current source Isf relatively small and appropriately setting the size of the source follower transistor Msf for a relatively large current. In this example, the intermediate signal Vsf is defined as the voltage across the second capacitor C2, and this voltage is controlled by the first and second signal changing elements.

[0073] When the output voltage signal Vcsa of CSA4 is lower than the value obtained by subtracting the threshold voltage of the source follower transistor Msf from the intermediate signal Vsf, the source follower transistor Msf becomes active and discharges the second capacitor C2 to lower the intermediate signal Vsf. However, when the output voltage signal Vcsa of CSA4 is higher than the value obtained by subtracting the threshold voltage of the source follower transistor Msf from the intermediate signal Vsf, the source follower transistor Msf is not active, and the current source Isf charges the second capacitor C2. By adjusting the current source Isf and the source follower transistor Msf accordingly, the voltage change rate of the second capacitor C2 can be made asymmetric with respect to positive and negative changes in the signal level.

[0074] Next, the intermediate signal Vsf is supplied to the signal generation unit 12. In this example, the signal generation unit 12 is composed of a comparison circuit 13 whose first input is connected to the second capacitor C2. Its second input is connected to a reference voltage Vref that depends on the baseline voltage Vbl at which CSA4 is reset after the signal pulse corresponding to the incident photons is processed. However, since the source follower transistor Msf introduces a level shift between the output voltage signal Vcsa and the intermediate signal Vsf when it is active, a reference transistor Mref is introduced, and the baseline voltage Vb is also level-shifted in the same way. The reference transistor Mref can be biased using a reference current Iref.

[0075] The comparison circuit 13 is configured to output the result of comparing the intermediate signal Vsf with the reference signal Vref. This comparison result indicates the deviation between the baseline voltage and the output voltage signal Vcsa, and thus also indicates the dark current component still present at the input of CSA4. Therefore, the comparison circuit 13 may be implemented such that the output of the comparison circuit 13 is directly used as the dark current compensation signal, or as shown in FIG. 5, the output of the comparison circuit 13 can be implemented such that it can be used as a control signal for a signal generator Mdcc (e.g., a transistor as shown in FIG. 5) that converts the control signal into a current and supplies that current to the input of CSA4. The signal generation unit 12 in this example further includes a first capacitor C1, also referred to throughout this disclosure as an output capacitor, which is connected between the power supply rail Vdd and the output of the comparison circuit 13. The control signal in this example is defined as the voltage at the control terminal of the signal generator Mdcc.

[0076] FIG. 6 shows another implementation of pixel 1 of FIG. 3 according to the present disclosure. This implementation differs from the implementation shown in FIG. 6 in that the polarity of the first signal is inverted. In particular, the photodetector 2 is biased at a positive high voltage +HV. In consideration of this, the signal following unit 11 is adapted by exchanging the signal change intensities of the respective circuits described with reference to FIG. 6. In particular, the source follower transistor Msf pulls up the intermediate signal Vsf when active, while the current source Isf pulls down the intermediate signal Vsf. The signal generation unit 12 can be similarly adapted by inverting the current direction of the signal generator Mdcc and inverting the level shift direction of the reference transistor Mref. However, since the operating principle is otherwise similar to that of FIG. 5, a detailed description thereof is omitted with reference to FIG. 6.

[0077] FIG. 7 shows a more detailed implementation of the DCCU 10 of the detector pixel 1 shown in FIG. 3, according to an embodiment of the present disclosure. For example, FIG. 7 can show a more detailed implementation of the DCCU 10 shown in FIG. 5. Descriptions of components and elements already described with reference to FIGS. 3 and 5 are omitted. In fact, the signal following unit 11 and the signal generation unit 12 of FIGS. 3 and / or 5 may be replaced by the DCCU 10 as shown in FIG. 7.

[0078] The comparison circuit 13 can be implemented as an operational transconductance amplifier (OTA) including, for example, transistors M1 to M4. In particular, the comparison circuit 13 can include a differential pair of input transistors M1 and M2. The first transistor M1 is connected to the reference voltage Vref, and the second transistor M2 is connected to the intermediate signal Vsf. The third and fourth transistors M3 and M4 form a current mirror. The differential pair is biased using a tail current source It. Those skilled in the art can understand that the present disclosure is not limited to a specific type of comparison circuit, and other types of comparison circuits can be used instead of the OTA shown in FIG. 7.

[0079] FIG. 8 shows a signal following unit 11 according to another embodiment of the present disclosure, which can replace the signal following unit 11 shown in FIGS. 5 to 7.

[0080] Here, the signal following unit 11 includes a buffer realized using a diode-connected first buffer transistor Mb1 and a second buffer transistor Mb2 in this example, and these are biased using a bias current source Ib. Further, the first signal changing element includes a source follower transistor Msf, and the second signal changing element further includes a further source follower transistor Msf-2 in addition to a current source Isf. In this example, the first and second buffer transistors Mb1, Mb2 may have the same dimensions as the source follower transistor Msf and the further source follower transistor Msf-2. Therefore, the level shift by the first buffer transistor Mb1 can effectively cancel the level shift by the further source follower transistor Msf-2, the level shift by the second buffer transistor Mb2 can effectively cancel the level shift by the source follower transistor Msf, and the intermediate signal Vsf can be made not to shift with respect to the output voltage signal Vcsa in the steady state.

[0081] Similar to FIGS. 5 to 7, by intentionally restricting the current supplied by the current source Isf, an asymmetric response with respect to the output signal of the CSA4 can be realized. For example, in the embodiment shown in FIG. 7, the strength of the pull-up is determined by the current source Isf, and the strength of the pull-down is determined by the source follower transistor Msf. By intentionally selecting the current supplied by the current source Isf to be relatively low compared to the current sinking ability of the source follower transistor Msf, different maximum signal change rates can be set for each direction of signal change.

[0082] In this embodiment of the signal following unit 11, since the comparison circuit 13 can directly and accurately compare the intermediate signal Vsf with the baseline voltage Vb, as described with reference to FIG. 5, the reference transistor Mref is unnecessary for the signal generation unit 12. Therefore, the reference transistor Mref and the reference current source Iref are omitted, and the baseline voltage Vbl is directly provided to the comparison circuit 13.

[0083] FIG. 9 shows a more detailed implementation of pixel 1 shown in FIG. 3 according to yet another embodiment of the present disclosure. This implementation differs from the implementation shown in FIG. 6 in that a diode Dsf is included in the signal follower unit 11 as a first signal modification element instead of a source follower transistor. A diode, such as diode Dsf, can provide a rectifying function and may itself be substantially unidirectional. In this example, when the output voltage signal Vcsa is greater than the signal level of the intermediate signal Vsf, the diode Dsf becomes forward biased, and the current flowing through the diode Dsf can charge the second capacitor C2. Conversely, when the output voltage signal Vcsa is less than the signal level of the intermediate signal Vsf, the diode Dsf is not forward biased and becomes a high impedance, and the current source Isf can discharge the second capacitor C2. By intentionally selecting the current supplied by the current source Isf to be very small compared to the current capacity of the diode Dsf, an asymmetric response to the output voltage signal Vcsa can be created.

[0084] To account for the level shift (i.e., voltage drop) across the entire diode Dsf, a baseline voltage Vbl can be applied to a reference diode Dref biased by a reference current source Iref. The reference current source Iref shifts the level of the baseline voltage Vbl in the same way as the level shift of the intermediate signal Vsf with respect to the output voltage signal Vcsa by the diode Dsf. To that end, the diode Dsf and the reference diode Dref can be made or configured to have the same or similar forward voltages.

[0085] Similar to FIGS. 5 and 6, corresponding schematic diagrams are shown with inverted polarities, but in the present disclosure, it is assumed that the polarity of FIG. 9 can also be inverted. In particular, in this case, the photodetector 2 provides the first signal in the form of free holes (i.e., positive charges), but implementations are also assumed where the photodetector 2 provides the first signal in the form of free electrons (i.e., negative charges) by adapting the signal follower unit 11 and the signal generation unit 12 accordingly.

[0086] FIG. 10 shows a signal tracking unit 11 according to another embodiment of the present disclosure, which replaces the signal tracking unit 11 shown in FIG. 9.

[0087] In this embodiment, the signal tracking unit 11 includes a first diode D1 connected in series with a first resistor element R1, and a second diode D2 connected in parallel with a series connection of a second diode D2 and a second resistor element R2. The first and second resistor elements R1 and R2 may be integrated with the first and second diodes D1 and D2, respectively, or may be provided as separate resistors. In the former case, the first and second resistor elements R1 and R2 may be implemented by appropriately setting the dimensions of the first and second diodes D1 and D2, respectively.

[0088] The first resistor element R1 and the first diode D1 may together form a first signal changing element, and the second resistor element R2 and the second diode D2 may together form a second signal changing element. In order to ensure that the first signal changing element has a greater signal changing ability than the second signal changing element, the first resistor element R1 may have a smaller associated resistance than the second resistor element R2.

[0089] FIG. 11 shows a signal tracking unit 11 according to another embodiment of the present disclosure. This embodiment is different from the embodiment shown in FIG. 10 in that a buffer 14 is provided. The buffer 14 may be an amplifier such as an operational amplifier, and can prevent or at least reduce the load on CSA4 by the signal tracking unit 11.

[0090] Furthermore, buffer 14 can be configured to compensate for a dead band in which neither the first diode D1 nor the second diode D2 in FIG. 10 is forward biased. In particular, when Vsf is lower than Vcsa, the output of buffer 14 goes high, and the voltage across the second capacitor C2 is pulled up via the first resistor R1 and the first diode D1 until Vsf equals Vcsa. The maximum signal change rate in this direction is limited by a first low-pass filter formed by the first resistor R1, the first diode D1, and the second capacitor C2. On the other hand, when Vsf is higher than Vcsa, the output of buffer 14 goes low, and the voltage across the second capacitor C2 is pulled down via the second resistor R2 and the second diode D2 until Vsf equals Vcsa. The maximum signal change rate in this direction is limited by a second low-pass filter formed by the second resistor R2, the second diode D2, and the second capacitor C2. By appropriately setting the dimensions of the first resistor R1, the second resistor R2, the first diode D1, and / or the second diode D2, an asymmetric response with respect to Vcsa can be achieved.

[0091] FIG. 12 shows a part of pixel 1' according to another embodiment of the present disclosure. Pixel 1' includes a photodetector 2, a CSA 4, and a trigger circuit 9, similar to FIG. 2. Although not shown, pixel 1' may further include the remaining signal processing circuit configured to process the output voltage signal of CSA 4. Pixel 1' further includes a DCCU 10'.

[0092] As shown by the dotted line in FIG. 12, the trigger circuit 9 can provide respective control signals to the CSA 4 and the DCCU 10'. In this embodiment, the trigger circuit 9 is configured to reset the CSA 4 using a reset signal rst, for example, by activating a feedback transistor Mf as shown in FIG. 2, after the first signal from the incident photons has been processed by the pixel 1'.

[0093] According to the present disclosure, the DCCU10' is configured to be operable in a first mode and a second mode. In the first mode, the DCCU10' is configured to generate a dark current compensation signal according to the difference between the output voltage signal of the CSA4 and the baseline voltage of the CSA4. In the second mode, the DCCU10' is configured to substantially maintain the signal level of the dark current compensation signal regardless of the output voltage signal of the CSA4. For example, in the second mode, the comparison between the output voltage signal and the baseline voltage can be temporarily disabled.

[0094] Furthermore, according to the present disclosure, the trigger circuit 9 is further configured to detect that photons have entered the photodetector. For example, the trigger circuit 9 can detect the incidence of photons based on the output voltage signal of the CSA4. Further, based on the determination that photons have entered, the trigger circuit 9 is configured to control the DCCU10' to temporarily operate in the second mode and then operate again in the first mode. For example, the trigger circuit 9 can use the trigger control signal Sc to cause the DCCU10' to operate in the second mode as described above until the signal pulse due to the incident photons is processed by the pixel 1'. In other words, the period of temporarily operating in the second mode corresponds to the time required for the pixel 1' to process the first signal from the photodetector 2 due to the incident photons. Thereafter, the trigger circuit 9 operates the DCCU10' again in the first mode and continues to dynamically compensate the dark current from the photodetector 2.

[0095] The trigger circuit 9 can provide the reset signal rst and / or the trigger control signal Sc as digital signals, but the present invention is not necessarily limited thereto.

[0096] As described above, according to the present disclosure, the dark current compensation provided by the DCCU10' as described above is temporarily fixed when the signal needs to be processed by the pixel 1', preventing or at least reducing the influence of the signal on the dark current compensation. By doing so, the dark current can be estimated and compensated more accurately.

[0097] FIG. 13 shows a more detailed implementation of pixel 1' shown in FIG. 12 according to an embodiment of the present disclosure.

[0098] In this embodiment, DCCU10' includes a comparison circuit 13 configured to compare a baseline voltage Vbl and an output voltage signal Vcsa. The result of this comparison is provided to a switch Mc controlled by a trigger circuit 9.

[0099] When there are no incident photons, the trigger circuit 9 controls the switch Mc to be active (i.e., conductive or low impedance), corresponding to DCCU10' operating in the first mode. In the first mode, the switch Mc is configured to function as a relay, connecting the output of the comparison circuit 13 to an output capacitor C1 and a signal generator Mdcc. Next, the signal generator Mdcc generates a dark current compensation signal based on the voltage across the output capacitor C1. In this state, since the comparison circuit 13 can change the voltage across the output capacitor C1 based on its input signal, the dark current compensation signal generated by the signal generator Mdcc can also be changed. However, when the trigger circuit 9 detects that photons have impinged on the photodetector 2 based on, for example, the output voltage signal Vcsa of CSA4, the trigger circuit 9 temporarily deactivates the switch Mc (i.e., the switch Mc becomes non-conductive or forms a high impedance). This corresponds to DCCU10' operating in the second mode. In the second mode, the signal path of the control signal from the output of the comparison circuit 13 to the signal generator Mdcc is prohibited, and the dark current compensation signal provided by the signal generator Mdcc is fixed. For example, the output capacitor C1 substantially maintains the charge from when DCCU10' last operated in the first mode while the switch Mc is deactivated. In this way, since the signal information due to incident photons is not propagated or hardly propagated through DCCU10', it does not affect or hardly affects the accuracy of the dark current compensation signal.

[0100] Figure 14 shows a more detailed implementation of pixel 1' shown in Figure 12, according to another embodiment of the present disclosure. This embodiment is different from the embodiment shown in Figure 13 in that switch Mc is connected between the output of CSA4 and the input of comparator circuit 13, rather than between the output of comparator circuit 13 and signal generator Mdcc. Further, input capacitor C3 is connected to the input of comparator circuit 13.

[0101] In this embodiment, when DCCU10' is operating in the second mode, input capacitor C3 substantially maintains its charge, and in this mode trigger circuit 9 controls switch Mc to deactivate switch Mc. Thus, when DCCU10' is operating in the second mode, the output of comparator circuit 13 does not change depending on output voltage signal Vcsa. As a result, the dark current compensation signal provided by signal generator Mdcc also does not change when DCCU10' is operating in the second mode. In this way, signal information due to incident photons is not propagated or hardly propagated through DCCU10', thus not affecting the accuracy of the dark current compensation signal.

[0102] Optionally, DCCU10' may further include a resistive element R3 (e.g., a resistor) that forms a low-pass filter in conjunction with input capacitor C3 when switch Mc is active and DCCU10' is operating in the first mode. Resistive element R3 may prevent or limit the load on CSA4 and comparator circuit 13, and / or prevent or limit kickback or charge injection from switch Mc to the output of CSA4. Further, the low-pass filter formed by resistive element R3 and input capacitor C3 implements a delay in the response of DCCU10' to changes in the output voltage of CSA4. This delay may be configured to provide sufficient time for trigger circuit 9 to respond to trigger control signal Sc before the change in the output voltage or at least most of the change reaches input capacitor C3.

[0103] Figure 15 shows DCCU10' according to yet another embodiment of the present disclosure. DCCU10' can be replaced with, for example, any of the DCCUs of Figures 12 - 14.

[0104] Here, the comparison circuit is implemented using transistors M1 to M4 in substantially the same manner as the comparison circuit 13 in FIG. 15. However, in this case, the tail current source It is not directly connected to the input transistors M1 and M2, but is connected to the first switch Mc1.

[0105] When DCCU10’ is operating in the first mode, the first switch Mc1 can be active. Therefore, when DCCU10’ is operating in the first mode, the comparison unit can operate normally. When the trigger circuit 9 deactivates the first switch Mc1 to control DCCU10’ to operate in the second mode, the current from the tail current source It is prevented from reaching transistors M1 - M4, and the comparison function of the comparison circuit is also deactivated. As a result, when DCCU10’ is operating in the second mode, for example, the dark current compensation signal is temporarily fixed by the charge accumulated in the output capacitor C1.

[0106] DCCU10’ may further include a second switch Mc2 that is controlled by the trigger circuit 9 complementarily to the first switch Mc1. In other words, when the first switch Mc1 is active, the second switch Mc2 is inactive, and vice versa. The second switch Mc2 enables the current from the tail current source It to flow through a different branch from transistors M1 to M4. This branch preferably includes a dump transistor Md to which the current from the tail current source It is supplied. The dump transistor Md can replicate or simulate the potential of the source terminals of transistors M1 and M2, thereby, on the one hand, the capacitance of DCCU10’ related to the output of the tail current source It is not completely discharged, and on the other hand, excessive capacitive current to the differential pair of the input transistors M1 and M2 is avoided or limited. This can be achieved, for example, by sizing the dump transistor Md similarly and supplying the baseline voltage Vbl to the dump transistor Md in addition to transistor M1.

[0107] The embodiments of FIGS. 13 to 15 can be combined, for example, by implementing the DCCU10' having the switch Mc at the output of the comparison circuit 13 as shown in FIG. 13, having the switch Mc at the input of the comparison circuit 13 as shown in FIG. 14, and / or having the switches Mc1 and Mc2 in the comparison circuit 13 as shown in FIG. 15.

[0108] The pixels 1 and 1' are implemented, at least in part, using individual components mounted, for example, on a printed circuit board (PCB), and / or are realized, at least in part, as an integrated circuit (IC). In the latter case, the IC is provided in a device package including a package material such as a molding compound configured to encapsulate and protect the IC, and leads providing external access to the IC.

[0109] In one embodiment, the pixels 1 and 1' may be partially realized as a module including a readout integrated circuit (ROIC) including a signal processing circuit (e.g., including CSA4, shaper 6, discriminator bank 7, counter array 8, trigger circuit 9, and / or DCCU10). In that case, the photodetector 2 is mounted directly on the surface of the ROIC and electrically connected to the input of the ROIC. Thereafter, the ROIC is mounted on a carrier (e.g., a PCB) and can be electrically connected to external components using wire bonds, (through-silicon) vias, etc. on the ROIC, as would be understood by those skilled in the art.

[0110] The present disclosure may relate to any of the following clauses.

[0111] Claim 1. A detector pixel for an energy-resolving photon counting detector, the pixel comprising: a photodetector configured to convert an incident photon into a first signal indicative of the energy of the incident photon; a charge sensitivity amplifier (CSA) configured to convert the first signal at the input of the CSA into a CSA output signal at the output of the CSA; and a dark current compensation unit (DCCU) for compensating the dark current of the photodetector, the DCCU including: a signal tracking unit configured to provide an intermediate signal, the intermediate signal being configured to track a signal indicative of the CSA output signal with a first maximum signal change rate in a first direction and a second maximum signal change rate lower than the first maximum signal change rate in a second direction opposite to the first direction, wherein the second direction is configured such that a signal indicative of the CSA output signal changes when a photon is incident on the photodetector; and a signal generation unit configured to generate a dark current compensation signal based on the intermediate signal and supply the dark current compensation signal to the CSA.

[0112] Claim 2. The pixel according to claim 1, wherein the signal generation unit further includes a comparison circuit configured to compare the intermediate signal with a reference signal based on a baseline level of the CSA and output a result representing the comparison for generating the dark current compensation signal, and the output of the comparison circuit is either the dark current compensation signal or a control signal for controlling a signal generator to generate the dark current compensation signal.

[0113] Claim 3. The pixel according to claim 1 or 2, wherein the signal tracking unit includes: a first signal change element configured to change a signal level of the intermediate signal in the first direction in response to a signal indicative of the CSA output signal; and a second signal change element configured to change a signal level of the intermediate signal in the second direction in response to a signal indicative of the CSA output signal.

[0114] Claim 4. The pixel according to claim 3, wherein the second signal change element includes a current source such as a transistor-implemented current source.

[0115] Item 5. The pixel according to Item 3 or 4, wherein the first signal changing element includes a source follower transistor, and a control terminal thereof is directly or indirectly connected to an output of the CSA.

[0116] Item 6. The pixel according to Item 2 and 5, wherein the signal generation unit further includes a reference transistor configured to level-shift the baseline level to provide a reference signal, thereby taking into account a level shift of the intermediate signal with respect to the CSA output signal caused by the source follower transistor.

[0117] Item 7. The pixel according to Item 4, 5, and optionally Item 6, wherein the second signal changing element includes a further source follower transistor having a channel arranged in series with the current source, and the signal following unit further includes a buffer connected between the output of the CSA and each of the source follower and the further source follower, and the buffer provides a level-shifted signal to each of the source follower transistor and the further source follower transistor, thereby being configured to take into account a level shift caused by each of the source follower transistor and the further source follower transistor.

[0118] Item 8. The pixel according to Item 3, wherein the first signal changing element includes a series connection of a first diode and a first resistance element, the second signal changing element includes a series connection of a second diode and a second resistance element, the second signal changing element is connected in parallel with the first signal changing element, the second diode is connected in anti-parallel with the first diode, a resistance of the first resistance element is smaller than a resistance of the second resistance element, and preferably, the first diode and the second diode are Schottky diodes.

[0119] Claim 9. The signal tracking unit further includes an amplifier connected to its first input between the output of the CSA and the first and second signal modification elements, the first and second signal modification elements being coupled between the output of the amplifier and the output of the signal tracking unit, and the output of the signal tracking unit being coupled to the second input of the amplifier, thereby forming a negative feedback loop including the amplifier and the first and second signal modification elements. The pixel according to claim 8.

[0120] Claim 10. The first signal modification element includes a diode connected to the output of the CSA, and the second signal modification element includes a current source such as a transistor-implemented current source. The pixel according to claim 3.

[0121] Claim 11. A pixel according to any one of claims 8 to 10 when dependent on claim 2, wherein the signal generation unit further includes a reference diode biased by a reference current source and configured to provide the reference signal by level-shifting the baseline level, thereby taking into account the level shift of the intermediate signal with respect to the CSA output signal caused by the diode when dependent on claim 10, or caused by the first diode and / or the second diode when dependent on claim 8 or 9.

[0122] Claim 12. A pixel according to any one of claims 2 to 11 when dependent on claim 2, wherein the signal generation unit further includes a first capacitor connected between the output of the comparison circuit and a reference terminal.

[0123] Claim 13. The signal tracking unit further includes a second capacitor to which the intermediate signal is supplied as a voltage. The pixel according to any one of claims 1 to 12.

[0124] Item 14. The pixel according to any one of Items 1 to 13, wherein the CSA includes an amplifier and a feedback network including a parallel connection of a feedback capacitor and a reset element configured to reset the CSA.

[0125] Item 15. The pixel according to Item 14, wherein the reset element includes a feedback resistor or includes a feedback transistor, and the pixel further includes a trigger circuit configured to generate a reset signal of the feedback transistor according to the CSA output signal.

[0126] Item 16. The pixel according to any one of Items 1 to 15, further including: a shaper configured to shape the CSA output signal into a second signal indicating the energy of incident photons, preferably including a differentiator and an integrator; a discriminator bank including a plurality of comparison units, each comparison unit being configured to compare the maximum value of the second signal with each respective threshold value and output the result of the comparison; and a counter array including a plurality of counters respectively connected to the plurality of comparison units, each counter being configured to cumulatively store the result of the comparison.

[0127] Item 17. The pixel according to any one of Items 1 to 16, wherein the photodetector includes a light absorption material such as cadmium zinc telluride (CZT) or cadmium telluride (CdTe).

[0128] Item 18. The pixel according to any one of Items 1 to 17, wherein the photodetector is a photodiode, a phototransistor, or a photoconductor.

[0129] Item 19. The pixel according to any one of Items 1 to 18, wherein the CSA output signal is a voltage signal, the intermediate signal is a voltage signal, and the baseline level is a baseline voltage.

[0130] Item 20. The pixel according to any one of Items 1 to 19, wherein the signal indicating the CSA output signal is the CSA output signal or a converted version thereof (e.g., a scaled and / or level-shifted version).

[0131] Item 21. An energy-resolving photon-counting detector including one or more detector pixels according to any one of Items 1 to 20, wherein the one or more detector pixels preferably include a plurality of detector pixels arranged in a matrix of rows and columns.

[0132] Item 22. A detector pixel for an energy-resolving photon-counting detector, the pixel including: a photodetector configured to convert an incident photon into a first signal indicating the energy of the incident photon; a charge sensitivity amplifier (CSA) configured to convert the first signal at the input of the CSA into a CSA output signal at the output of the CSA; and a dark current compensation unit (DCCU) configured to operate in the following modes: In a first mode, the DCCU is configured to generate a dark current compensation signal according to a difference between a baseline level of the CSA and a signal level of the CSA output signal or a signal indicating the same; in a second mode, the DCCU is configured to substantially maintain a signal level of the dark current compensation signal regardless of the CSA output signal; and a trigger circuit configured to detect that a photon has been incident on the photodetector and control the DCCU to temporarily operate in the second mode and then operate in the first mode again.

[0133] Item 23. The pixel according to Item 22, wherein the DCCU includes a comparison circuit configured to compare the CSA output signal or a signal indicating the same with the baseline level of the CSA and output a control signal according to a comparison result, and a signal generator configured to generate the dark current compensation signal based on the control signal.

[0134] Item 24. The DCCU further comprises one or more switches configured to disable the signal path from the output of the CSA to the signal generator in the second mode, and the trigger circuit is configured to activate the one or more switches using a trigger control signal to control the DCCU to operate in the second mode. The pixel according to Item 22 or 23.

[0135] Item 25. At least one of the one or more switches is connected between the output of the CSA and the input of the comparison circuit, and the DCCU further includes an input capacitance element connected to the input of the comparison circuit and configured to substantially maintain its charge when the DCCU is operating in the second mode. The pixel according to Item 23 and 24.

[0136] Item 26. The DCCU further includes a resistance element connected between the output of the CSA and the input capacitance element, and the resistance element and the input capacitance element together form a low-pass filter. The pixel according to Item 25.

[0137] Item 27. At least one of the one or more switches is connected between the output of the comparison circuit and the signal generator, and the DCCU further includes an output capacitor connected to the control terminal of the signal generator and configured to substantially maintain its charge when the DCCU is operating in the second mode. The pixel according to Item 23 and 24, and optionally Item 24 or 25.

[0138] Item 28. At least one of the one or more switches is included in the comparison circuit, and the DCCU further includes an output capacitor connected to the control terminal of the signal generator and configured to substantially maintain its charge when the DCCU is operating in the second mode. The pixel according to Item 23 and 24, optionally any one of Items 25 to 27.

[0139] Claim 29. The comparison unit includes an amplifier including a differential input transistor pair, wherein a first input transistor thereof is connected to the output of the CSA, a baseline level is supplied to a second input transistor thereof, the amplifier further includes a tail current source, and in a second mode, at least one of the one or more switches is configured to disable a current path from the tail current source to the differential input transistor pair, the pixel according to Claim 28.

[0140] Claim 30. In the second mode, at least one of the one or more switches provides a current path from the tail current source to another branch different from a branch corresponding to the differential input transistor pair, and the another branch preferably includes a transistor configured to replicate a potential across the differential input transistor pair, the pixel according to Claim 29.

[0141] Claim 31. The period of temporarily operating in the second mode is determined based on a time required for the pixel to process the first signal, the pixel according to any one of Claims 22 to 30.

[0142] Claim 32. The CSA includes a feedback network including a parallel connection of an amplifier, a feedback capacitor, and a reset element configured to reset the CSA, the pixel according to any one of Claims 22 to 31.

[0143] Claim 33. The reset element includes a feedback resistor; or a feedback transistor, and the trigger circuit is further configured to generate a reset signal for the feedback transistor according to the CSA output signal, or an intermediate signal reflecting the CSA output signal, the pixel according to Claim 32.

[0144] Item 34. Further, a shaper configured to shape the CSA output signal into a second signal indicating the energy of incident photons, preferably including a differentiator and an integrator; an identifier bank including a plurality of comparison units, each comparison unit being configured to compare the maximum value of the second signal with a respective threshold value and output the result of the comparison; and a counter array including a plurality of counters respectively connected to the plurality of comparison units, each counter being configured to cumulatively store the result of the comparison; a pixel according to any one of Items 22 to 33, including the counter array.

[0145] Item 35. The pixel according to any one of Items 22 to 34, wherein the photodetector includes a light absorption material such as cadmium zinc telluride (CZT) or cadmium telluride (CdTe).

[0146] Item 36. The pixel according to any one of Items 22 to 35, wherein the photodetector is a photodiode, a phototransistor, or a photoconductor.

[0147] Item 37. The pixel according to any one of Items 22 to 36, wherein the CSA output signal is a voltage signal and the baseline level is a baseline voltage.

[0148] Item 38. An energy-resolved photon counting detector including one or more detector pixels defined by any one of Items 22 to 37, wherein the one or more detector pixels preferably include a plurality of detector pixels arranged in a matrix of rows and columns.

[0149] The foregoing description provides only exemplary embodiments that are preferred and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the description of the preferred exemplary embodiments provides those skilled in the art with a useful explanation for implementing the preferred exemplary embodiments of the present disclosure, and various changes and / or combinations of features from different embodiments can be made without departing from the scope of the present disclosure as defined by the appended claims. It is understood that various changes can be made to the functions and arrangements of the elements.

Claims

1. A detector pixel (1) for an energy-resolving photon counting detector, said pixel (1) comprising: a photodetector (2) configured to convert incident photons into a first signal indicative of the energy of the incident photons; a charge sensitive amplifier (4) (CSA) configured to convert a first signal at an input of the CSA (4) to a CSA output signal (Vcsa) at an output of the CSA (4); and A dark current compensation unit (10) (DCCU) for compensating for the dark current of the photodetector (2); Including, The DCCU (10) a signal following unit (11) configured to provide an intermediate signal (Vsf), the intermediate signal (Vsf) configured to follow a signal indicative of the CSA output signal (Vcsa) with a first maximum signal rate of change in a first direction and with a second maximum signal rate of change lower than the first maximum signal rate of change in a second direction opposite to the first direction, where the second direction is a direction in which the signal indicative of the CSA output signal (Vcsa) is configured to change when a photon is incident on the photodetector (2); and a signal generating unit (12) configured to generate a dark current compensation signal based on the intermediate signal (Vsf) and to provide the dark current compensation signal to the CSA (4); Including, Pixel(1).

2. The signal generating unit (12) further comprises a comparison circuit (13) configured to compare the intermediate signal (Vsf) with a reference signal (Vref) based on a baseline level (Vbl) of the CSA (4) and output a result representative of the comparison to generate the dark current compensation signal; 2. The pixel (1) of claim 1, wherein an output of the comparison circuit (13) is the dark current compensation signal or the output of the comparison circuit (13) is a control signal for controlling a signal generator (Mdcc) to generate the dark current compensation signal.

3. The signal tracking unit (11) A first signal changing element configured to change the signal level of the intermediate signal (Vsf) in the first direction in response to a signal indicative of the CSA output signal (Vcsa); and a second signal changing element configured to change the signal level of the intermediate signal (Vsf) in the second direction in response to a signal indicative of the CSA output signal (Vcsa); The pixel (1) according to claim 1 or 2, comprising:

4. The pixel (1) of claim 3, wherein the second signal-modifying element comprises a current source, such as a transistor-implemented current source.

5. The pixel (1) according to claim 3 or 4, wherein the first signal modifying element comprises a source follower transistor (Msf), the control terminal of which is connected directly or indirectly to the output of the CSA (4).

6. The pixel (1) of claims 2 and 5, wherein the signal generating unit (12) further comprises a reference transistor (Mref) configured to level-shift the baseline level (Vbl) to provide a reference signal (Vref), thereby taking into account a level shift of the intermediate signal (Vsf) relative to the CSA output signal (Vcsa) caused by the source follower transistor (Msf).

7. the second signal modifying element comprises a further source follower transistor (Msf-2) having a channel arranged in series with the current source; The pixel (1) according to claims 4 and 5, and optionally claim 6, wherein the signal following unit (11) further comprises buffers (Mb1, Mb2) connected between an output of the CSA (4) and each of the source follower (Msf) and further source follower (Msf-2), the buffers (Mb1, Mb2) being configured to provide a level-shifted signal to each of the source follower transistor (Msf) and further source follower transistor (Msf-2), thereby taking into account a level shift caused by the source follower transistor (Msf) and further source follower transistor (Msf-2), respectively.

8. the first signal modifying element includes a series connection of a first diode (D1) and a first resistive element (R1); the second signal modifying element includes a series connection of a second diode (D2) and a second resistive element (R2); the second signal modifying element is connected in parallel with the first signal modifying element; and the second diode (D2) is connected in anti-parallel with the first diode (D1); The resistance of the first resistive element (R1) is smaller than the resistance of the second resistive element (R2); The pixel (1) according to claim 3, wherein preferably the first diode (D1) and the second diode (D2) are Schottky diodes.

9. The signal following unit (11) further comprises an amplifier (14) connected to its first input between the output of the CSA (4) and the first and second signal modifying elements; 9. The pixel (1) of claim 8, wherein the first and second signal modifying elements are coupled between an output of the amplifier and an output of the signal following unit (11), the output of the signal following unit (11) being coupled to a second input of the amplifier, thereby forming a negative feedback loop including the amplifier and the first and second signal modifying elements.

10. 4. The pixel (1) of claim 3, wherein the first signal modifying element comprises a diode (Dp) connected to an output of the CSA (4), and the second signal modifying element comprises a current source (Isf), such as a transistor-implemented current source.

11. Pixel (1) according to any one of claims 8 to 10 when dependent on claim 2, The signal generating unit (12) further comprises a reference diode (Dref) biased with a reference current source (Iref) and configured to provide the reference signal (Vref) by level-shifting the baseline level (Vbl), thereby taking into account a level shift of the intermediate signal (Vsf) relative to the CSA output signal (Vcsa) caused by the diode (Dp) in the case dependent on claim 10, or caused by the first diode (D1) and / or the second diode (D2) in the case dependent on claim 8 or 9.

12. The pixel (1) according to any one of claims 3 to 11 when dependent on claim 2, wherein the signal generating unit (12) further comprises a first capacitor (C1) connected between the output of the comparison circuit (13) and a reference terminal; and / or The signal following unit (11) further comprises a second capacitor (C2) to which the intermediate signal is supplied as a voltage, pixel (1).

13. the CSA (4) comprises an amplifier (4a) and a feedback network comprising a parallel connection of a feedback capacitor (Cf) and a reset element configured to reset the CSA (4), the reset element preferably comprising a feedback resistor (Rf), or the reset element preferably comprising a feedback transistor (Mf), the pixel (1) further comprising a trigger circuit (9) configured to generate a reset signal (rst) for the feedback transistor (Mf) in response to the CSA output signal (Vcsa); and / or The pixel (1) further comprises: a shaper (6) configured to shape the CSA output signal (Vcsa) into a second signal indicative of the energy of incident photons, the shaper (6) preferably comprising a differentiator (6a) and an integrator (6b); a discriminator bank (7) comprising a plurality of comparison units (7a), each comparison unit (7a) configured to compare a maximum value of the second signal with a respective threshold value and to output a result of the comparison; and a counter array (8) including a plurality of counters (8a) respectively connected to the plurality of comparison units (7a), each counter (8a) being configured to cumulatively store a result of the comparison; The pixel (1) according to any one of the preceding claims, comprising:

14. the photodetector (2) comprises a light absorbing material such as cadmium zinc telluride (CZT) or cadmium telluride (CdTe); and / or the photodetector (2) being a photodiode, a phototransistor, or a photoconductor; and / or the CSA output signal (Vcsa) is a voltage signal, the intermediate signal (Vsf) is a voltage signal, and the baseline level (Vbl) is a baseline voltage; and / or The pixel (1) according to any one of the preceding claims, wherein the signal indicative of the CSA output signal (Vcsa) is the CSA output signal (Vcsa) or a transformed version thereof (eg a scaled and / or level shifted version).

15. 15. An energy-resolving photon counting detector comprising one or more detector pixels (1) according to any one of the preceding claims, said one or more detector pixels (1) preferably comprising a plurality of detector pixels arranged in a matrix of rows and columns.

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