Semiconductor device

Abstract

To provide a semiconductor device capable of holding analog data.SOLUTION: Using four transistors and two capacitive elements, two holding circuits, two bootstrap circuits, and one source follower circuit are formed. The two holding circuits are respectively provided with storage nodes to one of which data potential is written and to the other of which reference potential is written. Upon data reading, the potential of one of the storage nodes is boosted by the one bootstrap circuit and the potential of the other storage node is boosted by the other bootstrap circuit. A potential difference between the two storage nodes is outputted using the source follower circuit. The use of the source follower circuit makes it possible to reduce output impedance.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited as an example.

Background Art

[0003] In recent years, electronic components such as a central processing unit (CPU), a graphics processing unit (GPU), a storage device, and a sensor have been used in various electronic devices such as personal computers, smartphones, and digital cameras. The electronic components are being improved in various aspects such as miniaturization and low power consumption.

[0004] In particular, in recent years, the amount of data handled by electronic devices has been increasing, and a storage device with a large storage capacity has been demanded. For this reason, the development of a storage device that holds multi-valued data or analog data in one storage element has been studied. Patent Document 1 and Patent Document 2 disclose semiconductor devices that enable writing and reading of multi-valued data.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] There is a demand for a semiconductor device capable of retaining analog data for a long period of time and accurately reading out the retained analog data.

[0007] In a transistor in which a semiconductor layer in which a channel is formed contains silicon (also referred to as a "Si transistor"), device miniaturization has progressed with the reduction of the process rules. Further, with the miniaturization of the device, the gate insulating film is also thinned, so that the leakage current through the gate insulating film becomes a problem.

[0008] One aspect of the present invention is to provide a semiconductor device capable of retaining analog data as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device capable of accurately reading out the retained analog data as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with a reduced occupied area as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with reduced power consumption as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with a large storage capacity as one of the problems. Or, one aspect of the present invention is to provide a highly reliable semiconductor device as one of the problems. Or, one aspect of the present invention is to provide a novel semiconductor device as one of the problems.

[0009] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Note that other problems are the problems not mentioned in this item described below. The problems not mentioned in this item can be derived by those skilled in the art from the description of the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not need to solve all of the problems listed above and other problems.

Means for Solving the Problem

[0010] One aspect of the present invention is a semiconductor device that uses four transistors and two capacitive elements to form two holding circuits, two bootstrap circuits, and one source follower circuit. Each of the two holding circuits is provided with a memory node, a data potential is written to one memory node, and a reference potential is written to the other memory node. When reading data, the potential of one memory node is boosted by one bootstrap circuit, and the potential of the other memory node is boosted by the other bootstrap circuit. The potential difference between the two memory nodes is output using the source follower circuit. By using the source follower circuit, the output impedance can be reduced.

[0011] Another aspect of the present invention is a semiconductor device having first to fifth circuits, wherein the first circuit has a function of holding a first potential, the second circuit has a function of boosting the first potential, the third circuit has a function of holding a second potential, the fourth circuit has a function of boosting the second potential, and the fifth circuit has a function of outputting a third potential corresponding to the potential difference between the boosted first potential and the boosted second potential.

[0012] The semiconductor device described above may include, for example, first to fourth transistors, a first capacitive element, and a second capacitive element. The first circuit includes the first transistor and the first capacitive element, the second circuit includes the second transistor and the first capacitive element, the third circuit includes the third transistor and the second capacitive element, the fourth circuit includes the fourth transistor and the second capacitive element, and the fifth circuit may include the second transistor and the fourth transistor.

[0013] Another aspect of the present invention has a first to fourth transistors, a first capacitor element, and a second capacitor element. One of the source or drain of the first transistor is electrically connected to the first terminal, and the other of the source or drain of the first transistor is electrically connected to the gate of the second transistor. The gate of the first transistor is electrically connected to the second terminal. One of the source or drain of the third transistor is electrically connected to the third terminal, and the other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The gate of the third transistor is electrically connected to the fourth terminal. One of the source or drain of the second transistor is electrically connected to the fifth terminal, and the other of the source or drain of the second transistor is electrically connected to the seventh terminal. One of the source or drain of the fourth transistor is electrically connected to the sixth terminal, and the other of the source or drain of the fourth transistor is electrically connected to the seventh terminal. One electrode of the first capacitor element is electrically connected to the gate of the second transistor, and the other electrode of the first capacitor element is electrically connected to the seventh terminal. One electrode of the second capacitor element is electrically connected to the gate of the fourth transistor, and the other electrode of the second capacitor element is electrically connected to the seventh terminal. It is a semiconductor device.

[0014] Also, the third terminal and the sixth terminal may be electrically connected. It is preferable that the first transistor and the third transistor include an oxide semiconductor in the semiconductor layer where the channel is formed. In addition, it is preferable that the second transistor and the fourth transistor include an oxide semiconductor in the semiconductor layer where the channel is formed. The oxide semiconductor preferably contains at least one of indium or zinc.

Advantages of the Invention

[0015] According to one aspect of the present invention, a semiconductor device capable of holding analog data can be provided. Or, a semiconductor device capable of accurately reading out the held analog data can be provided. Or, a semiconductor device with a reduced occupied area can be provided. Or, a semiconductor device with reduced power consumption can be provided. Or, a semiconductor device with a large storage capacity can be provided. Or, a highly reliable semiconductor device can be provided. Or, a novel semiconductor device can be provided.

[0016] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are those effects not mentioned in this item as described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above.

Brief Description of Drawings

[0017]

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Mode for Carrying Out the Invention

[0018] The embodiments of the present invention will be described below. However, one embodiment of the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as limited to the description of the embodiments shown below.

[0019] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, or an electronic component in which a chip is housed in a package is an example of a semiconductor device. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc. are semiconductor devices themselves and may have a semiconductor device.

[0020] Also, in this specification and the like, when it is described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also assumed to be disclosed in the figure or the text. X and Y are assumed to be objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0021] As an example of the case where X and Y are electrically connected, one or more elements that enable the electrical connection between X and Y (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. Note that the switch has a function of controlling the on state and the off state. That is, the switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not.

[0022] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, it is considered that X and Y are functionally connected.

[0023] Note that when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, the case where they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, the case where they are connected without another element or another circuit interposed between X and Y).

[0024] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By stipulating the connection order in the circuit configuration using an expression method similar to these examples, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0025] Note that even when components that are independent on the circuit diagram are shown to be electrically connected, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component. Therefore, the electrically connected in this specification includes such cases where one conductive film has the functions of multiple components within its scope.

[0026] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the "resistive element" includes wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, a coil, and the like. Therefore, the term "resistive element" can be paraphrased as terms such as "resistance", "load", "region having a resistance value", and conversely, the terms "resistance", "load", "region having a resistance value" can be paraphrased as terms such as "resistive element". As the resistance value, for example, it can be preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0027] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification and the like, the "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also parasitic capacitance that appears between wirings, gate capacitance that appears between one of the source or drain of a transistor and the gate, and the like. Also, terms such as "capacitive element", "parasitic capacitance", "gate capacitance" can be paraphrased as terms such as "capacitance", and conversely, the term "capacitance" can be paraphrased as terms such as "capacitive element", "parasitic capacitance", "gate capacitance". Also, the term "pair of electrodes" of "capacitance" can be paraphrased as "pair of conductors", "pair of conductive regions", "pair of regions", etc. Note that as the capacitance value, for example, it can be 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 μF or less.

[0028] In addition, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are considered interchangeable with each other. Also, in this specification and the like, when explaining the connection relationship of a transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, it may have a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0029] In addition, in this specification and the like, the "on-current" may refer to the current flowing between the source and the drain when the transistor is in the on-state. Also, the "off-current" may refer to the current flowing between the source and the drain when the transistor is in the off-state.

[0030] In addition, in this specification and the like, a node can be equivalently referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on the circuit configuration and / or device structure, etc. Also, it is possible to equivalently refer to a terminal, a wiring, etc. as a node.

[0031] Also, in this specification and the like, "voltage" and "electric potential" can be appropriately rephrased. "Voltage" is the potential difference from a reference potential. For example, when the reference potential is the ground potential (earth potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to a wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc. also change.

[0032] Also, in this specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as "VDD") indicates a power supply potential with a potential higher than the low power supply potential VSS (hereinafter, also simply referred to as "VSS"). Also, VSS indicates a power supply potential with a potential lower than VDD. Also, the ground potential (hereinafter, also simply referred to as "GND") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0033] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers, unless otherwise specified. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in wiring, etc. is defined as the direction in which the positive carriers move, and is described with a positive current amount. In other words, the direction in which the negative carriers move is the opposite direction to the direction of current, and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), descriptions such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, descriptions such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0034] Also, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0035] Also, the terms "above" or "below" do not limit that the positional relationship of the components is directly above or directly below and in direct contact. For example, in the expression "electrode B above insulating layer A", it is not necessary that electrode B is formed directly in contact above insulating layer A, and components other than insulating layer A and electrode B are not excluded from being included between them.

[0036] In addition, the positional relationship of the components changes as appropriate according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification or the like, and can be appropriately rephrased according to the situation. For example, in this specification or the like, terms indicating arrangements such as "above" and "below" may be used for convenience in order to explain the positional relationship of the components with reference to the drawings. Thus, the expression "an insulator located on the upper surface of the conductor" can be rephrased as "an insulator located on the lower surface of the conductor" by rotating the orientation of the shown drawing by 180 degrees. Also, in the expression "an insulator located on the upper surface of the conductor", by rotating the orientation of the shown drawing by 90 degrees, it can be rephrased as "an insulator located on the left surface (or right surface) of the conductor".

[0037] Similarly, in this specification or the like, terms such as "overlap" do not limit the state such as the stacking order of the components. For example, in the expression "electrode B overlapping insulating layer A", it is not limited to the state where "electrode B is formed on insulating layer A", and states such as "electrode B is formed under insulating layer A" or "electrode B is formed on the right side (or left side) of insulating layer A" are not excluded.

[0038] In addition, in this specification or the like, the terms "adjacent" or "proximate" do not limit that the components are in direct contact. For example, in the expression "electrode B adjacent to insulating layer A", it is not necessary for insulating layer A and electrode B to be formed in direct contact, and those including other components between insulating layer A and electrode B are not excluded.

[0039] In addition, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases, or depending on the situation, it is possible to replace the terms such as "film" and "layer" with other terms without using them. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0040] Also, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" and "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and, for example, a "terminal" can be part of "wiring" or "electrode". Also, the terms such as "electrode", "wiring", and "terminal" may be replaced with terms such as "region" in some cases.

[0041] Also, in this specification and the like, terms such as "wiring", "signal line", and "power supply line" can be interchanged with each other depending on the case or situation. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to terms such as "power supply line". Conversely, terms such as "signal line" and "power supply line" may be changed to the term "wiring". Terms such as "power supply line" may be changed to terms such as "signal line". Conversely, terms such as "signal line" may be changed to terms such as "power supply line". Also, the term "potential" applied to the wiring may be changed to terms such as "signal" depending on the case or situation. Conversely, terms such as "signal" may be changed to the term "potential".

[0042] In this specification and the like, the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, for example, there are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is silicon, examples of the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements excluding oxygen and hydrogen.

[0043] In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether to allow current to flow or not. Or, a switch refers to a device that has a function of selecting and switching a current path. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control current and is not limited to a specific one.

[0044] As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combined with these. When a transistor is used as a switch, the "conductive state (on state)" of the transistor refers to a state where the source and drain of the transistor can be regarded as being electrically short-circuited. Also, the "non-conductive state (off state)" of the transistor refers to a state where the source and drain of the transistor can be regarded as being electrically disconnected. When operating a transistor as a mere switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0045] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0046] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "substantially parallel" or "approximately parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Further, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially perpendicular" or "approximately perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Further, when described as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0048] Further, in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0049] Further, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0050] Note that the content described in one embodiment (which may be part of the content) can be applied to, combined with, or replaced with at least one of the content described in another content (which may be part of the content) described in that embodiment and the content (which may be part of the content) described in one or more other embodiments.

[0051] Note that the content described in the embodiments refers to the content described using various figures in each embodiment (or example) or the content described using the text described in the specification.

[0052] Note that the figure (which may be part of it) described in one embodiment can be combined with at least one of another part of that figure, another figure (which may be part of it) described in that embodiment, and the figure (which may be part of it) described in one or more other embodiments to form more figures.

[0053] The embodiments described in this specification will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways and the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention should not be construed as being limited to the described content of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used between different drawings for the same part or parts having the same function, and the repeated description may be omitted. Also, for ease of understanding the drawings, the description of some components may be omitted in perspective views or top views.

[0054] In this specification and the like, in a block diagram, components are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate components by function, and there may be cases where a single circuit is related to multiple functions, or where a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0055] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to its size, aspect ratio, etc. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0056] In this specification and the like, when the same reference numeral is used for a plurality of elements, especially when it is necessary to distinguish them, an identification symbol such as “_1”, “[n]”, “[m,n]”, etc. may be appended to the reference numeral for description. For example, one of the two wirings GL may be described as wiring GL[1], and the other may be described as wiring GL[2], etc.

[0057] (Embodiment 1) A semiconductor device 100 according to one embodiment of the present invention will be described with reference to the drawings.

[0058] <Configuration example of semiconductor device 100> FIG. 1A shows a circuit diagram of a semiconductor device 100 according to one aspect of the present invention. The semiconductor device 100 can function as a memory circuit capable of holding analog data. Also, the semiconductor device 100 can function as a memory element capable of holding analog data. The semiconductor device 100 includes transistors Tr11, Tr12, Tr21, Tr22, capacitor elements Cb1, and capacitor element Cb2.

[0059] Further, the semiconductor device 100 includes a holding circuit 110a, a holding circuit 110b, a bootstrap circuit 120a, a bootstrap circuit 120b, and a source follower circuit 130.

[0060] The holding circuit 110a includes a transistor Tr11 and a capacitor element Cb1, and the holding circuit 110b includes a transistor Tr21 and a capacitor element Cb2. The bootstrap circuit 120a includes a transistor Tr12 and a capacitor element Cb1, and the bootstrap circuit 120b includes a transistor Tr22 and a capacitor element Cb2. The source follower circuit 130 includes a transistor Tr12 and a transistor Tr22.

[0061] The gate of the transistor Tr11 is electrically connected to the terminal WW1, one of the source or drain of the transistor Tr11 is electrically connected to the terminal IN1, and the other is electrically connected to the gate of the transistor Tr12. One of the source or drain of the transistor Tr12 is electrically connected to the terminal PS1, and the other is electrically connected to the terminal OUT.

[0062] The gate of the transistor Tr21 is electrically connected to the terminal WW2, one of the source or drain of the transistor Tr21 is electrically connected to the terminal IN2, and the other is electrically connected to the gate of the transistor Tr22. One of the source or drain of the transistor Tr22 is electrically connected to the terminal OUT, and the other is electrically connected to the terminal PS2.

[0063] One electrode constituting the capacitor element Cb1 is electrically connected to the gate of the transistor Tr12, and the other electrode is electrically connected to the terminal OUT. One electrode constituting the capacitor element Cb2 is electrically connected to the terminal OUT, and the other electrode is electrically connected to the gate of the transistor Tr22.

[0064] The node where the other of the source or drain of transistor Tr11, the gate of transistor Tr12, and one electrode constituting capacitor element Cb1 are electrically connected functions as node SN1. The node where the other of the source or drain of transistor Tr21, the gate of transistor Tr22, and the other electrode constituting capacitor element Cb2 are electrically connected functions as node SN2. The node where the other electrode constituting capacitor element Cb1, one electrode constituting capacitor element Cb2, and terminal OUT are electrically connected functions as node BN. Note that node SN1 and node SN2 each function as a storage node.

[0065] Retention circuit 110a has a function of retaining the potential (charge) written to node SN1 via transistor Tr11. Retention circuit 110b has a function of retaining the potential (charge) written to node SN2 via transistor Tr21.

[0066] Specifically, a potential that turns on transistor Tr11 is supplied to the gate of transistor Tr11, and charge for setting node SN1 to a predetermined potential is supplied to node SN1 via the source and drain of transistor Tr11. Thereafter, a potential that turns off transistor Tr11 is supplied to the gate of transistor Tr11. By turning off transistor Tr11, the charge written to node SN1 is retained.

[0067] Similarly, a potential that turns on transistor Tr21 is supplied to the gate of transistor Tr21, and charge for setting node SN2 to a predetermined potential is supplied to node SN2 via the source and drain of transistor Tr21. Thereafter, a potential that turns off transistor Tr21 is supplied to the gate of transistor Tr21. By turning off transistor Tr21, the charge written to node SN2 is retained. Thus, node SN1 and node SN2 are also referred to as "retention nodes". Also, transistor Tr11 and transistor Tr21 are also referred to as "write transistors".

[0068] As the semiconductor layers of the transistors Tr11, Tr12, Tr21, and Tr22, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon, germanium, or the like can be used. Further, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used.

[0069] Note that the semiconductor layer used for the transistor may be a stack of a plurality of semiconductor layers. When stacking semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

[0070] In particular, the transistors Tr11 and Tr21 are preferably transistors (also referred to as "OS transistors") in which the semiconductor layer in which the channel is formed contains an oxide semiconductor. Since the oxide semiconductor has a band gap of 2 eV or more, the off-current is extremely small. When OS transistors are used for the transistors Tr11 and Tr21, the charges written in the holding nodes can be held for a long period. When OS transistors are used for the transistors Tr11 and Tr21, the semiconductor device 100 can be called an "OS memory".

[0071] The OS memory can hold the written information for a period of one year or more, and even ten years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0072] Further, since the amount of charge written in the OS memory hardly changes over a long period, the OS memory can hold not only binary (1-bit) but also multi-valued (multi-bit) information.

[0073] In addition, since the OS memory writes charges to the node via the OS transistor, the high voltage required for conventional flash memory is not necessary, and a high-speed write operation can also be achieved. Further, the erasure operation before data rewriting performed in flash memory is not required in the OS memory. Also, since charge injection and extraction to the floating gate or charge trapping layer are not performed, the OS memory can perform substantially unlimited data writing and reading. The OS memory has less degradation and higher reliability compared to conventional flash memory.

[0074] In addition, the OS memory does not involve structural changes at the atomic level like magnetic random access memory (MRAM) or resistive random access memory (ReRAM). Therefore, the OS memory has better rewrite resistance than magnetic random access memory and resistive random access memory.

[0075] Also, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is not easily reduced even in a high-temperature environment. The storage device including the OS memory operates stably even in a high-temperature environment and has high reliability. Also, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor for the transistors constituting the semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment. Therefore, it is preferable to use the OS transistor for the transistors Tr11, Tr21, Tr12, and Tr22.

[0076] Also, if the gate insulating films of the transistors Tr12 and Tr22 are extremely thin, the charges written to the nodes SN1 and SN2 via the gate insulating films may leak out (also referred to as "gate leakage"). The thickness of the gate insulating films of the transistors Tr12 and Tr22 is preferably about the same as the thickness of the gate insulating films of the transistors Tr11 and Tr21.

[0077] Further, for example, an OS transistor may be used for transistors Tr11 and Tr21, and an Si transistor may be used for transistors Tr12 and Tr22. For the Si transistors used for transistors Tr12 and Tr22, an Si transistor having a structure with low gate leakage may be used.

[0078] Since the Si transistor has a higher operating speed than the OS transistor, using Si transistors for transistors Tr12 and Tr22 can increase the data readout speed.

[0079] Also, as shown in FIG. 1B, the gates of transistors Tr11 and Tr21 may be electrically connected to wiring WWL.

[0080] Also, as shown in FIG. 2A, transistors having back gates may be used for transistors Tr12 and Tr22. FIG. 2A shows an example in which the back gate of transistor Tr12 is electrically connected to terminal BG14, and the back gate of transistor Tr22 is electrically connected to terminal BG24. By controlling the potential of terminal BG14, the threshold voltage of transistor Tr12 can be changed. By controlling the potential of terminal BG24, the threshold voltage of transistor Tr22 can be changed.

[0081] Also, as shown in FIG. 2B, transistors having back gates may be used for transistors Tr11 and Tr21. FIG. 2B shows an example in which the back gate of transistor Tr11 is electrically connected to terminal BG13, and the back gate of transistor Tr21 is electrically connected to terminal BG23. By controlling the potential of terminal BG13, the threshold voltage of transistor Tr11 can be changed. By controlling the potential of terminal BG23, the threshold voltage of transistor Tr21 can be changed.

[0082] In addition, in FIG. 3A, an example in which the gates and back gates of transistors Tr11, Tr12, Tr21, and Tr22 are electrically connected is shown. In FIG. 3B, an example in which the back gate of transistor Tr22 is electrically connected to the other of the source or drain of transistor Tr22 is shown. By providing the back gate, an electric field generated outside the transistor is less likely to act on the channel formation region, so that the operation of the semiconductor device is stabilized and the reliability of the semiconductor device can be improved.

[0083] In addition, each of transistors Tr11, Tr12, Tr21, and Tr22 may be a double-gate transistor. FIG. 4A shows an example of a circuit symbol of a double-gate transistor 180A.

[0084] Transistor 180A has a configuration in which transistor Tr1 and transistor Tr2 are connected in series. In FIG. 4A, one of the source or drain of transistor Tr1 is electrically connected to terminal S, the other of the source or drain of transistor Tr1 is electrically connected to one of the source or drain of transistor Tr2, and the other of the source or drain of transistor Tr2 is electrically connected to terminal D. Also, in FIG. 4A, the gates of transistor Tr1 and transistor Tr2 are electrically connected and are also electrically connected to terminal G.

[0085] The transistor 180A shown in FIG. 4A has a function of switching between a conductive state and a non-conductive state between terminal S and terminal D by changing the potential of terminal G. Therefore, the double-gate transistor 180A includes transistors Tr1 and Tr2 and functions as one transistor. That is, in FIG. 4A, it can be said that one of the source or drain of transistor 180A is electrically connected to terminal S, the other of the source or drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.

[0086] Further, each of transistor Tr11, transistor Tr12, transistor Tr21, and transistor Tr22 may be a triple-gate transistor. FIG. 4B shows an example of a circuit symbol of a triple-gate transistor 180B.

[0087] Transistor 180B has a configuration in which transistor Tr1, transistor Tr2, and transistor Tr3 are connected in series. In FIG. 4B, one of the source or drain of transistor Tr1 is electrically connected to terminal S, the other of the source or drain of transistor Tr1 is electrically connected to one of the source or drain of transistor Tr2, the other of the source or drain of transistor Tr2 is electrically connected to one of the source or drain of transistor Tr3, and the other of the source or drain of transistor Tr3 is electrically connected to terminal D. Further, in FIG. 4B, the gates of transistor Tr1, transistor Tr2, and transistor Tr3 are electrically connected and are shown in a state of being electrically connected to terminal G.

[0088] The transistor 180B shown in FIG. 4B has a function of switching the conduction state or non-conduction state between terminal S and terminal D by changing the potential of terminal G. Therefore, the transistor 180B, which is a triple-gate transistor, includes transistor Tr1, transistor Tr2, and transistor Tr3 and functions as one transistor. That is, in FIG. 4B, it can be said that one of the source or drain of transistor 180B is electrically connected to terminal S, the other of the source or drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.

[0089] Transistors having a plurality of gates and in which the plurality of gates are electrically connected, such as transistor 180A and transistor 180B, may be referred to as "multi-gate transistors" or "multi-gate transistors".

[0090] <Operation Example of Semiconductor Device 100> An operation example of the semiconductor device 100 will be described with reference to the drawings. As described above, the semiconductor device 100 according to one aspect of the present invention constitutes the source follower circuit 130 using the transistor Tr12 and the transistor Tr22.

[0091] Here, the source follower circuit will be described. FIG. 5A is a circuit diagram of a source follower circuit 901 including a transistor M1 and a resistor element R1. The transistor M1 is an n-channel transistor. In the source follower circuit 901 shown in FIG. 5A, the source of the transistor M1 is electrically connected to one terminal of the resistor element R1. Also, VDD is supplied to the drain of the transistor M1, and VSS is supplied to the other terminal of the resistor element. The gate of the transistor M1 is electrically connected to the terminal IN, and an input voltage Vin is input via the terminal IN. The source of the transistor M1 is electrically connected to the terminal OUT, and an output voltage Vout is output via the terminal OUT.

[0092] The transistor constituting the source follower circuit needs to operate in the saturation region. Therefore, assuming that the threshold voltage of the transistor M1 is Vth, it is necessary to operate the transistor M1 under the condition that the relationship of Equation 1 is satisfied.

[0093]

Equation

[0094] Subsequently, the operation of the source follower circuit 901 will be described. Since the output voltage Vout is the source voltage of the transistor M1, the output voltage Vout is always approximately the voltage obtained by subtracting Vth from Vin. More precisely, the output voltage Vout changes so as to satisfy Equation 2.

[0095]

Equation

[0096] In Equation 2, μ n is the mobility, C OX is the gate capacitance, W is the channel width, L is the channel length, Vin is the voltage input via terminal IN (the gate voltage of transistor M1), Vth is the threshold voltage of transistor M1, and R1 is the resistance value of resistor element R1.

[0097] In source follower circuit 901, when the input voltage Vin changes, the output voltage Vout changes following the change in the input voltage Vin.

[0098] Next, consider the case where the input voltage Vin is constant and the input impedance of the load connected to terminal OUT fluctuates. Let the current flowing between the source and drain of transistor M1 be Id, the current flowing through resistor element R1 be Ir, and the voltage between the gate and source of transistor M1 (gate voltage) be Vgs.

[0099] When no load is connected to terminal OUT, Id and Ir are equal. When a load is connected to terminal OUT and the input impedance of the load decreases, a part of Id is supplied to the load and Ir decreases. Then, the voltage generated across resistor element R1 decreases. That is, Vout decreases.

[0100] On the other hand, the decrease in Vout means a decrease in the source potential of transistor M1. Thus, Vgs increases and Id increases. The increase in Id continues until approximately Vout = Vin - Vth. More precisely, the output voltage Vout increases until it satisfies Equation 2.

[0101] Also, when the input impedance of the load connected to terminal OUT increases, the current supplied to the load side decreases, so Ir flowing through resistor element R1 increases. Then, the voltage generated across resistor element R1 increases. That is, Vout increases.

[0102] On the other hand, the increase in Vout means the increase in the source potential of transistor M1. Thus, Vgs becomes smaller and Id decreases. The decrease in Id continues until approximately Vout = Vin - Vth. More precisely, the output voltage Vout decreases until it satisfies Equation 2.

[0103] In this way, the source follower circuit has the function of always supplying a constant voltage even when the input impedance of the load varies. That is, the source follower circuit has the function of performing power amplification (amplifying the current value without changing the output voltage).

[0104] Also, like the source follower circuit 902 shown in FIG. 5B, the resistor element R1 of the source follower circuit 901 can be replaced with a transistor M2. Transistor M2 is an n-channel transistor. Also in the source follower circuit 902, transistors M1 and M2 operate in the saturation region.

[0105] In the source follower circuit 902, the gate of transistor M1 is electrically connected to terminal IN1, and the gate of transistor M2 is electrically connected to terminal IN2. The drain of transistor M2 is electrically connected to terminal OUT. Also, a low power supply voltage VSS is supplied to the source of transistor M2.

[0106] The source follower circuit 902 also has the function of performing power amplification. In the source follower circuit 902, if the current flowing between the source and drain of transistor M1 operating in the saturation region is Id1, and the current flowing between the source and drain of transistor M2 operating in the saturation region is Id2, then Id1 can be expressed by Equation 3 and Id2 can be expressed by Equation 4.

[0107]

Equation

[0108] In Equation 3, μ n is the mobility, C OXCg is the gate capacitance, W is the channel width, L is the channel length, Vin1 is the voltage input via terminal IN1 (the gate voltage of transistor M1), and Vth1 is the threshold voltage of transistor M1.

[0109]

Number

[0110] In Equation 4, μ n is the mobility, C OX is the gate capacitance, W is the channel width, L is the channel length, Vin2 is the voltage input via terminal IN2 (the gate voltage of transistor M2), and Vth2 is the threshold voltage of transistor M2.

[0111] In source follower circuit 902, Id1 and Id2 are equal. In addition, when the configurations and transistor characteristics of transistor M1 and transistor M2 are equal, the output voltage Vout of source follower circuit 902 can be expressed by Equation 5.

[0112]

Number

[0113] Return to the description of the operation example of semiconductor device 100. FIG. 6 is a timing chart for explaining the operation of semiconductor device 100. FIGS. 7 and 8 are diagrams for explaining the operation states of semiconductor device 100.

[0114] In drawings and the like, there may be cases where symbols indicating potentials such as "VDD" or "VSS" (also referred to as "potential symbols") are marked adjacent to terminals and wirings. In addition, in order to make the potential changes of terminals and wirings easier to understand, the potential symbols appended to the terminals and wirings where potential changes have occurred may be marked with enclosed characters. In addition, an "×" symbol may be appended to a transistor in the off state.

[0115] 〔Data writing operation〕 Before the data writing operation is started, the potentials of terminals WW1 and WW2 are set to the L potential, and the potentials of terminals PS1, PS2, IN1, IN2, node SN1, node SN2, and terminal OUT are set to VSS. In this specification and the like, the potential at which a transistor can be turned off is referred to as the L potential. The L potential may be, for example, VSS, but does not mean a specific potential. Also, in this specification and the like, the potential at which a transistor can be turned on is referred to as the H potential. The H potential may be, for example, VDD, but does not mean a specific potential.

[0116] For example, in the case of two wirings, if it is described for each that "an L potential is supplied", the L potentials supplied to the two wirings may not be equal to each other. Similarly, in the case of two wirings, if it is described for each that "an H potential is supplied", the H potentials supplied to the two wirings may not be equal to each other.

[0117] In period T31, an H potential is supplied to terminals WW1 and WW2 to turn on transistors Tr11 and Tr21 (see Fig. 7A). Also, a voltage (Vdata + Vref) obtained by adding the reference voltage Vref (reference potential) to the data Vdata is supplied to node SN1 via terminal IN1 and transistor Tr11.

[0118] Also, the reference voltage Vref is supplied to node SN2 as Vin2 via terminal IN2 and transistor Tr21. Since transistor Tr22 needs to operate in the saturation region during the read operation, it is preferable that the reference voltage Vref is equal to or less than the threshold voltage Vth2 of transistor Tr22. When the transistor characteristics of transistor Tr12 and transistor Tr22 are the same, Vref = Vth1 = Vth2.

[0119] During period T32, supply an L potential to terminals WW1 and WW2 to turn off transistors Tr11 and Tr21 (see FIG. 7B). When transistor Tr11 is turned off, node SN1 becomes a floating state and the potential (charge) of node SN1 is held. When transistor Tr21 is turned off, node SN2 becomes a floating state and the potential (charge) of node SN2 is held.

[0120] 〔Data read operation〕 During period T41, supply VDD to terminal PS1. Then, a current flows from terminal PS1 through transistor Tr12, and charge is supplied to node BN. FIG. 8A shows the state immediately after the start of period T41.

[0121] When charge is supplied to node BN, the potential of node BN rises. In period T41, node SN1 is in a floating state and is capacitively coupled to node BN via capacitor element Cb1. Therefore, due to the bootstrap effect, the potential of node SN1 (also referred to as "Vsn1") also rises. Similarly, in period T41, node SN2 is in a floating state and node SN2 is capacitively coupled to node BN via capacitor element Cb2. Therefore, due to the bootstrap effect, the potential of node SN2 (also referred to as "Vsn2") also rises (see FIG. 8B).

[0122] Thus, semiconductor device 100 has a bootstrap circuit 120a including transistor Tr12 and capacitor element Cb1. Bootstrap circuit 120a has a function of boosting the potential of node SN1. Further, semiconductor device 100 has a bootstrap circuit 120b including transistor Tr22 and capacitor element Cb2. Bootstrap circuit 120b has a function of boosting the potential of node SN2.

[0123] In the semiconductor device 100, the potential of the node BN can be read as the output voltage Vout. The potential of the node BN (output voltage Vout) is a potential corresponding to the potential difference between the node SN1 and the node SN2. Also, the potential of the node BN (output voltage Vout) changes until it satisfies the above-mentioned Equation 5. Specifically, it changes until it becomes Vsn1 - Vsn2. Therefore, finally, the potential of the node BN (output voltage Vout) becomes Vdata.

[0124] At this time, it can be said that the transistor Tr22 is operating in the saturation region. Also, in order to operate the transistor Tr12 in the saturation region, the potential Vin1 supplied to the terminal IN1 during the write operation needs to satisfy Equation 6.

[0125]

Equation

[0126] Also, by setting the potential supplied to the terminal IN2 to VSS, Vin1 = Vdata can be achieved. For example, as shown in FIG. 9, one of the source or drain of the transistor Tr21 electrically connected to the terminal IN2 may be electrically connected to the terminal PS2 instead of the terminal IN2. By setting the potential supplied to the terminal IN2 to VSS, it is not necessary to add Vref to Vin1, so the drive circuit of the semiconductor device 100 can be made smaller. Therefore, the occupied area of the semiconductor device including the semiconductor device 100 can be reduced. Also, the design freedom of the semiconductor device is improved. Also, the reliability of the semiconductor device can be improved.

[0127] When the potential supplied to the terminal IN2 is set to VSS, Vdata needs to satisfy Equation 7.

[0128]

Equation

[0129] As described above, the semiconductor device 100 according to one aspect of the present invention has a function of holding analog data and a function of power-amplifying and outputting the held analog data. Since the held data is power-amplified at the time of reading, it is possible to eliminate the need for a power amplification circuit or the like used after data reading. Alternatively, the quantity or scale of the power amplification circuit can be reduced.

[0130] In addition, the semiconductor device 100 according to one aspect of the present invention can stably output (read) the held data even when the impedance of the load connected to the output terminal (terminal OUT) fluctuates. Note that the semiconductor device 100 according to one aspect of the present invention can hold not only analog data but also digital data.

[0131] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0132] (Embodiment 2) In this embodiment, a semiconductor device 400 having a storage device or a semiconductor device according to one aspect of the present invention will be described.

[0133] FIG. 10A shows a block diagram illustrating a configuration example of the semiconductor device 400. The semiconductor device 400 shown in FIG. 10A includes a drive circuit 410 and a memory array 420. The memory array 420 includes a plurality of semiconductor devices 100. The semiconductor device 100 functions as a memory cell. FIG. 10A shows an example in which the memory array 420 includes a plurality of semiconductor devices 100 arranged in a matrix.

[0134] The drive circuit 410 includes PSW241 (power switch), PSW242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412 (Control Circuit), and a voltage generation circuit 428.

[0135] In the semiconductor device 400, each circuit, each signal, and each voltage can be appropriately selected or discarded as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0136] Also, the signals BW, CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. Note that the signals PON1 and PON2 may be generated by the control circuit 412.

[0137] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit logically operates the signals CE, GW, and BW to determine the operation mode of the semiconductor device 400 (e.g., write operation, read operation). Alternatively, the control circuit 412 generates control signals for the peripheral circuit 411 so that this operation mode is executed.

[0138] The voltage generation circuit 428 has a function of generating a negative voltage. WAKE has a function of controlling the input to the voltage generation circuit 428 of CLK. For example, when a high-level signal is applied to WAKE, the signal CLK is input to the voltage generation circuit 428, and the voltage generation circuit 428 generates a negative voltage.

[0139] The peripheral circuit 411 is a circuit for writing and reading data to and from the semiconductor device 100. The peripheral circuit 411 includes a row decoder 441 (Row Decoder), a column decoder 442 (Column Decoder), a row driver 423 (Row Driver), a column driver 424 (Column Driver), an input circuit 425 (Input Cir.), and an output circuit 426 (Output Cir.). A sense amplifier or the like may be provided as necessary.

[0140] The row decoder 441 and the column decoder 442 have the function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying the row to be accessed, and the column decoder 442 is a circuit for specifying the column to be accessed. The row driver 423 has the function of selecting the wiring specified by the row decoder 441. The column driver 424 has functions such as writing data to the semiconductor device 100, reading data from the semiconductor device 100, and holding the read data.

[0141] The input circuit 425 has the function of holding the signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is the data (Din) to be written to the semiconductor device 100. The data (Dout) read by the column driver 424 from the semiconductor device 100 is output to the output circuit 426. The output circuit 426 has the function of holding Dout. Also, the output circuit 426 has the function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is the signal RDA.

[0142] PSW241 has a function of controlling the supply of VDD to the peripheral circuit 415. PSW242 has a function of controlling the supply of VHM to the row driver 423. Here, the high power supply voltage of the semiconductor device 400 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW241 is controlled by the signal PON1, and the on / off of PSW242 is controlled by the signal PON2. In FIG. 10A, in the peripheral circuit 415, the number of power supply domains to which VDD is supplied is set to 1, but it can also be plural. In this case, a power switch may be provided for each power supply domain.

[0143] The drive circuit 410 and the memory array 420 included in the semiconductor device 400 may be provided on the same plane. Also, as shown in FIG. 10B, the drive circuit 410 and the memory array 420 may be provided so as to overlap. By providing the drive circuit 410 and the memory array 420 so as to overlap, the signal propagation distance can be shortened.

[0144] Also, for the control circuit 412 included in the drive circuit 410 of the semiconductor device 400, an arithmetic processing device such as a CPU (Central Processing Unit) and / or a GPU (Graphics Processing Unit) may be used. By using a CPU and / or a GPU or the like, a semiconductor device 400 having an arithmetic processing function can be realized.

[0145] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0146] (Embodiment 3) In this embodiment, an example of an arithmetic processing device that can include the semiconductor device shown in the above embodiment will be described.

[0147] FIG. 11 shows a block diagram of the arithmetic processing device 1100. In FIG. 11, a configuration example of a CPU is shown as a configuration example that can be used for the arithmetic processing device 1100.

[0148] The arithmetic processing unit 1100 shown in FIG. 11 has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198), a cache 1199, and a cache interface 1189. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may have a rewritable ROM and a ROM interface. Also, the cache 1199 and the cache interface 1189 may be provided on a separate chip.

[0149] The cache 1199 is connected via the cache interface 1189 to a main memory provided on a separate chip. The cache interface 1189 has a function of supplying a part of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding the data.

[0150] The arithmetic processing unit 1100 shown in FIG. 11 is merely an example showing a simplified configuration thereof, and the actual arithmetic processing unit 1100 has various configurations depending on its use. For example, a configuration including the arithmetic processing unit 1100 or an arithmetic circuit shown in FIG. 11 may be used as one core, and a plurality of such cores may be included and each core may operate in parallel, that is, a configuration such as a GPU. Also, the number of bits that the arithmetic processing unit 1100 can handle with its internal arithmetic circuit and data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0151] Instructions input to the arithmetic processing unit 1100 via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0152] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, during program execution of the arithmetic processing unit 1100, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priorities and mask states. The register controller 1197 generates addresses for the registers 1196 and reads from and writes to the registers 1196 according to the state of the arithmetic processing unit 1100.

[0153] Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the various circuits described above.

[0154] In the arithmetic processing unit 1100 shown in FIG. 11, storage devices are provided in the registers 1196 and the cache 1199. As the storage device, for example, the semiconductor device 100 shown in the previous embodiment may be used.

[0155] In the arithmetic processing unit 1100 shown in FIG. 11, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cells of the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed. When holding data by a capacitive element is selected, data can be rewritten to the capacitive element, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0156] Note that the arithmetic processing unit 1100 is not limited to a CPU, and may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), or the like.

[0157] The semiconductor device 400 and the arithmetic processing unit 1100 shown in the above embodiment can be provided one on top of the other. FIGS. 12A and 12B show perspective views of the semiconductor device 1150A. The semiconductor device 1150A has the semiconductor device 400 that functions as a storage device on the arithmetic processing unit 1100. The arithmetic processing unit 1100 and the semiconductor device 400 have an overlapping area. To make the configuration of the semiconductor device 1150A easy to understand, in FIG. 12B, the arithmetic processing unit 1100 and the semiconductor device 400 are shown separately.

[0158] By providing the semiconductor device 400 and the arithmetic processing unit 1100 one on top of the other, the connection distance between the two can be shortened. Therefore, the communication speed between the two can be increased. Also, since the connection distance is short, the power consumption can be reduced.

[0159] In addition, a plurality of semiconductor devices 400 may be provided overlaid with the arithmetic processing unit 1100. FIGS. 13A and 13B show perspective views of the semiconductor device 1150B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the arithmetic processing unit 1100. The arithmetic processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions with each other. To clarify the configuration of the semiconductor device 1150B, in FIG. 13B, the arithmetic processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately.

[0160] The semiconductor devices 400a and 400b function as storage devices. For example, a NOR-type storage device may be used for one of the semiconductor devices 400a or 400b, and a NAND-type storage device may be used for the other. Both the semiconductor device 400a and the semiconductor device 400b may be NAND-type storage devices, or may be NOR-type storage devices. Examples of NOR-type storage devices include DRAM and SRAM. Since NOR-type storage devices can operate faster than NAND-type storage devices, for example, a part of the semiconductor device 400a can also be used as the main memory and / or cache 1199. Note that the overlapping order of the semiconductor device 400a and the semiconductor device 400b may be reversed.

[0161] FIGS. 14A and 14B show perspective views of the semiconductor device 1150C. The semiconductor device 1150C has a configuration in which the arithmetic processing unit 1100 is sandwiched between the semiconductor device 400a and the semiconductor device 400b. The arithmetic processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions with each other. To clarify the configuration of the semiconductor device 1150C, in FIG. 14B, the arithmetic processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately.

[0162] By adopting the configuration of the semiconductor device 1150C, both the communication speed between the semiconductor device 400a and the arithmetic processing unit 1100 and the communication speed between the semiconductor device 400b and the arithmetic processing unit 1100 can be increased. Also, the power consumption can be reduced compared to the semiconductor device 1150B.

[0163] A semiconductor device according to one aspect of the present invention can be used for an artificial neural network. Hereinafter, a configuration example of the artificial neural network will be described.

[0164] FIG. 15A shows a configuration example of a neural network NN. The neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units). Note that the intermediate layer HL may be one layer or two or more layers. A neural network having two or more intermediate layers HL can also be called a DNN (Deep Neural Network), and learning using a deep neural network can also be called deep learning.

[0165] Input data is input to each neuron in the input layer IL, output signals of neurons in the previous layer or the next layer are input to each neuron in the intermediate layer HL, and output signals of neurons in the previous layer are input to each neuron in the output layer OL. Note that each neuron may be connected to all neurons in the previous and next layers (fully connected) or may be connected to some neurons.

[0166] FIG. 15B shows an example of an operation by a neuron. Here, a neuron N and two neurons in the previous layer that output signals to the neuron N are shown. To the neuron N, the output x 1 of the neuron in the previous layer and the output x 2 of the neuron in the previous layer are input. Then, in the neuron N, the sum x 1 of the multiplication result (x 1 w 1 ) of the output x 1 and the weight w 2 and the multiplication result (x 2 w 2 ) of the output x 2 and the weight w 1 w 1 +x 2 w 2 is calculated, and then a bias b is added as necessary, and the value a = x1 w 1 +x 2 w 2 +b is obtained. Then, the value a is converted by the activation function h, and the output signal y = h(a) is output from the neuron N.

[0167] Thus, the operation by the neuron includes an operation of adding the product of the output of the neuron in the previous layer and the weight, that is, a sum-of-products operation (the above x 1 w 1 +x 2 w 2 ). This sum-of-products operation may be performed on software using a program, or may be performed by hardware. When performing the sum-of-products operation by hardware, a sum-of-products operation circuit can be used. As this sum-of-products operation circuit, a digital circuit or an analog circuit may be used. When an analog circuit is used for the sum-of-products operation circuit, it is possible to reduce the circuit scale of the sum-of-products operation circuit, or improve the processing speed and reduce the power consumption by reducing the number of accesses to the memory.

[0168] Also, when an analog circuit is used for the sum-of-products operation circuit, analog data is used as weight information. The semiconductor device 100 according to one aspect of the present invention can hold analog data without converting it into a digital value. Therefore, conversion circuits such as a DAC (Digital to Analog Converter) and / or an ADC (Analog to Digital Converter) can be reduced, and reduction of power consumption and occupied area can be realized.

[0169] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0170] (Embodiment 4) In this embodiment, a configuration example of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked and provided will be described. By adopting such a configuration, the degree of freedom in the design of the semiconductor device can be increased. Further, by stacking and providing transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0171] A part of the cross-sectional structure of the semiconductor device is shown in FIG. 16. The semiconductor device shown in FIG. 16 includes a transistor 550, a transistor 500, and a capacitor element 600. FIG. 17A is a top view of the transistor 500. FIG. 17B is a cross-sectional view taken along the portion L1-L2 indicated by the dashed-dotted line in FIG. 17A, and is a cross-sectional view of the transistor 500 in the channel length direction. FIG. 17C is a cross-sectional view taken along the portion W1-W2 indicated by the dashed-dotted line in FIG. 17A, and is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to the OS transistor included in the semiconductor device 100 shown in the above embodiment, that is, a transistor having an oxide semiconductor in the channel formation region. Further, the transistor 550 corresponds to the Si transistor included in the drive circuit 410 shown in the above embodiment, that is, a transistor having silicon in the channel formation region.

[0172] The transistor 500 is an OS transistor. The OS transistor has an extremely small off-current. Therefore, it is possible to hold the data voltage or charge written to the storage node via the transistor 500 for a long period of time. That is, since the refresh operation frequency of the storage node is reduced or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

[0173] In FIG. 16, the transistor 500 is provided above the transistor 550, and the capacitor element 600 is provided above the transistor 550 and the transistor 500.

[0174] The transistor 550 is provided on the substrate 371. The substrate 371 is, for example, a p-type silicon substrate. The substrate 371 may also be an n-type silicon substrate. The oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed by a buried oxide in the substrate 371, for example, silicon oxide. The transistor 550 is provided on a single-crystal silicon, so-called SOI (Silicon On Insulator) substrate provided on the substrate 371 via the oxide layer 374.

[0175] In the SOI substrate, an insulator 373 that functions as an element isolation layer is provided on the substrate 371. The substrate 371 also has a well region 372. The well region 372 is a region imparted with n-type or p-type conductivity according to the conductivity type of the transistor 550. In the single-crystal silicon in the SOI substrate, a semiconductor region 375, low-resistance regions 376a and 376b that function as a source region or a drain region are provided. Further, a low-resistance region 376c is provided on the well region 372.

[0176] The transistor 550 can be provided overlapping a well region 372 doped with an impurity element that imparts conductivity. The well region 372 can function as the bottom gate electrode of the transistor 550 by independently changing the potential via the low-resistance region 376c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 372, the threshold voltage of the transistor 550 can be made larger and the off-current can be reduced. Therefore, by applying a negative potential to the well region 372, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be made smaller. As a result, the power consumption based on the through-current or the like in the arithmetic circuit having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0177] The transistor 550 is preferably of a so-called Fin type in which the upper surface of the semiconductor layer and the side surfaces in the channel width direction are covered with the conductor 378 via the insulator 377. By making the transistor 550 of the Fin type, the effective channel width increases, thereby improving the on characteristics of the transistor 550. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 550 can be improved.

[0178] Note that the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.

[0179] The conductor 378 may function as a first gate (also referred to as a top gate) electrode. Further, the well region 372 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the potential applied to the well region 372 can be controlled via the low resistance region 376c.

[0180] In the region where the channel of the semiconductor region 375 is formed, the region in the vicinity thereof, the source region, or the drain region, the low resistance regions 376a and 376b, and the low resistance region 376c connected to the electrode for controlling the potential of the well region 372, etc., it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs, etc., the transistor 550 may be a HEMT.

[0181] The well region 372, the low resistance regions 376a, 376b, and 376c include elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor region 375.

[0182] The conductor 378 that functions as a gate electrode can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a conductive material such as a metal oxide material. Further, the conductor 378 may use a silicide such as nickel silicide.

[0183] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0184] The low-resistance regions 376a, 376b, and 376c may be configured by laminating another conductor, for example, a silicide such as nickel silicide. By adopting such a configuration, the conductivity of the region that functions as an electrode can be enhanced. Further, at this time, an insulator that functions as a sidewall spacer (also referred to as a sidewall insulating layer) may be provided on the side surface of the conductor 378 that functions as a gate electrode and on the side surface of the insulator that functions as a gate insulating film. By adopting such a configuration, it is possible to prevent the conductor 378 and the low-resistance regions 376a and 376b from being in a conductive state.

[0185] Over the transistor 550, an insulator 379, an insulator 381, an insulator 383, and an insulator 385 are sequentially laminated and provided.

[0186] As the insulator 379, the insulator 381, the insulator 383, and the insulator 385, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0187] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0188] The insulator 381 may function as a planarization film that planarizes a step formed by a transistor 550 or the like provided thereunder. For example, the upper surface of the insulator 381 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0189] Further, for the insulator 383, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 371 or the transistor 550 or the like into the region where the transistor 500 is provided.

[0190] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0191] The amount of hydrogen desorption can be analyzed using, for example, temperature programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 383 is such that in TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, per unit area of the insulator 383, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2The following may be sufficient.

[0192] Note that the insulator 385 preferably has a lower dielectric constant than the insulator 383. For example, the relative dielectric constant of the insulator 385 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 385 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 383. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0193] In addition, the capacitor element 600, or conductors 328 and 330 connected to the transistor 500, etc. are embedded in the insulators 379, 381, 383, and 385. Note that the conductors 328 and 330 have the function of plugs or wirings. Also, conductors having the function of plugs or wirings may be given the same reference numeral for a plurality of configurations. Also, in this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0194] As the material of each plug and wiring (conductors 328, 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used singly or in a laminated manner. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferably formed of a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0195] A wiring layer may be provided on the insulator 385 and the conductor 330. For example, in FIG. 16, the insulators 350, 352, and 354 are stacked in order. Further, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug connected to the transistor 550 or as a wiring. Note that the conductor 356 can be provided using the same material as the conductors 328 and 330.

[0196] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350 as in the case of the insulator 383. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0197] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, the diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0198] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 16, the insulators 360, 362, and 364 are stacked in order. Further, a conductor 366 is formed in the insulators 360, 362, and 364. The conductor 366 functions as a plug or as a wiring. Note that the conductor 366 can be provided using the same material as the conductors 328 and 330.

[0199] Note that, for example, as with insulator 383, it is preferable to use an insulator having a barrier property against hydrogen for insulator 360. Further, conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of insulator 360 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0200] A wiring layer may be provided on insulator 364 and conductor 366. For example, in FIG. 16, insulators 370, 369, and 368 are sequentially stacked and provided. Further, conductor 376 is formed in insulators 370, 369, and 368. Conductor 376 has a function as a plug or wiring. Note that conductor 376 can be provided using the same material as conductors 328 and 330.

[0201] Note that, for example, as with insulator 383, it is preferable to use an insulator having a barrier property against hydrogen for insulator 370. Further, conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of insulator 370 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0202] A wiring layer may be provided on insulator 368 and conductor 376. For example, in FIG. 16, insulators 380, 382, and 384 are sequentially stacked and provided. Further, conductor 386 is formed in insulators 380, 382, and 384. Conductor 386 has a function as a plug or wiring. Note that conductor 386 can be provided using the same material as conductors 328 and 330.

[0203] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 383. Further, the conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0204] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or may be five or more.

[0205] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked and provided. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 preferably uses a material having a barrier property against oxygen and hydrogen.

[0206] For example, for the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property against hydrogen and impurities from, for example, the substrate 371 or the region where the transistor 550 is provided to the region where the transistor 500 is provided. Therefore, a material similar to the insulator 383 can be used.

[0207] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor device having an oxide semiconductor such as transistor 500, the characteristics of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between transistor 500 and transistor 550.

[0208] Also, as a film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulator 510 and insulator 514.

[0209] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxide constituting transistor 500. Therefore, it is suitable to be used as a protective film for transistor 500.

[0210] Also, for example, the same materials as insulator 379 can be used for insulator 512 and insulator 516. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as insulator 512 and insulator 516.

[0211] Also, conductor 518 and conductors (for example, conductor 503) constituting transistor 500 are embedded in insulator 510, insulator 512, insulator 514, and insulator 516. Note that conductor 518 has a function as a capacitor element 600, a plug connected to transistor 550, or a wiring. Conductor 518 can be provided using the same materials as conductor 328 and conductor 330.

[0212] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0213] Above the insulator 516, the transistor 500 is provided.

[0214] As shown in FIGS. 17A to 17C, the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 disposed on the bottom surface and the side surface of the opening, and a conductor 560 disposed on the formation surface of the insulator 545.

[0215] Also, as shown in FIGS. 17B and 17C, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Also, as shown in FIGS. 17A to 17C, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 17B and 17C, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.

[0216] Note that in this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0217] Note that in the transistor 500, a configuration in which two layers of the oxide 530a and the oxide 530b are laminated in the region where the channel is formed and in its vicinity is shown, but the present invention is not limited to this. For example, a single layer of the oxide 530b or a laminated configuration of three or more layers may be provided.

[0218] Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated configuration, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer configuration or a laminated configuration of three or more layers. Also, the transistor 500 shown in FIGS. 16, 17A, and 17C is an example, and the present invention is not limited to its configuration, and an appropriate transistor may be used according to the circuit configuration and / or driving method.

[0219] Here, the conductor 560 functions as the gate electrode of the transistor 500, and the conductors 542a and 542b function as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-alignedly selected with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, and the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

[0220] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have an overlapping region with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Thus, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0221] The conductor 560 may function as a first gate (also referred to as a gate or a top gate) electrode. Also, the conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0 V than when no negative potential is applied.

[0222] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected and can cover the channel formation region formed in the oxide 530.

[0223] In this specification and the like, a configuration of a transistor in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. Also, the S-channel configuration disclosed in this specification and the like is different from the Fin type configuration and the planar type configuration. By adopting the S-channel configuration, the resistance to the short channel effect can be enhanced, in other words, a transistor in which the short channel effect hardly occurs can be obtained.

[0224] Further, the conductor 503 has the same configuration as the conductor 518. A conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is further formed inside. Note that, in the transistor 500, a configuration in which the conductor 503a and the conductor 503b are laminated is shown, but the present invention is not limited to this. For example, the conductor 503 may be provided in a single-layer or a laminated configuration of three or more layers.

[0225] Here, it is preferable to use a conductive material for the conductor 503a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use a conductive material for the conductor 503a that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that, in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0226] For example, by having the function of suppressing the diffusion of oxygen in the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0227] Further, when the conductor 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b. Note that, in this embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer configuration.

[0228] The insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.

[0229] Here, it is preferable to use an insulator 524 in contact with the oxide 530 that contains more oxygen than the oxygen that satisfies the stoichiometric composition. The oxygen is likely to be released from the film by heating. In this specification and the like, the oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. When hydrogen enters the oxygen vacancies in the oxide 530, the defect (hereinafter, may be referred to as V O H) may function as a donor, and electrons as carriers may be generated. Also, a part of the hydrogen may combine with the oxygen that binds to the metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Also, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the oxide 530 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to fill the oxygen vacancies (also referred to as "oxygen addition treatment"). By using an oxide semiconductor in which impurities such as V O H are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0230] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which some oxygen is desorbed by heating. The oxide that desorbs oxygen by heating means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0231] Further, the insulator having the excess oxygen region and the oxide 530 may be subjected to any one or more of heat treatment, microwave treatment, or RF treatment in contact with each other. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction in which the bond of VoH is broken occurs, in other words, a reaction of "V O H→Vo+H" occurs, and dehydrogenation can be performed. A part of the hydrogen generated at this time may be removed as H 2 O from the oxide 530 or the insulator near the oxide 530 by combining with oxygen. Also, a part of the hydrogen may be gettered by the conductor 542a and the conductor 542b.

[0232] Also, the above microwave treatment is preferably carried out using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Further, the above microwave treatment may be carried out at a pressure of 133 Pa or more, preferably 200 Pa or more, more preferably 400 Pa or more. Further, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O 2 / (O 2 +Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0233] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be carried out, for example, at 100 °C or more and 450 °C or less, more preferably 350 °C or more and 400 °C or less. The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably carried out in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O ). The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously carried out in an atmosphere of nitrogen gas or an inert gas.

[0234] By subjecting the oxide 530 to an oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired with the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H 2 O. As a result, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with the oxygen vacancies to form V O H.

[0235] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0236] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, so that the oxygen in the oxide 530 does not diffuse to the insulator 520 side. Also, it is possible to suppress the reaction of the conductor 503 with the oxygen in the insulator 524 and / or the oxide 530.

[0237] The insulator 522 is preferably a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0238] In particular, an insulator containing one or both oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (wherein oxygen is difficult to permeate), may be used. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0239] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated and used on the above insulators.

[0240] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining the insulator of the high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0241] In the transistor 500 of FIGS. 17A to 17C, the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer laminated structure, but the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0242] The transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0243] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0244] Also, for the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use a metal oxide having a band gap of preferably 2 eV or more, more preferably 2.5 eV or more. Thus, by using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0245] The oxide 530 has the oxide 530a under the oxide 530b, so that the diffusion of impurities from the constituent formed below the oxide 530a to the oxide 530b can be suppressed.

[0246] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0247] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0248] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is preferable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0249] Specifically, by having a common element (as the main component) other than oxygen in the oxide 530a and the oxide 530b, a mixed layer with a low density of defect energy levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0250] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0251] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc. are preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0252] In addition, in FIG. 17B, although the conductors 542a and 542b are shown as a single-layer structure, they may also have a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0253] In addition, there is a three-layer structure in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film is provided, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, and the like. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0254] As shown in FIG. 17B, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0255] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0256] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided to cover the side surface of the oxide 530 and contact the insulator 524.

[0257] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, silicon oxynitride or silicon nitride can also be used as the insulator 544.

[0258] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent process. When the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material that does not significantly decrease in conductivity even when absorbing oxygen, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0259] By having the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the oxide 530b. In addition, it is possible to suppress the oxidation of the conductor 542 due to the excess oxygen of the insulator 580.

[0260] The insulator 545 functions as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excessive amount of oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0261] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they are stable against heat.

[0262] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less. Also, the microwave treatment described above may be performed before and / or after the formation of insulator 545.

[0263] Further, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from insulator 545 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0264] Note that insulator 545 may have a stacked structure, similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0265] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 17B and 17C, but it may be a single-layer structure or a laminated structure of three or more layers.

[0266] It is preferable to use a conductive material for the conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By having the function of suppressing the diffusion of oxygen, the conductor 560b can be prevented from being oxidized by the oxygen contained in the insulator 545 and the conductivity from decreasing. As the conductive material having the function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Further, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0267] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, since the conductor 560b also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0268] Insulator 580 is provided on conductor 542a and conductor 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, as insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, or resin, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide with pores are preferable because an excess oxygen region can be easily formed in a later process.

[0269] Insulator 580 preferably has an excess oxygen region. By providing insulator 580 that releases oxygen upon heating, oxygen in insulator 580 can be efficiently supplied to oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in insulator 580 is reduced.

[0270] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b. Thereby, conductor 560 is formed to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0271] When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of conductor 560 from decreasing. Therefore, if the film thickness of conductor 560 is increased, conductor 560 can have a high aspect ratio shape. In the present embodiment, since conductor 560 is provided to be embedded in the opening of insulator 580, even if conductor 560 has a high aspect ratio shape, it can be formed without collapsing conductor 560 during the process.

[0272] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0273] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0274] In particular, aluminum oxide has high barrier properties, and even a thin film with a thickness of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0275] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0276] Also, conductors 540a and 540b are disposed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductors 546 and 548 described later.

[0277] An insulator 582 is provided on the insulator 581. It is preferable to use a material that is barrier - resistant to oxygen and hydrogen for the insulator 582. Therefore, the same material as that of the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0278] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture which are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the intrusion of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0279] Also, an insulator 586 is provided on the insulator 582. The same material as that of the insulator 379 can be used for the insulator 586. Further, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film or a silicon oxynitride film can be used.

[0280] Also, conductors 546, 548, etc. are embedded in the insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0281] The conductors 546 and 548 function as plugs connected to the capacitor element 600, the transistor 500, or the transistor 550, or as wirings. The conductors 546 and 548 can be provided using the same materials as the conductors 328 and 330.

[0282] Also, after forming the transistor 500, an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening. By enclosing the transistor 500 with the above-described insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively enclosed with an insulator having a high barrier property against hydrogen or water. When forming an opening so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the above-described insulator having a high barrier property is formed so as to be in contact with the insulator 522 or the insulator 514. This is preferable because it can also serve as part of the manufacturing process of the transistor 500. As the insulator having a high barrier property against hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 may be used.

[0283] Subsequently, a capacitor element 600 is provided above the transistor 500. The capacitor element 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0284] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor element 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0285] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0286] In the present embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the present invention is not limited to this configuration, and a laminated configuration of two or more layers may be used. For example, a conductor having barrier properties, and a conductor having high adhesiveness to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0287] The conductor 620 is provided so as to overlap the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when formed simultaneously with other components such as a conductor, Cu (copper) or Al (aluminum), which is a low-resistance metal material, may be used.

[0288] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be formed using the same material as the insulator 379. Further, the insulator 640 may function as a planarization film that covers the uneven shape thereunder.

[0289] By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0290] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0291] (Embodiment 5) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0292] The metal oxide preferably contains one of indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0293] (Classification of crystal structure) First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 18A. FIG. 18A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0294] As shown in FIG. 18A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, "Crystal" includes single crystal and poly crystal.

[0295] Note that the structure within the thick frame shown in FIG. 18A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" or completely different from "Crystal".

[0296] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 18B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 18B is simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 18B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 18B is 500 nm.

[0297] As shown in Fig. 18B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating distinct crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in Fig. 18B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0298] Also, the crystal structure of the film or the substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 18C. Fig. 18C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in Fig. 18C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0299] As shown in Fig. 18C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0300] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from Fig. 18A. For example, oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Also, non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0301] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0302] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. Here, the specific direction means the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor having c-axis orientation and no clear orientation in the a-b plane direction.

[0303] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0304] Also, in an In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Here, indium and element M are mutually substitutable. Thus, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0305] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0306] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0307] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0308] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and carriers are likely to be trapped, causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that to form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0309] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that CAAC-OS is less likely to have a reduction in electron mobility due to crystal grain boundaries. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation and defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0310] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0311] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0312] [[Configuration of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material composition.

[0313] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. Hereinafter, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0314] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0315] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0316] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0317] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0318] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0319] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching operation can be realized.

[0320] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0321] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0322] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0323] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less than, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced, and the density of defect levels may be reduced. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0324] In addition, since the density of defect levels of an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic is low, the density of trap levels may also be low.

[0325] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0326] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0327] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0328] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×1017 atoms / cm 3 Shall be as follows.

[0329] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0330] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0331] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thereby forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / cm 3 less than.

[0332] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0333] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0334] (Embodiment 6) In this embodiment, an example of a semiconductor wafer on which a semiconductor device or the like described in the above embodiment is formed and an example of an electronic component in which the semiconductor device is incorporated are shown.

[0335] <Semiconductor Wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 19A.

[0336] The semiconductor wafer 4800 shown in Fig. 19A has a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion without the circuit portions 4802 is a spacing 4803, which is an area for dicing.

[0337] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the side opposite to the side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warping of the wafer 4801 and the like can be reduced, and miniaturization as a component can be achieved.

[0338] As the next process, a dicing process is performed. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. Note that the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular in order to facilitate the dicing process.

[0339] By performing the dicing process, a chip 4800a as shown in Fig. 19B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, circuit portions 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately equal to the kerf of the scribe line SCL1 or the kerf of the scribe line SCL2.

[0340] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 19A. For example, a semiconductor wafer having a rectangular shape may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0341] <Electronic component> FIG. 19C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 19C has a chip 4800a in a mold 4711. As the chip 4800a, a storage device or the like according to one aspect of the present invention can be used.

[0342] FIG. 19C omits a part in order to show the inside of the electronic component 4700. The electronic component 4700 has lands 4712 outside the mold 4711. The lands 4712 are electrically connected to electrode pads 4713, and the electrode pads 4713 are electrically connected to the chip 4800a by wires 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0343] FIG. 19D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 4730, an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

[0344] As the semiconductor device 4710, for example, a chip 4800a, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), or the like can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device can be used.

[0345] The package substrate 4732 can use a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 4731 can use a silicon interposer, a resin interposer, or the like.

[0346] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Further, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate". Further, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. In the case of a silicon interposer, a TSV (Through Silicon Via) can also be used as the through electrode.

[0347] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult in the case of a resin interposer.

[0348] In HBM, it is necessary to connect many wirings in order to realize a wide memory bandwidth. For this reason, fine and high-density wiring formation is required for the interposer on which HBM is mounted. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0349] In addition, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer is less likely to occur. Also, since the silicon interposer has high surface flatness, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0350] Further, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0351] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 19D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix shape at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix shape at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0352] The electronic component 4730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0353] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0354] (Embodiment 7) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described.

[0355] A semiconductor device according to one aspect of the present invention can be applied to, for example, a storage device of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game machines, etc.). It can also be used for image sensors, IoT (Internet of Things), healthcare, etc. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale computers such as server systems.

[0356] An example of an electronic device having a semiconductor device according to one aspect of the present invention will be described. FIGS. 20A to 20J and FIGS. 21A to 21E illustrate how the electronic component 4700 or the electronic component 4730 having the semiconductor device is included in each electronic device.

[0357] [Mobile phone] The information terminal 5500 shown in FIG. 20A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0358] By applying a semiconductor device according to one aspect of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated during the execution of an application.

[0359] [Wearable terminal] In addition, FIG. 20B shows an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.

[0360] Similar to the aforementioned information terminal 5500, the wearable terminal can hold temporary files generated during the execution of an application by applying the semiconductor device according to one aspect of the present invention.

[0361] [Information Terminal] In addition, FIG. 20C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0362] Similar to the aforementioned information terminal 5500, the desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the semiconductor device according to one aspect of the present invention.

[0363] In the above description, smartphones, wearable terminals, and desktop information terminals are illustrated in FIGS. 20A to 20C as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0364] [Household Appliance] In addition, FIG. 20D shows an electric refrigerator-freezer 5800 as an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0365] The semiconductor device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can transmit and receive information such as food stored in the electric refrigerator 5800 and the expiration date of the food to and from an information terminal or the like through the Internet or the like. The electric refrigerator 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.

[0366] In this example, an electric refrigerator has been described as an electrical appliance. Other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, and the like.

[0367] [Game console] Also, FIG. 20E shows a portable game console 5200 which is an example of a game console. The portable game console 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0368] Furthermore, FIG. 20F shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 20F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like. In addition, the shape of the controller 7522 is not limited to the shape shown in FIG. 20F, and the shape of the controller 7522 may be variously changed according to the genre of the game. For example, in a shooting game such as a first-person shooter (FPS), a controller in the shape of a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller in the shape of a musical instrument or a music device can be used. Furthermore, the stationary game machine may be configured to be operated by a gesture and / or voice of a game player, instead of using a controller, and may be provided with a camera, a depth sensor, a microphone, and the like.

[0369] In addition, the video of the game machine described above can be output by a display device such as a television apparatus, a personal computer display, a game display, or a head-mounted display.

[0370] By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, a low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized. In addition, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence of the heat generation on the circuit itself, peripheral circuits, and modules can be minimized.

[0371] Furthermore, by applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, it is possible to hold a temporary file or the like necessary for calculations generated during the execution of the game.

[0372] As an example of a game machine, a portable game machine is shown in FIG. 20E. Also, a home stationary game machine is shown in FIG. 20F. Note that the electronic device according to one aspect of the present invention is not limited to this. Examples of the electronic device according to one aspect of the present invention include, for example, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), a pitching machine for batting practice installed in a sports facility, and the like.

[0373] [Mobile body] The semiconductor device described in the above embodiment can be applied to an automobile, which is a mobile body, and the periphery of the driver's seat of the automobile.

[0374] FIG. 20G shows an automobile 5700, which is an example of a mobile body.

[0375] Around the driver's seat of the automobile 5700, there is an instrument panel that provides various information by displaying a speedometer, a tachometer, the driving distance, a fuel gauge, the gear state, the air conditioner settings, and the like. Also, a display device for indicating those information may be provided around the driver's seat.

[0376] In particular, the display device can supplement the field of vision blocked by a pillar or the like, the blind spot of the driver's seat, etc. by projecting the video from an imaging device (not shown) provided in the automobile 5700, and can improve safety. That is, by displaying the image from the imaging device provided outside the automobile 5700, the blind spot can be supplemented and safety can be improved.

[0377] Since the semiconductor device described in the above embodiment can temporarily hold information, for example, the computer can be used to hold necessary temporary information in an automatic driving system of an automobile 5700, a system that performs road guidance, danger prediction, etc. The display device may be configured to display temporary information such as road guidance and danger prediction. Further, it may be configured to hold the video of a driving recorder provided in the automobile 5700.

[0378] Note that in the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc.

[0379] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0380] FIG. 20H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0381] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, since heat generation from the circuit can be reduced due to low power consumption, the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

[0382] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0383] FIG. 20I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0384] When recording the video taken by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can hold temporary files generated during encoding.

[0385] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0386] FIG. 20J is a schematic cross-sectional view showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0387] The ICD body 5400 is implanted into the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0388] The ICD main body 5400 has the function as a pacemaker and performs pacing on the heart when the heart rate goes out of the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia or ventricular fibrillation), treatment by electric shock is performed.

[0389] In order to appropriately perform pacing and electric shock, the ICD main body 5400 needs to constantly monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store data on the heart rate acquired by the sensor etc., the number of times and time of treatment by pacing, etc. in the electronic component 4700.

[0390] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, by having a plurality of batteries in the ICD main body 5400, the safety can be enhanced. Specifically, even if some of the batteries of the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0391] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activity may be configured such that physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.

[0392] [Expansion device for PC] The semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0393] FIG. 21A shows an expansion device 6100 that can be carried and is externally attached to a PC and equipped with a chip capable of storing information as an example of the expansion device. The expansion device 6100 can store information by the chip by connecting to the PC via, for example, a USB (Universal Serial Bus). Note that FIG. 21A illustrates the expansion device 6100 in a portable form, but the expansion device according to an aspect of the present invention is not limited thereto, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0394] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. A circuit for driving a semiconductor device or the like described in the above embodiment is provided on the substrate 6104. For example, an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0395] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0396] FIG. 21B is a schematic diagram of the appearance of an SD card, and FIG. 21C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a writing circuit, a load driver, a reading circuit, etc. provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0397] By providing the electronic component 4700 also on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data of the electronic component 4700 can be read and written.

[0398] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0399] FIG. 21D is a schematic diagram of the appearance of the SSD, and FIG. 21E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, etc. Note that the circuit configurations of each of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a memory that functions as a work memory may also be provided in the controller chip 5156.

[0400] [Computer] The computer 5600 shown in FIG. 22A is an example of a large computer. A plurality of rack-mounted computers 5620 are stored in a rack 5610 in the computer 5600.

[0401] The computer 5620 can have, for example, the configuration of the perspective view shown in FIG. 22B. In FIG. 22B, the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are respectively connected to the motherboard 5630.

[0402] The PC card 5621 shown in Fig. 22C is an example of a processing board equipped with a CPU, GPU, semiconductor devices, etc. The PC card 5621 has a board 5622. The board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Although Fig. 22C shows semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, for those semiconductor devices, the descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below may be referred to.

[0403] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe, etc.

[0404] The connection terminals 5623, 5624, and 5625 can be used as interfaces for, for example, supplying power to and inputting signals to the PC card 5621. Also, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Also, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark), etc.

[0405] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminals into sockets (not shown) provided on the board 5622.

[0406] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0407] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5628 include semiconductor devices. For example, the electronic component 4700 can be used as the semiconductor device 5628.

[0408] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0409] By using the semiconductor device according to one aspect of the present invention in the above various electronic devices and the like, miniaturization, high speed, or low power consumption of the electronic device can be achieved. In addition, since the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to the heat generation can be reduced. Further, by using the semiconductor device according to one aspect of the present invention, an electronic device with stable operation even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0410] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

Example

[0411] The operation of the semiconductor device 100 described in FIG. 1A was verified using a circuit simulator. The circuit simulator used SmartSpice from SILVACO.

[0412] As verification conditions, for transistors Tr11 and Tr21, an OS transistor with a channel length and width of 60 nm each was assumed. Also, for transistors Tr12 and Tr22, a Si transistor with a channel length and width of 1 μm each was assumed. Further, the capacitance values of capacitors Cb1 and Cb2 were each set to 1 pF. Also, VSS was set to 0.0 V and VDD was set to 6.0 V.

[0413] Vin1 held at node SN1 was assumed to have five levels (0.9 V, 1.1 V, 1.3 V, 1.5 V, 1.7 V), and Vref held at node SN2 was assumed to have two levels (0.0 V, 0.7 V). The output voltage Vout for all combinations was calculated using a circuit simulator. Each of the five levels of Vin1 satisfies the mathematical formulas 6 and 7 shown in the above embodiment.

[0414] The calculation results are shown in FIGS. 23A and 23B. The vertical axis in FIGS. 23A and 23B indicates the output voltage Vout, and the horizontal axis indicates time. In this embodiment, it is assumed that the writing operation described in the above embodiment has ended at time 0.0 μs. More specifically, it is assumed that the period T32 described in the above embodiment has ended and the potentials of nodes SN1 and SN2 are being held.

[0415] FIG. 23A shows the output voltage Vout for each level of Vin1 when Vref is 0.7 V. FIG. 23B shows the output voltage Vout for each level of Vin1 when Vref is 0.0 V.

[0416] Until time 0.5 μs, VSS is supplied to terminals PS1 and PS2 in the semiconductor device 100. When time reaches 0.5 μs, the read operation starts. During the read operation, VDD is supplied to terminal PS1 and the output voltage Vout is supplied to terminal OUT.

[0417] The calculation results of the source-drain voltage Vds_Tr12 of the transistor Tr12 after the start of the read operation are shown in FIG. 24. Since the potential of the node BN is VSS (0.0 V) until immediately before the start of the read operation, Vds_Tr12 is approximately 6 V immediately after the potential of the terminal PS1 changes from VSS to VDD (6.0 V).

[0418] Also, since Vin1 is equal to or higher than the threshold voltage of the transistor Tr12, when the potential of the terminal PS1 becomes VDD, a current flows between the source and drain of the transistor Tr12, and the potential of the node BN rises. The current flowing between the source and drain of the transistor Tr12 is larger as Vin1 is larger. Therefore, the potential of the node BN rises as Vin1 is larger. That is, Vds_Tr12 becomes smaller as Vin1 is larger. As a result, when Vref is constant, Vout becomes larger as Vin1 is larger.

[0419] Also, FIGS. 23A and 23B show that a voltage corresponding to Equation 5 described in the above embodiment can be obtained as the output voltage Vout. In this embodiment, Vin2 included in Equation 5 corresponds to Vref.

[0420] FIG. 25 is a graph showing the relationship between Vin1 and Vout calculated by a circuit simulator. In the figure, circles (“〇”) indicate the relationship between Vin1 and Vout when Vref is 0.0 V, and squares (“□”) indicate the relationship between Vin1 and Vout when Vref is 0.7 V.

[0421] Also, in FIG. 25, approximate straight lines 851 and 852 are added. The approximate straight line 851 is the approximate straight line of the above-described circles (“〇”), and approximates the relationship between Vin1 and Vout when Vref is 0.0 V. The approximate straight line 852 is the approximate straight line of the above-described squares (“□”), and approximates the relationship between Vin1 and Vout when Vref is 0.7 V. The coefficient of determination R 2 (contribution rate) is 0.9966, and the coefficient of determination R 2(Contribution rate) was 0.9955. From this, it can be seen that when Vref is constant, the output voltage Vout changes in response to the change in Vin1.

[0422] Through verification by a circuit simulator, it was found that in the semiconductor device 100 according to one aspect of the present invention, when Vref is constant, the output voltage Vout changes in response to the change in Vin1. Also, it was found that the semiconductor device 100 according to one aspect of the present invention can accurately read out the analog data it holds.

Explanation of Signs

[0423] 100: Semiconductor device, 110a: Holding circuit, 110b: Holding circuit, 120a: Bootstrap circuit, 120b: Bootstrap circuit, 130: Source follower circuit, Tr11: Transistor, Tr12: Transistor, Tr21: Transistor, Tr22: Transistor, SN1: Node, SN2: Node, BN: Node, Cb1: Capacitor element, Cb2: Capacitor element, IN1: Terminal, IN2: Terminal, PS1: Terminal, PS2: Terminal, WW1: Terminal, WW2: Terminal

Claims

1. The transistor includes first to fourth transistors, a first capacitance element, and a second capacitance element, one of a source and a drain of the first transistor is electrically connected to a first terminal; the other of the source and the drain of the first transistor is electrically connected to a first gate of the second transistor; a gate of the first transistor electrically connected to a second terminal; one of a source and a drain of the third transistor is electrically connected to a third terminal; the other of the source and the drain of the third transistor is electrically connected to a first gate of the fourth transistor; a gate of the third transistor electrically connected to a fourth terminal; one of a source and a drain of the second transistor is electrically connected to a fifth terminal; the other of the source and the drain of the second transistor is electrically connected to a seventh terminal; one of a source and a drain of the fourth transistor is electrically connected to a sixth terminal; the other of the source and the drain of the fourth transistor is electrically connected to the seventh terminal; a second gate of the second transistor electrically connected to an eighth terminal; a second gate of the fourth transistor electrically connected to a ninth terminal; one electrode of the first capacitance element is electrically connected to a gate of the second transistor; the other electrode of the first capacitance element is electrically connected to the seventh terminal; one electrode of the second capacitance element is electrically connected to a gate of the fourth transistor; the other electrode of the second capacitive element is electrically connected to the seventh terminal.

2. In claim 1, The semiconductor device is configured such that analog data is supplied to the first terminal.

3. In claim 1 or 2, The first transistor and the third transistor are semiconductor devices each including an oxide semiconductor in a semiconductor layer in which a channel is formed.

4. In claim 3, The second transistor and the fourth transistor are semiconductor devices each including an oxide semiconductor in a semiconductor layer in which a channel is formed.

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