Photoelectric conversion device and device

Abstract

To provide technique in advantageous for suppressing a coupling capacitance.SOLUTION: A first semiconductor layer to which a first FD and a second FD are arranged, a second semiconductor layer, a first wiring structure body that is arranged to between the first semiconductor layer and the second semiconductor layer, and a second wiring structure body that is arranged to between the first semiconductor layer and the second semiconductor layer, and is bonded to the first wiring structure body via a plurality of metal pads are laminated. The first FD is connected to a first transistor to be arranged to the second semiconductor layer via a first metal pad of the plurality of metal pads. The second FD is connected to a second transistor to be arranged to the second semiconductor layer vi a second metal pad of the plurality of metal pads. The plurality of metal pads contains a third metal pad to be arranged to between the first metal pad and the second metal pad. In the first wiring structure body, a conductive pattern to be extended toward the first semiconductor layer from the third metal pad is arranged.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and equipment.

Background Art

[0002] Patent Document 1 shows an image sensor in which a first structure including a first substrate and a second structure including a second substrate are laminated. Patent Document 1 shows that in a wiring structure for electrically connecting elements arranged on the first substrate and the second substrate, a coupling suppression line is arranged to suppress the coupling capacitance between pads arranged at a portion where the first structure and the second structure are joined.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to further improve the image quality in a photoelectric conversion device, further suppression of the coupling capacitance is desired.

[0005] An object of the present invention is to provide a technique advantageous for suppressing the coupling capacitance.

Means for Solving the Problems

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention includes a first semiconductor layer provided with first and second floating diffusions, a second semiconductor layer, a first wiring structure disposed between the first semiconductor layer and the second semiconductor layer, and a second wiring structure disposed between the first wiring structure and the second semiconductor layer and joined to the first wiring structure via a plurality of metal pads, the photoelectric conversion device being a laminated structure, wherein the first floating diffusion is connected to a first transistor disposed in the second semiconductor layer via a first metal pad among the plurality of metal pads, the second floating diffusion is connected to a second transistor disposed in the second semiconductor layer via a second metal pad among the plurality of metal pads, the plurality of metal pads includes a third metal pad disposed between the first metal pad and the second metal pad, and a conductive pattern extending from the third metal pad toward the first semiconductor layer is disposed in the first wiring structure.

Effects of the Invention

[0007] According to the present invention, a technique advantageous for suppressing coupling capacitance can be provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] With reference to FIGS. 1 to 11, a photoelectric conversion device according to an embodiment of the present disclosure will be described. The following embodiments are all examples showing the present disclosure and do not limit the invention according to the claims.

[0011] FIG. 1 is a diagram showing a circuit configuration example of pixels arranged in the photoelectric conversion device 100 of the present embodiment. FIG. 2 is a plan view focusing on a metal pad 151, which will be described later, arranged in the pixel. FIG. 3 is a cross-sectional view taken along the line A-A' of FIG. 2.

[0012] The photoelectric conversion device 100 is configured by laminating a substrate 161 and a substrate 162. More specifically, as shown in FIG. 3, the photoelectric conversion device 100 includes a semiconductor layer 110, a semiconductor layer 140, a wiring structure 120 disposed between the semiconductor layer 110 and the semiconductor layer 140, and a wiring structure 130 disposed between the wiring structure 120 and the semiconductor layer 140 and joined to the wiring structure 120 via a plurality of metal pads 151. Here, the combination of the semiconductor layer 110 and the wiring structure 120 on the side of the semiconductor layer 110 rather than the joint surface 150 between the wiring structure 120 and the wiring structure 130 is referred to as the substrate 161. Also, the combination of the semiconductor layer 140 and the wiring structure 130 on the side of the semiconductor layer 140 rather than the joint surface 150 is referred to as the substrate 162.

[0013] On the substrate 161, a photodiode (PD) 111, a transfer transistor 112, and a floating diffusion (FD) 113 are disposed. More specifically, the PD 111 and the FD 113 are disposed in the semiconductor layer 110 of the substrate 161. Also, the transfer transistor 112 is disposed across the semiconductor layer 110 and the wiring structure 120 of the substrate 161.

[0014] On the substrate 162, a source follower (SF) transistor 141, a selection transistor 142, and a reset transistor 143 are disposed. The output from the pixel including the PD 111 is supplied to the output line Vout via the selection transistor 142. More specifically, the SF transistor 141, the selection transistor 142, and the reset transistor 143 are disposed across the semiconductor layer 140 and the wiring structure 130 of the substrate 162. Also, the output line Vout is disposed in the wiring structure 130, for example.

[0015] In the configuration shown in FIG. 1, four PD111s are connected to one FD113. However, the number of PDs connected to one FD113 may be one, two, three, or five or more, depending on the specifications of the photoelectric conversion device 100. An appropriate number of PD111s are connected to one FD113 according to the specifications of the photoelectric conversion device 100. Further, a microlens (ML) for condensing light onto the PD111 may be provided on the light incident surface side of the substrate 161. When the ML is provided, the configuration may be such that a separate ML is provided for each PD111, or two or more PD111s may share one ML. In the latter configuration, the phase difference can be detected using the output signals of the PD111s sharing the ML. Also, the FD113 is connected to the gate of the SF transistor 141 via a metal pad 151 that joins the substrate 161 and the substrate 162. It can also be said that the substrate 161 and the substrate 162 are joined by metal bonding (MB) via the metal pad 151 arranged on the joining surface 150 of the wiring structure 120 and the wiring structure 130.

[0016] FIG. 2 is a schematic plan view focusing on the metal pad 151. In FIG. 2, 4×4 PD111s are shown, and as shown in the circuit diagram of FIG. 1, one metal pad 151 is arranged for one FD113 connected to 2×2 PD111s. The metal pad 151 may be arranged, for example, at the center of the 2×2 PD111s as shown in FIG. 2. When the metal pad 151 connected to the FD113 is denoted as the metal pad 151A as shown in FIG. 2. In the configuration shown in FIG. 2, one FD113 is arranged for every 2×2 PD111s with respect to the 4×4 PD111s. Therefore, four metal pads 151A1 to 151A4 are shown corresponding to the four FD113s. Also, between each of the metal pads 151A1 to 151A4 connected to the FD113, a metal pad 151B not connected to the FD113 is arranged.

[0017] As shown in FIG. 3, the pixel including PD111, transfer transistor 112, and FD113 (in FIG. 3, the description of PD111 is omitted) is separated by a pixel isolation region 115 composed of an insulating film such as silicon oxide or metal. Hereinafter, it will be described assuming that one PD111 corresponds to one pixel. For example, in the above-described configuration, it will be described that four pixels (PD111) share one FD113.

[0018] FD113-1 shown on the left side of FIG. 3 is connected to a transistor such as SF transistor 141 disposed in semiconductor layer 140 via metal pad 151A1 among a plurality of metal pads 151. Also, FD113-2 shown on the right side of FIG. 3 is connected to a transistor such as SF transistor 141 disposed in semiconductor layer 140 via metal pad 151A2 among a plurality of metal pads 151. As shown in FIG. 1, for one FD113, one metal pad 151A, SF transistor 141, selection transistor 142, and reset transistor 143 are disposed. FD113 and metal pad 151A are connected by wiring pattern 153 disposed in wiring structure 120. Metal pad 151A and SF transistor 141 disposed in semiconductor layer 140 are connected by wiring pattern 154 disposed in wiring structure 130.

[0019] As described above, between the metal pads 151A, metal pads 151B not connected to the FD113 are arranged. As shown in FIG. 2, between the metal pad 151A1 and the metal pad 151A2, a metal pad 151B1 is arranged. The metal pad 151A1 and the metal pad 151B1 are arranged adjacent to each other, and the metal pad 151A2 and the metal pad 151B1 are arranged adjacent to each other. It can also be said that between the metal pads 151A connected to the FD113, metal pads 151B not connected to the FD113 are arranged so that the metal pads 151A connected to the FD113 do not adjacent to each other. In that case, in the wiring structure 120, a conductive pattern 152 extending from the metal pad 151B (151B1) not connected to the FD113 toward the semiconductor layer 110 is arranged.

[0020] The conductive pattern 152 is arranged between the wiring patterns 153 connecting the FD113 and the metal pads 151A. The conductive pattern 152 can be formed simultaneously when forming the wiring pattern 153. Therefore, the conductive pattern 152 can be formed in the wiring structure 120 without adding a process for forming the conductive pattern 152. Further, the conductive pattern 152 is arranged at a position closer to the semiconductor layer 110 than the plurality of metal pads 151 arranged in the wiring structure 120.

[0021] The conductive pattern 152 may be in contact with the semiconductor layer 110. That is, the conductive pattern 152 may be electrically connected to the semiconductor layer 110. For example, a well potential such as 0V may be supplied to a pixel including the PD111 and the FD113 arranged in the semiconductor layer 110 via the metal pad 151B and the conductive pattern 152.

[0022] The signal output from the FD113 arranged in the semiconductor layer 110 of the substrate 161 is supplied to the SF transistor 141 arranged in the semiconductor layer 140 of the substrate 162 and the like. In that case, between adjacent pixels, the wiring patterns 153 and 154 through which the signal passes will be close to each other over a long distance in the stacking direction of the substrates 161 and 162, and it is assumed that the coupling capacitance will increase. Due to the crosstalk through the coupling capacitance between these wiring patterns 153 and 154, there is a possibility that the signal of another wiring pattern may be partially superimposed as noise on the signal of a certain wiring pattern 153 or 154. The noise due to crosstalk may deteriorate the image quality of the image obtained by the photoelectric conversion device 100. Also, the metal pads 151 that connect the wiring structure 120 of the substrate 161 and the wiring structure 130 of the substrate 162 can be formed larger than the wiring patterns 153 and 154 and are close to each other, so the coupling capacitance becomes large.

[0023] Therefore, in the present embodiment, metal pads 151B that are not connected to the FD113 are arranged between the metal pads 151A connected to the FD113. Thereby, it becomes possible to suppress the coupling capacitance between adjacent metal pads 151A. Further, a conductive pattern 152 extending from the metal pad 151B toward the semiconductor layer 110 of the substrate 161 is arranged. Thereby, it becomes possible to suppress the coupling capacitance between the wiring patterns 153 connected to adjacent FD113s (and metal pads 151A). That is, it is also possible to suppress the coupling capacitance generated on the substrate 161 side. Thereby, the image quality of the image obtained by the photoelectric conversion device 100 can be improved.

[0024] Furthermore, as described above, the metal pad 151B and the conductive pattern 152 may function as a supply line for supplying a predetermined potential to the semiconductor layer 110. Thereby, for example, in the wiring structure 120 of the photoelectric conversion device 100, the efficiency of the layout can be realized. However, it is not limited thereto, and the metal pad 151B and the conductive pattern 152 may be in a floating state. In that case, the conductive pattern 152 may or may not reach the semiconductor layer 110 from the metal pad 151B. Also, for example, the metal pad 151B may be connected to the output of the SF transistor 141 to which the metal pad 151A is connected to the gate via the wiring pattern 154 (between the SF transistor 141 and the selection transistor 142 shown in FIG. 1). Thereby, the capacitance added between the FD 113 and the conductive pattern 152 (and the metal pad 151B) can be reduced, and the FD capacitance can be reduced.

[0025] Figs. 4(a) and 4(b) are plan views showing modified examples of the arrangement of the metal pads 151 shown in Fig. 2. In the configuration shown in Fig. 2, in the orthographic projection onto the joint surface 150 where the wiring structure 120 and the wiring structure 130 are joined, the metal pads 151A and the metal pads 151B have the same shape. However, it is not limited thereto. As shown in Fig. 4(a), the shapes of the metal pads 151A and the metal pads 151B may be different. For example, when considering preventing a short circuit caused by foreign matter in the manufacturing process, a wider space between the metal pads 151A and the metal pads 151B can suppress the possibility of a short circuit. Therefore, in the orthographic projection onto the joint surface 150, the length of the metal pad 151B1 in the direction in which the metal pads 151A1 and 151A2 are arranged may be shorter than the lengths of the metal pads 151A1 and 151A2 in the direction in which the metal pads 151A1 and 151A2 are arranged. That is, the length of the two metal pads 151B arranged between the two metal pads 151A in the direction in which the two metal pads 151A are arranged may be shorter than the length of the metal pads 151A in that direction. Also, in that case, the length of the metal pad 151B1 in the direction intersecting the direction in which the metal pads 151A1 and 151A2 are arranged may be equal to or greater than the lengths of the metal pads 151A1 and 151A2 in the direction intersecting the direction in which the metal pads 151A1 and 151A2 are arranged. That is, the length of the metal pad 151B in the direction intersecting the direction in which the two metal pads 151A are arranged may be equal to or greater than the length of the metal pads 151A in that direction. Thereby, the effect of suppressing the coupling capacitance between the two metal pads 151A arranged with the metal pad 151B therebetween can be improved.

[0026] Also, for example, as shown in FIG. 4(b), a plurality of metal pads 151B shown in FIGS. 2 and 4(a) may be arranged to be connected. For example, in the orthographic projection onto the bonding surface 150, the metal pads 151B may be arranged to surround the metal pads 151A respectively. When arranging the plurality of metal pads 151B independently, when attempting to fix the metal pads 151B (and the conductive pattern 152) to a predetermined potential, it is necessary to supply a potential to each metal pad 151B. On the other hand, in the configuration shown in FIG. 4(b), for example, by giving a predetermined electron in one place, a potential can be supplied to the metal pads 151B in the entire region, so that the layout efficiency of the wiring structure 120 can be improved.

[0027] FIG. 5 is a plan view showing a further modification of the arrangement of the metal pads 151. Compared with the configuration shown in FIG. 2, the arrangement direction of the metal pads 151 (151A, 151B) is rotated by 45° with respect to PD111. Also in the configuration shown in FIG. 5, the above-described effects can be obtained. Furthermore, compared with the configuration shown in FIG. 2, the configuration shown in FIG. 5 can reduce the number of arrangements of the metal pads 151B. Therefore, the configuration shown in FIG. 5 is advantageous when miniaturizing the pixels in the photoelectric conversion device 100.

[0028] FIG. 6 is a diagram showing a modification of the cross-sectional view shown in FIG. 3. In the configuration shown in FIG. 6, compared with the configuration shown in FIG. 3, a conductive pattern 155 extending from the metal pad 151B toward the semiconductor layer 140 is arranged in the wiring structure 130. Since other configurations may be the same as the above-described configuration, the following description will focus on the conductive pattern 155.

[0029] The conductive pattern 155 is disposed between the metal pad 151A and the wiring pattern 154 that connects the transistor disposed in the semiconductor layer 140 such as the SF transistor 141. The conductive pattern 155 can be formed simultaneously when the wiring pattern 154 is formed. Therefore, the conductive pattern 155 can be formed in the wiring structure 130 without adding a process for forming the conductive pattern 155. Further, the conductive pattern 155 is disposed at a position closer to the semiconductor layer 140 than the plurality of metal pads 151 disposed in the wiring structure 130.

[0030] A conductive pattern 155 extending from the metal pad 151B toward the semiconductor layer 140 of the substrate 162 is disposed. Thereby, it becomes possible to suppress the coupling capacitance between the wiring patterns 154 connected to the adjacent FD113 (and the metal pad 151A). That is, it is also possible to suppress the coupling capacitance generated not only on the substrate 161 side but also on the substrate 162 side. Thereby, the image quality of the image obtained by the photoelectric conversion device 100 can be improved.

[0031] A further modification example of the above-described photoelectric conversion device 100 will be described with reference to FIGS. 7 to 10. Hereinafter, configurations different from the above-described embodiments will be described in detail, and descriptions of configurations that may be the same will be omitted as appropriate.

[0032] FIG. 7 is a diagram showing a modified example of the cross-sectional view shown in FIG. 3. In each of the above-described embodiments, elements such as the SF transistor 141 disposed in the semiconductor layer 140 are disposed on the surface of the semiconductor layer 140 facing the semiconductor layer 110. On the other hand, in the configuration shown in FIG. 7, elements such as the SF transistor 141 disposed in the semiconductor layer 140 are disposed on the surface of the semiconductor layer 140 opposite to the surface facing the semiconductor layer 110. Therefore, the wiring pattern 154 that connects the metal pad 151A and the transistors disposed in the semiconductor layer 140 such as the SF transistor 141 is disposed so as to penetrate the semiconductor layer 140. Accordingly, through-holes for allowing the wiring pattern 154 to pass therethrough are disposed in the semiconductor layer 140. An insulating film using silicon oxide or the like, a barrier metal film using titanium or the like, or the like may be disposed between the through-hole provided in the semiconductor layer 140 and the wiring pattern 154. Further, the wiring pattern 154 is disposed not only in the wiring structure 130 between the wiring structure 120 (bonding surface 150) and the semiconductor layer 140, but also in the wiring structure 131 that contacts the surface of the semiconductor layer 140 opposite to the surface in contact with the wiring structure 130.

[0033] In the configuration shown in FIG. 3, an insulator constituting the wiring structure 130 is disposed between adjacent wiring patterns 154. On the other hand, in the configuration shown in FIG. 7, a part of the portion where adjacent wiring patterns 154 are arranged in parallel is surrounded by the semiconductor layer 140. Thereby, the semiconductor layer 140 serves as a shield for suppressing the coupling between the wiring patterns 154. Therefore, it becomes possible to suppress the coupling capacitance between the wiring patterns 154 connected to the adjacent FD113 (and the metal pad 151A). That is, the coupling generated on the substrate 162 side can be reduced.

[0034] Figs. 8(a) to 8(c) are plan views showing a configuration example of the pixel array 101 and the peripheral region 102 of the photoelectric conversion device 100 in the present embodiment. Fig. 8(a) shows an arrangement example of the wiring pattern 153 and the conductive pattern 152 arranged in the wiring structure 120 of the substrate 161. Fig. 8(b) shows an arrangement example of the metal pads 151 for joining the wiring structure 120 and the wiring structure 130. Fig. 8(b) also shows a position (or a position penetrating the semiconductor layer 140) in contact with the metal pad 151A among the wiring patterns 154 arranged in the wiring structure 130 of the substrate 162. Fig. 8(c) shows a pattern penetrating the semiconductor layer 140 among the wiring patterns 154, a pattern connecting the pattern penetrating the semiconductor layer 140 and the gate of the SF transistor 141. Fig. 9 is a cross-sectional view taken along the line B-B' shown in Fig. 8(a).

[0035] The conductive pattern 152 may be arranged so as to at least partially surround the wiring pattern 153 connecting the FD113 and the metal pad 151A. As shown in Fig. 8(a), the conductive pattern 152 may be arranged so as to surround each of the wiring patterns 153. Thereby, it becomes possible to suppress the coupling between adjacent wiring patterns 153 in any of the vertical and horizontal directions shown in Fig. 8(a). The arrangement relationship between the conductive pattern 152 and the wiring pattern 153 shown in Fig. 8(a) is applicable not only to the configuration shown in Fig. 7 but also to each of the above-described configurations.

[0036] As shown in Figs. 8(b) and 9, a metal pad 151C may also be arranged in the peripheral region 102. The metal pad 151C may be larger than the metal pads 151A and 151B. The metal pad 151C joins the wiring structure 120 of the substrate 161 and the wiring structure 130 of the substrate 162. Further, as shown in Fig. 9, the metal pad 151C may be connected to the wiring patterns 153 and 154 arranged in the wiring structures 120 and 130 and function as a conductive path between various elements arranged in the semiconductor layers 110 and 140.

[0037] FIG. 10 is a diagram showing a modified example of the cross-sectional view shown in FIG. 7. As shown in FIG. 10, a conductive pattern 155 extending from a metal pad 151B not connected to the FD113 toward the semiconductor layer 140 may penetrate the semiconductor layer 140. Thereby, similar to the configuration shown in FIG. 6, it is possible to suppress the coupling capacitance between the wiring patterns 154 connected to the adjacent FD113s (and the metal pads 151A) and suppress the coupling capacitance generated on the substrate 162 side.

[0038] Similar to the relationship between the conductive pattern 152 and the wiring pattern 153 as shown in FIG. 8(a), the conductive pattern 155 may be arranged so as to surround at least partially the wiring pattern 154 that connects the metal pad 151A and a transistor such as the SF transistor 141 arranged in the semiconductor layer 140. Thereby, it becomes possible to suppress the coupling between the adjacent wiring patterns 154. For example, the portions of the conductive pattern 155 arranged in the wiring structures 130 and 131 surround the respective wiring patterns 154. FIG. 11 shows a configuration example in which a substrate 163 including a semiconductor layer 180 and a wiring structure 170 is further stacked on the configuration shown in FIG. 9. In the configuration shown in FIG. 11, a semiconductor layer 140 is disposed between the semiconductor layer 110 and the semiconductor layer 180. The wiring structure 131 of the substrate 162 and the wiring structure 170 of the substrate 163 are joined via a plurality of metal pads 151D, similarly to the joining of the wiring structure 120 of the substrate 161 and the wiring structure 130 of the substrate 162. Elements 181 such as transistors are disposed on the surface of the semiconductor layer 180 facing the semiconductor layer 140. The element 181 may receive, for example, a signal output from the FD113 disposed in the semiconductor layer 110 and perform signal processing or the like. For example, as the output line Vout shown in FIG. 1, a wiring pattern 156 disposed in the wiring structure 131 shown in FIG. 11 or a wiring pattern 171 disposed in the wiring structure 170 may be used. Thereby, the signal output from the FD113 can be processed by the element 181 disposed in the semiconductor layer 110. By increasing the number of substrates (semiconductor layers) in this way, further high functionality of the photoelectric conversion device 100 is realized.

[0039] Here, an application example of the photoelectric conversion device 100 according to the above-described embodiment will be described below. FIG. 12 is a schematic diagram of a device EQP equipped with the photoelectric conversion device 100. As shown in FIG. 12, the photoelectric conversion device 100 is housed in a semiconductor package PKG. The package PKG may include a base body to which the photoelectric conversion device 100 is fixed, a lid such as glass facing the photoelectric conversion device 100, and a conductive connection member such as a bonding wire or a bump that connects a terminal provided on the base body and a terminal provided on the photoelectric conversion device 100. The device EQP may further include at least one of a control device CTRL, a processing device PRCS, a display device DSPL, and a storage device MMRY.

[0040] The optical system OPT forms an image on the pixel array 101 and can be, for example, a lens, a shutter, a mirror, or the like. The control device CTRL controls the operation of the photoelectric conversion device 100 and can be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device 100 and can be a semiconductor device such as a CPU or an ASIC. The display device DSPL can be an EL display device or a liquid crystal display device that displays the data obtained by the photoelectric conversion device 100. The storage device MMRY is a magnetic device or a semiconductor device that stores the data obtained by the photoelectric conversion device 100. The storage device MMRY can be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN can have a movable part or a propulsion part such as a motor or an engine. Also, the mechanical device MCHN drives the components of the optical system OPT, for example, for zooming, focusing, and shutter operation. In the equipment EQP, the data output from the photoelectric conversion device 100 is displayed on the display device DSPL or transmitted externally by a communication device (not shown) provided in the equipment EQP. For this reason, the equipment EQP may include the storage device MMRY and the processing device PRCS.

[0041] The equipment EQP incorporating the photoelectric conversion device 100 can also be applied to a surveillance camera or an in-vehicle camera mounted on a transportation device such as an automobile, a railway vehicle, a ship, an aircraft, or an industrial robot. In addition, the equipment EQP incorporating the photoelectric conversion device 100 can be applied not only to transportation devices but also to devices that widely utilize object recognition, such as an advanced road traffic system (ITS).

[0042] The disclosure of this specification includes the following photoelectric conversion device and equipment.

[0043] (Item 1) A photoelectric conversion device in which a first semiconductor layer provided with a first floating diffusion and a second floating diffusion, a second semiconductor layer, a first wiring structure disposed between the first semiconductor layer and the second semiconductor layer, and a second wiring structure disposed between the first wiring structure and the second semiconductor layer and joined to the first wiring structure via a plurality of metal pads are laminated, The first floating diffusion is connected to a first transistor disposed in the second semiconductor layer via a first metal pad among the plurality of metal pads, The second floating diffusion is connected to a second transistor disposed in the second semiconductor layer via a second metal pad among the plurality of metal pads, The plurality of metal pads includes a third metal pad disposed between the first metal pad and the second metal pad, The photoelectric conversion device is characterized in that a conductive pattern extending from the third metal pad toward the first semiconductor layer is disposed in the first wiring structure.

[0044] (Item 2) The photoelectric conversion device according to Item 1, wherein the conductive pattern is in contact with the first semiconductor layer.

[0045] (Item 3) The photoelectric conversion device according to Item 2, wherein a well potential is supplied to a pixel including the first floating diffusion and the second floating diffusion disposed in the first semiconductor layer via the third metal pad and the conductive pattern.

[0046] (Item 4) The photoelectric conversion device according to Item 1 or 2, wherein the third metal pad is in a floating state.

[0047] (Item 5) The first metal pad is connected to a gate of the first transistor via a wiring pattern, The photoelectric conversion device according to item 1 or 2, wherein the third metal pad is connected to the output of the first transistor.

[0048] (Item 6) The first metal pad and the third metal pad are arranged adjacent to each other, The photoelectric conversion device according to any one of items 1 to 5, wherein the second metal pad and the third metal pad are arranged adjacent to each other.

[0049] (Item 7) The photoelectric conversion device according to any one of items 1 to 6, wherein the conductive pattern is arranged at a position closer to the first semiconductor layer than the plurality of metal pads.

[0050] (Item 8) The photoelectric conversion device according to any one of items 1 to 7, wherein the conductive pattern is arranged so as to at least partially surround a wiring pattern connecting the first floating diffusion and the first metal pad.

[0051] (Item 9) Regarding the conductive pattern as a first conductive pattern, The photoelectric conversion device according to any one of items 1 to 8, wherein a second conductive pattern extending from the third metal pad toward the second semiconductor layer is arranged in the second wiring structure.

[0052] (Item 10) The photoelectric conversion device according to item 9, wherein the second conductive pattern is arranged at a position closer to the second semiconductor layer than the plurality of metal pads.

[0053] (Item 11) The photoelectric conversion device according to item 9 or 10, wherein the second conductive pattern is arranged so as to at least partially surround a wiring pattern connecting the first metal pad and the first transistor.

[0054] (Item 12) The first transistor and the second transistor are arranged on a surface of the second semiconductor layer facing the first semiconductor layer, and the photoelectric conversion device according to any one of Items 1 to 11, characterized in that.

[0055] (Item 13) The first transistor and the second transistor are arranged on a surface of the second semiconductor layer opposite to the surface facing the first semiconductor layer, A wiring pattern connecting the first metal pad and the first transistor and a wiring pattern connecting the second metal pad and the second transistor are arranged to penetrate the second semiconductor layer, and the photoelectric conversion device according to any one of Items 1 to 11, characterized in that.

[0056] (Item 14) The first transistor and the second transistor are arranged on a surface of the second semiconductor layer opposite to the surface facing the first semiconductor layer, A wiring pattern connecting the first metal pad and the first transistor and a wiring pattern connecting the second metal pad and the second transistor are arranged to penetrate the second semiconductor layer, The second conductive pattern penetrates the second semiconductor layer, and the photoelectric conversion device according to any one of Items 9 to 11, characterized in that.

[0057] (Item 15) In a orthographic projection with respect to a bonding surface where the first wiring structure and the second wiring structure are bonded, the first metal pad, the second metal pad, and the third metal pad have the same shape, and the photoelectric conversion device according to any one of Items 1 to 14, characterized in that.

[0058] (Item 16) In the orthographic projection onto the bonding surface where the first wiring structure and the second wiring structure are bonded, the length of the third metal pad in the direction in which the first metal pad and the second metal pad are arranged is shorter than the lengths of the first metal pad and the second metal pad in the arranged direction, according to any one of Items 1 to 14. The photoelectric conversion device described.

[0059] (Item 17) In the direction intersecting the arranged direction, the length of the third metal pad is equal to or greater than the lengths of the first metal pad and the second metal pad in the intersecting direction. The photoelectric conversion device according to Item 16.

[0060] (Item 18) In the orthographic projection onto the bonding surface where the first wiring structure and the second wiring structure are bonded, the third metal pad is arranged so as to surround the first metal pad and the second metal pad respectively. The photoelectric conversion device according to any one of Items 1 to 14.

[0061] (Item 19) The third semiconductor layer is further laminated, The second semiconductor layer is arranged between the first semiconductor layer and the third semiconductor layer, On the surface of the third semiconductor layer facing the second semiconductor layer, an element for receiving the signal output from the first floating diffusion is arranged. The photoelectric conversion device according to any one of Items 1 to 18.

[0062] (Item 20) The photoelectric conversion device according to any one of Items 1 to 19, A processing device for processing the signal output from the photoelectric conversion device, A device characterized by comprising.

[0063] The invention is not limited to the above embodiments, and various changes and modifications are possible without departing from the spirit and scope of the invention. Therefore, claims are attached to disclose the scope of the invention.

Description of Signs

[0064] 100: Photoelectric conversion device, 110, 140: Semiconductor layer, 113: Floating diffusion, 120, 130: Wiring structure, 141: Source follower transistor, 151: Metal pad, 152: Conductive pattern

Claims

1. A first semiconductor layer provided with a first floating diffusion and a second floating diffusion, a second semiconductor layer, a first wiring structure disposed between the first semiconductor layer and the second semiconductor layer, and disposed between the first wiring structure and the second semiconductor layer, A photoelectric conversion device in which a second wiring structure joined to the first wiring structure via a plurality of metal pads is laminated, The first floating diffusion is connected to a first transistor disposed in the second semiconductor layer via a first metal pad among the plurality of metal pads, The second floating diffusion is connected to a second transistor disposed in the second semiconductor layer via a second metal pad among the plurality of metal pads, The plurality of metal pads includes a third metal pad disposed between the first metal pad and the second metal pad, The photoelectric conversion device is characterized in that a conductive pattern extending from the third metal pad toward the first semiconductor layer is disposed in the first wiring structure.

2. The photoelectric conversion device according to claim 1, wherein the conductive pattern is in contact with the first semiconductor layer.

3. The photoelectric conversion device according to claim 2, wherein a well potential is supplied to a pixel including the first floating diffusion and the second floating diffusion disposed in the first semiconductor layer via the third metal pad and the conductive pattern.

4. The photoelectric conversion device according to claim 1, wherein the third metal pad is in a floating state.

5. The first metal pad is connected to a gate of the first transistor via a wiring pattern, The photoelectric conversion device according to claim 1, wherein the third metal pad is connected to an output of the first transistor.

6. The first metal pad and the third metal pad are arranged adjacent to each other. The photoelectric conversion device according to claim 1, wherein the second metal pad and the third metal pad are arranged adjacent to each other.

7. The photoelectric conversion device according to claim 1, wherein the conductive pattern is arranged at a position closer to the first semiconductor layer than the plurality of metal pads.

8. The photoelectric conversion device according to claim 1, wherein the conductive pattern is arranged so as to at least partially surround a wiring pattern connecting the first floating diffusion and the first metal pad.

9. Regarding the conductive pattern as a first conductive pattern, The photoelectric conversion device according to claim 1, wherein a second conductive pattern extending from the third metal pad toward the second semiconductor layer is arranged in the second wiring structure.

10. The photoelectric conversion device according to claim 9, wherein the second conductive pattern is arranged at a position closer to the second semiconductor layer than the plurality of metal pads.

11. The photoelectric conversion device according to claim 9, wherein the second conductive pattern is arranged so as to at least partially surround a wiring pattern connecting the first metal pad and the first transistor.

12. The photoelectric conversion device according to claim 1, wherein the first transistor and the second transistor are arranged on a surface of the second semiconductor layer facing the first semiconductor layer.

13. The first transistor and the second transistor are arranged on a surface of the second semiconductor layer opposite to the surface facing the first semiconductor layer. The wiring pattern connecting the first metal pad and the first transistor and the wiring pattern connecting the second metal pad and the second transistor are arranged to penetrate the second semiconductor layer, according to the photoelectric conversion device of claim 1.

14. The first transistor and the second transistor are arranged on the surface of the second semiconductor layer opposite to the surface facing the first semiconductor layer, The wiring pattern connecting the first metal pad and the first transistor and the wiring pattern connecting the second metal pad and the second transistor are arranged to penetrate the second semiconductor layer, The second conductive pattern penetrates the second semiconductor layer, according to the photoelectric conversion device of claim 9.

15. In the orthographic projection onto the bonding surface where the first wiring structure and the second wiring structure are bonded, the first metal pad, the second metal pad, and the third metal pad have the same shape, according to the photoelectric conversion device of claim 1.

16. In the orthographic projection onto the bonding surface where the first wiring structure and the second wiring structure are bonded, the length of the third metal pad in the direction in which the first metal pad and the second metal pad are arranged is shorter than the lengths of the first metal pad and the second metal pad in the arranged direction, according to the photoelectric conversion device of claim 1.

17. The length of the third metal pad in the direction intersecting the arranged direction is equal to or greater than the lengths of the first metal pad and the second metal pad in the intersecting direction, according to the photoelectric conversion device of claim 16.

18. In the orthographic projection onto the bonding surface where the first wiring structure and the second wiring structure are bonded, the third metal pad is arranged to surround the first metal pad and the second metal pad respectively, according to the photoelectric conversion device of claim 1.

19. The third semiconductor layer is further laminated, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer, The photoelectric conversion device according to claim 1, wherein an element for receiving a signal output from the first floating diffusion is disposed on a surface of the third semiconductor layer facing the second semiconductor layer.

20. A photoelectric conversion device according to any one of claims 1 to 19, A processing device that processes a signal output from the photoelectric conversion device, An apparatus comprising the same.

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