Thin film transistor and display device including the same

Abstract

To provide an organic light emitting display device including hybrid-type thin film transistors using different types of semiconductor materials.SOLUTION: In a display area AA of an organic light emitting display device, a driving thin film transistor DT includes a gate electrode 305 disposed under an oxide semiconductor pattern 311, and includes a dummy electrode 315, a source electrode 319S and a drain electrode 319D that are over an oxide semiconductor pattern. The dummy electrode can be electrically connected to the source electrode to increase the s-factor of the driving thin film transistor. In addition, the display area also includes a plurality of switching thin film transistors ST-1, ST-2 including an oxide semiconductor pattern, and the switching thin film transistors have mutually different distances between an oxide semiconductor pattern 312 and each of gate electrodes 306A, 306B so that the switching thin film transistors have mutually different threshold voltages.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] [1] The present invention relates to an organic light-emitting display device, and particularly to an organic light-emitting display device including a hybrid thin-film transistor using different types of semiconductor materials when forming a plurality of thin-film transistors constituting a pixel circuit portion of a sub-pixel and a plurality of thin-film transistors of a gate in-panel (GIP) circuit portion.

Background Art

[0002] [2] Since an organic light-emitting display device uses a light-emitting element that emits light spontaneously without using a backlight as compared with a liquid crystal display device, it has excellent thin-film properties and image quality and has become a mainstream in the display field.

[0003] [3] In particular, since a light-emitting element can be formed on a flexible substrate, the screen can be configured in various forms such as bending and folding, and it is suitable as a display device for small electronic devices such as smart watches because of its excellent thin-film properties.

[0004] [4] Further, in order to apply to a display device such as a smart watch having many still images, a display device including a new type of pixel circuit capable of preventing leakage current in a still image is required.

[0005] [5] As a thin-film transistor advantageous for blocking such leakage current, those using an oxide semiconductor as an active layer have been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0006] [6] However, in a display device using a hybrid thin-film transistor, since different types of semiconductor elements are used, for example, a polycrystalline thin-film transistor (polycrystalline TFT) using a polycrystalline semiconductor pattern as an active layer and an oxide thin-film transistor (oxide TFT) using an oxide semiconductor pattern as an active layer, the process of forming the polycrystalline semiconductor pattern and the process of forming the oxide semiconductor pattern must be performed separately, which makes the process complex. In addition, since the polycrystalline semiconductor pattern and the oxide semiconductor pattern have different etching characteristics with respect to chemical gases, more complex processes are required.

[0007] [7] In particular, since the polycrystalline semiconductor pattern has a faster carrier mobility, such as electrons and holes, than the oxide semiconductor pattern, it is suitable for a driving thin-film transistor that requires rapid driving. As a result, a normal driving thin-film transistor uses a polycrystalline semiconductor pattern.

[0008] [8] However, a driving thin-film transistor using a polycrystalline semiconductor pattern has a problem that is disadvantageous for low-tone expression because, although it has a high driving speed, the current fluctuation rate due to current stress is large. Therefore, an object of the present invention is to provide a pixel circuit portion that includes a driving thin-film transistor using an oxide semiconductor pattern, has a small current fluctuation rate after current stress, and has a large s-factor value.

Means for Solving the Problems

[0009] [9] The thin-film transistor included in the organic light-emitting display device of the present invention for achieving the above object includes a semiconductor pattern including a channel region, a source region and a drain region corresponding to each other with the channel region therebetween, a gate electrode overlapping the channel region under the semiconductor pattern, a source electrode and a drain electrode respectively connected to the source region and the drain region on the semiconductor pattern, and a dummy electrode overlapping the semiconductor pattern on the semiconductor pattern, and the dummy electrode is connected to either one of the source electrode or the drain electrode.

[0010]

[10] The semiconductor pattern may include an oxide semiconductor pattern.

[0011]

[11] The thin film transistor further includes a gate insulating layer disposed between the gate electrode and the semiconductor pattern and including at least one inorganic insulating layer, and a first interlayer insulating layer disposed between the semiconductor pattern and the dummy electrode and including at least one inorganic insulating layer, and the thickness of the gate insulating layer may be greater than the thickness of the first interlayer insulating layer.

[0012]

[12] Further, the thin film transistor further includes a gate insulating layer disposed between the gate electrode and the semiconductor pattern and including at least one inorganic insulating layer, and a first interlayer insulating layer disposed between the semiconductor pattern and the dummy electrode and including at least one inorganic insulating layer, and the dielectric constant of the first interlayer insulating layer may be greater than the dielectric constant of the gate insulating layer.

[0013]

[13] Further, the gate insulating layer may include a silicon oxide thin film, and the first interlayer insulating layer may include a fluorine silicon nitride film having a dielectric constant greater than the dielectric constant of the silicon oxide thin film.

[0014]

[14] Further, the dummy electrode may include a conductive metal pattern.

[0015]

[15] Further, the source electrode may be connected to the source region and the dummy electrode through one contact hole, and the dummy electrode may be connected to the source electrode through side contact with the contact hole.

[0016]

[16] On the one hand, the organic light-emitting display device of the present invention includes a substrate including a display area and a non-display area disposed around the display area, a first thin-film transistor disposed on the substrate and including a first semiconductor pattern, a first gate electrode disposed on the first semiconductor pattern, a first source electrode, and a first drain electrode, and a second thin-film transistor disposed on the substrate and including a second semiconductor pattern disposed in a layer different from the first semiconductor pattern, a second gate electrode disposed under the second semiconductor pattern, a second source electrode, and a second drain electrode disposed on the semiconductor pattern. On the second semiconductor pattern, a dummy electrode connected to any one of the second source electrode or the second drain electrode and overlapping the second semiconductor pattern may be included.

[0017]

[17] Further, the organic light-emitting display device of the present invention may further include a third thin-film transistor including a third semiconductor pattern disposed on the same layer as the second semiconductor pattern, a third gate electrode disposed under the third semiconductor pattern, a third source electrode, and a third drain electrode disposed on the third semiconductor pattern.

[0018]

[18] Further, the organic light-emitting display device of the present invention may further include a fourth thin-film transistor including a fourth semiconductor pattern disposed on the same layer as the second semiconductor pattern, a fourth gate electrode disposed under the fourth semiconductor pattern, a fourth source electrode, and a fourth drain electrode disposed on the fourth semiconductor pattern, and the third gate electrode and the fourth gate electrode may be disposed in different layers from each other.

[0019]

[19] Further, in the organic light-emitting display device of the present invention, the first gate electrode and the second gate electrode may be disposed on the same layer.

[0020]

[20] Further, the organic light-emitting display device of the present invention further includes a storage capacitor including a first electrode of the storage capacitor disposed on the same layer as the first gate electrode and a second electrode of the storage capacitor disposed on top of the first electrode of the storage capacitor, and the second gate electrode may be disposed on the same layer as the second electrode of the storage capacitor.

[0021]

[21] Further, the organic light-emitting display device of the present invention further includes a gate insulating layer disposed between the second gate electrode and the second semiconductor pattern and including at least one inorganic insulating layer, and a first interlayer insulating layer disposed between the second semiconductor pattern and the dummy electrode and including at least one inorganic insulating layer, and the thickness of the gate insulating layer may be greater than the thickness of the first interlayer insulating layer.

[0022]

[22] Further, the organic light-emitting display device of the present invention further includes a gate insulating layer disposed between the second gate electrode and the second semiconductor pattern and including at least one inorganic insulating layer, and a first interlayer insulating layer disposed between the second semiconductor pattern and the dummy electrode and including at least one inorganic insulating layer, and the dielectric constant of the first interlayer insulating layer may be greater than the dielectric constant of the gate insulating layer.

[0023]

[23] Further, the gate insulating layer may include a silicon oxide thin film, and the first interlayer insulating layer may include a fluorine silicon nitride film having a dielectric constant greater than the dielectric constant of the silicon oxide thin film.

[0024]

[24] Further, the first semiconductor pattern includes a polycrystalline semiconductor pattern, and at least any one of the second semiconductor pattern, the third semiconductor pattern, and the fourth semiconductor pattern may include an oxide semiconductor pattern.

[0025]

[25] Further, the first thin film transistor may be disposed in a non-display area, and the second thin film transistor may be disposed in a display area.

[0026]

[26] Further, the organic light-emitting display device of the present invention may further include a fifth gate electrode disposed on the third semiconductor pattern and electrically connected to the third gate electrode.

Advantages of the Invention

[0027]

[27] The organic light-emitting display device of the present invention can reduce the leakage current in the off state and reduce power consumption by introducing a driving thin-film transistor and a switching thin-film transistor including an oxide semiconductor pattern.

[0028]

[28] Also, by adjusting the parasitic capacitance formed inside the driving thin-film transistor, the effective voltage applied to the oxide semiconductor pattern can be reduced, and defects such as unevenness can be controlled by precise gradation expression in low gradations.

[0029]

[29] Further, the driving thin-film transistor uses a bottom gate in which the gate electrode is disposed under the active layer and is provided with a dummy electrode on the active layer, thereby obtaining the effect of protecting the active layer from hydrogen particles that can flow in from above and below the active layer.

[0030]

[30] Also, when forming a plurality of layers for the configuration of the thin-film transistor, a mask can be integrally used, so that the process can be simplified.

[0031]

[31] Also, oxide thin-film transistors having different structures can be arranged in the pixel circuit portion of one sub-pixel.

Brief Description of the Drawings

[0032]

Figure 1

[32] FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention.

Figure 2

[33] FIG. 2 is a circuit diagram showing a pixel circuit for driving one pixel in a display device according to an embodiment of the present invention.

Figure 3

[34] FIG. 3 is a cross-sectional view of one thin-film transistor disposed in a non-display area, a driving thin-film transistor, a switching thin-film transistor, and a storage capacitor disposed in a pixel area according to an embodiment of the present invention.

Figure 4A

[35] FIG. 4A is a cross-sectional view showing a driving thin-film transistor according to an embodiment of the present invention.

Figure 4B

[36] FIG. 4B is a circuit diagram showing the connection relationship between parasitic capacitors generated in the driving thin film transistor of the present invention.

Figure 5

[37] FIG. 5 is a cross-sectional view of a driving thin film transistor disposed in a pixel region according to an embodiment of the present invention, and two switching thin film transistors having different structures from each other.

Figure 6

[38] FIG. 6 is a cross-sectional view of a display device in which a switching thin film transistor according to an embodiment of the present invention is configured with a dual gate.

Figure 7

[39] FIG. 7 is a cross-sectional view of a display device in which a thin film transistor including a polycrystalline semiconductor pattern and a thin film transistor including an oxide semiconductor pattern in a non-display region constitute a CMOS.

Figure 8

[40] FIG. 8 is a cross-sectional view of a display device using an inorganic insulating layer having a high dielectric constant for an interlayer insulating layer of a driving thin film transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033]

[41] The advantages and features of the present invention, and the methods for achieving them, will become apparent by reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and to indicate the scope of the invention to those of ordinary skill in the technical field to which the present invention pertains.

[0034]

[42] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. The same components throughout the specification may be referred to by the same reference numerals. Also, in the description of the present invention, when it is determined that a detailed description of related known technologies will unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

[0035]

[43] When terms such as "including", "having", "comprising", etc. mentioned in this specification are used, other parts may be added unless the expression "only" is used. When a component is expressed in the singular, it includes a plurality unless otherwise explicitly stated.

[0036]

[44] In the interpretation of components, even without separate explicit description, it is interpreted as including the error range.

[0037]

[45] For example, when the positional relationship between two parts is described by "on", "above", "below", "on the side of", etc., unless the expressions "immediately" or "directly" are used, one or more other parts may be located between the two parts.

[0038]

[46] Spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. can be used to easily describe the correlation between one element or component and another element or component as shown in the drawing. Spatially relative terms should be understood as terms including not only the directions shown in the drawing but also different directions of the element during use or operation. For example, when covering an element shown in the drawing, an element described as "below (below or beneath)" another element can be located "above" the other element. Therefore, the exemplary term "below" can include both the lower and upper directions. Similarly, the exemplary term "above" can include both the upper and lower directions.

[0039]

[47] In the case of an explanation of the time relationship, for example, when the time sequence is described by "after", "subsequent to", "next", "before", etc., unless the expressions "immediately" or "directly" are used, it can include cases where they are not consecutive.

[0040]

[48] The terms such as "first", "second", etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical idea of the present invention.

[0041]

[49] The term "at least one" should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" can mean not only each of the first item, the second item, or the third item alone, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0042]

[50] The respective features of each embodiment of the present invention can be partially or wholly combined or combined with each other, various interlocks and drives are technically possible, and each embodiment may be implemented independently of each other or may be implemented in relation to each other together.

[0043]

[51] When attaching reference numerals to the components of each drawing for explaining the embodiments of the present invention, for the same component, as much as possible, the same numeral is attached even if it is shown on other drawings.

[0044]

[52] In the embodiments of the present invention, the source electrode and the drain electrode are only distinguished for convenience of explanation, and the source electrode and the drain electrode can be interchanged with each other. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Also, the source electrode of one embodiment can become the drain electrode in another embodiment, and the drain electrode of one embodiment can become the source electrode in another embodiment.

[0045]

[53] In an embodiment of the present invention, for the sake of convenience of explanation, the source region and the source electrode may be distinguished, and the drain region and the drain electrode may be distinguished, but the embodiments of the present invention are not limited thereto. The source region can serve as the source electrode, and the drain region can serve as the drain electrode. Also, the source region can serve as the drain electrode, and the drain region can serve as the source electrode.

[0046]

[54] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0047]

[55] FIG. 1 is a plan view showing a display device (100) according to the present invention.

[0048]

[56] The display panel (102) includes a display area (AA) provided on a substrate (101) and a non-display area (NA) disposed in the vicinity (e.g., adjacent) of the display area (AA) or surrounded by the display area (AA). The substrate (101) can include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be formed of a plastic material having flexibility so as to be bendable. For example, the substrate (101) may be formed of materials such as polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polysilene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, and polystyrene (PS). However, glass is not excluded as a material for the substrate.

[0049]

[57] The sub-pixels in the display area (AA) include thin-film transistors using an oxide semiconductor material or a polycrystalline silicon semiconductor as the active layer. For example, the oxide semiconductor material may be formed from any one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0050]

[58] At least one of the data driving unit (104) and the gate driving unit (103) may be disposed in the non-display area (NA). Further, it may further include a bending area (BA) where the substrate (101) is bent. For example, the bending area (BA) may be provided within the display area (AA).

[0051]

[59] Among these, the gate driving unit (103) may be directly formed on the substrate (101) using a thin-film transistor using a polycrystalline semiconductor material as the active layer, or may be formed in pairs including a thin-film transistor using a polycrystalline semiconductor material as the active layer and a thin-film transistor using an oxide semiconductor material as the active layer, but the present invention is not limited thereto. When the thin-film transistors disposed in the non-display area (NA) and the display area (AA) respectively include the same semiconductor material, the thin-film transistors disposed in the non-display area (NA) and the display area (AA) respectively can be formed simultaneously in the same process.

[0052]

[60] Such thin-film transistors having an oxide semiconductor pattern and thin-film transistors having a polycrystalline semiconductor pattern have high electron mobility in the channel, so that high resolution and low power can be realized.

[0053]

[61] In the display area (AA), a plurality of data lines and a plurality of gate lines may be arranged. For example, the plurality of data lines may be arranged in rows or columns, and the plurality of gate lines may be arranged in columns or rows. Also, sub-pixels (PX) may be arranged in the area defined by the data lines and the gate lines.

[0054]

[62] In the non-display area (NA), a gate driving unit (103) including a gate driving circuit may be arranged. The gate driving circuit of the gate driving unit (103) sequentially supplies scan signals to the plurality of gate lines to drive each pixel row in the display area in sequence. Here, the gate driving circuit is also called a scan driving circuit. Here, a pixel row refers to a row formed by pixels connected to one gate line.

[0055]

[63] The gate driving circuit may be composed of thin film transistors having a polycrystalline semiconductor pattern, may be composed of thin film transistors having an oxide semiconductor pattern, or may be configured in pairs with thin film transistors having a polycrystalline semiconductor pattern and thin film transistors having an oxide semiconductor pattern. When the same semiconductor material is used for the thin film transistors arranged in the non-display area (NA) and the display area (AA), it can be performed simultaneously in the same process.

[0056]

[64] The gate driving circuit may include a shift register, a level shifter, etc.

[0057]

[65] The gate driving circuit may be embodied in a gate in-panel type and directly arranged on the substrate (101) like the display device according to the embodiments of this specification. Or, the gate driving unit (103) may be integrally arranged on the display panel (102), and each gate driving unit (103) may be embodied by a chip on film (COF) method in which elements are mounted on a film connected to the display panel (102).

[0058]

[66] The gate driving unit (103) including a gate driving circuit sequentially supplies a scan signal of an on voltage or an off voltage to a plurality of gate lines.

[0059]

[67] The display device (100) according to an embodiment of the present specification may further include a data driving circuit. Further, when a specific gate line becomes effective by the gate driving unit (103) including a gate driving circuit, the data driving circuit converts image data into a data voltage in an analog form and supplies the data voltage to a plurality of data lines. The data line (DL) may be connected to the data driving unit (104) via a data pad. In FIG. 1, the data driving unit (104) is shown as being disposed on one side of the display panel (102), but the number and position of the data driving unit (104) are not limited thereto.

[0060]

[68] The plurality of gate lines (GL) disposed on the substrate (101) may include a plurality of scan lines and a plurality of light emission control lines, etc. The plurality of scan lines and the plurality of light emission control lines are wirings that transmit different types of gate signals (scan signals, light emission control signals) to the gate nodes of different types of transistors (scan transistors, light emission control transistors).

[0061]

[69] The gate driving unit (103) including a gate driving circuit may include a scan driving circuit that outputs a scan signal to a plurality of scan lines which are one type of the gate line (GL), and a light emission driving circuit that outputs a light emission control signal to a plurality of light emission control lines which are another type of the gate line (GL).

[0062]

[70] The data line (DL) may be disposed so as to pass through the bending region (BA), and various data lines (DL) may be disposed and connected to the data pad (PAD).

[0063]

[71] The bending region (BA) may be a region where the substrate (101) is bent. The substrate (101) is maintained in a flat state in a region excluding the bending region (BA).

[0064]

[72] FIG. 2 is a pixel circuit diagram of a sub-pixel proposed in an embodiment of the present invention. As an example, a pixel circuit diagram composed of seven thin film transistors and one storage capacitor is disclosed. Among the seven thin film transistors, one may be a driving thin film transistor, and the rest may be switching thin film transistors for internal compensation (e.g., threshold voltage and / or mobility) of the thin film transistors, but the present invention is not limited thereto.

[0065]

[73] As an example, in the present invention, the driving thin film transistor (D-TFT) may use an oxide semiconductor pattern as an active layer, and the rest may be switching thin film transistors using an oxide semiconductor pattern as an active layer. Also, at least one of the switching thin film transistors for internal compensation may use a polycrystalline semiconductor pattern as an active layer. However, the present invention is not limited to the circuit diagram of the pixel presented in FIG. 2, and various configurations of internal compensation circuits are possible. For example, the number of thin film transistors in the pixel circuit of the present invention may be three or more, and the number of storage capacitors may be one or more. For example, the pixel circuit of the present invention may be a 3T1C pixel circuit including three thin film transistors and one storage capacitor, a 3T2C pixel circuit including three thin film transistors and two storage capacitors, a 5T1C pixel circuit including five thin film transistors and one storage capacitor, a 5T2C pixel circuit including five thin film transistors and two storage capacitors, a 7T2C pixel circuit including seven thin film transistors and two storage capacitors, and so on.

[0066]

[74] FIG. 3 is a cross-sectional view showing a non-display area (NA), particularly a first thin-film transistor (GT) for gate driving disposed in a gate driving unit and using a polycrystalline semiconductor pattern as an active layer, a driving thin-film transistor (DT) composed of an oxide thin-film transistor disposed in a sub-pixel (PX), and a first switching thin-film transistor (ST-1) and a storage capacitor (Cst). However, the embodiments are not limited thereto. As an example, the active layer of the first thin-film transistor (GT) and the active layer of the driving thin-film transistor (DT) may be formed of the same material or different materials.

[0067]

[75] Briefly explaining the cross-sectional configuration of one sub-pixel (PX), it can be divided into a pixel circuit portion (370) disposed on a substrate (101) and constituting the circuit of each sub-pixel, a light-emitting element portion (380) electrically connected to the pixel circuit portion (370), and first and second planarization layers (PLN1, PNL2) that separate the pixel circuit portion (370) and the light-emitting element portion (380) from each other and planarize the upper surface of the pixel circuit portion (370). A sealing portion (328) and a touch panel portion (not shown) may be further disposed on the light-emitting element portion (380).

[0068]

[76] Here, the pixel circuit portion (370) refers to an array portion that includes a driving thin-film transistor (DT), a first switching thin-film transistor (ST-1), and a storage capacitor (Cst) and drives one sub-pixel (PX). The light-emitting element portion (380) includes an anode electrode, a cathode electrode, and a light-emitting layer disposed therebetween, and refers to an array portion for light emission.

[0069]

[77] In FIG. 3, as an example of the pixel circuit portion (370), one driving thin-film transistor (DT), one first switching thin-film transistor (ST-1), and one storage capacitor (Cst) are shown.

[0070]

[78] In particular, in one embodiment of the present invention, the driving thin-film transistor (DT) and at least one first switching thin-film transistor (ST-1) use an oxide semiconductor pattern as an active layer.

[0071]

[79] The oxide thin-film transistor not only has an excellent effect of blocking leakage current, but also has a relatively low manufacturing cost compared to a polycrystalline thin-film transistor. Therefore, in order to reduce power consumption and lower the manufacturing cost, one embodiment of the present invention manufactures a driving thin-film transistor using an oxide semiconductor material, and also manufactures at least one switching thin-film transistor using an oxide semiconductor material.

[0072]

[80] The oxide semiconductor may be an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and these oxides. More specifically, the oxide semiconductor includes, but is not limited to, zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), indium gallium oxide (IGO), etc.

[0073]

[81] In the pixel circuit portion of one sub-pixel, all the thin-film transistors may be configured as oxide thin-film transistors, or only a part of them may be configured as oxide thin-film transistors.

[0074]

[82] However, while it is difficult to ensure the reliability of oxide thin film transistors, polycrystalline thin film transistors have high operating speed and high reliability. Therefore, in one embodiment of the present invention shown in FIG. 3, at least one of the switching thin film transistors and the driving thin film transistor (DT) is manufactured as an oxide thin film transistor, and the thin film transistors constituting the gate driving unit are manufactured as polycrystalline thin film transistors, which will be described as an example.

[0075]

[83] However, the present invention is not limited to the embodiment shown in FIG. 3. That is, in the present invention, all the thin film transistors constituting the sub-pixel may be configured using an oxide semiconductor, and all the thin film transistors constituting the gate driving unit may be configured with polycrystalline semiconductor patterns. Or the thin film transistors constituting the gate driving unit may be configured by mixing oxide thin film transistors and polycrystalline thin film transistors.

[0076]

[84] The substrate (101) may be composed of a multi-layer in which an organic film and an inorganic film are alternately laminated. For example, the substrate (101) may be configured by alternately laminating an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2). As another example, the substrate (101) may include a plastic material having flexibility so as to be bendable. For example, the substrate (101) may include a material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), or cyclic olefin copolymer (COC).

[0077]

[85] A lower buffer layer (301) is formed on the substrate (101). The lower buffer layer (301) is for blocking moisture and the like that penetrates from the outside, and may be formed of a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film is silicon oxide (SiO x ) film or silicon nitride (SiN x) It may be a film. The multilayer inorganic film may be formed by alternately laminating one or more silicon oxide (SiO x ) films, one or more silicon nitride (SiN x ) films, and one or more amorphous silicon (a-Si), but the present invention is not limited thereto.

[0078]

[86] On the lower buffer layer (301), a second buffer layer (not shown) may be further formed to further protect the thin film transistor disposed in the pixel circuit portion (370) from moisture permeation.

[0079]

[87] A first thin film transistor (GT) is formed in the non-display area (NA) on the substrate (101). The first thin film transistor may be a polycrystalline thin film transistor. The first thin film transistor (GT) includes a polycrystalline semiconductor pattern (303) including a channel through which electrons or holes move, a first gate electrode (304), and a first source electrode (317S) and a first drain electrode (317D).

[0080]

[88] The polycrystalline semiconductor pattern (303) includes a first channel region (303C) in the center, and a first source region (303S) and a first drain region (303D) are disposed sandwiching the first channel region (303C).

[0081]

[89] The first source region (303S) and the first drain region (303D) may be regions formed by doping a pure polycrystalline semiconductor pattern with impurity ions of group V or group III, such as phosphorus (P) or boron (B), at a predetermined concentration to make it conductive.

[0082]

[90] The first channel region (303C) maintains the polycrystalline semiconductor material in an intrinsic state and provides a path for electrons and holes to move.

[0083]

[91] On the one hand, the first thin film transistor (GT) includes a first gate electrode (304) overlapping with a first channel region (303C) of the polycrystalline semiconductor pattern (303). A first gate insulating layer (302) is interposed between the first gate electrode (304) and the polycrystalline semiconductor pattern (303). For example, the first gate insulating layer (302) may be an inorganic layer. For example, the first gate insulating layer (302) may be SiO x or SiN x and may include.

[0084]

[92] In an embodiment of the present invention, the first thin film transistor (GT) adopts a top gate method in which the first gate electrode (304) is located on top of the polycrystalline semiconductor pattern (303). By adopting the top gate method, the first thin film transistor (GT) can arrange the second gate electrode (305) of the driving thin film transistor (DT) adopting the bottom gate method and the first gate electrode (304) in the same layer, and has the advantage of being able to be manufactured using one mask. However, the present invention is not limited thereto. For example, the first thin film transistor (GT) may be a bottom gate type or a dual gate type.

[0085]

[93] The first gate electrode (304) is composed of a metallic substance. For example, the first gate electrode (304) can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0086]

[94] A first interlayer insulating layer (307) is deposited on the first gate electrode (304). The first interlayer insulating layer (307) may be composed of silicon oxide (SiO2) or silicon nitride (SiNx). Or it may be composed of a plurality of layers which are these laminates. In particular, the first interlayer insulating layer (307) may include a silicon nitride (SiNx) layer containing minority particles.

[0087]

[95] After forming the first semiconductor pattern (303) (polycrystalline semiconductor pattern) and depositing the first interlayer insulating layer (307) on the first semiconductor pattern (303), when a heat treatment process is performed, hydrogen particles contained in the first interlayer insulating layer (307) penetrate into the first source region (303S) and the first drain region (303D), and the voids in the first semiconductor pattern (303) are filled with hydrogen, which can contribute to improving and stabilizing the conductivity of the polycrystalline semiconductor material. This is also called a hydrogenation process.

[0088]

[96] Further, a first source electrode (317S) and a first drain electrode (317D) are disposed on the first interlayer insulating layer (307).

[0089]

[97] A plurality of inorganic insulating layers may be interposed between the first interlayer insulating layer (307), the first source electrode (317S), and the first drain electrode (317D).

[0090]

[98] The first source electrode (317S) and the first drain electrode (317D) may be electrically connected to the first source region (303S) and the first drain region (303D) through a first contact hole (CH1) and a second contact hole (CH2), respectively. The first contact hole (CH1) and the second contact hole (CH2) may be formed to penetrate the first interlayer insulating layer (307), the second interlayer insulating layer (308), the upper buffer layer (310) (third interlayer insulating layer), and the first gate insulating layer (302).

[0091]

[99] In an embodiment of the present invention with reference to FIG. 3, the first interlayer insulating layer (307) can function as a separation insulating film. That is, a driving thin film transistor (DT) including an oxide semiconductor pattern and a first switching thin film transistor (ST-1) can be formed on the first interlayer insulating layer (307). Thereby, the first interlayer insulating layer (307) can serve as a separation insulating film that insulates the polycrystalline semiconductor pattern (303) and the oxide semiconductor pattern from each other.

[0092]

[0100] When the first interlayer insulating layer (307) includes a silicon nitride (SiNx) layer containing hydrogen particles, the first interlayer insulating layer (307) may be configured in a procedure where a silicon nitride (SiNx) layer and a silicon oxide (SiO2) layer are laminated thereon. The hydrogen particles contained in the silicon nitride (SiNx) layer can contribute to the conductivity of the polycrystalline semiconductor pattern, but they may also reduce the oxide vacancies in the oxide semiconductor and impair the reliability of the oxide semiconductor. Therefore, when an oxide semiconductor pattern is formed on the first interlayer insulating layer (307), the lamination procedure of the inorganic insulating layer can be selected so that the oxide semiconductor pattern is formed directly on the silicon oxide (SiO2) layer.

[0093]

[0101] The first source electrode (317S) and the first drain electrode (317D) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0094]

[0102] On the other hand, the driving thin film transistor (DT) is formed on the first interlayer insulating layer (307).

[0095]

[0103] In one embodiment of the present invention, a driving thin film transistor (DT) includes a first oxide semiconductor pattern (311). The first oxide semiconductor pattern (311) includes a channel region (311C), a source region (311S), and a drain region (311D). In one embodiment, the source region (311S) is at a first end of the channel region (311C), and the drain region (311D) is at a second end opposite to the first end of the channel region (311C). A source electrode (319S) is connected to the source region (311S) of the first oxide semiconductor pattern (311), and a drain electrode (319D) is connected to the drain region (311D) of the first oxide semiconductor pattern (311). A gate electrode (305) overlaps with a first side of the first oxide semiconductor pattern (311). In one embodiment, a dummy electrode (315) overlaps with a second side opposite to the first side of the first oxide semiconductor pattern (311).

[0096]

[0104] Conventionally, a polycrystalline thin film transistor, which is advantageous for high-speed operation, has been used as a driving thin film transistor (DT). However, the polycrystalline thin film transistor has a problem in that a large amount of power is consumed because a leakage current occurs in the off state. Therefore, a driving thin film transistor (DT) using an oxide semiconductor pattern advantageous for blocking the occurrence of leakage current as an active layer is proposed in one embodiment of the present invention.

[0097]

[0105] However, in the case of an oxide thin film transistor, due to the material characteristics of the oxide semiconductor, a defect often occurs in a low gradation region that requires precise current control because the current variation value with respect to the unit voltage variation value is large. Therefore, in one embodiment of the present invention, a driving thin film transistor is provided in which the current variation value is relatively insensitive to the variation value of the voltage applied to the gate electrode in the active layer.

[0098]

[0106] Referring to FIG. 3, the driving thin film transistor (DT) includes a first oxide semiconductor pattern (311) on a first interlayer insulating layer (307), a second interlayer insulating layer (308) covering the first oxide semiconductor pattern (311), a second gate electrode (305) disposed below the first oxide semiconductor pattern (311 with the first interlayer insulating layer (307) interposed therebetween), a dummy electrode (315) disposed on the second interlayer insulating layer (308), a third interlayer insulating layer (310) covering the dummy electrode (315), and a second source electrode (319S) and a second drain electrode (319D) disposed on the third interlayer insulating layer (310).

[0099]

[0107] The first oxide semiconductor pattern (311) includes a second channel region (311C) in the center, and a second source region (311S) and a second drain region (311D) disposed on both sides of the second channel region (311C) and facing each other.

[0100]

[0108] The second source electrode (319S) and the second drain electrode (319D) are connected to the second source region (311S) and the second drain region (311D) via a third contact hole (CH3) and a fourth contact hole (CH4), respectively.

[0101]

[0109] In particular, the dummy electrode (315) is disposed on the first oxide semiconductor pattern (311) and is disposed so as to partially overlap the first oxide semiconductor pattern (311). Also, the dummy electrode (315) is electrically connected to either one of the second source electrode (319S) or the second drain electrode (319D).

[0102]

[0110] The dummy electrode (315) serves to protect the first oxide semiconductor pattern (311) from hydrogen particles that can flow in from above the first oxide semiconductor pattern (311). Therefore, the dummy electrode (315) may contain a titanium (Ti) material having a trapping ability for hydrogen particles. For example, the dummy electrode (315) may be a single layer of titanium, or a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, without being limited thereto, other metal layers containing titanium (Ti) are also possible.

[0103]

[0111] When the dummy electrode (315) is connected to either one of the second source electrode (319S) or the second drain electrode (319D), the following further effects can be obtained. (For the sake of explanation, it will be described as being connected to the second source electrode)

[0104]

[0112] This will be described with reference to FIGS. 4A and 4B.

[0105]

[0113] FIG. 4A is a cross-sectional view showing only the driving thin film transistor (DT) separated in FIG. 3. FIG. 4B is a circuit diagram showing the relationship between the parasitic capacitance generated in the driving thin film transistor (DT) and the applied voltage.

[0106]

[0114] Referring to FIG. 4A, due to the conduction of the second source region (311S) and the second drain region (311D), a parasitic capacitance Cact is generated inside the first oxide semiconductor pattern (311), a parasitic capacitance Cgi is generated between the second gate electrode (305) and the first oxide semiconductor pattern (311), and a parasitic capacitance Cbuf is generated between the dummy electrode (315) electrically connected to the second source electrode (319S) and the first oxide semiconductor pattern (311).

[0107]

[0115] Since the first oxide semiconductor pattern (311) and the dummy electrode (315) are electrically connected by the second source electrode (319S), the parasitic capacitance Cact and the parasitic capacitance Cbuf are connected in parallel to each other, and the parasitic capacitance Cact and the parasitic capacitance Cgi are connected in series. Also, when a gate voltage Vgat is applied to the second gate electrode (305), the effective voltage Veff actually applied to the first oxide semiconductor pattern (311) satisfies the following Equation 1.

[0108]

[0116] TIFF2025090651000002.tif13170

[0117] Here, Cgi represents the parasitic capacitance between the second gate electrode (305) and the first oxide semiconductor pattern (311), Cact represents the parasitic capacitance of the first oxide semiconductor pattern (311), and Cbuf represents the parasitic capacitance between the dummy electrode (315) and the first oxide semiconductor pattern (311). ΔVgat represents the change in the voltage actually applied to the second gate electrode (305), and ΔV represents the change in the effective voltage Veff actually applied to the first oxide semiconductor pattern (311).

[0109]

[0118] Therefore, the effective voltage applied to the channel of the first oxide semiconductor pattern (311) is in an inverse proportional relationship with the parasitic capacitance Cbuf, and by adjusting the parasitic capacitance Cbuf, the effective voltage applied to the first oxide semiconductor pattern (311) can be adjusted.

[0110]

[0119] That is, when the dummy electrode (315) is arranged near the first oxide semiconductor pattern (311) to increase the parasitic capacitance Cbuf value, the actual current value flowing through the first oxide semiconductor pattern (311) can be decreased.

[0111]

[0120] The fact that the effective current value flowing through the first oxide semiconductor pattern (311) decreases means that the control range of the driving thin film transistor (DT) that can be controlled by the gate voltage Vgat actually applied to the second gate electrode (305) becomes wider.

[0112]

[0121] Therefore, in one embodiment of the present invention with reference to FIG. 3, the dummy electrode (315) is disposed closer to the first oxide semiconductor pattern (311), and the range in which the driving thin film transistor (DT) controls gradation is widened. As a result, the light emitting element can be precisely controlled even at low gradations, and the problem of screen unevenness that often occurs at low gradations can be solved. Similarly, since the effective voltage applied to the channel of the first oxide semiconductor pattern (311) is inversely proportional to the parasitic capacitance Cgi, the effective voltage applied to the first oxide semiconductor pattern (311) can be controlled by controlling the parasitic capacitance Cgi.

[0113]

[0122] Therefore, in this embodiment, the parasitic capacitance Cbuf value may be larger than the parasitic capacitance Cgi value.

[0114]

[0123] On the other hand, the first switching thin film transistor (ST-1) includes a second oxide semiconductor pattern (312) formed on the first interlayer insulating layer (307), a third gate electrode (306A) disposed below the second oxide semiconductor pattern (312), a second interlayer insulating layer (308) and a third interlayer insulating layer (310) covering the second oxide semiconductor pattern (312), and a third source electrode (318S) and a third drain electrode (318D) formed on the third interlayer insulating layer (310).

[0115]

[0124] The second oxide semiconductor pattern (312) includes a third channel region (312C) in the center and a third source region (312S) and a third drain region (312D) disposed on both sides of the third channel region (312C).

[0116]

[0125] The third source electrode (318S) and the third drain electrode (318D) are connected to the third source region (312S) and the third drain region (312D) via a sixth contact hole (CH6) and a seventh contact hole (CH7), respectively.

[0117]

[0126] In particular, the second gate electrode (305) and the third gate electrode (306A) are respectively disposed under the first oxide semiconductor pattern (311) and the second oxide semiconductor pattern (312), and also function to protect the oxide semiconductor patterns from light that may flow in from the lower portions of the oxide semiconductor patterns.

[0118]

[0127] Further, the first gate electrode (304), the second gate electrode (305), and the third gate electrode (306A) can be disposed on the same layer and can be formed simultaneously using one mask. That is, there is an advantage in that the number of mask processes can be reduced.

[0119]

[0128] On the other hand, the first source electrode (317S), the first drain electrode (317D), the second source electrode (319S), the second drain electrode (319D), the third source electrode (318S), and the third drain electrode (318D) may be disposed on the same layer. That is, all of the source electrodes and the drain electrodes may be disposed on the third interlayer insulating layer (310). Therefore, there is an advantage in that the source electrodes and the drain electrodes can be formed simultaneously using one mask, and the number of mask processes can be reduced.

[0120]

[0129] On the other hand, referring to FIG. 3, one sub-pixel according to an embodiment of the present invention further includes a storage capacitor (Cst).

[0121]

[0130] The storage capacitor (Cst) stores a data voltage applied via a data line for a certain period and then provides it to the light-emitting element.

[0122]

[0131] The storage capacitor (Cst) includes two electrodes corresponding to each other and a dielectric disposed therebetween. The storage capacitor (Cst) includes a first electrode (309A) of the storage capacitor (Cst) formed of the same material as the polycrystalline semiconductor pattern (303) and made conductive, and a second electrode (309B) of the storage capacitor (Cst) made of the same material as the first gate electrode (304) and disposed on the same layer as the first electrode (309A).

[0123]

[0132] A first gate insulating layer (302) is interposed between a first electrode (309A) of the storage capacitor (Cst) and a second electrode (309B) of the storage capacitor (Cst).

[0124]

[0133] Among the storage capacitors (Cst), the second electrode (309B) of the storage capacitor may be electrically connected to the second source electrode (319S) through an eighth contact hole (CH8) formed so as to penetrate the first interlayer insulating layer (307), the second interlayer insulating layer (308), and the upper buffer layer (310) (third interlayer insulating layer).

[0125]

[0134] On the other hand, the contact holes, that is, the first contact hole (CH1) to the eighth contact hole (CH8) may be formed simultaneously using one mask. As a result, it is possible to reduce the use of a plurality of masks for forming a plurality of different contact holes and shorten the process.

[0126]

[0135] By simultaneously forming the first contact hole (CH1) to the eighth contact hole (CH8) using one mask, the first source electrode (317S), the first drain electrode (317D), the second source electrode (319S), and the second drain electrode (319D) can be simultaneously formed on the third interlayer insulating layer (310). Thereby, it is possible to obtain the effect of reducing the number of masks and shortening the process.

[0127]

[0136] The configuration of the pixel circuit portion (370) constituting the sub-pixel according to an embodiment of the present invention has been described above. Since the pixel circuit portion (370) according to an embodiment of the present invention is composed of a plurality of thin film transistors including different types of semiconductor materials, it has a plurality of layers and must use a large number of masks. Therefore, it can be seen that the configuration has a plurality of layers formed simultaneously so as to reduce the number of masks used in an embodiment of the present invention.

[0128]

[0137] That is, the polycrystalline semiconductor pattern (303) constituting the first thin film transistor (GT) and the first electrode (309A) of the storage capacitor may be simultaneously formed on the same layer.

[0129]

[0138] Also, the first gate electrode (304), the second gate electrode (305), the third gate electrode (306A), and the second electrode (309B) of the storage capacitor may be simultaneously formed on the same layer.

[0130]

[0139] Also, the first oxide semiconductor pattern (311) and the second oxide semiconductor pattern (312) may be simultaneously formed on the same layer.

[0131]

[0140] Also, the first source electrode (317S), the first drain electrode (317D), the second source electrode (319S), the second drain electrode (319D), the third source electrode (318S), and the third drain electrode (318D) may be simultaneously formed on the same layer.

[0132]

[0141] On the other hand, referring to FIG. 3, a first planarization layer (PLN1) and a second planarization layer (PLN2) may be sequentially formed on the pixel circuit portion (370) in order to planarize the upper end of the pixel circuit portion (370). A fourth interlayer insulating layer (313) may be further formed before the first planarization layer (PLN1) is formed. However, the formation of the fourth interlayer insulating layer (313) is not essential.

[0133]

[0142] The light emitting element portion (380) includes a first electrode (323) as an anode electrode, a second electrode (327) which is a cathode electrode corresponding to the first electrode (323), and a light emitting layer (325) interposed between the first electrode (323) and the second electrode (327). The first electrode (323) is formed for each sub-pixel. That is, each of the plurality of sub-pixels has the first electrode (323), and the plurality of sub-pixels commonly have the second electrode (327), but the present invention is not limited thereto. For example, the light emitting layer (325) may be embodied as an inorganic light emitting device layer such as a micro LED.

[0134]

[0143] On the one hand, the light-emitting element portion (380) is connected to the pixel circuit portion (370) via a connection electrode (321) formed on the first planarization layer (PLN1). In particular, the first electrode (323) of the light-emitting element portion (380) and the second drain electrode (319D) of the driving thin-film transistor (DT) constituting the pixel circuit portion (370) may be electrically connected to each other by a connection electrode (321) filled in a ninth contact hole (CH9) formed so as to penetrate the fourth interlayer insulating layer (313) and the first planarization layer (PLN1).

[0135]

[0144] The first electrode (323) is connected to the connection electrode (321) via a tenth contact hole (CH10) penetrating the second planarization layer (PLN2).

[0136]

[0145] The first electrode (323) may be formed in a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film is made of a material with a relatively large work function value such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film may be a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. For example, the first electrode (323) may be formed in a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are laminated in this order, or may be formed in a structure in which a transparent conductive film and an opaque conductive film are laminated in this order. The first electrode (323) may supply holes to the light-emitting layer (325). The type of the first electrode (323) is not particularly limited as long as it can supply holes to the light-emitting layer (325).

[0137]

[0146] The light-emitting layer (325) is formed by laminating a hole-related layer, an organic light-emitting layer, and an electron-related layer in this order or in the reverse order on the first electrode (323). For example, the light-emitting layer (325) may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but the present invention is not limited thereto.

[0138]

[0147] The bank layer (324) is a pixel definition film that exposes the first electrode (323) of each sub-pixel. The bank layer (324) may be formed of an opaque material (e.g., black) so as to prevent light interference between adjacent sub-pixels. In this case, the bank layer (324) includes a light-shielding material composed of at least any one of a color pigment, organic black, and carbon. A spacer (326) may be further disposed on the bank layer (324). The spacer (326) can secure a gap between the fine metal mask and the first electrode (323) so that the fine metal mask does not contact the first electrode (323) in the deposition process of the light-emitting layer (325).

[0139]

[0148] The second electrode (327), which is a cathode electrode, faces the first electrode (323) with the light-emitting layer (325) interposed therebetween, and is formed on the upper surface and side surface of the light-emitting layer (325). The second electrode (327) may be integrally formed over the entire active region. When applied to a surface-emitting type organic electroluminescent display device, the second electrode (327) may be made of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

[0140]

[0149] A sealing portion (328) that inhibits the penetration of moisture is disposed on the second electrode (327).

[0141]

[0150] The sealing portion (328) may include a first inorganic sealing layer (328a), a second organic sealing layer (328b), and a third inorganic sealing layer (328c) that are laminated in order.

[0142]

[0151] The first inorganic encapsulation layer (328a) and the third inorganic encapsulation layer (328c) may be formed of an inorganic substance such as silicon oxide (SiOx). The second organic encapsulation layer (328b) may be formed of an organic substance such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. However, the substances forming the first inorganic encapsulation layer (328a), the second organic encapsulation layer (328b), and the third inorganic encapsulation layer (328c) are not limited thereto.

[0143] On the other hand, the encapsulation portion (328) is not limited to three layers. For example, the encapsulation portion (328) may include n layers (n is an integer of 3 or more) in which an inorganic encapsulation layer and an organic encapsulation layer are alternately laminated.

[0152] Although not shown in FIG. 3, a touch panel may be further disposed on the encapsulation portion (328).

[0144]

[0153] Thus far, with reference to FIG. 3, among the plurality of thin film transistors disposed in the sub-pixel of the display region (AA), the driving thin film transistor (DT) including an oxide semiconductor pattern, the first switching thin film transistor (ST-1) using the oxide semiconductor pattern, and the first thin film transistor (GT) disposed in the gate in-panel region of the non-display region (NA) and including a polycrystalline semiconductor pattern have been described for the first embodiment of the present invention.

[0145]

[0154] However, in the present invention, switching thin film transistors having different structures from each other may be disposed in the sub-pixel.

[0146]

[0155] Hereinafter, with reference to FIG. 5, a case where the first switching thin film transistor (ST-1) and the second switching thin film transistor (ST-2) having different structures from each other are provided will be described.

[0147]

[0156] For the same configurations as those in the first embodiment of the present invention with reference to FIG. 3, the description thereof will be omitted, and the description will focus on the differences.

[0148]

[0157] Referring to FIG. 5, the first thin film transistor (GT) disposed in the non-display area (NA) may be the same as that in the first embodiment with reference to FIG. 3. Also, the driving thin film transistor (DT) disposed in the sub-pixel of the display area (AA) may have the same configuration as that in the first embodiment with reference to FIG. 3.

[0149]

[0158] Referring to FIG. 2, the sub-pixel includes an internal compensation circuit including a plurality of switching thin film transistors. Among them, the second switching thin film transistor (T3) connected to the gate node of the driving thin film transistor (DT) operates very sensitively to the driving voltage compared to other switching thin film transistors, which causes initial luminance unevenness of the sub-pixel. To solve this, it is necessary to increase the threshold voltage of the second switching thin film transistor (T3).

[0150]

[0159] Therefore, the internal compensation circuit of the present invention may include a second switching thin film transistor (ST-2) having a higher threshold voltage among the switching thin film transistors.

[0151]

[0160] Referring to FIG. 5, the first switching thin film transistor (ST-1) shows a switching thin film transistor whose threshold voltage is not adjusted, and the second switching thin film transistor (ST-2) shows a structure in which the threshold voltage is higher than that of the first switching thin film transistor (ST-1).

[0152]

[0161] In an oxide thin film transistor, a parasitic capacitance is generated between the gate electrode and the active pattern. When the distance between the gate electrode and the active pattern becomes longer, the parasitic capacitance becomes smaller, and as a result, the threshold voltage becomes higher.

[0153]

[0162] Therefore, referring to FIG. 5, the fourth gate electrode (306B) of the second switching thin film transistor (ST-2) is located further away from the second oxide semiconductor pattern (312) than the third gate electrode (306A) of the first switching thin film transistor (ST-1).

[0154]

[0163] That is, the fourth gate electrode (306B) is disposed on the first gate insulating layer (302) that is on the same layer as the first gate electrode (304), and the third gate electrode (306A) is disposed on the first interlayer insulating layer (307) deposited on the first gate insulating layer (302). Also, the second oxide semiconductor pattern (312) is disposed on the second gate insulating layer (314) deposited on the first interlayer insulating layer (307). Therefore, the distance between the second oxide semiconductor pattern (312) and the fourth gate electrode (306B) of the second switching thin film transistor (ST-2) can be configured to be further than the distance between the second oxide semiconductor pattern (312) and the third gate electrode (306A) of the first switching thin film transistor (ST-1).

[0155]

[0164] For reference, components having the same configuration in the first switching thin film transistor (ST-1) and the second switching thin film transistor (ST-2) are denoted by the same reference numerals for convenience of explanation.

[0156]

[0165] The second switching thin film transistor (ST-2) may be an example of a sampling switching transistor connected to the gate node of the driving thin film transistor (DT), and the first switching thin film transistor (ST-1) may be an example of other switching thin film transistors.

[0157]

[0166] Also, in the second embodiment of the present invention with reference to FIG. 5, the storage capacitor (Cst) may include a first electrode (309A) of the storage capacitor disposed on the same layer as the fourth gate electrode (306B) and a second electrode (309B) of the storage capacitor (Cst) disposed on the first interlayer insulating layer (307).

[0158]

[0167] The fourth gate electrode (306B) and the first electrode (309A) of the storage capacitor may be formed using one mask on the first gate insulating layer (302).

[0159]

[0168] Further, the second gate electrode (305) of the driving thin film transistor (DT), the third gate electrode (306A) of the first switching thin film transistor (ST-1), and the second electrode (309B) of the storage capacitor may be formed using one mask on the first interlayer insulating layer (307).

[0160]

[0169] Referring to FIG. 5, as a result, all the thin film transistors disposed in the subpixel can have a bottom gate structure in which the gate electrode is disposed under the active pattern.

[0161]

[0170] On the other hand, the switching thin film transistor in the subpixel of the present invention can have a dual gate structure.

[0162]

[0171] Referring to FIG. 6, the switching thin film transistor can have a dual gate structure in which gate electrodes are respectively provided above and below the active pattern.

[0163]

[0172] Referring to FIG. 6, since the configurations of the first thin film transistor (GT), the storage capacitor (Cst), and the driving thin film transistor (DT) are the same as those of the subpixel referring to FIG. 5, the description thereof is omitted.

[0164]

[0173] Although only one switching thin film transistor is shown in FIG. 6 for convenience of explanation, all the switching thin film transistors in the subpixel can have the same structure. However, switching thin film transistors having different structures from each other as in FIG. 5 may be mixed in one subpixel.

[0165]

[0174] Referring to FIG. 6, it is explained that the first switching thin film transistor (ST-1) constituting the sub-pixel can have a dual gate structure.

[0166]

[0175] The first switching thin film transistor (ST-1) includes a third gate electrode (306A) disposed below the second oxide semiconductor pattern (312) and a fifth gate electrode (306C) disposed above the second oxide semiconductor pattern (312). In some embodiments, the third gate electrode (306A) overlaps with the first side of the second oxide semiconductor pattern (312), and the fifth gate electrode (306C) overlaps with the second side opposite to the first side of the second oxide semiconductor pattern (312). The third gate electrode (306A) and the fifth gate electrode (306C) may be electrically connected to each other.

[0167]

[0176] When the switching thin film transistor is configured to have a dual gate, the mobility of the channel can be increased, and more current can flow. By protecting the active layer from external light, the stability of the thin film transistor can be enhanced.

[0168]

[0177] A plurality of switching thin film transistors are arranged in the sub-pixel, and all the switching thin film transistors except the driving thin film transistor (DT) in the sub-pixel can be manufactured with a dual gate structure.

[0169]

[0178] Also, as shown in FIG. 5, when some of the switching thin film transistors in the sub-pixel are configured with the same structure as the first switching thin film transistor (ST-1) and some other switching thin film transistors are configured with the same structure as the second switching thin film transistor (ST-2), all the switching thin film transistors in the sub-pixel can have a dual gate structure.

[0170]

[0179] Referring to FIG. 6, the third gate electrode (306A) may be formed of the same material in the same layer as the second gate electrode (305) of the driving thin film transistor (DT). That is, the third gate electrode (306A) and the second gate electrode (305) are formed on the first interlayer insulating layer (307).

[0171]

[0180] Further, the fifth gate electrode (306C) and the dummy electrode (315) may be formed of the same material on the same layer. That is, the fifth gate electrode (306C) and the dummy electrode (315) are formed on the second interlayer insulating layer (308).

[0172]

[0181] Thus, the third gate electrode (306A) and the second gate electrode (305) can be formed simultaneously using one mask, and the fifth gate electrode (306C) and the dummy electrode (315) can be formed simultaneously using one mask, so that the effect of shortening the process can be obtained.

[0173]

[0182] On the other hand, referring to FIG. 7, some of the thin film transistors disposed in the non-display area (NA) of the present invention can also be configured with CMOS. That is, referring to FIG. 7, a P-type first thin film transistor (GT) including a polycrystalline semiconductor pattern and an N-type third switching thin film transistor (ST-3) including an oxide semiconductor pattern may be complementary to each other to form CMOS.

[0174]

[0183] The third switching thin film transistor (ST-3) can have the same structure as the first switching thin film transistor (ST-1).

[0175]

[0184] In FIG. 7, an example is shown in which the third switching thin film transistor (ST-3) adopts the same structure as the first switching thin film transistor (ST-1) having the dual gate structure shown in FIG. 6. However, the third switching thin film transistor (ST-3) can also have a single gate structure like the first switching thin film transistor (ST-1) shown in FIG. 5.

[0176]

[0185] Also, referring to FIG. 8, the second interlayer insulating layer (308) disposed between the first oxide semiconductor pattern (311) and the dummy electrode (315) may also be composed of a plurality of inorganic insulating layers having a high dielectric constant.

[0177]

[0186] On the other hand, referring to FIG. 8, the second interlayer insulating layer (308) may be formed by laminating a first sub-second interlayer insulating layer (308a) made of a silicon oxide film (SiO2) and a second sub-second interlayer insulating layer (308b) made of a fluorine silicon nitride film (SiN:F). The dielectric constant of the silicon oxide film (SiO2) is about 4.5, while the dielectric constant of the fluorine silicon nitride film (SiN:F) is about 7. Therefore, when the second interlayer insulating layer (308) is composed of multiple layers including the fluorine silicon nitride film (SiN:F), the dielectric constant of the insulating layer can be increased compared to the case of forming a single film of the silicon oxide film (SiO2). That is, in order to form the second interlayer insulating layer (308), by using a laminate of the silicon oxide film (SiO2) and the fluorine silicon nitride film (SiO2) instead of using a single film of the silicon oxide film (SiO2), the thickness of the insulating film can be further reduced.

[0178]

[0187] Further, since the fluorine silicon nitride film (SiN:F) has a low oxygen content in the insulating film, it is suitable for depositing on the oxide semiconductor pattern that is vulnerable to oxygen particles.

[0179]

[0188] Reducing the thickness of the second interlayer insulating layer (308) can increase the parasitic capacitance Cbuf value and, as a result, increase the S-factor, as confirmed by Equation 1.

[0180]

[0189] On the one hand, referring to FIG. 8, the second source electrode (319S) may be connected to the second source region (311S) via the third contact hole (CH3). Also, the second source electrode (319S) is also electrically connected to the dummy electrode (315). At this time, referring to FIG. 8, the second source electrode (319S) may adopt a side contact method in which the second source electrode (319S) contacts the side surface of the dummy electrode (315) so as to be simultaneously connected to the second source region (311S) and the dummy electrode (315) via one contact hole, that is, the third contact hole (CH3). By configuring in this way, the area where the dummy electrode (315) overlaps with the first oxide semiconductor pattern (311) can be increased. Also, the number of contact holes can be reduced.

[0181]

[0190] The above description and the accompanying drawings merely exemplarily show the technical idea of the present invention. For those having ordinary knowledge in the technical field to which the present invention pertains, various modifications or deformations such as combinations, separations, replacements, and changes in the configuration can be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not for limiting the technical idea of the present invention but for explanation. The scope of the technical idea of the present invention is not limited by such embodiments. The protection scope of the present invention should be interpreted according to the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

Description of Reference Numerals

[0182] 100: Display device, 101: Substrate, 102: Display panel 103: Gate driving unit, 104: Data driving unit 370: Pixel circuit portion, 380: Light emitting element portion, 328: Sealing portion ST-1, ST-2, ST-3: First, second, third switching thin film transistors Cst: Storage capacitor DT: Driving thin film transistor 317S, 318S, 319S: Source electrodes, 317D, 318D, 319D: Drain electrodes 304: First gate electrode, 305: Second gate electrode, 306A: Third gate electrode, 306B: Fourth gate electrode, 306C: Fifth gate electrode 303: Polycrystalline semiconductor pattern 311, 312: Oxide semiconductor patterns 315:Dummy electrode

Claims

1. a semiconductor pattern including a channel region, and a source region and a drain region corresponding to each other with the channel region therebetween; a gate electrode overlapping the channel region under the semiconductor pattern; a source electrode and a drain electrode respectively connected to the source region and the drain region on the semiconductor pattern; a dummy electrode on the semiconductor pattern and overlapping the semiconductor pattern, The dummy electrode is connected to one of the source electrode and the drain electrode.

2. The thin film transistor of claim 1 , wherein the semiconductor pattern comprises an oxide semiconductor pattern.

3. a gate insulating layer disposed between the gate electrode and the semiconductor pattern, the gate insulating layer including at least one inorganic insulating layer; a first interlayer insulating layer disposed between the semiconductor pattern and the dummy electrode, the first interlayer insulating layer including at least one inorganic insulating layer; The thin film transistor of claim 1 , wherein the gate insulating layer has a thickness greater than a thickness of the first interlayer insulating layer.

4. a gate insulating layer disposed between the gate electrode and the semiconductor pattern, the gate insulating layer including at least one inorganic insulating layer; a first interlayer insulating layer disposed between the semiconductor pattern and the dummy electrode, the first interlayer insulating layer including at least one inorganic insulating layer; The thin film transistor of claim 1 , wherein the dielectric constant of the first interlayer insulating layer is greater than the dielectric constant of the gate insulating layer.

5. the gate insulating layer includes a silicon oxide thin film; The thin film transistor according to claim 4 , wherein the first interlayer insulating layer includes a fluorine silicon nitride film having a dielectric constant greater than a dielectric constant of the silicon oxide thin film.

6. The thin film transistor of claim 1 , wherein the dummy electrode comprises a conductive metal pattern.

7. the source electrode is connected to the source region and the dummy electrode through one contact hole; The thin film transistor of claim 1 , wherein the dummy electrode is connected to the source electrode through a side contact with the contact hole.

8. The thin film transistor of claim 1 , wherein a parasitic capacitance generated between the dummy electrode and the semiconductor pattern is greater than a parasitic capacitance generated between the semiconductor pattern and the gate electrode.

9. a substrate including a display area and a non-display area disposed around the display area; a first thin film transistor disposed on the substrate, the first thin film transistor including a first semiconductor pattern, a first gate electrode disposed on the first semiconductor pattern, a first source electrode, and a first drain electrode; a second thin film transistor including a second semiconductor pattern disposed on the substrate and disposed in a layer different from the first semiconductor pattern, a second gate electrode disposed under the second semiconductor pattern, and a second source electrode and a second drain electrode disposed over the semiconductor pattern; the display device further comprising: a dummy electrode on the second semiconductor pattern, the dummy electrode being connected to one of the second source electrode and the second drain electrode and overlapping the second semiconductor pattern.

10. 10. The display device of claim 9, further comprising a third thin film transistor including a third semiconductor pattern disposed on the same layer as the second semiconductor pattern, a third gate electrode disposed under the third semiconductor pattern, and a third source electrode and a third drain electrode disposed on the third semiconductor pattern.

11. a fourth thin film transistor including a fourth semiconductor pattern disposed on the same layer as the second semiconductor pattern, a fourth gate electrode disposed under the fourth semiconductor pattern, and a fourth source electrode and a fourth drain electrode disposed on the fourth semiconductor pattern, The display device according to claim 10 , wherein the third gate electrode and the fourth gate electrode are disposed in different layers.

12. The display device according to claim 9 , wherein the first gate electrode and the second gate electrode are disposed on the same layer.

13. a storage capacitor including a first electrode of the storage capacitor disposed on the same layer as the first gate electrode, and a second electrode of the storage capacitor disposed on an upper portion of the first electrode of the storage capacitor, The display device of claim 9 , wherein the second gate electrode is disposed on the same layer as the second electrode of the storage capacitor.

14. a gate insulating layer disposed between the second gate electrode and the second semiconductor pattern, the gate insulating layer including at least one inorganic insulating layer; a first interlayer insulating layer disposed between the second semiconductor pattern and the dummy electrode, the first interlayer insulating layer including at least one inorganic insulating layer; The display device of claim 9 , wherein the gate insulating layer has a thickness greater than a thickness of the first interlayer insulating layer.

15. a gate insulating layer disposed between the second gate electrode and the second semiconductor pattern, the gate insulating layer including at least one inorganic insulating layer; a first interlayer insulating layer disposed between the second semiconductor pattern and the dummy electrode, the first interlayer insulating layer including at least one inorganic insulating layer; The display device according to claim 9 , wherein the first interlayer insulating layer has a dielectric constant greater than a dielectric constant of the gate insulating layer.

16. the gate insulating layer includes a silicon oxide thin film; 16. The display device according to claim 15, wherein the first interlayer insulating layer includes a fluorine silicon nitride film having a dielectric constant larger than a dielectric constant of the silicon oxide thin film.

17. the first semiconductor pattern includes a polycrystalline semiconductor pattern, The display device of claim 11 , wherein at least one of the second semiconductor pattern, the third semiconductor pattern, and the fourth semiconductor pattern includes an oxide semiconductor pattern.

18. The display device according to claim 9 , wherein the first thin film transistor is disposed in the non-display region, and the second thin film transistor is disposed in the display region.

19. The display device of claim 10 , further comprising a fifth gate electrode disposed on the third semiconductor pattern and electrically connected to the third gate electrode.

20. The display device of claim 9 , wherein a parasitic capacitance generated between the dummy electrode and the second semiconductor pattern is greater than a parasitic capacitance generated between the second semiconductor pattern and the second gate electrode.

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