Semiconductor device

Abstract

To provide a semiconductor device that is suitable for microfabrication and high density.SOLUTION: A semiconductor device comprises: a first transistor; a second transistor overlapped with the first transistor; a capacitive element overlapped with the second transistor; and first wiring electrically connected with the capacitive element. The first wiring has a region overlapped with an electrode of the second transistor. The first transistor, the second transistor and the capacitive element are electrically connected with each other. A channel of the first transistor has a single crystal semiconductor. A channel of the second transistor has an oxide semiconductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device having a field effect transistor.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition ·of·matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, a semiconductor device, a display device, a liquid crystal display device, a light emitting device, a lighting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification etc., the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro- optical device, a power generation device (including thin film solar cells, organic thin film solar cells, etc.), and electronic devices may have a semiconductor device.

Background Art

[0004] Techniques for constructing transistors using semiconductor materials have attracted attention. The transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials. ​

[0005] For example, a technique for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as the oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2). Further, in recent years, with the improvement in performance, miniaturization, or weight reduction of electronic devices, the demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density has been increasing. For example,

[0006] Tri-Gate transistors and MIM capacitors with a COB (capacitor over bitline) structure have been introduced (Non-Patent Document 1). Tri-Gate transistor and COB (capacitor over bitline) e) structure MIM capacitor has been introduced (Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] One aspect of the present invention is to provide a semiconductor device suitable for miniaturization and high density as one of the problems. To do so.

[0010] Or, one of the problems is to impart good electrical characteristics to a semiconductor device. Or, reliability One of the problems is to provide a highly reliable semiconductor device. Or, a semiconductor device with a novel configuration is provided.

[0011] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention is not required to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] One aspect of the present invention includes a first transistor, a second transistor overlapping the first transistor, a first capacitive element overlapping the first transistor, a second capacitive element overlapping the second transistor, and a first wiring electrically connected to the second capacitive element, the first wiring having a region overlapping an electrode of the second transistor, and the first transistor, the second transistor, the first capacitive element, and the second capacitive element being electrically connected, the channel of the first transistor having a single-crystalline semiconductor, and the channel of the second transistor having an oxide semiconductor, characterized by a semiconductor device.

[0013] Also, another aspect of the present invention includes a first transistor, a second transistor overlapping the first transistor, a first capacitive element overlapping the first transistor, a second capacitive element overlapping the second transistor, and a first wiring electrically connected to the second capacitive element​ It has the wiring of 1, and the first wiring has a region overlapping with the electrode of the second transistor. The first transistor, the second transistor, the first capacitor element, and the second capacitor element are electrically connected. The channel of the first transistor has a single-crystalline semiconductor, and the channel of the second transistor has an oxide semiconductor. One electrode of the first capacitor element includes a convex portion, and the other electrode of the first capacitor element includes a concave portion. A semiconductor device is characterized by this.

[0014] Also, in the above configuration, it has the second wiring electrically connected to the first capacitor element. The second wiring has a region overlapping with the electrode of the first transistor.

[0015] Also, in the above configuration, the second wiring may have a function as a common wiring.

[0016] Also, in the above configuration, the second wiring preferably contains copper.

[0017] Also, another aspect of the present invention is a first transistor, a second transistor overlapping with the first transistor, a capacitor element overlapping with the second transistor, and a first wiring electrically connecting the capacitor element. The first wiring has a region overlapping with the electrode of the second transistor. The first transistor, the second transistor, and the capacitor element are electrically connected. The channel of the first transistor has a single-crystalline semiconductor, and the channel of the second transistor has an oxide semiconductor. A semiconductor device is characterized by this. Also, another aspect of the present invention is a first transistor, a second transistor overlapping with the first transistor.

[0018] Also, another aspect of the present invention is a first transistor, a second transistor overlapping with the first transistor. a second transistor that becomes, a capacitive element overlapping with the second transistor, and the capacitive element and a first wiring electrically connected thereto, the first wiring having an overlapping region with an electrode of the second transistor, the channel of the first transistor having a single crystal semiconductor, the channel of the second transistor having an oxide semiconductor, the first transistor, the second transistor, and the capacitive element being electrically connected, one electrode of the capacitive element including a convex portion, and the other electrode of the capacitive element including a concave portion, the semiconductor device being characterized in that. Also, in the above configuration, the capacitive element is located between the first transistor and the second transistor. Also, in the above configuration, the capacitive element is located above the second transistor.

[0019] Also, in the above configuration, the electrode of the second transistor is a gate electrode. Also, in the above configuration, it is preferable that the first wiring has a function as a common wiring.

[0020] Also, in the above configuration, the first transistor and the second transistor are connected by a plug, and the plug preferably contains copper or tungsten.

[0021] Also, in the above configuration, it is preferable that the first wiring contains copper.

[0022]

[0023]

[0024]

[0025]

Advantages of the Invention

[0025] According to one aspect of the present invention, a semiconductor device suitable for miniaturization and high density can be provided.

[0026] ​Alternatively, good electrical characteristics can be imparted to the semiconductor device. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with a novel configuration or the like can be provided. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0027]

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Mode for Carrying Out the Invention

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

[0029] In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof will be omitted. In addition, when referring to the same function, the hatch pattern may be the same and may not be particularly labeled.

[0030] In each of the drawings described in this specification, the size of each component, the thickness of the layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0031] The ordinal numbers such as "first" and "second" in this specification are attached to avoid confusion of components and are not numerically limiting.

[0032] A transistor is a type of semiconductor device and can realize operations such as amplification of current or voltage and switching operations for controlling conduction or non-conduction. The transistor in this specification is an IGFET (Insulated Gate Field Effect Trans including an (istor) or a thin film transistor (TFT: Thin Film Transistor )

[0033] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less . Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less . Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less . Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less

[0034] . Also, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system .

[0035] (Embodiment 1) [Configuration Example of Stacked Structure] Hereinafter, an example of a stacked structure applicable to a semiconductor device according to an aspect of the present invention will be described. FIG. 3 is a schematic cross-sectional view of a stacked structure 10 shown below

[0036] The stacked structure 10 has a stacked structure in which a first layer 11 including a first transistor, a first insulating film 21, a first wiring layer 31, a barrier film 41, a second wiring layer 32, a second insulating film 22, and a second transistor including a star are sequentially stacked

[0037] The first transistor included in the first layer 11 is composed of a first semiconductor material . Also, the second transistor included in the second layer 12 is composed of a second semiconductor material This is the case. The first semiconductor material and the second semiconductor material may be the same material, but it is preferable that they are different semiconductor materials. The first transistor and the second transistor each have a semiconductor film, a gate electrode, a gate insulating film, a source electrode, and a drain electrode (or a source region and a drain region).

[0038] For example, semiconductors that can be used as the first semiconductor material or the second semiconductor material include, for example, silicon, silicon carbide, germanium, gallium arsenide, gallium phosphide phosphorus, gallium nitride and other semiconductor materials, typical semiconductor materials of III-V group semiconductor materials as, one or more selected from B, Al, Ga, In, Tl and one or more selected from N, P, As, Sb combined compound semiconductor materials, typical semi- of II-VI group semiconductor materials conductor materials, as one or more selected from Mg, Zn, Cd, Hg and one or more selected from O, S, Se, Te combined compound semiconductor materials, organic semiconductor materials, or oxide semiconductor materials and the like.

[0039] Here, the case where single-crystal silicon is used as the first semiconductor material and an oxide semiconductor is used as the second semiconductor material will be described.

[0040] The barrier film 41 is a layer having a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. Note that the barrier film 41 may have an opening or a plug for electrically connecting an electrode or wiring provided above this and an electrode or wiring provided below it. For example, it has a plug for electrically connecting a wiring or an electrode included in the first wiring layer 31 and a wiring or an electrode included in the second wiring layer 32. ​​​

[0041] As materials used for wirings or electrodes included in the first wiring layer 31 and the second wiring layer 32 in addition to metal or alloy materials, conductive metal nitrides can be used. Also, a layer containing such a material may be used as a single layer or laminated in two or more layers.

[0042] The first insulating film 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. Also, the first insulating film 21 may have openings or plugs for electrically connecting the first transistor, electrode or wiring included in the first layer 11 and the electrode or wiring included in the first wiring layer 31.

[0043] The second insulating film 22 has a function of electrically insulating the second layer 12 and the second wiring layer 32. Also, the second insulating film 22 may have openings or plugs for electrically connecting the second transistor, electrode or wiring included in the second layer 12 and the electrode or wiring included in the second wiring layer 32.

[0044] Also, the second insulating film 22 preferably contains an oxide. In particular, it preferably contains an oxide material from which a part of oxygen is desorbed by heating. Preferably, an oxide containing more oxygen than oxygen satisfying the stoichiometric composition is used. When an oxide semiconductor is used as the second semiconductor material, oxygen desorbed from the second insulating film 22 is supplied to the oxide semiconductor, and it becomes possible to reduce oxygen vacancies in the oxide semiconductor. As a result, fluctuations in the electrical characteristics of the second transistor can be suppressed, and the reliability can be improved.

[0045] Here, in the layer below the barrier film 41, hydrogen, water, etc. should be reduced as much as possible. is preferable. Alternatively, it is preferable to reduce the release of hydrogen, water, etc. as much as possible. Hydrogen and water can be factors that cause fluctuations in the electrical characteristics of oxide semiconductors. Also, hydrogen and water diffusing from the lower layer to the upper layer through the barrier film 41 can be suppressed by the barrier film 41, but hydrogen and water may diffuse into the upper layer through openings, plugs, etc. provided in the barrier film 41. There are cases where this happens.

[0046] To reduce hydrogen and water contained in each layer located below the barrier film 41, or to reduce the release of hydrogen and water, before forming the barrier film 41, or immediately after forming an opening for forming a plug in the barrier film 41, it is preferable to perform a heat treatment for removing hydrogen and water contained in the layer below the barrier film 41. As long as the heat resistance of the conductive film, etc. constituting the semiconductor device and the electrical characteristics of the transistor do not deteriorate, the higher the heat treatment temperature, the more preferable. Specifically, for example, a temperature of 450 °C or higher, preferably 490 °C or higher, more preferably 530 °C or higher may be used, but it may also be performed at 650 °C or higher. In an inert gas atmosphere or under a reduced pressure atmosphere for 1 hour or more, preferably 5 hours or more, more preferably 10 hours or more of heat treatment is preferably performed. Also, the heat treatment temperature may be determined in consideration of the heat resistance of the material of the wiring or electrode contained in the first layer 11 and the first wiring layer 31, and the plug provided in the first insulating film 21. For example, if the heat resistance of the material is low, it may be performed at a temperature of 5 50 °C or lower, or 600 °C or lower, or 650 or lower, or 800 °C or lower. Also, such heat treatment may be performed at least once or more, but it is more preferable to perform it multiple times. preferable. 50 °C or lower, or 600 °C or lower, or 650 or lower, or 800 °C or lower. Also, such heat treatment may be performed at least once or more, but it is more preferable to perform it multiple times. preferable.

[0047] The insulating film provided under the barrier film 41 is analyzed by thermal desorption spectroscopy (TDS analysis). The desorption of hydrogen molecules (m / z=2) at a substrate surface temperature of 400°C, as measured by the The amount of hydrogen desorbed is preferably 130% or less, more preferably 110% or less, of the amount of hydrogen desorbed at 300°C. It is more preferable that the hydrogen molecule is removed by TDS analysis when the substrate surface temperature is 450°C. The amount of hydrogen desorption at 350°C is preferably 130% or less, and more preferably 110% or less. It is more preferable that there is.

[0048] In addition, it is preferable that the water and hydrogen contained in the barrier film 41 itself be reduced. For example, As a barrier film 41, TDS analysis was performed at substrate surface temperatures ranging from 20°C to 600°C. The amount of hydrogen molecules released is 2×10 15 pieces / cm 2 Less than 1 x 10 15 pcs / c m 2 less than 5×10 14 pieces / cm 2 It is preferable to use materials having a viscosity of less than Or, if the TDS analysis shows that the moisture content of the substrate surface is within the range of 20℃ to 600℃, The amount of desorption of the molecule (m / z=18) is 1×10 16 pieces / cm 2 Less than 5 x 10 15 pieces / cm 2 less than 2×10 12 pieces / cm 2 Barrier film material that is less than 41 It is preferable to use it for the following.

[0049] In addition, single crystal silicon is used for the semiconductor film of the first transistor included in the first layer 11. In this case, the heat treatment breaks down the dangling bonds of silicon. It can also serve as a process terminated by hydrogen (also referred to as a hydrogenation process). The hydrogenation process causes a part of the hydrogen contained in the first layer 11 and the first insulating film 21 to desorb and diffuse into the semiconductor film of the first transistor, and by terminating the dangling bonds in silicon, the reliability and static characteristics of the first transistor can be improved.

[0050] Materials that can be used for the barrier film 41 include silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and the like. In particular, aluminum oxide is preferable because of its excellent barrier properties against water and hydrogen.

[0051] In addition to a film made of a material that is difficult to permeate water and hydrogen, the barrier film 41 may be used by laminating a film containing other insulating materials. For example, a film containing silicon oxide or silicon oxynitride, a film containing a metal oxide, or the like may be laminated and used.

[0052] Also, it is preferable to use a material for the barrier film 41 that is difficult to permeate oxygen. The materials described above are materials that have excellent barrier properties against oxygen in addition to hydrogen and water. By using such a material, it is possible to suppress the diffusion of oxygen released when the second insulating film 22 is heated to a layer below the barrier film 41. As a result, the amount of oxygen that can be released from the second insulating film 22 and supplied to the semiconductor film of the second transistor in the second layer 12 can be increased.

[0053] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 41 is reduced. Alternatively, hydrogen and water are removed, and the barrier film 41 prevents the hydrogen and water from diffusing into the second layer. In addition, the barrier film 41 suppresses the release of hydrogen and water. The insulating film 22 and the hydrogen and the like in each layer constituting the second transistor included in the second layer For example, the second insulating film 22 and the second The hydrogen concentration in the semiconductor film or gate insulating film of a transistor is 5×10 18 cm -3 Less than 1 x 10 18 cm -3 less than 3×10 17 cm - 3 It is possible to reduce the

[0054] By applying the stacked structure 10 to the semiconductor device according to one embodiment of the present invention, The first transistor included in the second layer 12 and the second transistor included in the second layer 13 are This makes it possible to achieve high reliability even in high-temperature environments, thereby realizing extremely reliable semiconductor devices. It can be realized.

[0055] [Configuration example] FIG. 1A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a first transistor 110, a second transistor 100, and a capacitor element 1. 30, wiring SL, wiring BL, wiring WL, and wiring CL.

[0056] The first transistor 110 has a source or a drain electrically connected to a wiring BL. The other end is electrically connected to a wiring SL, and the gate is the source or The second transistor is electrically connected to one of the drain electrodes and one of the electrodes of the capacitor 130. In the transistor 100, one of the source or drain is electrically connected to the wiring BL, and the gate is electrically connected to the wiring WL. One electrode of the capacitor element 130 is electrically connected to the wiring CL. Note that the node between the gate of the first transistor 110 and one of the source or drain of the second transistor 100 and one electrode of the capacitor element 130 is called the node FN.

[0057] When the second transistor 100 in the semiconductor device shown in FIG. 1(A) is in the conductive state (on state), a potential corresponding to the potential of the wiring BL is applied to the node FN. Also, when the second transistor 10 0 is in the non-conductive state (off state), it has a function of holding the potential of the node FN. That is, the semiconductor device shown in FIG. 1(A) has a function as a memory cell of a memory device. In addition When the semiconductor device has a display element such as a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to the node FN, the semiconductor device in FIG. 1(A) can also function as a pixel of a display device.

[0058] The selection of the conductive state and non-conductive state of the second transistor 100 can be controlled by the potential applied to the wiring WL. Also, the threshold voltage of the second transistor 100 can be controlled by the potential applied to the wiring WL. By using a transistor with a small off-current as the second transistor 100, the potential of the node FN in the non-conductive state can be held over a long period of time. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. Note that, as an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be cited. ​

[0059] Note that a fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the second transistor 100 varies depending on the potential of the node FN. By utilizing the change in the conduction state and non-conduction state of the first transistor 110 due to the variation in the apparent threshold voltage, the information of the potential held at the node FN can be read out as data. 0

[0060] In the semiconductor device according to one aspect of the present invention, since the hydrogen concentration in the layer below the barrier film is sufficiently reduced or the diffusion and release of the hydrogen concentration are suppressed, as a result, a transistor using an oxide semiconductor in the upper layer thereof can achieve an extremely low off-current.

[0061] By arranging the semiconductor devices shown in FIG. 1(A) in a matrix, a memory device (memory cell array) can be configured.

[0062] FIG. 1(B) shows an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. 1(A). Further, FIG. 2(A) shows a top view of arranging the semiconductor devices of FIG. 1(B) side by side. Note that each semiconductor device shares a wiring CL having a function as a common wiring.

[0063] As shown in FIG. 2(A), the second transistor 100 and the capacitor element 130 are provided within the occupied area of the first transistor 110. Further, when arranging the semiconductor devices in a matrix, as shown in FIG. 2(B), the wiring SL (low resistance layer 113b) may be shared with an adjacent semiconductor device.

[0064] As shown in FIG. 1(B), the semiconductor device includes a first transistor 110, a second transistor 100, and a capacitor element 130. The second transistor 100 is provided above the first transistor 110, and a barrier film 120 is provided between the first transistor 110 and the second transistor 100. The first transistor 110 is provided on a semiconductor substrate 111 and includes a semiconductor film 112 formed of a part of the semiconductor substrate 111, a gate insulating film 114, a gate electrode 115, and low resistance layers 113a and 113b that function as a source region or a drain region. The first transistor 110 may be either a p-channel type or an n-channel type, and an appropriate transistor may be used according to the circuit configuration and driving method. In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor).

[0065] The first transistor 110 may be either a p-channel type or an n-channel type, and an appropriate transistor may be used according to the circuit configuration and driving method. In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). The first transistor 110 may be either a p-channel type or an n-channel type, and an appropriate transistor may be used according to the circuit configuration and driving method.

[0066] The first transistor 110 may be either a p-channel type or an n-channel type, and an appropriate transistor may be used according to the circuit configuration and driving method. In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor).

[0067] In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor). In a region where the channel of the semiconductor film 112 is formed, a region in the vicinity thereof, and the low resistance layers 113a and 113b that serve as a source region or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs, GaAlAs, etc., the first transistor 110 may be a HEMT (High Electron Mobility Transistor).

[0068] The low-resistance layers 113a and 113b are made of a semiconductor material applied to the semiconductor film 112 and contain an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0069] The gate electrode 115 can be made of a conductive material such as a semiconductor material like silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. To adjust the threshold voltage, it is preferable to adjust the work function using the gate electrode. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the gate electrode. Furthermore, to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum laminated on the gate electrode. In particular, using tungsten is preferable in terms of heat resistance. Here, the configuration including the first transistor 110 corresponds to the first layer 11 in the stacked structure 10.

[0070] Here, instead of the first transistor 110, a transistor 160 as shown in FIG. 4 may be used. The cross-section in the channel length direction of the transistor 160 is shown to the left of the dashed-dotted line in FIG. 4,

[0071] and the cross-section in the channel width direction is shown to the right of the dashed-dotted line. The transistor 160 shown in FIG. 4 has a convex shape in the semiconductor film 112 (a part of the semiconductor substrate) where the channel is formed, and a gate insulating film 114, a gate electrode 115a, and a gate electrode 115b are provided along its side surface and upper surface. Note that the gate electrode 115a may use a material for adjusting the work function. In this way, along the side surface and upper surface of the convex semiconductor film 112 (a part of the semiconductor substrate) where the channel is formed, a gate insulating film 114, a gate electrode 115a, and a gate electrode 115b are provided. Note that the gate electrode 115a may use a material for adjusting the work function. The transistor 160 is a FIN type transistor because it uses a protruding portion of a semiconductor substrate. It is also called a mask that comes into contact with the top of the protrusion and functions as a mask for forming the protrusion. The semiconductor substrate may have an insulating film. In this embodiment, a part of the semiconductor substrate is processed to form a protrusion. However, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0072] The first transistor 110 is covered with an insulating film 121, an insulating film 122, an insulating film 123, and Insulating films 124 are provided in a layered manner.

[0073] When the semiconductor film 112 is made of a silicon-based semiconductor material, the insulating film 122 contains hydrogen. It is preferable that the insulating film 122 containing hydrogen is provided over the first transistor 110 and heat treatment is performed. By this, the dangling bonds in the semiconductor film 112 are terminated by hydrogen in the insulating film 122. As a result, the reliability of the first transistor 110 can be improved.

[0074] The insulating film 123 is a step formed by the first transistor 110 and the like provided below. The upper surface of the insulating film 123 is made of a material such as aluminum, which functions as a planarizing film for planarizing the difference between the thickness of the insulating film 123 and the thickness of the insulating film 123. Chemical Mechanical Polishing (CMP) The surface may be planarized by a planarization process using a method such as a .

[0075] The insulating film 124 may function as a barrier film. It is not necessary to provide such a section.

[0076] In addition, the insulating film 121, the insulating film 122, the insulating film 123, and the insulating film 124 are provided with the low resistance layer 113. a, plugs 161 and 163 electrically connected to the low resistance layer 113b are embedded, A plug 162 or the like that is electrically connected to the gate electrode 115 of the first transistor 110 is embedded. In this specification and the like, an electrode and a wiring that is electrically connected to the electrode may be an integral body. That is, a part of the wiring may function as an electrode, or a part of the electrode may function as a wiring.

[0077] A configuration including the insulating films 121, 122, 123, and 124 corresponds to the first insulating film 21 in the stacked structure 10.

[0078] One electrode 136 of the capacitor element 130 is provided on the upper part of the insulating film 124 and the upper part of the plug 162. The electrode 136 is electrically connected to the plug 162.

[0079] An insulating film 137 is provided on the electrode 136 of the capacitor element 130, and the other electrode 138 of the capacitor element 130 is provided on the insulating film 137. Note that the electrode 138 is electrically connected to the wiring CL. Also, the wiring CL has a region that overlaps with the gate electrode 105 of the second transistor 100.

[0080] Here, a configuration including the electrode 136, the electrode 138, the wiring CL, and the like corresponds to the first wiring layer 31 in the stacked structure 10.

[0081] As materials for each plug (such as plug 161 to plug 163) and each electrode (such as electrode 136, electrode 138), conductive materials such as metal materials, alloy materials, or metal oxide materials can be used. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is particularly preferable to use tungsten. Also, copper or the like It is preferably formed of a low-resistance conductive material.

[0082] In addition, as the material of the wiring CL, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using the above materials, the wiring resistance can be reduced. In addition, as the material of the wiring CL, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using the above materials, the wiring resistance can be reduced. In addition, as the material of the wiring CL, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using the above materials, the wiring resistance can be reduced. 。

[0083] In addition, the electrodes 136, 138, the wiring CL, etc. are preferably provided so as to be embedded in the insulating film 125, and the upper surface of the insulating film 125 is preferably planarized. In addition, the electrodes 136, 138, the wiring CL, etc. are preferably provided so as to be embedded in the insulating film 125, and the upper surface of the insulating film 125 is preferably planarized.

[0084] The barrier film 120 is provided to cover the upper surface of the insulating film 125. The barrier film 120 corresponds to the barrier film 41 in the stacked structure 10. As the material of the barrier film 120, the description of the above barrier film 41 can be incorporated by reference. The barrier film 120 is provided to cover the upper surface of the insulating film 125. The barrier film 120 corresponds to the barrier film 41 in the stacked structure 10. As the material of the barrier film 120, the description of the above barrier film 41 can be incorporated by reference. The barrier film 120 is provided to cover the upper surface of the insulating film 125. The barrier film 120 corresponds to the barrier film 41 in the stacked structure 10. As the material of the barrier film 120, the description of the above barrier film 41 can be incorporated by reference.

[0085] In addition, the barrier film 120 has openings into which the plugs 164, 165, and 166 described later are embedded. In addition, the barrier film 120 has openings into which the plugs 164, 165, and 166 described later are embedded.

[0086] A wiring 132 is provided on the barrier film 120. The configuration including the wiring 132 corresponds to the second wiring layer 32 in the stacked structure 10. A wiring 132 is provided on the barrier film 120. The configuration including the wiring 132 corresponds to the second wiring layer 32 in the stacked structure 10.

[0087] The wiring 132 is provided so as to overlap with the channel formation region of the second transistor 100 described later and functions as the second gate electrode of the second transistor 100. The wiring 132 is provided so as to overlap with the channel formation region of the second transistor 100 described later and functions as the second gate electrode of the second transistor 100.

[0088] Here, as the material constituting the wiring 132, etc., a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, when heat resistance is required, tungsten Here, as the material constituting the wiring 132, etc., a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. In particular, when heat resistance is required, tungsten It is preferable to use high melting point materials such as tungsten and molybdenum. Also, considering conductivity , it is preferable to use a metal material or alloy material with low resistance, such as aluminum, chromium, copper , tantalum, titanium and other metal materials, or alloy materials containing the metal material in a single layer, or they may be used in a laminated form.

[0089] Also, as the material constituting the wiring 132 and the like, it is preferable to use a metal oxide containing an element other than the main component such as phosphorus, boron, carbon, nitrogen, or a transition metal element. Such a metal oxide can achieve high conductivity. For example, materials with enhanced conductivity by incorporating the above-mentioned elements into metal oxides such as In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) can be used.

[0090] An insulating film 126 is provided covering the barrier film 120 and the wiring 132. Here, the region including the insulating film 126 corresponds to the second insulating film 22 in the laminated structure 10.

[0091] The upper surface of the insulating film 126 is preferably flattened by the above-described flattening process.

[0092] The insulating film 126 is preferably made of an oxide material in which a part of oxygen is desorbed by heating .

[0093] As the oxide material that desorbs oxygen by heating, it is preferable to use an oxide containing more oxygen than the oxygen that satisfies the stoichiometric composition. An oxide film containing more oxygen than the oxygen that satisfies the stoichiometric composition desorbs a part of oxygen by heating. Oxygen that satisfies the stoichiometric composition An oxide film containing more oxygen has an oxygen desorption amount, converted to oxygen atoms, of 1.0×10 or more, preferably 3.0×10 or more, as determined by thermal desorption spectroscopy (TDS) analysis. Here, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. 18 atoms / cm 3 20 at oms / cm 3 For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide can also be used. In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. A second transistor 100 is provided above the insulating film 126. The configuration including the second transistor 100 corresponds to the second layer 12 in the stacked structure 10.

[0094] The second transistor 100 includes an insulating film 106a in contact with the upper surface of the insulating film 126, an oxide semiconductor film 101a in contact with the upper surface of the insulating film 106a, an oxide semiconductor film 101b in contact with the upper surface of the oxide semiconductor film 101a, electrodes 103a and 103b that are separated in a region overlapping with the oxide semiconductor film 101b and in contact with the upper surface of the oxide semiconductor film 101b, and an oxide semiconductor film 10 in contact with the upper surface of the oxide semiconductor film 101b, the upper surface of the electrode 103a, and the upper surface of the electrode 103b.

[0095]

[0096] ​​​​​​​​​​​1c, a gate insulating film 104 on the oxide semiconductor film 101c, and a gate electrode 105 overlapping the oxide semiconductor film 101b through the gate insulating film 104 and the oxide semiconductor film 101c. It has. Also, an insulating film 107, an insulating film 108, and an insulating film 127 are provided covering the second transistor 100. It is.

[0097] Also, a plug 164 electrically connected to the plug 161 and the electrode 103a is provided to be embedded in the insulating film 125, the barrier film 120, the insulating film 126, the insulating film 106a, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the electrode 103a. Also, a plug 165 electrically connected to the electrode 136 and the electrode 103b is provided to be embedded in the insulating film 125, the barrier film 120, the insulating film 126, the insulating film 106a, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the electrode 103b. It is. It is. It is. It is. It is.

[0098] Also, an insulating film 106b, an oxide semiconductor film 131a, an oxide semiconductor film 131b, and an electrode 103c are formed simultaneously with the second transistor 100, and a plug 166 electrically connected to the plug 163 and the electrode 103c is provided to be embedded in the insulating film 125, the barrier film 120, the insulating film 126, the insulating film 106b, the oxide semiconductor film 131a, the oxide semiconductor film 131b, and the electrode 103c. It is. It is. It is. It is.

[0099] Here, a node including the gate electrode 115 of the first transistor 110, the electrode 136 of the capacitor element 130, and the electrode 103b of the second transistor 100 corresponds to the node FN shown in FIG. 1(A). It is. It is.

[0100] Note that at least a part (or all) of the electrode 103a (and / or the electrode 103b) ) is provided on at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a).

[0101] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a). Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is in contact with at least a part (or all) of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a).

[0102] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is electrically connected to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a). Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is electrically connected to a part (or all) of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a).

[0103] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is close to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a). ​​​​​​​​​​​​​​Alternatively, at least one of the electrodes 103a (and / or 103b) is arranged in contact with the other. At least a part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film The semiconductor film is disposed adjacent to a part (or the whole) of the semiconductor film, such as 101a.

[0104] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. The lateral side of at least part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is disposed A part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 10 1a) is disposed on the side of a part (or the whole) of a semiconductor film.

[0105] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. Obliquely displace at least a part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane. Alternatively, at least one of the electrodes 103a (and / or 103b) is At least a part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) or the like.

[0106] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. On at least a portion (or all) of the surface, side, upper surface, and / or lower surface of the body membrane It is disposed at. Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) is disposed above at least a part (or all) of a semiconductor film such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a).

[0107] For example, as the above oxide semiconductor, it is preferably contained at least indium (In) or zinc (Zn). More preferably, it contains an oxide represented by an In-M-Zn-based oxide (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf).

[0108] In particular, as the semiconductor film, it is preferable to use an oxide semiconductor film having a plurality of crystal parts, wherein the c-axis of the crystal parts is oriented perpendicular to the surface to be formed of the semiconductor film or the upper surface of the semiconductor film, and there is no grain boundary between adjacent crystal parts.

[0109] By using such a material as the semiconductor film, fluctuations in electrical characteristics can be suppressed, and a highly reliable transistor can be realized.

[0110] Note that preferred forms of the oxide semiconductor applicable to the semiconductor film and its formation method will be described in detail in the following embodiments.

[0111] A semiconductor device according to an aspect of the present invention preferably has a first oxide semiconductor film containing, as a constituent element, at least one of the metal elements constituting the oxide semiconductor film between the oxide semiconductor film and an insulating film overlapping the oxide semiconductor film. Thereby, the formation of trap levels at the interface between the oxide semiconductor film and the insulating film overlapping the oxide semiconductor film can be suppressed. ​​​​​​​​​​​​​

[0112] That is, one embodiment of the present invention is a method for forming an oxide semiconductor film in at least a channel formation region. The top and bottom surfaces of the oxide semiconductor film function as a barrier film for preventing the formation of an interface state of the oxide semiconductor film. It is preferable that the oxide semiconductor film is in contact with the oxide semiconductor film. Prevents the generation of oxygen vacancies and the inclusion of impurities, which are factors that cause carrier generation in conductor films and at interfaces. Since the amount of the oxide semiconductor film that is generated can be suppressed, the oxide semiconductor film can be highly purified and made intrinsic. The term "to be made intrinsic" refers to making the oxide semiconductor film intrinsic or substantially intrinsic. A highly reliable semiconductor device can be obtained by suppressing a change in electrical characteristics of a transistor including the oxide semiconductor film. It will be possible to provide a place for

[0113] Note that in this specification and the like, when an oxide semiconductor film is referred to as being substantially intrinsic, the carrier density of the oxide semiconductor film is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 By purifying the oxide semiconductor film to be intrinsic, the transistor has stable electrical characteristics. It is possible to give the

[0114] The oxide semiconductor film 101a is provided between the insulating film 106a and the oxide semiconductor film 101b. It is being done.

[0115] The oxide semiconductor film 101c is provided between the oxide semiconductor film 101b and the gate insulating film 104. More specifically, the oxide semiconductor film 101c has an upper surface which is in contact with the electrode 103a and the The gate insulating film 104 is provided in contact with the lower surface of the electrode 103 b and the lower surface of the gate insulating film 104 .

[0116] The oxide semiconductor films 101a and 101c each contain an oxide containing one or more of the same metal elements as the oxide semiconductor film 10 1b.

[0117] Note that the boundaries between the oxide semiconductor film 101b and the oxide semiconductor film 101a, and between the oxide semiconductor film 101b and the oxide semiconductor film 101c may be unclear.

[0118] For example, the oxide semiconductor films 101a and 101c contain In or Ga, and typically include In-based oxides, Ga-based oxides, In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and materials are used such that the energy of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 101b. Typically, the difference between the energy of the lower end of the conduction band of the oxide semiconductor films 101a and 10 1c and the energy of the lower end of the conduction band of the oxide semiconductor film 101b is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 e V or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, which is preferably the case.

[0119] By using oxides with a higher Ga content that function as stabilizers compared to the oxide semiconductor film 101b for the oxide semiconductor films 101a and 101c provided so as to sandwich the oxide semiconductor film 101b, the release of oxygen from the oxide semiconductor film 101b can be suppressed.

[0120] As the oxide semiconductor film 101b, for example, In:Ga:Zn = 1:1:1 or 3:1: ​​​​When an In-Ga-Zn oxide with an atomic ratio of 2 is used, the oxide semiconductor film 101a or as the oxide semiconductor film 101c, for example, In:Ga:Zn = 1:3:2, 1:3:4, 1 :3:6, 1:6:4, 1:6:8, 1:6:10, or 1:9:6, etc. of the atomic ratio of In-Ga-Zn oxide can be used. Note that the atomic ratios of the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c each include a variation of plus or minus 20% of the above atomic ratio as an error. Also, the oxide semiconductor film 101a and the oxide semiconductor film 101c may use materials with the same composition or materials with different compositions.

[0121] Also, when an In-M-Zn oxide is used as the oxide semiconductor film 101b, the target used to form the semiconductor film that becomes the oxide semiconductor film 101b has a metal element atomic ratio of In:M:Zn = x1:y1:z1. When the value of x1 / y 1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less of the atomic ratio of the oxide is preferably used. Note that by setting z1 / y1 to 6 or less, the CAAC-OS film described later is likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2 etc.

[0122] Also, when an In-M-Zn oxide is used as the oxide semiconductor film 101a and the oxide semiconductor film 101c, the target used to form the oxide semiconductor film that becomes the oxide semiconductor film 101a and the oxide semiconductor film 101c has a metal element atomic ratio of the oxide semiconductor film to be formed. ​​​​When In:M:Zn = x2:y2:z2, x2 / y2 < x1 / y1, and the value of z2 / y2 is an oxide with an atomic ratio of 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, which is preferably used. By setting z2 / y2 to 6 or less, the CAAC-OS film described later is more likely to be formed. Representative examples of the atomic ratio of the target metal elements include In:M:Zn = 1:3:4, 1:3:6, 1:3:8, etc.

[0123] In addition, by using a material in the oxide semiconductor film 101a and the oxide semiconductor film 101c whose energy at the lower end of the conduction band is closer to the vacuum level than that in the oxide semiconductor film 101 b, a channel is mainly formed in the oxide semiconductor film 101b, and the oxide semiconductor film 101b becomes the main current path. In this way, by sandwiching the oxide semiconductor film 101b in which the channel is formed between the oxide semiconductor film 101a and the oxide semiconductor film 101c containing the same metal element, the generation of these interface levels is suppressed, and the reliability of the electrical characteristics of the transistor is improved.

[0124] Note that the present invention is not limited to this, and those having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen elements, interatomic distance, density, etc. of the oxide semiconductor film 101a, the oxide semiconductor film 10 1b, and the oxide semiconductor film 101c appropriate.

[0125] Here, there may be a mixed region between the oxide semiconductor film 101a and the oxide semiconductor film 101b. In addition, the oxide semiconductor film 101b and the oxide semiconductor film 101c may have a mixed region between the oxide semiconductor film 101b and the oxide semiconductor film 101c.​​​​​​​​​ Between the conductor film 101b and the oxide semiconductor film 101c, there may be a mixed region of the oxide semiconductor film 101b and the oxide semiconductor film 101c. The mixed region has a low interface state density. Therefore, in the laminate of the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 1 01c, the energy changes continuously in the vicinity of each interface (also referred to as a continuous junction).) It has a band structure.

[0126] Here, the band structure will be described. For ease of understanding, the conduction band bottom energy (Ec) of the insulating film 1 25, the oxide semiconductor film 101a, the oxide semiconductor film 101b, the oxide semiconductor film 101c, and the gate insulating film 104 is shown.

[0127] As shown in FIGS. 5(A) and 5(B), in the oxide semiconductor film 101a, the oxide semiconductor film 10 1b, and the oxide semiconductor film 101c, the energy of the conduction band bottom changes continuously. This is also understood from the fact that the elements constituting the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c are common, and oxygen diffuses easily among them. Therefore, although the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c are a laminate of layers with different compositions, it can also be said that they are physically continuous.

[0128] The oxide semiconductor films laminated with a common main component are not simply laminated but are continuously joined (here, in particular, a U-shaped well structure in which the energy of the conduction band bottom changes continuously between layers is formed). That is, the laminate structure is formed so that there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of the respective layers. If , if impurities are mixed between the layers of the stacked multilayer film, the continuity of the energy band is lost and carriers disappear at the interface due to trapping or recombination.

[0129] In addition, in FIG. 5(A), the case where the Ec of the oxide semiconductor film 101a and the oxide semiconductor film 101c is the same is shown, but they may be different from each other. For example, when the Ec of the oxide semiconductor film 101c has a higher energy than that of the oxide semiconductor film 101a, a part of the band structure is shown as in FIG. 5(B).

[0130] From FIGS. 5(A) and 5(B), it can be seen that the oxide semiconductor film 101b becomes a well, and in the second transistor 100, the channel is formed in the oxide semiconductor film 101b. Note that since the energy at the lower end of the conduction band of the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 10 1c changes continuously, it can also be called a U-shaped well. In addition, the channel formed in such a configuration can also be called a buried channel.

[0131] Note that trap levels caused by impurities or defects can be formed near the interfaces between the oxide semiconductor films 101a and 101c and an insulating film such as a silicon oxide film. Due to the presence of the oxide semiconductor films 101a and 101c, the oxide semiconductor film 101 b can be separated from the trap levels. However, when the energy difference between the Ec of the oxide semiconductor film 101a or the oxide semiconductor film 101c and the Ec of the oxide semiconductor film 101b is small, electrons in the oxide semiconductor film 101b can reach the trap levels across the energy difference. ​​​​​It may occur. By being trapped at the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction.

[0132] Therefore, in order to reduce the variation in the threshold voltage of the transistor, an energy difference needs to be provided between the Ec of the oxide semiconductor films 101a and 101c and the oxide semiconductor film 101b. Each such energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0133] Note that the oxide semiconductor films 101a, 101b, and 101c preferably contain crystal parts. In particular, by using crystals oriented along the c-axis, stable electrical characteristics can be imparted to the transistor.

[0134] Also, in the band structure as shown in Fig. 5(B), the oxide semiconductor film 101c may not be provided, and an In-Ga oxide (for example, In:Ga = 7:93 in terms of atomic ratio) may be provided between the oxide semiconductor film 101b and the gate insulating film 104.

[0135] The oxide semiconductor film 101b uses an oxide with a smaller electron affinity than the oxide semiconductor films 101a and 101c. For example, as the oxide semiconductor film 101b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less greater than those of the oxide semiconductor films 101a and 101c is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band.

[0136] ​​​​​​​​​​​​​Here, the thickness of the oxide semiconductor film 101b is preferably at least greater than that of the oxide semiconductor film 101a. The thicker the oxide semiconductor film 101b, the higher the on-current of the transistor can be increased. Also, the oxide semiconductor film 101a may have a thickness such that the effect of suppressing the generation of interface levels at the interface with the oxide semiconductor film 101b is not lost. For example, the oxide semiconductor film 101b may have a thickness greater than 1 times, preferably 2 times or more, more preferably 4 times or more, and even more preferably 6 times or more, the thickness of the oxide semiconductor film 101a. However, this is not the case when it is not necessary to increase the on-current of the transistor. The thickness of the oxide semiconductor film 101a may be equal to or greater than the thickness of the oxide semiconductor film 101b.

[0137] Also, the oxide semiconductor film 101c may have a thickness such that the effect of suppressing the generation of interface levels at the interface with the oxide semiconductor film 101b is not lost, similar to the oxide semiconductor film 101a. For example, it may have a thickness equal to or less than that of the oxide semiconductor film 101a. If the oxide semiconductor film 101c is thick, there is a possibility that the electric field by the gate electrode may not easily reach the oxide semiconductor film 101b. Therefore, it is preferable to form the oxide semiconductor film 101c thinly. For example, it may be thinner than the thickness of the oxide semiconductor film 101b. However, it is not limited to this. The thickness of the oxide semiconductor film 101c may be appropriately set according to the voltage for driving the transistor, taking into account the breakdown voltage of the gate insulating film 104.

[0138] Here, for example, when the oxide semiconductor film 101b is in contact with an insulating film having different constituent elements (for example, an insulating film containing a silicon oxide film, etc.), interface levels are formed at these interfaces, and at these interfaces The level may form a channel. In such a case, a second transistor with a different threshold voltage may appear, and the apparent threshold voltage of the transistor may vary. However, in the transistor of this configuration, since the oxide semiconductor film 101a contains one or more metal elements constituting the oxide semiconductor film 101b, it is difficult to form interface levels at the interface between the oxide semiconductor film 101a and the oxide semiconductor film 101b. Therefore, by providing the oxide semiconductor film 101a, variations and fluctuations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Also, when a channel is formed at the interface between the gate insulating film 104 and the oxide semiconductor film 101b, interface scattering may occur at this interface, and the field-effect mobility of the transistor may decrease. However, in the transistor of this configuration, since the oxide semiconductor film 101b contains one or more metal elements constituting the oxide semiconductor film 101c, carrier scattering hardly occurs at the interface between the oxide semiconductor film 101b and the oxide semiconductor film 101c, and the field-effect mobility of the transistor can be increased. One of the electrodes 103a and 103b functions as a source electrode, and the other functions as a drain electrode. The electrodes 103a and 103b are used in a single-layer structure or a stacked structure of a metal such as aluminum, titanium, chromium, nickel, copper, indium, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked on a titanium film

[0139]

[0140]

[0141] ​​​​​​​​​​​​​​​ A two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium-aluminum alloy film with a copper film laminated thereon, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on top of the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon to form a three-layer structure, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on top of the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon to form a three-layer structure, etc. In addition, a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used. The gate insulating film 104 may be, for example, a single layer or a laminate of an insulating film containing a so-called high-k material such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)T iO3 (BST). Alternatively, for example, aluminum oxide, bismuth oxide,

[0142] germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulating films. Or these insulating films may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the above insulating films and used. In addition, as the gate insulating film 104, similar to the insulating film 126, an acid that satisfies the stoichiometric composition is used. Or these insulating films may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the above insulating films and used.

[0143] Also, as the gate insulating film 104, similar to the insulating film 126, an acid that satisfies the stoichiometric composition ​​It is preferable to use an oxide insulating film containing more oxygen than the substrate.

[0144] Note that when a specific material is used for the gate insulating film, electrons can be trapped in the gate insulating film under specific conditions to increase the threshold voltage. For example, like a laminated film of silicon oxide and hafnium oxide using a material with many electron trapping levels such as hafnium oxide, aluminum oxide, or tantalum oxide in part of the gate insulating film, at a higher temperature (higher than the operating temperature or storage temperature of the semiconductor device, or a temperature of 125 °C or higher and 450 °C or lower, typically 1 50 °C or higher and 300 °C or lower), by maintaining the potential of the gate electrode at a higher state than the potential of the source electrode or drain electrode for 1 second or more, typically 1 minute or more, electrons move from the semiconductor film towards the gate electrode, and some of them are trapped in the electron trapping levels. In this way, the threshold voltage of the transistor that has trapped the required amount of electrons in the electron trapping levels shifts to the positive side. By controlling the voltage of the gate electrode, the amount of electrons trapped can be controlled, and accordingly, the threshold voltage can be controlled. Also, the process of trapping electrons can be performed during the manufacturing process of the transistor.

[0145] For example, it may be performed at any stage before factory shipment, such as after forming the wiring connected to the source electrode or drain electrode of the transistor, or after the end of the previous process (wafer processing), or after the wafer dicing process, or after packaging. In any case, it is preferable that it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. In any case, it is preferable that it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. In any case, it is preferable that it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter.

[0146] For example, it may be performed at any stage before factory shipment, such as after forming the wiring connected to the source electrode or drain electrode of the transistor, or after the end of the previous process (wafer processing), or after the wafer dicing process, or after packaging. Or after the end of the previous process (wafer processing), or after the wafer dicing process, or after packaging, etc. In any case, it is preferable that it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter. In any case, it is preferable that it is not exposed to a temperature of 125 °C or higher for 1 hour or more thereafter.

[0147] The gate electrode 105 can be formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metals as components, or an alloy combining the above-described metals. Further, a metal selected from any one or more of manganese and zirconium may be used. Also, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, a silicide such as nickel silicide, etc. may be used. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film is formed, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, etc. exist. Further, an alloy film or a nitride film combining aluminum with one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

[0148] Further, the gate electrode 105 can also be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Also, a laminated structure of the above-described conductive material having translucency and the above-described metal can also be used.

[0149] Also, a plug 167 electrically connected to the plug 164 is an insulating film 127, an insulating film 107, ​​​​​​​​​​It is provided so as to be embedded in the insulating film 108. Also, a plug 168 that is electrically connected to the gate electrode 105 is provided so as to be embedded in the insulating film 127, the insulating film 107, and the insulating film 108. Also, a plug 169 that is electrically connected to the plug 166 is provided so as to be embedded in the insulating film 127, the insulating film 107, and the insulating film 108. Also, a plug 169 that is electrically connected to the plug 166 is provided so as to be embedded in the insulating film 127, the insulating film 107, and the insulating film 108. Also, a plug 169 that is electrically connected to the plug 166 is provided so as to be embedded in the insulating film 127, the insulating film 107, and the insulating film 108.

[0150] Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used. Also, between the gate electrode 105 and the gate insulating film 104, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the oxide semiconductor film 101b, specifically 7 atomic% or more, is used.

[0151] Similar to the barrier film 120, it is preferable to use a material in which water and hydrogen hardly diffuse for the insulating film 107. In particular, it is preferable to use a material in which oxygen hardly permeates as the insulating film 107. Similar to the barrier film 120, it is preferable to use a material in which water and hydrogen hardly diffuse for the insulating film 107. In particular, it is preferable to use a material in which oxygen hardly permeates as the insulating film 107. Similar to the barrier film 120, it is preferable to use a material in which water and hydrogen hardly diffuse for the insulating film 107. In particular, it is preferable to use a material in which oxygen hardly permeates as the insulating film 107.

[0152] By covering the oxide semiconductor film 101b with the insulating film 107 containing a material in which oxygen hardly permeates, the release of oxygen from the oxide semiconductor film 101b above the insulating film 107 is suppressed. By covering the oxide semiconductor film 101b with the insulating film 107 containing a material in which oxygen hardly permeates, the release of oxygen from the oxide semiconductor film 101b above the insulating film 107 is suppressed. This is possible. Further, since the oxygen detached from the insulating film 126 can be confined to a position below the insulating film 107, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. This is possible.

[0153] In addition, the insulating film 107 that hardly permeates water or hydrogen can suppress the entry of water and hydrogen, which are impurities for the oxide semiconductor, from the outside, suppress fluctuations in the electrical characteristics of the second transistor 100, and realize a highly reliable transistor.

[0154] Note that an insulating film similar to the insulating film 126, from which oxygen is detached by heating, may be provided below the insulating film 107, and oxygen may also be supplied from above the oxide semiconductor film 101b through the gate insulating film 104.

[0155] Here, a configuration example of a transistor applicable to the second transistor 100 is shown. FIG. 6(A) is a schematic top view of the transistor exemplified below, and FIGS. 6(B) and 6(C) are schematic cross-sectional views when cut along the cutting lines A1 - A2 and B1 - B2 in FIG. 6(A), respectively. Note that FIG. 6(B) corresponds to a cross-section in the channel length direction of the transistor, and FIG. 6(C) corresponds to a cross-section in the channel width direction of the transistor.

[0156] As shown in FIG. 6(C), in the cross-section in the channel width direction of the transistor, by providing the gate electrode so as to face the upper surface and the side surface of the oxide semiconductor film 101b, a channel is formed not only near the upper surface but also near the side surface of the oxide semiconductor film 101b, the effective channel width is increased, and the current in the on state (on-current) can be increased. In particular, for the oxide semiconductor ​​​​​​​​When the width of the film 101b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably 20 nm or less), since the region where channels are formed extends to the inside of the oxide semiconductor film 101b, the contribution to the on-current increases as the miniaturization progresses.

[0157] Note that, as shown in FIGS. 7(A), 7(B), and 7(C), the width of the gate electrode 105 may be narrowed. In that case, for example, using the electrodes 103a and 103b, the gate electrode 105, etc. as masks, impurities such as argon, hydrogen, phosphorus, and boron can be introduced into the oxide semiconductor film 101b etc. As a result, in the oxide semiconductor film 101b etc., low-resistance regions 109a and 109b can be provided. Note that the low-resistance regions 10 9a and 109b do not necessarily have to be provided. Note that not only in FIG. 6, but also in other drawings, the width of the gate electrode 105 can be narrowed. The transistors shown in FIGS. 8(A) and 8(B) are mainly different in that the oxide semiconductor film 101c is provided in contact with the lower surfaces of the electrodes 103a and 103b

[0158] compared with the transistor illustrated in FIG. 6. By adopting such a configuration, when forming each of the oxide semiconductor films 101a, 101b, and oxide semiconductor film 101c, continuous film formation can be achieved without exposure to the atmosphere, so that interface defects can be reduced.

[0159] In addition, in the above description, a configuration in which the oxide semiconductor film 101a and the oxide semiconductor film 101c are provided in contact with the oxide semiconductor film 101b has been described. However, the oxide semiconductor film 101a or the oxide semiconductor film 101c can be provided in contact with the oxide semiconductor film 101b, or the oxide semiconductor film 101c can be provided in contact with the oxide semiconductor film 101a.

[0160] Also, in the above, a configuration in which the oxide semiconductor film 101a and the oxide semiconductor film 101c are provided in contact with the oxide semiconductor film 101b has been described. However, the oxide semiconductor film 101a or the oxide semiconductor film 101c can be provided in contact with the oxide semiconductor film 101b, or the oxide semiconductor film 101c can be provided in contact with the oxide semiconductor film 101a. It may be configured not to provide one or both of the body films 101c.

[0161] Note that also in FIG. 8, similar to FIG. 6, the width of the gate electrode 105 can be narrowed. . Examples in that case are shown in FIGS. 9(A) and 9(B). Note that not only in FIGS. 6 and 8, but also in other drawings, the width of the gate electrode 105 can be narrowed.

[0162] Note that the channel length is, for example, in the top view of the transistor, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. The channel width is, for example, the width of the source or drain in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the region where the channel is formed. Note that in one transistor, the channel

[0163] width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0164] Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor to the ratio of the channel region formed on the top surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. Therefore, in this specification, in the top view of the transistor, the apparent channel width, which is the width of the source or drain in the region where the semiconductor and the gate electrode overlap, is sometimes referred to as the "surrounded channel width (SCW)". Also, in this specification, when simply described as the channel width, it refers to the surrounded channel width. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor to the ratio of the channel region formed on the top surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. In the case of the above, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

[0165] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0166] Therefore, in this specification, in the top view of the transistor, the apparent channel width, which is the width of the source or drain in the region where the semiconductor and the gate electrode overlap, is sometimes referred to as the "surrounded channel width (SCW)". Also, in this specification, when simply described as the channel width, it refers to the surrounded channel width. width. ​​​​It may refer to the width or apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by obtaining a cross-sectional TEM image or the like and analyzing the image. It is possible.

[0167] In addition, when calculating the field-effect mobility of a transistor or the current value per channel width, etc., the enclosed channel width may be used for calculation. In that case, it may take a value different from the case of calculating using the effective channel width.

[0168]

[0169] The above is the description of the second transistor 100.

[0169] The insulating film 127 covering the second transistor 100 functions as a planarizing film covering the uneven shape of its lower layer. Also, the insulating film 108 may have a function as a protective film when forming the insulating film 127. If the insulating film 108 is unnecessary, it may not be provided.

[0170] Also, the plug 170 is provided to be embedded in the insulating film 128 and is electrically connected to the plug 167. Also, the plug 171 is provided to be embedded in the insulating film 128 and is electrically connected to the plug 168. Also, the plug 172 is provided to be embedded in the insulating film 128 and is electrically connected to the plug 169.

[0171] Also, the electrode 173 is electrically connected to the plug 170 and the wiring BL, the electrode 174 is electrically connected to the plug 171 and the wiring WL, and the electrode 175 is electrically connected to the plug 172 and the wiring SL. is connected to.

[0172] The semiconductor device according to one aspect of the present invention includes a first transistor 110 and the second transistor 100 located above the first transistor. Therefore, by stacking and providing these, the occupied area of the element can be reduced. Further, since the capacitive element 130 is located below the second trans istor 100, the occupied area of the element can be reduced by stacking and providing these. Also, since the wiring CL has an area overlapping with the gate electrode 105 of the second transistor 100, the occupied area of the element can be further reduced. Furthermore, the barrier film 120 provided between the first transistor 110 and the second transistor 100 can suppress the diffusion of impurities such as water and hydrogen existing in the lower layer to the second transistor 10 0 side.

[0173] The above is the description of the configuration example.

[0174] [Example of manufacturing method] Hereinafter, an example of the manufacturing method of the semiconductor device shown in the above configuration example will be described with reference to FIGS. 10 to 1 2.

[0175] First, a semiconductor substrate 111 is prepared. As the semiconductor substrate 111, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride can be used. Also, as the semiconductor substrate 111, an SOI substrate may be used. Hereinafter, the case where single crystal silicon is used as the semiconductor substrate 111 will be described.

[0176] ​​​Next, an element isolation layer (not shown) is formed on the semiconductor substrate 111. The element isolation layer is formed by LOC OS (Local Oxidation of Silicon) method or STI (Sh allow Trench Isolation) method or the like.

[0177] When forming a p-type transistor and an n-type transistor on the same substrate, an n-well or a p-well may be formed in a part of the semiconductor substrate 1 11. For example, an impurity element such as boron that imparts p-type conductivity may be added to the n-type semiconductor substrate 11 1 to form a p-well, and an n-type transistor and a p-type transistor may be formed on the same substrate.

[0178] Next, an insulating film serving as the gate insulating film 114 is formed on the semiconductor substrate 111. For example, after surface nitridation treatment, an oxidation treatment is performed to oxidize the silicon and silicon nitride interface to form a silicon oxynitride film. For example, a silicon oxynitride film can be obtained by performing oxygen radical oxidation after forming a thermal silicon nitride film on the surface at 700 °C in an NH3 atmosphere.

[0179] The insulating film may be formed by a sputtering method, a CVD (Chemical Vapor Depo sition) method (including a thermal CVD method, a MOCVD (Metal Organic CVD) method 、a PECVD (Plasma Enhanced CVD) method, etc.), an MBE (Mo lecular Beam Epitaxy) method, an ALD (Atomic Layer Deposition) method, or a PLD (Pulsed Laser Deposit ion) method or the like.

[0180] Subsequently, a conductive film serving as the gate electrode 115 is formed. As the conductive film, a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, etc., or an alloy material or compound material mainly composed of these metals is preferably used. Also, polycrystalline silicon doped with impurities such as phosphorus can be used. Further, a laminated structure of a metal nitride film and the above-mentioned metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved, and peeling can be prevented. Also, a metal film for controlling the work function of the gate electrode 115 may be provided. The conductive film can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.). Also, to reduce damage by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable. Subsequently, a resist mask is formed on the conductive film using a lithography method or the like, and unnecessary portions of the conductive film are removed. Then, by removing the resist mask, the gate electrode 115 can be formed. Here, the processing method of the film to be processed will be described. When finely processing the film to be processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Also, a dummy pattern is formed by a lithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed. After that, a sidewall is formed on the remaining pattern. When forming a fine pattern, a method of performing an etching process using the sidewall as a mask may be used. In addition, when forming a fine pattern, a method of performing a deposition process using the sidewall as a mask may be used.

[0181] When forming a fine pattern, a method of performing a thermal treatment using the sidewall as a mask may be used. When forming a fine pattern, a method of performing a plasma treatment using the sidewall as a mask may be used. When forming a fine pattern, a method of performing an ion implantation process using the sidewall as a mask may be used.

[0182] Subsequently, a resist mask is formed on the conductive film using a lithography method or the like, and unnecessary portions of the conductive film are removed. Then, by removing the resist mask, the gate electrode 115 can be formed. Here, the processing method of the film to be processed will be described. When finely processing the film to be processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Also, a dummy pattern is formed by a lithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed.

[0183] Here, the processing method of the film to be processed will be described. When finely processing the film to be processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Also, a dummy pattern is formed by a lithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed. After that, a sidewall is formed on the remaining pattern. When forming a fine pattern, a method of performing an etching process using the sidewall as a mask may be used. Remove the turns and use the remaining sidewalls as a resist mask to etch the film to be processed It may be. Also, as the etching of the film to be processed, it is preferable to use anisotropic dry etching in order to achieve a high aspect ratio In addition, a hard mask made of an inorganic film or a metal film may be used For the light used to form the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 43

[0184] 6 nm), h-line (wavelength 405 nm), or light obtained by mixing these can be used In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used In addition, exposure may be performed by immersion lithography technology. Also, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Also Instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays or an electron beam is preferable because extremely fine processing becomes possible. When performing exposure by scanning a beam such as an electron beam a photomask is not required In addition, before forming the resist film that becomes the resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed, for example, by spin coating or the like so as to cover the steps of its lower layer and flatten the surface

[0185] and the variation in the thickness of the resist mask provided on the upper layer of the organic resin film can be reduced In addition, when performing particularly fine processing, it is preferable to use, as the organic resin film, a material that functions as an antireflection film for the light used for exposure In this way, a material having such a function can be used to reduce the variation in the thickness of the resist mask provided on the upper layer of the organic resin film. Also, when performing particularly fine processing, it is preferable to use, as the organic resin film, a material that functions as an antireflection film for the light used for exposure In addition, when performing particularly fine processing, it is preferable to use, as the organic resin film, a material that functions as an antireflection film for the light used for exposure For the light used to form the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 43 Examples of the organic resin film include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed simultaneously with the removal of the resist mask, or may be removed after the resist mask is removed.

[0186] After the formation of the gate electrode 115, a sidewall covering the side surface of the gate electrode 115 may be formed. The sidewall can be formed by depositing an insulating film thicker than the thickness of the gate electrode 115 and then performing anisotropic etching to leave only the insulating film on the side surface portion of the gate electrode 115.

[0187] When the sidewall is formed, the insulating film that will become the gate insulating film 114 is also etched simultaneously, so that the gate insulating film 114 is formed under the gate electrode 115 and the sidewall. Alternatively, after the gate electrode 115 is formed, the insulating film may be etched using the resist mask for processing the gate electrode 115 or the gate electrode 115 as an etching mask to form the gate insulating film 114. Or, the insulating film can be used as the gate insulating film 114 as it is without performing etching processing on the insulating film.

[0188] Subsequently, an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron is added to a region of the semiconductor substrate 111 where the gate electrode 115 (and the sidewall) is not provided. The schematic cross-sectional view at this stage corresponds to FIG. 10(A).

[0189] Subsequently, after the insulating film 121 is formed, a first heat treatment is performed to activate the element that imparts the above-described conductivity.

[0190] The insulating film 121 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc., and may be provided in a laminated or single-layer form. The insulating film 121 can be formed by a sputtering method, a CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or PLD method. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, the coating property can be improved, which is preferable. Also, to reduce plasma damage, a thermal CVD method, MOCVD method or ALD method is preferable. The first heat treatment can be performed, for example, at 400°C or higher and below the strain point of the substrate in an inert gas atmosphere such as a rare gas or nitrogen gas, or in a reduced pressure atmosphere.

[0191] At this stage, the first transistor 110 is formed.

[0192]

[0193]

[0194] Subsequently, the insulating film 122 and the insulating film 123 are formed.

[0194] In addition to the materials that can be used for the insulating film 121, when silicon oxynitride containing oxygen and hydrogen (SiNOH) is used for the insulating film 122, the amount of hydrogen desorbed by heating can be increased, which is preferable. In addition to the materials that can be used for the insulating film 121, for the insulating film 123, it is preferable to use a silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane, etc., with oxygen or nitrous oxide, etc.

[0195] ​The insulating films 122 and 123 can be formed, for example, by a sputtering method, a CVD method (including a thermal CVD method , an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, when forming the insulating film by a CVD method, preferably a plasma CVD method , it is preferable because the coating property can be improved. Also, to reduce the damage caused by the plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0196] Subsequently, the upper surface of the insulating film 123 is planarized using a CMP method or the like.

[0197] Thereafter, a second heat treatment is performed to terminate the dangling bonds in the semiconductor film 112 with hydrogen that detaches from the insulating film 122.

[0198] The second heat treatment can be performed under the conditions exemplified in the description of the above laminate structure 10.

[0199] Subsequently, an insulating film 124 is formed on the insulating film 123.

[0200] Subsequently, openings reaching the low-resistance layers 113a, the low-resistance layer 113b, the gate electrode 115, etc. are formed in the insulating film 121, the insulating film 122, the insulating film 123, and the insulating film 124. Thereafter, a conductive film is formed so as to fill the openings, and a planarization process is performed on the conductive film so that the upper surface of the insulating film 124 is exposed, thereby forming plugs 161, plugs 162, plugs 163, etc. The formation of the conductive film can be performed, for example, by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD D method, etc.), an MBE method, an ALD method, or a PLD method. The cross-sectional schematic diagram at this stage corresponds to FIG. 10(B). D method, etc.), an MBE method, an ALD method, or a PLD method.

[0201] Subsequently, a conductive film is formed on the insulating film 124. Then, a resist mask is formed in the same manner as above, and unnecessary portions of the conductive film are removed by etching. Then, the resist mask is removed to form an electrode 136 that serves as one electrode of the capacitor element.

[0202] Subsequently, an insulating film 137 and an electrode 138 are formed on the electrode 136 using a resist mask in the same manner as before. Note that the electrode 138 is preferably formed so as to overlap with the gate electrode 105 of the second transistor 100 to be formed later.

[0203] Also, the electrode 138 is electrically connected to the wiring CL. The wiring CL is configured to have a region that overlaps with the gate electrode 105 of the second transistor 100 as shown in FIG. 2 so that the occupied area of the element can be reduced.

[0204] At this stage, the capacitor element 130 is formed (see FIG. 10(C)).

[0205] Subsequently, an insulating film covering the capacitor element 130 is formed, and a planarization process is performed so that the upper surfaces of the respective wirings are exposed, thereby forming the insulating film 125. The insulating film that becomes the insulating film 125 can be formed by the same material and method as the insulating film 121 or the like.

[0206] After forming the insulating film 125, it is preferable to perform a third heat treatment. By the third heat treatment, water and hydrogen contained in each layer are desorbed, thereby reducing the content of water and hydrogen. The third heat treatment is performed immediately before forming the barrier film 120 described later, and after thoroughly removing hydrogen and water contained in the layer below the barrier film 120, the barrier film 120 is formed. By doing so, it is possible to suppress water and hydrogen from diffusing and releasing again to the lower layer side than the barrier film 120 in subsequent processes. This can be suppressed.

[0207] The third heat treatment can be performed under the conditions exemplified in the description of the laminated structure 10.

[0208] Subsequently, a barrier film 120 is formed on the insulating film 125 (see Fig. 10(D)).

[0209] The barrier film 120 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, forming the insulating film by a CVD method, preferably a plasma CVD method is preferable because the coating property can be improved. Also, to reduce damage by plasma, a thermal CVD method, a MOCVD method, or an ALD method is preferable.

[0210] After forming the barrier film 120, a heat treatment may be performed to reduce or remove water and hydrogen contained in the barrier film 120 and suppress outgassing.

[0211] Subsequently, after forming a conductive film on the barrier film 120, a resist mask is formed in the same manner as above, and unnecessary portions of the conductive film are removed by etching. Thereafter, by removing the resist mask, the wiring 132 can be formed.

[0212] Subsequently, an insulating film that becomes the insulating film 126 is formed. The insulating film that becomes the insulating film 126 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an M BE method, an ALD method, or a PLD method. In particular, the insulating film ​When the film is formed by CVD method, preferably plasma CVD method, the coating property can be improved, which is preferable. Also, in order to reduce the damage caused by plasma, thermal CVD method, MOCVD method or ALD method is preferable. To increase the oxygen content in the insulating film that becomes the insulating film 126, for example, the insulating film 125 may be formed in an oxygen atmosphere. Or, oxygen may be introduced into the insulating film that becomes the insulating film 126 after film formation to form a region with excessive oxygen content, or both means may be combined. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film that becomes the insulating film 126 after film formation to form a region with excessive oxygen content. As the method for introducing oxygen, ion implantation method, ion doping method, plasma immersion ion implantation method, plasma treatment, etc. can be used.

[0213] For the oxygen introduction treatment, a gas containing oxygen can be used. As the gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. Also, in the oxygen introduction treatment, a rare gas may be included in the gas containing oxygen. For example, a mixed gas of carbon dioxide, hydrogen, and argon can be used. After forming the insulating film that becomes the insulating film 126, in order to improve the flatness of its upper surface, a planarization treatment using CMP method or the like is performed to form the insulating film 126 (see Fig. 11(A)). Also, an insulating film that becomes the insulating film 126 is formed on the barrier film 120, and a resist is formed on the insulating film.

[0214]

[0215]

[0216]

[0217] ​​​​​​​​​​​​Form a mask, remove unnecessary portions of the insulating film that will become the insulating film 126 by etching, and after forming the insulating film 126, form a conductive film, form a resist mask on the conductive film, and remove unnecessary portions of the conductive film by etching to form wiring 132. After forming the insulating film 126, a conductive film may be formed, a resist mask may be formed on the conductive film, and unnecessary portions of the conductive film may be removed by etching to form wiring 132.

[0218] Subsequently, an insulating film that will become the insulating film 106a, an oxide semiconductor film that will become the oxide semiconductor film 101a, and an oxide semiconductor film that will become the oxide semiconductor film 101b are sequentially formed. It is preferable to continuously form the oxide semiconductor film without exposing it to the atmosphere. After forming the oxide semiconductor film that will become the oxide semiconductor film 101b, it is preferable to perform a fourth heat treatment. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or in a reduced pressure state. Also, the atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas to supplement the released oxygen after heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after forming the oxide semiconductor film that will become the oxide semiconductor film 101b, or may be performed after processing the oxide semiconductor film that will become the oxide semiconductor film 101b into an island-shaped oxide semiconductor film 101b. By the heat treatment, oxygen is supplied from the insulating film 126 and the insulating film that will become the insulating film 106a to the oxide semiconductor film, and oxygen deficiency in the semiconductor film can be reduced.

[0219]

[0220] Thereafter, a conductive film serving as a hard mask and a resist mask are formed on the oxide semiconductor film that will become the oxide semiconductor film 101b in the same manner as above, and unnecessary portions of the conductive film are etched. ​​​​​​​​​​​​​Remove it by [specific method]. Then, using the conductive film as a mask, the insulating film and oxide that will become the insulating film 106a Remove the unnecessary portions of the semiconductor film by etching. Then remove the resist mask Thus, a stacked structure of the island-shaped conductive film 103, the insulating film 106a, the island-shaped oxide semiconductor film 101a, and the island-shaped oxide semiconductor film 101b can be formed (see Fig. 11(B)).

[0221] Also, simultaneously, a stacked structure of the electrode 103c, the insulating film 106b, the island-shaped oxide semiconductor film 131a, and the island-shaped oxide semiconductor film 131b can be formed.

[0222] The conductive film can be formed, for example, by sputtering, CVD methods (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. In particular, when forming the insulating film by CVD, preferably plasma CVD, it is preferable because the coating property can be improved. Also, to reduce damage by plasma, thermal CVD, MOCVD, or ALD is preferable. subsequently, a resist mask is formed on the conductive film 103 by the same method as above, and the unnecessary portions of the conductive film 1 03 are removed by etching. Then, by removing the resist mask,

[0223] the electrode 103a and the electrode 103b can be formed. subsequently, a resist mask is formed on the insulating film 126, the electrode 103a, and the electrode 103b by the same method as above, and using this mask, the oxide semiconductor film 101b, the oxide semiconductor film 1 01a, the insulating film 106a, the insulating film 126, the barrier film 120, and the insulating film 125 are provided with a plug 1

[0224] subsequently, a resist mask is formed on the insulating film 126, the electrode 103a, and the electrode 103b by the same method as above, and using this mask, the oxide semiconductor film 101b, the oxide semiconductor film 1 01a, the insulating film 106a, the insulating film 126, the barrier film 120, and the insulating film 125 are provided with a plug 1 01a, the insulating film 106a, the insulating film 126, the barrier film 120, and the insulating film 125 are provided with a plug 1 An opening reaching the electrodes 61 and 136 is formed. At the same time, a resist mask is formed on the electrode 103c by the same method as described above, and using this mask, openings reaching the plug 163 are formed in the oxide semiconductor film 131b, the oxide semiconductor film 131a, the insulating film 106b, the insulating film 126, the barrier film 120, and the insulating film 125. Subsequently, a conductive film is formed and processed to form plugs 164, 165, and 166 (see Fig. 11(C)). Subsequently, an oxide semiconductor film 101c, a gate insulating film 104, and a gate electrode 105 are formed (see Fig. 12(A)). At this stage, the second transistor 100 is formed.

[0225] Subsequently, an insulating film 107 is formed. The insulating film 107 can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PVD methods. In particular, when the insulating film is formed by CVD, preferably plasma CVD, the coating property can be improved, which is preferable. Also, to reduce plasma damage, thermal CVD, MOCVD, or ALD methods are preferable. After forming the insulating film 107, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen can be supplied from the insulating film 126 etc. to the oxide semiconductor film 101b, and the oxygen deficiency in the oxide semiconductor film 101b can be reduced. Also, at this time, the oxygen desorbed from the insulating film 126

[0226] Subsequently, a conductive film is formed and processed to form plugs 164, 165, and 166 (see Fig. 11(C)). Subsequently, an oxide semiconductor film 101c, a gate insulating film 104, and a gate electrode 105 are formed (see Fig. 12(A)).

[0227] At this stage, the second transistor 100 is formed.

[0228] Subsequently, an insulating film 107 is formed. The insulating film 107 can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PVD methods. In particular, when the insulating film is formed by CVD, preferably plasma CVD, the coating property can be improved, which is preferable. Also, to reduce plasma damage, thermal CVD, MOCVD, or ALD methods are preferable. Subsequently, a conductive film is formed and processed to form plugs 164, 165, and 166 (see Fig. 11(C)). Subsequently, an oxide semiconductor film 101c, a gate insulating film 104, and a gate electrode 105 are formed (see Fig. 12(A)). At this stage, the second transistor 100 is formed. Subsequently, an insulating film 107 is formed. The insulating film 107 can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PVD methods. In particular, when the insulating film is formed by CVD, preferably plasma CVD, the coating property can be improved, which is preferable. Also, to reduce plasma damage, thermal CVD, MOCVD, or ALD methods are preferable. After forming the insulating film 107, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen can be supplied from the insulating film 126 etc. to the oxide semiconductor film 101b, and the oxygen deficiency in the oxide semiconductor film 101b can be reduced. Also, at this time, the oxygen desorbed from the insulating film 126

[0229] After forming the insulating film 107, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen can be supplied from the insulating film 126 etc. to the oxide semiconductor film 101b, and the oxygen deficiency in the oxide semiconductor film 101b can be reduced. Also, at this time, the oxygen desorbed from the insulating film 126 After forming the insulating film 107, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen can be supplied from the insulating film 126 etc. to the oxide semiconductor film 101b, and the oxygen deficiency in the oxide semiconductor film 101b can be reduced. Also, at this time, the oxygen desorbed from the insulating film 126 After forming the insulating film 107, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen can be supplied from the insulating film 126 etc. to the oxide semiconductor film 101b, and the oxygen deficiency in the oxide semiconductor film 101b can be reduced. Also, at this time, the oxygen desorbed from the insulating film 126 is blocked by the barrier film 120 and the insulating film 107 and does not diffuse to the layer below the barrier film 120 and the layer above the insulating film 107, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased , and the oxygen deficiency in the oxide semiconductor film 101b can be effectively reduced.

[0230] Subsequently, the insulating film 108 and the insulating film 127 are formed in order (see FIG. 12(B)). The insulating films 108 and the insulating film 127 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, an APCVD (Atmospheric Pressure CVD ) method, etc.), an MBE method, an ALD method, or a PLD method. In particular, when the insulating film 108 is formed by a DC sputtering method, it is preferable because a film with high barrier properties can be formed thickly with good productivity. Also, when formed by an ALD method, it is preferable because ion damage can be reduced and the coverage can be made good. Also, as the insulating film 127 when an organic insulating material such as an organic resin is used, a coating method such as a spin coating method may be used for formation. Further, it is preferable to perform a planarization treatment on the upper surface after forming the insulating film 127. Also, heat treatment may be performed to fluidize and planarize. Also, in order to make the flatness better, after forming the insulating film 127, it is preferable to perform a planarization treatment on the upper surface after laminating an insulating film using a CVD method. Subsequently, openings are provided in the insulating film 126, the insulating film 108, and the insulating film 107 in the same manner as described above, and a plug 167 reaching the plug 164 and a plug 168 reaching the gate electrode 105 are formed.

[0231] ​​​A plug 169 is formed which reaches the plug 166 .

[0232] Next, the insulating film 128 is formed. Note that the insulating film 128 can be formed by using the insulating film 127. can be done.

[0233] Next, an opening is provided in the insulating film 128 by the same method as above, and the opening reaches the plug 167. Plug 170, plug 171 reaching plug 168, plug 172 reaching plug 169 Form.

[0234] Next, an electrode 173 electrically connected to the plug 170 and an electrode 174 electrically connected to the plug 171 are An electrode 174 electrically connected to the plug 172 and an electrode 175 electrically connected to the plug 172 are formed.

[0235] Furthermore, the electrode 173 is electrically connected to the wiring BL, and the electrode 174 is electrically connected to the wiring WL. The electrode 175 is electrically connected to the wiring SL (see FIG. 1B). The materials of the wiring BL, the wiring WL, and the wiring SL can be those of the wiring CL.

[0236] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0237] <Variation 1> As a modification of this embodiment, the position of the capacitance element is changed to a second position as shown in FIG. Specifically, the wiring BL, the wiring WL, the wiring SL, an insulating film 151 is formed on the insulating film 128. Then, the insulating film 151 and the insulating film 128 are , an opening is provided in the insulating film 127, the insulating film 108, and the insulating film 107, and the plug 165 is electrically connected to the opening. A plug 153 is then formed. Then, an electrode 154 is formed to electrically connect to the plug 153. , form the insulating film 155 on the electrode 154 and the electrode 156 on the insulating film 155 to form the capacitor element 150 Thereafter, an insulating film 152 covering the capacitor element 150 is formed. Note that the electrode 15 6 is electrically connected to the wiring CL1 and has a region overlapping with the gate electrode 105 .

[0238] Also, as shown in FIG. 13(B), the capacitor elements 130 and 150 may be provided above and below the gate electrode 105 of the second transistor 100.

[0239] <Modification Example 2> Also, as a modification of the present embodiment, the configuration shown in FIG. 14 may be adopted. The difference from FIG. 1 is the shape of the capacitor element 130. Specifically, it will be described below.

[0240] Form an electrode 136a that becomes a part of one electrode 136 of the capacitor element 130 on the insulating film 124 . Thereafter, form an insulating film 119 covering the electrode 136a, form a resist mask on the insulating film 119, provide an opening in the insulating film 119 using the mask, and form an electrode 136b that is electrically connected to the electrode 136a in the opening. Thereafter, form an insulating film that becomes the insulating film 125, perform a planarization process, and then form an insulating film 125 that provides an opening so that the electrode 136b and the insulating film 119 are exposed using the resist mask. The insulating film that becomes the insulating film 125 can utilize the insulating film 128 or the like.

[0241] Thereafter, form an insulating film 137 on the insulating film 125, the electrode 136b, and the insulating film 119, and form an electrode 138 so as to fill the opening of the insulating film 125. Thereafter, form the insulating films 118, 117, and 116. Note that the electrode 138 is electrically connected to the wiring CL, It has a region overlapping with the gate electrode 105.

[0242] Thereafter, openings are provided in the insulating film 118, insulating film 117, insulating film 116, insulating film 137, insulating film 125 and insulating film 119, and plugs 157, 158 and 159 are provided. Note that the plug 157 is electrically connected to the plugs 161 and 164, and the plug 158 is electrically connected to the electrode 136 and the plug 165, and the plug 159 is electrically connected to the plugs 163 and plug 166.

[0243] <Modification Example 3> Also, as a modification of the present embodiment, as shown in FIG. 15, in addition to the configuration of FIG. 14, a second capacitor element 150 shown in FIG. 13 may be provided above the gate electrode 105 of the transistor 100. It may be.

[0244] Note that when a plurality of capacitor elements are provided, the capacitor elements are not limited to one type, and for example, the capacitor elements shown in FIG. 1 and the capacitor elements shown in FIG. 14 can be appropriately combined.

[0245] This embodiment can be implemented in appropriate combination with at least a part of it and other embodiments described in this specification. It can be implemented in combination.

[0246] (Embodiment 2) In this embodiment, a semiconductor device different from that of Embodiment 1 will be described.

[0247] [Configuration Example] FIG. 16(A) is an example of a circuit diagram of a semiconductor device according to one aspect of the present invention. In FIG. 16(A), the semiconductor device shown includes a first transistor 110, a second transistor 100, a capacitor element 130, a capacitor element 150, a wiring SL, a wiring BL, a wiring WL, a wiring CL2, and It has wiring CL3.

[0248] One of the source or drain of the first transistor 110 is electrically connected to the wiring BL and the other is electrically connected to the wiring SL, and the gate is either the source of the second transistor 100 or one of the source or drain, one electrode of the capacitor element 130, and one electrode of the capacitor element 150 and is electrically connected. The second transistor 100 has the other of the source or drain electrically connected to the wiring BL and the gate is electrically connected to the wiring WL. The other electrode of the capacitor element 130 is electrically connected to the wiring CL2. The other electrode of the capacitor element 150 is electrically connected to the wiring CL3. Note that the gate of the first transistor 110, one of the source or drain of the second transistor 100, one electrode of the capacitor element 130, and one electrode of the capacitor element 150, the node between them is called the node FN.

[0249] FIG. 16(B) shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG. 16(A). FIG. 17(A) shows a top view of the semiconductor devices shown in FIG. 16(B) arranged side by side. Note that each semiconductor device shares the wiring CL2 and the wiring CL3 which function as common wiring.

[0250] As shown in FIG. 17, the second transistor 100, the capacitor element 130, and the capacitor element 150 are provided within the occupied area of the first transistor 110.

[0251] The semiconductor device has the first transistor 110, the second transistor 100, the capacitor element 130, and the capacitor element 150 as shown in FIG. 16(B). The second transistor 100 is provided above the first transistor 110, and between the first transistor 110 and the second transistor 100 A barrier film 120 is provided between the dies 100.

[0252] The structure below the barrier film 120, such as the first transistor 110 and the capacitor element 130, can refer to the description of Embodiment 1.

[0253] Also, the barrier film 120 has openings in which plugs 164, plugs 166, and the capacitor element 150, which will be described later, are embedded.

[0254] A wiring 132 is provided on the barrier film 120. The structure including the wiring 132 corresponds to the second wiring layer 32 in the stacked structure 10.

[0255] The wiring 132 is provided so as to overlap with the channel formation region of the second transistor 100, which will be described later, and functions as the second gate electrode of the second transistor 100.

[0256] An insulating film 126 is provided to cover the barrier film 120 and the wiring 132. Here, the region including the insulating film 126 corresponds to the second insulating film 22 in the stacked structure 10.

[0257] Preferably, the upper surface of the insulating film 126 is flattened by the above-described planarization process.

[0258] Preferably, the insulating film 126 uses an oxide material from which some oxygen desorbs by heating.

[0259] A second transistor 100 is provided above the insulating film 126. The structure including the second transistor 100 corresponds to the second layer 12 in the stacked structure 10.

[0260] The second transistor 100 includes an insulating film 106a in contact with the upper surface of the insulating film 126 and an insulating film An oxide semiconductor film 101a in contact with the upper surface of 106a, and in contact with the upper surface of the oxide semiconductor film 101a is an oxide semiconductor film 101b, and is in contact with the upper surface of the oxide semiconductor film 101b. The oxide semiconductor film is separated in a region overlapping with the oxide semiconductor film 101b by electrodes 103a and 103b, and the oxide semiconductor film 10 is an oxide semiconductor film 101c in contact with the upper surface of 1b, the upper surface of the electrode 103a, and the upper surface of the electrode 103b. The oxide semiconductor film 10 is an oxide semiconductor film 101c, and a gate insulating film 104 on the oxide semiconductor film 101c, and a gate electrode 105 overlapping with the oxide semiconductor film 101b through the gate insulating film 104 and the oxide semiconductor film 101c are provided. Further, an insulating film 107, an insulating film 108, an insulating film 127, and an insulating film 129 are provided covering the second transistor 100.

[0261] Further, a plug 161 and a plug 164 electrically connected to the electrode 103a are provided to be embedded in the insulating film 125 , a barrier film 120, an insulating film 126, an insulating film 106a, an oxide semiconductor film 101a, an oxide semiconductor film 101b, and the electrode 103a. Further, an electrode 136 and an electrode 181 of a capacitor element 150 electrically connected to the electrode 103b are provided to be embedded in the insulating film 125, a barrier film 120, an insulating film 126, an insulating film 106a, an oxide semiconductor film 101a, an oxide semiconductor film 101b, the electrode 103b, an insulating film 107, an insulating film 108, an insulating film 127, and an insulating film 12 9.

[0262] Further, an insulating film 106b, an oxide semiconductor film 131a, an oxide semiconductor film 131b, and an electrode 103c are formed simultaneously with the second transistor 100, and a plug 163 and a plug 166 electrically connected to the electrode 103c are provided to be embedded in the insulating film 125, a barrier film 120, an insulating film 126, an insulating film 106b, the oxide semiconductor film 131a, the oxide semiconductor film 131b, and the electrode 103c are provided so as to be embedded. It is provided so as to be embedded.

[0263] Here, the gate electrode 115 of the first transistor 110, the electrode 136 of the capacitor element 130 , the electrode 181 of the capacitor element 150, and the electrode 103b of the second transistor 100 include the node corresponds to the node FN shown in FIG. 16(A).

[0264] Note that the description of the first embodiment can be applied to the second transistor 100.

[0265] The insulating films 127 and 129 covering the second transistor 100 function as a planarizing film covering the uneven shape of the lower layer thereof. Also, the insulating film 108 may function as a protective film when forming the insulating film 127. The insulating films 108 and 129 may not be provided if unnecessary. The insulating films 127 and 129 covering the second transistor 100 function as a planarizing film covering the uneven shape of the lower layer thereof. Also, the insulating film 108 may function as a protective film when forming the insulating film 127. The insulating films 108 and 129 may not be provided if unnecessary. The insulating films 108 and 129 may not be provided if unnecessary. It may not be provided if unnecessary.

[0266] Also, the plug 170 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 167. Also, the plug 171 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 168. Also, the plug 172 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 169. Also, the plug 176 is provided so as to be embedded in the insulating film 128 and is electrically connected to the electrode 183 of the capacitor element 150. Also, the plug 170 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 167. Also, the plug 171 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 168. Also, the plug 172 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 169. Also, the plug 176 is provided so as to be embedded in the insulating film 128 and is electrically connected to the electrode 183 of the capacitor element 150. Also, the plug 171 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 168. Also, the plug 172 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 169. Also, the plug 176 is provided so as to be embedded in the insulating film 128 and is electrically connected to the electrode 183 of the capacitor element 150. Also, the plug 172 is provided so as to be embedded in the insulating film 128 and is electrically connected to the plug 169. Also, the plug 176 is provided so as to be embedded in the insulating film 128 and is electrically connected to the electrode 183 of the capacitor element 150. Also, the plug 176 is provided so as to be embedded in the insulating film 128 and is electrically connected to the electrode 183 of the capacitor element 150. It is electrically connected.

[0267] Also, the electrode 173 is electrically connected to the plug 170 and the wiring BL, the electrode 174 is electrically connected to the plug 171 and the wiring WL, and the electrode 175 is electrically connected to the plug 172 and the wiring SL. Also, the electrode 173 is electrically connected to the plug 170 and the wiring BL, the electrode 174 is electrically connected to the plug 171 and the wiring WL, and the electrode 175 is electrically connected to the plug 172 and the wiring SL. is connected, and the electrode 177 is electrically connected to the plug 176 and the wiring CL3.

[0268] A semiconductor device according to one aspect of the present invention includes a first transistor 110 and a second transistor 100 located above the first transistor, and by stacking and providing these, the occupied area of the element can be reduced. Further, since the capacitor element 130 is located below the second transistor 100, by stacking and providing these, the occupied area of the element can be reduced. Further, since the capacitor element 150 is located above the first transistor 110, by stacking and providing these, the occupied area of the element can be reduced. In addition, since the wiring CL2 has an overlapping region with the gate electrode 105 of the second transistor 100, the occupied area of the element can be further reduced. Also, since the wiring CL3 has an overlapping region with the gate electrode 115 of the first transistor 110, the occupied area of the element can be further reduced. Further, the barrier film 120 provided between the first transistor 110 and the second transistor 100 can suppress the diffusion of impurities such as water and hydrogen existing in the lower layer to the second transistor 100 side.

[0269] The above is the description of the configuration example.

[0270] [Example of manufacturing method] Hereinafter, an example of the manufacturing method of the semiconductor device shown in the above configuration example will be described with reference to FIGS. 10 to 12, FIGS. 18 to 19.

[0271] Referring to FIGS. 10 to 12(A) of the [Example of manufacturing method] of Embodiment 1, the second transistor Form the gate insulating film 104 and the gate electrode 105 of the transistor 100 (see Fig. 18(A)).

[0272] At this stage, the second transistor 100 is formed.

[0273] Subsequently, an insulating film 107 is formed. After the formation of the insulating film 107, it is preferable to perform a heat treatment. By the heat treatment, oxygen can be supplied from the insulating film 126 or the like to the oxide semiconductor film 101b, and oxygen deficiency in the oxide semiconductor film 101b can be reduced. At this time, the oxygen desorbed from the insulating film 126 is blocked by the barrier film 120 and the insulating film 107 and does not diffuse to the layer below the barrier film 120 and the layer above the insulating film 107. Therefore, the oxygen can be effectively confined. As a result, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased, and oxygen deficiency in the oxide semiconductor film 101b can be effectively reduced.

[0274] Subsequently, an insulating film 108, an insulating film 127, and an insulating film 129 are formed in this order (see Fig. 18(B)). The insulating film 108, the insulating film 127, and the insulating film 129 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, an APCVD (Atmospheric Pressure CVD) method, etc.), an MBE method, an ALD method, or a PLD method. In particular, it is preferable to form the insulating film 108 by a DC sputtering method because a film with high barrier properties can be formed thickly with good productivity. Also, when forming by an ALD method, ion damage can be reduced and the coating property can be made good, so it is preferable. When an organic insulating material such as an organic resin is used as the insulating film 127, spin coating or the like can be used. ​​​​​​​​​​​​It may be formed using a coating method such as the spin coating method. Further, after forming the insulating film 127, it is preferable to perform a planarization process on the upper surface thereof. Further, heat treatment may be performed to fluidize and planarize it. Further, in order to make the flatness better, after forming the insulating film 127, an insulating film is laminated using the CVD method, and then a planarization process is preferably performed on the upper surface thereof. Subsequently, in the same manner as described above, openings are provided in the insulating film 129, the insulating film 127, the insulating film 108, and the insulating film 107, and a plug 167 reaching the plug 164, a plug 168 reaching the gate electrode 105, a plug 169 reaching the plug 166, and a plug 176 reaching the plug 165 are formed. Subsequently, a resist mask is provided so that the plug 176 and the plug 165 are etched, and the plug 176 and the plug 165 are etched to form an opening 179 (see FIG. 19(A)). Subsequently, an electrode 181 of the capacitor element 150 is formed in the opening 179, an insulating film 182 is formed on the electrode 181, and an electrode 183 is formed on the insulating film 182 (see FIG. 19(B)). Note that the material of the capacitor element 150 can be the same as that of the capacitor element 130 described above. Subsequently, an insulating film 128 is formed. Note that the insulating film 128 can be the same as the insulating film 127.

[0275] Subsequently, in the same manner as described above, openings are provided in the insulating film 128, and a plug 170 reaching the plug 167, a plug 171 reaching the plug 168, and a plug 172 reaching the plug 169 are formed. Subsequently, a resist mask is provided so that the plug 176 and the plug 165 are etched, and the plug 176 and the plug 165 are etched to form an opening 179 (see FIG. 19(A)). Subsequently, an electrode 181 of the capacitor element 150 is formed in the opening 179, an insulating film 182 is formed on the electrode 181, and an electrode 183 is formed on the insulating film 182 (see FIG. 19(B)). Note that the material of the capacitor element 150 can be the same as that of the capacitor element 130 described above. Subsequently, an insulating film 128 is formed. Note that the insulating film 128 can be the same as the insulating film 127.

[0276] Subsequently, a resist mask is provided so that the plug 176 and the plug 165 are etched, and the plug 176 and the plug 165 are etched to form an opening 179 (see FIG. 19(A)). Subsequently, an electrode 181 of the capacitor element 150 is formed in the opening 179, an insulating film 182 is formed on the electrode 181, and an electrode 183 is formed on the insulating film 182 (see FIG. 19(B)). Note that the material of the capacitor element 150 can be the same as that of the capacitor element 130 described above. Subsequently, an insulating film 128 is formed. Note that the insulating film 128 can be the same as the insulating film 127.

[0277] Subsequently, an electrode 181 of the capacitor element 150 is formed in the opening 179, an insulating film 182 is formed on the electrode 181, and an electrode 183 is formed on the insulating film 182 (see FIG. 19(B)). Note that the material of the capacitor element 150 can be the same as that of the capacitor element 130 described above. Subsequently, an insulating film 128 is formed. Note that the insulating film 128 can be the same as the insulating film 127. Subsequently, a resist mask is provided so that the plug 176 and the plug 165 are etched, and the plug 176 and the plug 165 are etched to form an opening 179 (see FIG. 19(A)).

[0278] Subsequently, an insulating film 128 is formed. Note that the insulating film 128 can be the same as the insulating film 127. Subsequently, a resist mask is provided so that the plug 176 and the plug 165 are etched, and the plug 176 and the plug 165 are etched to form an opening 179 (see FIG. 19(A)).

[0279] Subsequently, an electrode 181 of the capacitor element 150 is formed in the opening 179, an insulating film 182 is formed on the electrode 181, and an electrode 183 is formed on the insulating film 182 (see FIG. 19(B)). Note that the material of the capacitor element 150 can be the same as that of the capacitor element 130 described above. Subsequently, a resist mask is provided so that the plug 176 and the plug 165 are etched, and the plug 176 and the plug 165 are etched to form an opening 179 (see FIG. 19(A)). , a plug 176 reaching the electrode 183 is formed.

[0280] Next, an electrode 173 electrically connected to the plug 170 and an electrode 174 electrically connected to the plug 171 are an electrode 174 electrically connected to the plug 172; an electrode 175 electrically connected to the plug 176; An electrode 177 is formed to connect to the

[0281] Furthermore, the electrode 173 is electrically connected to the wiring BL, and the electrode 174 is electrically connected to the wiring WL. The electrode 175 is electrically connected to the wiring SL, and the electrode 177 is electrically connected to the wiring CL3. (See FIG. 16B). The material can be the same as that of the wiring CL in the first embodiment.

[0282] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0283] <Modification 4> As a modification of this embodiment, the position of the capacitance element 130 is changed as shown in FIG. may be provided above the second transistor 100. Specifically, the wiring BL and the wiring WL An insulating film 151 is formed on the wiring SL and the insulating film 128. Then, an opening is formed in the insulating film 151. The plug 178 is then electrically connected to the plug 176. Then, a capacitance element 130 is formed to electrically connect to the insulating film 130. The capacitor 130 is electrically connected to the wiring CL2 and has a gate electrode 152. 105 and has an overlapping area.

[0284] As shown in FIG. 20B, the upper and lower portions of the gate electrode 105 of the second transistor 100 It may be configured to provide the capacitive element 130 and the capacitive element 190. In addition, as shown in FIG. 20(B), the opening for forming the capacitive element 150 may be deeper than that in FIG. 20(A), or as shown in FIG. 21, the opening for forming the capacitive element 150 may be shallower than that in FIG. 20(A).

[0285] In addition, in this embodiment, the shapes of the capacitive element 130 and the capacitive element 190 are parallel plate types, but it is not limited to this.

[0286] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0287] (Embodiment 3) In this embodiment, an oxide semiconductor suitably used for the semiconductor film of a semiconductor device according to an aspect of the present invention will be described.

[0288] The oxide semiconductor has a large energy gap of 3.0 eV or more, and an oxide semiconductor film obtained by processing the oxide semiconductor under appropriate conditions and sufficiently reducing its carrier density is applied. In the transistor, the leakage current (off-current) between the source and the drain in the off state can be made extremely low compared to a conventional transistor using silicon.

[0289] As an applicable oxide semiconductor, it is preferably included at least indium (In) or zinc (Zn). In particular, it is preferably included In and Zn. In addition, as a stabilizer for reducing the variation in the electrical characteristics of a transistor using the oxide semiconductor, in addition to those, gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr) ​​, one or more selected from titanium (Ti), scandium (Sc), yttrium (Y), lanthanoids (for example , cerium (Ce), neodymium (Nd), gadolinium (Gd)), or preferably a plurality thereof are included.

[0290] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide , Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide , In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO ), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc-Zn -based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based acid oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide , In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide , In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, I n-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga- Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, I n-Hf-Al-Zn-based oxide can be used.

[0291] Here, the In-Ga-Zn-based oxide has In, Ga, and Zn as main components and is an oxide It means a substance, and the ratio of In, Ga, and Zn does not matter. Also, metal elements other than In, Ga, and Zn may be contained.

[0292] Also, as the oxide semiconductor, InMO3(ZnO) m (m > 0 and m is not an integer ) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co, or the elements as the above stabilizer . Also, as the oxide semiconductor, In2SnO5(ZnO) n (n > 0 and n is an integer) may be used.

[0293] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:3:2, In:Ga :Zn = 1:3:4, In:Ga:Zn = 1:3:6, In:Ga:Zn = 3:1:2, or In:Ga:Zn = 2:1:3, or oxides in the vicinity of its composition may be used.

[0294] When a large amount of hydrogen is contained in the oxide semiconductor film, by combining with the oxide semiconductor, a part of hydrogen becomes a donor and generates electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after forming the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film and purify it to be as free of impurities as possible. is preferred.

[0295] Note that by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen may also simultaneously decrease from the oxide semiconductor film. Therefore, the dehydration treatment (dehydration A process of adding oxygen to the oxide semiconductor film to compensate for oxygen defects increased by the dehydrogenation treatment (dehydrogenation process). It is preferable to perform this. In this specification and the like, the case of supplying oxygen to the oxide semiconductor film may be referred to as an oxygen addition process, or the case of making the oxygen contained in the oxide semiconductor film more than the stoichiometric composition may be referred to as a peroxygenation process.

[0296] In this way, the oxide semiconductor film is hydrogen or moisture removed by the dehydration treatment (dehydrogenation treatment), and by compensating for oxygen defects by the oxygen addition process, it can be made into an oxide semiconductor film that is i-type (intrinsic) or substantially i-type approaching i-type without limit. Note that substantially intrinsic means that the carriers derived from donors in the oxide semiconductor film are extremely few (close to zero), the carrier density is 1×10 / cm 17 / cm 3 or less, 1×10 16 / cm 3 or less , 1×10 15 / cm 3 or less, 1×10 14 / cm 3 or less, 1×10 13 / cm 3 or less is what is meant.

[0297] Also, in this way, a transistor including an oxide semiconductor film that is i-type or substantially i-type can achieve extremely excellent off-current characteristics. For example, the drain current when the transistor using the oxide semiconductor film is in the off state is 1×10 A or less at room temperature (about 25°C), preferably 1×10 -18 A or less, more preferably 1×10 A or less, or -21 85°C at 1×10 -24 A or less, preferably 1×10 A or less, preferably 1×10 -15 A or less, more preferably 1×10 -18A or less, more preferably 1×10 -21 It can be A or less. Note that when the transistor is in the off state, in the case of an n-channel transistor, it means a state where the gate voltage is sufficiently smaller than the threshold voltage. Specifically, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold voltage, the transistor is in the off state. Specifically, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold voltage, the transistor is in the off state.

[0298] <Structure of Oxide Semiconductor> Hereinafter, the structure of the oxide semiconductor will be described.

[0299] Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semicond uctor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous l ike Oxide Semiconductor), amorphous oxide semiconductors, and the like.

[0300] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC- OS, polycrystalline oxide semiconductors, nc-OS, and the like.

[0301] As the definition of an amorphous structure, generally, it is known that it is not fixed in a metastable state, is isotropic, and does not have a heterogeneous structure. Also, it can be rephrased as a structure with a flexible bond angle, having short-range order but not having long-range order. It can also be said that it has a flexible bond angle, has short-range

[0302] Conversely, in the case of an essentially stable oxide semiconductor, it cannot be called a completely amorphous oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a minute region) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has voids and is an unstable structure. Therefore, it can be said that, in terms of physical properties, it is close to an amorphous oxide semiconductor. tely amorphous) oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a minute region) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has voids and is an unstable structure. Therefore, it can be said that, in terms of physical properties, it is close to an amorphous oxide semiconductor. oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has voids and is an unstable structure. Therefore, it can be said that, in terms of physical properties, it is close to an amorphous oxide semiconductor. oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has voids and is an unstable structure. Therefore, it can be said that, in terms of physical properties, it is close to an amorphous oxide semiconductor. oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has voids and is an unstable structure. Therefore, it can be said that, in terms of physical properties, it is close to an amorphous oxide semiconductor. oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has voids and is an unstable structure. Therefore, it can be said that, in terms of physical properties, it is close to an amorphous oxide semiconductor.

[0303] <caac-os> First, CAAC-OS will be described.

[0304] CAAC-OS is an oxide semiconductor having a plurality of c-axis oriented crystal parts (also referred to as pellets). It is one of the semiconductor materials.

[0305] By using a transmission electron microscope (TEM: Transmission Electron Microscope), a composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS can be observed, and a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. oscope) to observe the composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS, and a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. oscope) to observe the composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS, and a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. oscope) to observe the composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS, and a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. oscope) to observe the composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS, and a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. oscope) to observe the composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS, and a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0306] Hereinafter, CAAC-OS observed by TEM will be described. FIG. 22(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. Hereinafter, CAAC-OS observed by TEM will be described. FIG. 22(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function is used. The high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, by using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function is used. The high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, by using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function is used. The high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, by using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function is used. The high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, by using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function is used. The high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, by using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0307] FIG. 22(B) shows a magnified Cs-corrected high-resolution TEM image of the region (1) in FIG. 22(A). From FIG. 22(B), it can be confirmed that in the pellet, the metal atoms are arranged in layers. FIG. 22(B) shows a magnified Cs-corrected high-resolution TEM image of the region (1) in FIG. 22(A). From FIG. 22(B), it can be confirmed that in the pellet, the metal atoms are arranged in layers. It is as follows. The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) on which the CAAC-OS film is formed and is parallel to the surface to be formed or the upper surface of the CAAC-OS. Or it reflects the unevenness of the upper surface and is parallel to the surface to be formed or the upper surface of the CAAC-OS.

[0308] As shown in FIG. 22(B), CAAC-OS has a characteristic atomic arrangement. FIG. 22(C ) shows the characteristic atomic arrangement indicated by auxiliary lines. From FIGS. 22(B) and 22(C ), the size of one pellet is 1 nm or more or 3 nm or more, and it can be seen that the size of the gap generated by the inclination between the pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc). Also, CAAC-OS can be called an oxide semiconductor having CANC (C-Axis Aligned nanocry stals). Here, based on the Cs-corrected high-resolution TEM image, when schematically showing the arrangement of the pellets 5100 of CAAC-OS on the substrate 5120, it has a structure like bricks or blocks stacked (see FIG. 22(D)). The portion where an inclination occurs between the pellets observed in FIG. 22(C) corresponds to the region 5161 shown in FIG. 22(D).

[0309] Also, FIG. 23(A) shows the Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The enlarged Cs-corrected high-resolution TEM images of the regions (1), (2), and (3 ) in FIG. 23(A) are shown in FIGS. 23(B), 23(C), and FIG. 23(D), respectively. From FIGS. 23(B), 23(C), and 23(D), it can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape in the pellet. However,

[0310] Also, FIG. 23(A) shows the Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The enlarged Cs-corrected high-resolution TEM images of the regions (1), (2), and (3 ) in FIG. 23(A) are shown in FIGS. 23(B), 23(C), and ) are shown in FIGS. 23(B), 23(C), and FIG. 23(D), respectively. From FIGS. 23(B), 23(C), and 23(D), it can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape in the pellet. However, However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0311] Next, C analyzed by X-ray diffraction (XRD) AAC-OS will be described. For example, for CAAC-OS having a crystal of InGaZnO4, when performing a structural analysis by the out-of-plane method on S, peaks may appear at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the crystal of InGa ZnO4, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0312] In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak at around 2θ of 31 °, peaks may also appear at around 2θ of 36°. The peak at around 2θ of 36 ° indicates that a part of CAAC-OS contains crystals having no c-axis orientation. More preferable CAAC-OS shows a peak at around 2θ of 31° and does not show a peak at around 2θ of 36° in the structural analysis by the out-of-plane method.

[0313] On the other hand, when performing a structural analysis of CAAC-OS by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at around 2θ of 56°. This peak is attributed to the (110) plane of the crystal of InGaZnO4. In the case of CAAC-OS, even when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 5 6°, no distinct peak appears as shown in Fig. 24(B). (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 5 On the other hand, in the case of a single-crystalline oxide semiconductor of InGaZnO4, when 2θ is fixed near 56° and φ is scanned, as shown in Fig. 24(C), six peaks attributable to crystal planes equivalent to the (110) plane are observed. Therefore, from the structural analysis using XRD, it can be confirmed that in CAAC-OS , the orientations of the a-axis and the b-axis are irregular.

[0314] Next, CAAC-OS analyzed by electron diffraction will be described. For example, for CAAC-OS having a crystal of InGa ZnO4, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface, a diffraction pattern as shown in Fig. 25(A) (also referred to as a limited-field transmission electron diffraction pattern) may appear. This diffraction pattern includes spots attributable to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets included in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, for the same sample, the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface is shown in Fig. 25(B). From Fig. 2 5(B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and the b-axis of the pellets included in CAAC-OS have no orientation. Note that the first ring in Fig. 25(B) is considered to be attributable to the (010) plane and the (100) plane, etc. of the InGaZnO4 crystal. Also, the second ring in Fig. 25(B) is considered to be attributable to the (110) plane, etc.

[0315] As described above, CAAC-OS is a highly crystalline oxide semiconductor. For the oxide semiconductor Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0316] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0317] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0318] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Such an oxide semiconductor is a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and low defect level density. In other words, it has stable characteristics. It can be said that the oxide semiconductor has the above structure.

[0319] <nc-os> Next, nc-OS will be described.

[0320] In a high-resolution TEM image, nc-OS has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed. The crystal parts contained in nc-OS often have a size of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. In addition, an oxide semiconductor with a crystal part size larger than 10 nm and 100 nm or less may be called a microcrystalline oxide semiconductor. In nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed. Note that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystal parts of nc-OS may sometimes be referred to as pellets.

[0321] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS shows no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Consequently, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or amorphous oxide semiconductors. For example, when using X-rays with a diameter larger than that of the pellets for nc-OS, in the analysis by the out-of-plane method, peaks indicating crystal planes are not detected. Also, when performing electron diffraction using an electron beam with a probe diameter larger than that of the pellets (for example, 50 nm or more) for nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, for nc-OS, when using a probe diameter close to or smaller than the size of the pellets ​​​​When performing nanobeam electron diffraction using an electron beam with a lobe diameter, spots are observed. Also, When performing nanobeam electron diffraction on nc-OS, there are cases where regions with high luminance are observed in a circular (ring-like) pattern. Furthermore, there are cases where multiple spots are observed within the ring-like region.

[0322] Thus, since the crystal orientations among the pellets (nanocrystals) have no regularity, nc-OS can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

[0323] nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore, nc-OS has a lower density of defect levels than a-like OS or an amorphous oxide semiconductor. However, nc-OS does not show regularity in crystal orientation among different pellets. Therefore, nc-OS has a higher density of defect levels than CAAC-OS.

[0324] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

[0325] In a high-resolution TEM image, looseness may be observed for a-like OS. Also, in a high-resolution TEM image, there are regions where the crystal part can be clearly confirmed and regions where the crystal part cannot be confirmed.

[0326] Due to having looseness, a-like OS has an unstable structure. Below, a-lik ​​​​​​​The e-OS has a less stable structure compared to CAAC-OS and nc-OS, indicating structural changes due to electron irradiation.

[0327] As samples for electron irradiation, a-like OS (denoted as sample A), nc-OS (denoted as sample B), and CAAC-OS (denoted as sample C) are prepared. All samples are In-Ga-Zn oxides.

[0328] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, it can be seen that each sample has a crystalline part.

[0329] The determination of which part is regarded as one crystalline part can be carried out as follows. For example , the unit cell of InGaZnO4 crystals has a structure in which three In-O layers and six Ga-Zn-O layers are stacked in layers in the c-axis direction, with a total of nine layers. It is known that the distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also referred to as the d-value), and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the lattice fringe spacing is between 0.28 nm and 0.30 nm can be regarded as the crystalline part of InGaZnO4. The lattice fringes correspond to the a-b plane of the InGaZnO4 crystals.

[0330] Figure 26 shows an example of investigating the average size of the crystalline parts (from 22 to 45 locations) of each sample. However, the length of the lattice fringes described above is used as the size of the crystalline part. From Figure 26, it can be seen that the crystalline part of a-like OS increases with the cumulative electron irradiation dose. Specifically ​​​​​​​The crystal part (also referred to as the initial nucleus) with a certain degree of size has a cumulative irradiation dose of 4.2×10 8 e - / n m 2 It can be seen that it has grown to a size of about 2.6 nm at. On the other hand, nc-O S and CAAC-OS show no change in the size of the crystal part from the start of electron irradiation until the cumulative electron irradiation dose reaches 4.2×10 8 e - / nm 2 . Specifically, as shown in (2) and (3) in FIG. 26, regardless of the cumulative electron irradiation dose, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm and about 2.1 nm respectively, as can be seen.

[0331] Thus, a-like OS may show crystal growth by electron irradiation. On the other hand, it can be seen that nc-OS and CAAC-OS show almost no crystal growth by electron irradiation. That is, a-like OS has a more unstable structure compared to nc-OS and CAAC- OS.

[0332] Also, due to having looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition. Also, the density of nc-OS and CAA C-OS is 92.3% or more and less than 100% of the density of a single crystal with the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself. For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio],

[0333] ​The density of single-crystalline InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 becomes. Thus, in an oxide semiconductor satisfying, for example, In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 becomes. Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 becomes.

[0334] Note that there may be cases where single crystals of the same composition do not exist. In that case, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor takes various structures, each having various characteristics. Note that the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0335] As described above, the present embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. Note that the present embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. Note that the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0336] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0337] (Embodiment 4) In this embodiment, an example of a circuit using a transistor of one aspect of the present invention will be described with reference to the drawings. A description will be given with reference to it.

[0338] [Circuit configuration example] In the configuration shown in Embodiment 1, by varying the connection configurations of transistors, wirings, and electrodes, various circuits can be configured. Hereinafter, an example of a circuit configuration that can be realized by using a semiconductor device according to an aspect of the present invention will be described.

[0339] [CMOS circuit] The circuit diagram shown in FIG. 27(A) shows a so-called CM OS circuit configuration in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. In the figure, the transistors to which the second semiconductor material is applied are indicated with the symbol "OS".

[0340] [Analog switch] Also, the circuit diagram shown in FIG. 27(B) shows a configuration in which the sources and drains of transistor 2100 and transistor 2200 are connected. By adopting such a configuration, it can function as a so-called analog switch.

[0341] [Example of a memory device] An example of a semiconductor device (memory device) that can hold stored contents even in a situation where no power is supplied and has no limitation on the number of write operations by using a transistor that is an aspect of the present invention is shown in FIG. 2 7(C). The semiconductor device shown in FIG. 27(C) has a transistor 3200 using the first semiconductor material,

[0342] a transistor 3300 using the second semiconductor material, and a capacitor element 3400. As the transistor 3300, the transistors exemplified in the above embodiment are used. ​ It is possible.

[0343] The transistor 3300 is a transistor in which a channel is formed in a semiconductor film having an oxide semiconductor. The off-state current of the transistor 3300 is small, so that the transistor 3300 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. To provide a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0344] In FIG. 27C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0345] In the semiconductor device shown in FIG. 27C, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0346] The writing and holding of data will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (writing). Here, it is assumed that either one of two different potential level charges ( hereinafter referred to as Low level charge and High level charge) is applied . Then, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, and the transistor 3300 is turned off, so that the charge applied to the gate electrode of the transistor 3200 is held (holding). Since the off-current of the transistor 3300 is extremely small, the charge on the gate electrode of the transistor 3200 is held for a long time.

[0347]

[0348] Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes different potentials according to the amount of charge held on the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold value V when a High level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold value V when a Low level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage means the potential of the fifth wiring 3005 required to turn the transistor 3200 "on". Therefore, the potential of the fifth wiring 3005 is set to V and V th_ H th_L th_H and V​​​​​​​​ th_L Between By setting the potential to V0, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, in writing, when a high-level charge is applied, if the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 enters the " on state". When a low-level charge is applied, even if the potential of the fifth wiring 3005 becomes V0 (< V th_L ), the transistor 3200 remains in the "off state". Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out.

[0349] When the memory cells are arranged and used in an array, it is necessary to be able to read out only the information of the desired memory cell. When the information is not read out in this way, a potential such that the transistor 3200 enters the "off state" regardless of the state of the gate electrode, that is, a potential smaller than V th_ H th_L H can be applied to the fifth wiring 3005. Or, a potential such that the transistor 3200 enters the "on state" regardless of the state of the gate electrode, that is, a potential larger than V th_L th_L th_L can be applied to the fifth wiring 3005.

[0350] Here, a cross-sectional schematic diagram of the circuit diagram in Fig. 27(A) and a cross-sectional schematic diagram of the configuration in which the wirings 3001 and 3003 in Fig. 27(C) are shared (the circuit diagram in Fig. 1(A)) are shown in Fig. 28. The cross-sectional schematic diagram of Fig. 27(A) is shown on the left side of the dotted line, and the cross-sectional schematic diagram of the circuit diagram in Fig. 1(A) is shown on the right side of the dotted line.

[0351] ​​​​As shown in the figure, a transistor 3200 and a transistor located above the transistor 3200 3300, and by stacking these, the area occupied by the element is reduced. Furthermore, since the capacitor element 3400 is located below the transistor 3300, By stacking these layers, the area occupied by the element can be reduced. 3005 has an area overlapping with the gate electrode of the transistor 3300, The child's footprint can be reduced.

[0352] Also, as shown in FIG. 29, the transistor 3300 and the transistor 2100 are fabricated in separate processes. It may be configured as follows.

[0353] The semiconductor device shown in FIG. 27D is different from the semiconductor device shown in FIG. 2 mainly in that the transistor 3200 is not provided. 7(C). In this case, the same operations as above are performed to write and hold information. It is possible to create

[0354] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The change in the potential of the third wiring 3003 is proportional to the change in the potential of the first terminal of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0355] For example, the potential of the first terminal of the capacitance element 3400 is V, the capacitance of the capacitance element 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of the first terminal of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0356] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0357] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor in which a second semiconductor material is applied is used as the transistor 3300. The transistor may be laminated on the driver circuit.

[0358] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0359] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem of element degradation. For example, unlike conventional non-volatile memories, there is no need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories. The reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0360] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. It can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0361] (Embodiment 5) In this embodiment, the RF tag including the transistor or the memory device exemplified in the above embodiment will be described with reference to FIG. 30.

[0362] The RF tag in this embodiment has a memory circuit inside, stores information necessary for the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Due to such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for these applications.

[0363]

[0364] The configuration of the RF tag will be described with reference to FIG. 30. FIG. 30 is a block diagram showing a configuration example of the RF tag.

[0364] As shown in FIG. 30, the RF tag 800 includes a communicator 801 (such as an interrogator, a reader / writer, etc.) An antenna that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as a communicator). It has an antenna 804. The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing the reverse current in a transistor exhibiting a rectifying action included in the demodulation circuit 807, for example, an oxide semiconductor, may be used. With this configuration, it is possible to suppress a decrease in the rectifying action caused by the reverse current and prevent the output of the demodulation circuit from saturating. That is, it is possible to make the output of the demodulation circuit closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. For example, a material such as an oxide semiconductor that can sufficiently suppress the reverse current in a transistor showing a rectifying action may be used. By this, a decrease in the rectifying action due to the reverse current can be suppressed, and it can be prevented that the output of the demodulation circuit saturates. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. That is, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods.

[0365] Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and generates an input potential by smoothing the rectified signal with a capacitive element provided in the subsequent stage. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

[0366] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. It is a circuit for this purpose. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating the reset signal of the logic circuit 8 09 by utilizing the rising edge of a stable power supply voltage.

[0367] The demodulation circuit 807 demodulates the input AC signal by envelope detection and generates a demodulated signal. It is a circuit for this purpose. Also, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

[0368] The logic circuit 809 analyzes the demodulated signal and is a circuit for performing processing. The memory circuit 810 is a circuit for holding the input information and has a row decoder, a column decoder, a storage area, etc. Also, the ROM 811 stores unique numbers (IDs), etc., and is a circuit for outputting according to processing.

[0369] Note that each of the above circuits can be appropriately selected or discarded as necessary.

[0370] Here, the memory circuit described in the previous embodiment can be used as the memory circuit 810. Since the memory circuit according to one aspect of the present invention can hold information even when the power supply is cut off, it can be suitably used for an RF tag. Furthermore, since the memory circuit according to one aspect of the present invention requires significantly less power (voltage) for writing data compared to conventional non-volatile memories, it is also possible not to cause a difference in the maximum communication distance between the read and write operations of the data. Furthermore, it is possible to suppress the occurrence of malfunction or incorrect writing due to insufficient power during data writing. ​

[0371] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to the ROM811. In that case, the producer prepares a command for writing data to the ROM811 separately, and it is preferable to prevent the user from freely rewriting it. After the producer writes the unique number before shipping, the product is shipped. In this way, it is possible to assign unique numbers only to the non-defective products to be shipped, rather than to all the manufactured RF tags, so that the unique numbers of the products after shipping are not discontinuous, and customer management corresponding to the products after shipping becomes easy.

[0372] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0373] (Embodiment 6) In this embodiment, at least the transistors described in the embodiment can be used, and a CPU including the memory device described in the previous embodiment will be described.

[0374] FIG. 31 is a block diagram showing a configuration example of a CPU using at least some of the transistors described in the previous embodiment.

[0375] The CPU shown in FIG. 31 includes, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface - 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in FIG. 31 is only an example shown with its configuration simplified, and an actual CPU has a wide variety of configurations depending on its application. For example, a configuration including the CPU or arithmetic circuit shown in FIG. 31 may be used as one core, and a plurality of such cores may be included so that each core operates in parallel. Also, the number of bits that the CPU can handle

[0376] with its internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc. Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192,

[0377] interrupt controller 1194, register controller 1197, and timing controller 1195. The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller Generate a dress and read from and write to register 1196 according to the state of the CPU .

[0378] Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 11 92, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0379] In the CPU shown in FIG. 31, memory cells are provided in the register 1196. As the memory cells of the register 1196, the transistors shown in the previous embodiment can be used.

[0380] In the CPU shown in FIG. 31, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cells included in the register 1 196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed. When holding data in the capacitive element is selected, data can be rewritten to the capacitive element, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0381] FIG. 32 is an example of a circuit diagram of a storage element that can be used as the register 1196 ​​​​​​​。The memory element 1200 includes a circuit 1201 in which stored data is volatile when the power supply is cut off, a circuit 1202 in which stored data is non-volatile when the power supply is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210 and. Note that the memory element 1200 may further include other elements such as a diode, a resistive element, and an inductor as necessary.

[0382] Here, the memory device described in the previous embodiment can be used for the circuit 1202. When the supply of the power voltage to the memory element 1200 is stopped, the gate of the transistor 12 09 in the circuit 1202 is configured to receive a ground potential (0 V) or a potential at which the transistor 1209 is turned off continuously. For example, the gate of the transistor 1209 is grounded through a load such as a resistor .

[0383] The switch 1203 is configured by using a transistor 1213 of one conductivity type (for example, an n-channel type), and the switch 1204 is configured by using a transistor 1214 of a conductivity type opposite to that of the one conductivity type (for example, a p-channel type) . Here, the first terminal of the switch 1203 corresponds to one of the source and drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 selects conduction or non-conduction (that is, the on state or off state of the transistor 1213) between the first terminal and the second terminal by a control signal RD input to the gate of the transistor 1213. The first terminal of the switch 1204 is the source and drain of the transistor 1214 corresponds to one of them, the second terminal of the switch 1204 corresponds to the other of the source and drain of the transistor 1214, and the switch 1204 is controlled by a control signal WR input to the gate of the transistor 1214, and conduction or non-conduction (that is, the on state or off state of the transistor 1214) between the first terminal and the second terminal is selected. rain of the transistor 1214, and the second terminal of the switch 1204 corresponds to the other of the source and drain of the transistor 1214. The switch 1204 is controlled by a control signal WR input to the gate of the transistor 1214, and conduction or non-conduction (that is, the on state or off state of the transistor 1214) between the first terminal and the second terminal is selected. Corresponding to one side of the rain, the second terminal of switch 1204 is the source of transistor 1214 and corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214 by the control signal RD input thereto, the conduction or non - conduction between the first terminal and the second terminal (that is, the on - state or off - state of transistor 1214) is selected.

[0384] One of the source and drain of transistor 1209 is electrically connected to one of a pair of electrodes of capacitor element 1208, and to the gate of transistor 1210. Here, the connection part is taken as node M2. One of the source and drain of transistor 1210 is electrically connected to a wiring (for example, GND line) capable of supplying a low power supply potential, and the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). The second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain of transistor 1214). The second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of switch 1203 (the other of the source and drain of transistor 1213 ), the first terminal of switch 1204 (one of the source and drain of transistor 1214), the input terminal of logic element 1206, and one of a pair of electrodes of capacitor element 1207 are electrically connected. Here, the connection part is taken as node M1. The other of a pair of electrodes of capacitor element 1207 can be configured to input a constant potential. For example, a low electric potential is electrically connected. Here, the connection part is taken as node M1. The other of a pair of electrodes of capacitor element 1207 can be configured such that a certain potential is input. For example, a low electric It can be configured such that a source potential (such as GND) or a high power supply potential (such as VDD) is input. The other of the pair of electrodes of the capacitor element 1207 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential. The other of the pair of electrodes of the capacitor element 1208 can be configured such that a constant potential is input. For example, it can be configured such that a low power supply potential (such as GND) or a high power supply potential (such as VDD) is input. The other of the pair of electrodes of the capacitor element 1208 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential.

[0385] Note that the capacitor elements 1207 and 1208 can also be omitted by actively using parasitic capacitances of transistors, wirings, etc.

[0386] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

[0387] A signal corresponding to the data held in the circuit 1201 is input to the other of the source and drain of the transistor 1209. In FIG. 32, an example is shown in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is , it becomes an inverted signal whose logical value is inverted by the logic element 1206, and is input to the circuit 1201 via the circuit 1220. and is input to the circuit 1201 through the circuit 1220.

[0388] In addition, in FIG. 32, the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. Although an example of input to the circuit 1201 is shown, it is not limited to this. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) may be input to the circuit 1201 without inverting the logical value. For example, when there is a node in the circuit 1201 that holds a signal whose logical value is inverted from the signal input from the input terminal, the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) can be input to the node. In addition, in FIG. 32, among the transistors used in the memory element 1200, transistors other than the transistor 1209 can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, they can be transistors in which a channel is formed in a silicon layer or a silicon substrate. Also, all the transistors used in the memory element 1200 can be transistors in which a channel is formed of an oxide semiconductor film.

[0389] Alternatively, the memory element 1200 may include transistors in which a channel is formed of an oxide semiconductor film in addition to those other than the transistor 1209, and the remaining transistors can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, they can be transistors in which a channel is formed in a silicon layer or a silicon substrate. In addition, all the transistors used in the memory element 1200 can be transistors in which a channel is formed of an oxide semiconductor film. Or, the memory element 1200 may include transistors in which a channel is formed of an oxide semiconductor film in addition to those other than the transistor 1209, and the remaining transistors can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. In addition to those other than the transistor 1209, the memory element 1200 may include transistors in which a channel is formed of an oxide semiconductor film, and the remaining transistors can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. ​

[0390] In the circuit 1201 in FIG. 32, for example, a flip-flop circuit can be used. Also, as the logic element 1206, for example, an inverter, a clocked inverter, etc. can be used. can be used.

[0391] In the semiconductor device according to one aspect of the present invention, while the power supply voltage is not supplied to the memory element 1200 the data stored in the circuit 1201 can be held by the capacitive element 120 8 provided in the circuit 1202.

[0392] Also, the off-current of a transistor in which a channel is formed in an oxide semiconductor film is extremely small. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Thus, by using the transistor as the transistor 1209, the signal held in the capacitive element 1208 can be maintained for a long time even while the power supply voltage is not supplied to the memory element 1200. In this way, the memory element 1200 can hold the stored content ( data) even while the supply of the power supply voltage is stopped. data) can be held.

[0393] Also, by providing the switch 1203 and the switch 1204, since it is a memory element characterized by performing a precharge operation, after the resumption of the power supply voltage supply, the time until the circuit 1201 retains the original data again can be shortened.

[0394] Also, in the circuit 1202, the signal held by the capacitive element 1208 is input to the gate of the transistor 1210. Therefore, when the supply of the power supply voltage to the memory element 1200 is resumed ​After being opened, the signal held by the capacitive element 1208 can be converted into the state (on state or off state) of the transistor 1210 and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held by the capacitive element 1208 fluctuates slightly, the original signal can be accurately read out.

[0395] By using such a memory element 1200 in a storage device such as a register or a cache memory that the processor has, it is possible to prevent the loss of data in the storage device due to the stop of the supply of the power voltage. In addition, after the supply of the power voltage is resumed, it is possible to return to the state before the stop of the power supply in a short time. Therefore, in the entire processor or one or a plurality of logic circuits constituting the processor, it is possible to stop the power supply even for a short time, so that the power consumption can be suppressed.

[0396] In this embodiment, an example of using the memory element 1200 in a CPU has been described. However, the memory element 1200 can also be applied to LSIs such as DSP (Digital Signal Processor), custom LSIs, PLDs (Programmable Logic Device), and RF (Radio Frequency) devices.

[0397] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0398] (Embodiment 7) In this embodiment, a configuration example of a display panel according to an aspect of the present invention will be described.

[0399] [Configuration Example] ​FIG. 33(A) is a top view of a display panel according to an aspect of the present invention, and FIG. 33(B) is a circuit diagram for explaining a pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to an aspect of the present invention. Further, FIG. 33(C) is a circuit diagram for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel of a display panel according to an aspect of the present invention.

[0400] The transistors disposed in the pixel portion can be formed according to the above embodiment. Also, since it is easy to make the transistor an n-channel type, a part of the drive circuit composed of n-channel type transistors in the drive circuit can be formed on the same substrate as the transistors in the pixel portion. Thus, by using the transistors shown in the above embodiment for the pixel portion and the drive circuit, a highly reliable display device can be provided.

[0401] An example of a block diagram of an active matrix type display device is shown in FIG. 33(A). On a substrate 700 of the display device, there are a pixel portion 701, a first scan line drive circuit 702, a second scan line drive circuit 703, and a signal line drive circuit 704. A plurality of signal lines extend from the signal line drive circuit 704 and are disposed in the pixel portion 701, and a plurality of scan lines extend from the first scan line drive circuit 702 and the second scan line drive circuit 703 and are disposed. In the intersection region of the scan lines and the signal lines, pixels each having a display element are provided in a matrix. Further, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0402] ​​​​​​​​​​​​​In FIG. 33(A), the first scanning line driving circuit 702, the second scanning line driving circuit 703, and the signal line driving circuit 704 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as driving circuits provided externally is reduced, and cost reduction can be achieved. Also, when a driving circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. When the driving circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced, and reliability improvement or yield improvement can be achieved.

[0403] 〔Liquid Crystal Panel〕 Further, an example of the circuit configuration of a pixel is shown in FIG. 33(B). Here, a pixel circuit applicable to pixels of a VA type liquid crystal display panel is shown.

[0404] This pixel circuit can be applied to a configuration in which a plurality of pixel electrodes are provided for one pixel. Each pixel electrode is connected to a different transistor, and each transistor is configured to be drivable with a different gate signal. Thus, the signals applied to the individual pixel electrodes of pixels designed with multi-domains can be controlled independently.

[0405] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be applied. On the other hand, the source electrode or drain electrode 714 that functions as a data line is commonly used by the transistor 716 and the transistor 717. The transistor 716 and the transistor 717 can appropriately use the transistors described in the above embodiments in the form. Thus, a highly reliable liquid crystal display panel can be provided.

[0406] Further, a first pixel electrode is electrically connected to the transistor 716, and a second pixel electrode is electrically connected to the transistor 7 17. The first pixel electrode and the second pixel electrode are separated from each other. Note that the shapes of the first pixel electrode and the second pixel electrode are not particularly limited, and for example, they may be V-shaped.

[0407] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are applied to the gate wiring 712 and the gate wiring 71 3 to make the operation timings of the transistor 716 and the transistor 717 different, so that the alignment of the liquid crystal can be controlled.

[0408] Further, a holding capacitor may be formed by the capacitance wiring 710, a gate insulating film that functions as a dielectric, and a capacitance electrode that is electrically connected to the first pixel electrode or the second pixel electrode.

[0409] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel . The first liquid crystal element 718 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween, and the second liquid crystal element 719 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0410] Note that the pixel circuit shown in FIG. 33(B) is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, sensor, or logic circuit etc. may be added to the pixel shown in FIG. 33(B).

[0411] 〔Organic EL Panel〕 Another example of the circuit configuration of the pixel is shown in FIG. 33(C). Here, the pixel structure of the panel using the organic EL element is shown. ​

[0412] When a voltage is applied to the light-emitting element, electrons are emitted from one of the pair of electrodes, and holes are injected from the other into the layer containing the light-emitting organic compound, and a current flows. Then, when the electrons and holes recombine, the light-emitting organic compound forms an excited state, and light is emitted when this excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0413] FIG. 33(C) is a diagram showing an example of an applicable pixel circuit. Here, an example is shown in which two n-channel transistors are used for one pixel. Note that the metal oxide film of one aspect of the present invention can be used for the channel formation region of an n-channel transistor. Further, the pixel circuit can apply digital time gradation driving.

[0414] The configuration of the applicable pixel circuit and the operation of the pixel when digital time gradation driving is applied will be described.

[0415] Pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitive element 723. The switching transistor 721 has a gate electrode connected to the scanning line 726, a first electrode (one of the source electrode and the drain electrode) connected to the signal line 725, and a second electrode (the other of the source electrode and the drain electrode) connected to the gate electrode of the driving transistor 722. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The light-emitting element 72 is connected to the scanning line 726, a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 725, and a second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 722. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The light-emitting element 72 is connected to the scanning line 726, a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 725, and a second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 722. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The light-emitting element 72 is connected to the scanning line 726, a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 725, and a second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 722. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The light-emitting element 72 is connected to the scanning line 726, a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 725, and a second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 722. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The light-emitting element 72 is connected to the scanning line 726, a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 725, and a second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 722. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The light-emitting element 72 The second electrode of 4 corresponds to a common electrode 728. The common electrode 728 is formed on the same substrate. It is electrically connected to a common potential line.

[0416] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. The transistors described below can be used appropriately. This makes it possible to realize a highly reliable organic EL display. A display panel can be provided.

[0417] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727. For example, D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0418] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode and the gate electrode.

[0419] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive Apply it to the gate electrode of the transistor 722. Also, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power line voltage is applied to the signal line 725.

[0420] When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 72 4 is applied to the gate electrode of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region, and a current flows through the light emitting element 724. Also, in order to operate the driving transistor 722 in the saturation region, the potential of the power line 727 is made higher than the gate potential of the driving transistor 722. By making the video signal analog, a current corresponding to the video signal flows through the light emitting element 724, and analog gradation driving can be performed.

[0421] Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 33(C). For example, FIG. 3 A switch, a resistance element, a capacitance element, a sensor, a transistor, or a logic circuit or the like may be added to the pixel circuit shown in 3(C).

[0422] When applying the transistor exemplified in the above embodiment to the circuit exemplified in FIG. 33, a low voltage The source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side, respectively. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. It may be configured such that the potentials exemplified above can be input.

[0423] This embodiment can be appropriately combined with at least a part of other embodiments described in this specification. They can be implemented in combination.

[0424] (Embodiment 8) A semiconductor device according to an aspect of the present invention can be used in a display device, a personal computer, an image playback device having a recording medium (typically a device having a display capable of playing a recording medium such as DVD: Digital Versatile Disc c and displaying its image). In addition, electronic devices that can use the semiconductor device according to an aspect of the present invention include mobile phones, game machines including portable types, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays ), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 34.

[0425] FIG. 34(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 90 8, etc. Note that the portable game machine shown in FIG. 31(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this.

[0426] FIG. 34(B) is a portable data terminal, which has a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 91 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. There is. And the first housing 911 and the second housing 912 are connected by a connection part 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. It is also possible to configure the video on the first display part 913 to be switched according to the angle between the first housing 911 and the second housing 912 at the connection part 915. Further, a display device with a function as a position input device may be used for at least one of the first display part 913 and the second display part 914. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel part of the display device.

[0427] Figure 34(C) is a notebook personal computer, which has a housing 921, a display part 922, a keyboard 923, a pointing device 924, etc.

[0428] Figure 34(D) is an electric refrigerator-freezer, which has a housing 931, a refrigerator door 932, a freezer door 9 33, etc.

[0429] Figure 34(E) is a video camera, which has a first housing 941, a second housing 942, a display part 943, operation keys 944, a lens 945, a connection part 946, etc. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display part 943 is provided on the second housing 942. And the first housing 941 and the second housing 942 are connected by a connection part 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. ​​​It is possible. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 94 at the connection unit 946. It may be configured to switch according to the angle between the first housing 941 and the second housing 94 at the connection unit 946.

[0430] FIG. 34(F) shows a passenger car, which has a vehicle body 951, wheels 952, a dashboard 953, lights 954, etc.

[0431] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. It can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0432] (Embodiment 9) In this embodiment, a usage example of an RF device according to an aspect of the present invention will be described with reference to FIG. 35. Although the uses of RF devices are extensive, for example, banknotes, coins, securities, bearer bonds, certificates (such as driver's licenses and residence cards, see FIG. 35(A)), recording media (DVDs, video tapes, etc., see FIG. 35(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 35 (C)), vehicles (bicycles, etc., see FIG. 35(D)), personal belongings (bags, glasses, etc.), foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones) and other articles, or it can be provided and used on tags (see FIGS. 35(E) and 35(F)) attached to each article. or it can be provided and used on tags (see FIGS. 35(E) and 35(F)) attached to each article. It can be used.

[0433] An RF device 4000 according to an aspect of the present invention is fixed to an article by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each article. An R according to an aspect of the present invention is fixed to each article by being embedded inside the organic resin if it is a package made of an organic resin. An R according to an aspect of the present invention In order to achieve a small size, thin profile, and light weight, the F device 4000 does not impair the design of the article even after being fixed to the article. Also, by providing the RF device 4000 according to one aspect of the present invention to paper money, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and by utilizing this authentication function, forgery can be prevented. Also, by attaching the RF device according to one aspect of the present invention to packaging containers, recording media, personal belongings, food products, clothing, daily necessities, or electronic devices, the efficiency of systems such as inspection systems can be improved. Also, even in vehicles, by attaching the R F device according to one aspect of the present invention, the security against theft and the like can be enhanced.

[0434] As described above, by using the RF device according to one aspect of the present invention for each of the applications listed in this embodiment, the operating power including information writing and reading can be reduced, so that the maximum communication distance can be increased. Also, even in a state where the power is cut off, the information can be held for an extremely long period, so it can be suitably used for applications with low writing and reading frequencies.

[0435] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

Explanation of Reference Numerals

[0436] 10 Laminated structure 11 First layer 12 Second layer 21 First insulating film 22 Second insulating film 31 First wiring layer 32 Second wiring layer 41 Barrier film 100 Second transistor 101a Oxide semiconductor film 101b Oxide semiconductor film 101c Oxide semiconductor film 103 Conductive film 103a Electrode 103b Electrode 103c Electrode 104 Gate insulating film 105 Gate electrode 106a Insulating film 106b Insulating film 107 Insulating film 108 Insulating film 109a Low-resistance region 109b Low-resistance region 110 First transistor 111 Semiconductor substrate 112 Semiconductor film 113a Low-resistance layer 113b Low-resistance layer 114 Gate insulating film 115 Gate electrode 115a Gate electrode 115b Gate electrode 116 Insulating film 117 Insulating film 118 Insulating film 119 Insulating film 120 Barrier film 121 Insulating film 122 Insulating film 123 Insulating film 124 Insulating film 125 Insulating film 126 Insulating film 127 Insulating film 128 Insulating film 129 Insulating film 130 Capacitor element 131a Oxide semiconductor film 131b Oxide semiconductor film 132 Wiring 136 Electrode 136a Electrode 136b electrode 137 insulating film 138 electrode 150 capacitor element 151 insulating film 152 insulating film 153 plug 154 electrode 155 insulating film 156 electrode 157 plug 158 plug 159 plug 160 transistor 161 plug 162 plug 163 plug 164 plug 165 plug 166 plug 167 plug 168 plug 169 plug 170 plug 171 plug 172 plug 173 electrode 174 electrode 175 electrode 176 plug 177 electrode 178 plug 181 electrode 182 insulating film 183 electrode 190 capacitor element 700 substrate 701 pixel section 702 scanning line drive circuit 703 scanning line drive circuit 704 signal line drive circuit 710 capacitance wiring 712 gate wiring 713 gate wiring 714 drain electrode 716 transistor 717 transistor 718 liquid crystal element 719 liquid crystal element 720 pixels 721 Switching transistor 722 Driving transistor 723 Capacitive element 724 Light-emitting element 725 Signal line 726 Scanning line 727 Power supply line 728 Common electrode 800 RF tag 801 Communicator 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Memory circuit 811 ROM 901 Housing 902 Housing 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display unit 914 Display unit 915 Connection part 916 Operation key 921 Housing 922 Display unit 923 Keyboard 924 Pointing device 931 Housing 932 Freezer door 933 Refrigerator door 941 Housing 942 Housing 943 Display unit 944 Operation key 945 Lens 946 Connection part 951 Vehicle body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface 1190 Substrate 1191 ALU 1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM 1200 Memory element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic element 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitive element 4000 RF device 5120 Substrate

Claims

1. A first transistor; a second transistor overlapping the first transistor; a first capacitance element overlapping the first transistor; a second capacitive element overlapping the second transistor; a first wiring electrically connected to the second capacitance element; the first wiring has a region overlapping with an electrode of the second transistor; the first transistor, the second transistor, the first capacitance element, and the second capacitance element are electrically connected to each other; a channel of the first transistor having a single crystal semiconductor; A semiconductor device, wherein a channel of the second transistor includes an oxide semiconductor.

2. A first transistor; a second transistor overlapping the first transistor; a first capacitance element overlapping the first transistor; a second capacitive element overlapping the second transistor; a first wiring electrically connected to the second capacitance element; the first wiring has a region overlapping with an electrode of the second transistor; the first transistor, the second transistor, the first capacitance element, and the second capacitance element are electrically connected to each other; a channel of the first transistor having a single crystal semiconductor; a channel of the second transistor includes an oxide semiconductor; one electrode of the first capacitance element includes a protruding portion, The other electrode of the first capacitance element includes a recess.

3. In claim 1 or 2, a second wiring electrically connected to the first capacitance element; The second wiring has an area where it overlaps with an electrode of the first transistor.

Images