Variable device, mobile terminal, and dcdc converter

Abstract

To provide a variable device that is easily miniaturized and has an adjustable electrical characteristic.SOLUTION: A variable device has a pair of input-output terminals and an electrical first characteristic that is variable between the pair of input-output terminals. The variable device has a first terminal and a second terminal functioning as the pair of input-output terminals, and a third terminal and a fourth terminal, and includes: an antisymmetric device in which an electrical resistance has an antisymmetric component; and a variable element that is connected to the third terminal and the fourth terminal and has an electrical second characteristic that is variable.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a variable device, a mobile terminal, and a DC-DC converter.

Background Art

[0002] Conventionally, a technique is known in which electrical characteristics of an element are made variable by making a part of the element movable (see, for example, Patent Document 1). [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-091438

Summary of the Invention

Problems to be Solved by the Invention

[0003] To provide a variable device that is easy to miniaturize and has variable electrical characteristics.

Means for Solving the Problems

[0004] In a first aspect of the present invention, there is provided a variable device having a pair of input / output terminals, wherein an electrical first characteristic between the pair of input / output terminals is variable. The variable device may include a first terminal and a second terminal that function as the pair of input / output terminals, and a third terminal and a fourth terminal, and may include an antisymmetric device having an electrical resistance with an antisymmetric component. Any of the variable devices may include a variable element connected to the third terminal and the fourth terminal, and having a variable electrical second characteristic.

[0005] In any of the variable devices, the first characteristic and the second characteristic may be different characteristics.

[0006] In any of the variable devices, the variable element may be a variable capacitor.

[0007] Any of the variable devices may include a control unit that sets an inductance value as the first characteristic and controls a capacitance value of the variable element based on the set inductance value.

[0008] In any of the variable devices described above, the variable element may be a variable coil.

[0009] Any of the variable devices described above may be provided with a control unit that sets a capacitance value as the first characteristic and controls an inductance value of the variable element based on the set capacitance value.

[0010] In any of the variable devices described above, the variable element may be a variable resistor.

[0011] In any of the variable devices described above, the antisymmetric device may have a pair of power terminals and a Hall element having the first terminal and the second terminal. In any of the variable devices described above, the antisymmetric device may have a magnetic field generation unit that applies a magnetic field to the Hall element.

[0012] In any of the variable devices described above, the magnetic field generation unit may apply a fixed magnetic field to the Hall element.

[0013] In any of the variable devices described above, the antisymmetric device may have an antisymmetric layer having an antisymmetric component in its electrical resistance. In any of the variable devices described above, the antisymmetric device may have a magnetic field generation layer that is laminated with the antisymmetric layer and generates a magnetic field in the lamination direction.

[0014] In any of the variable devices described above, the antisymmetric layer may include an InSb layer.

[0015] In any of the variable devices described above, the antisymmetric device may have a laminated portion in which at least two types of layers are laminated, the electrical resistance has an antisymmetric component, and a magnetic field in the lamination direction is generated.

[0016] In any of the variable devices described above, the laminated portion may include a Co layer and a Pd layer.

[0017] In any of the variable devices described above, the antisymmetric device may have an InSb layer.

[0018] In any of the variable devices described above, the antisymmetric device may have a structure that generates a two-dimensional electron gas in the plane to generate a conductive layer that spreads in the plane. In any of the variable devices described above, the first terminal, the second terminal, the third terminal, and the fourth terminal may be provided at different positions in the plane with respect to the conductive layer.

[0019] In any of the variable devices described above, the voltage Vx at the first terminal, the current Ix flowing from the first terminal to the second terminal, the voltage Vy at the third terminal, and the current Iy flowing from the third terminal to the fourth terminal are the antisymmetric component R A and the diagonal component R may be represented by Equation (1). Equation (1)

Number

[0020] In a second aspect of the present invention, a mobile terminal including an oscillator for clock generation is provided. In the mobile terminal, the oscillator may have a pair of input / output terminals and may have a variable device in which the inductance value between the pair of input / output terminals is variable. In any of the mobile terminals, the variable device may have a first terminal and a second terminal that function as a pair of the input / output terminals, and a third terminal and a fourth terminal, and may include an antisymmetric device having an antisymmetric component in its electrical resistance. In any of the mobile terminals, the variable device may be connected to the third terminal and the fourth terminal and may have a variable capacitor having a variable capacitance value.

[0021] In a third aspect of the present invention, there is provided a DC-DC converter that steps up or steps down an input voltage and outputs it by accumulating the input energy in an inductance component. The DC-DC converter has a pair of input / output terminals, the inductance value between the pair of input / output terminals is variable, and may include a variable device that functions as the inductance component. In any of the above DC-DC converters, the variable device may have a first terminal and a second terminal that function as the pair of input / output terminals, and a third terminal and a fourth terminal, and may include an antisymmetric device having an antisymmetric component in its electrical resistance. In any of the above DC-DC converters, the variable device may be connected to the third terminal and the fourth terminal and may include a variable capacitor having a variable capacitance value.

[0022] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of Drawings

[0023]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10A

Figure 10B

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Mode for Carrying Out the Invention

[0024] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0025] FIG. 1 is a diagram showing an example of a variable device 100 according to an embodiment of the present invention. The variable device 100 has a pair of input / output terminals I / O. The variable device 100 is a device in which an electrical first characteristic between the pair of input / output terminals I / O is variable. The first characteristic is, for example, any one of an inductance value, a capacitance value, an impedance value, and an admittance value, but is not limited thereto.

[0026] The pair of input / output terminals I / O is connected to a circuit in which the variable device 100 is mounted. For example, the pair of input / output terminals I / O is connected to the wiring of the circuit. In the circuit, the variable device 100 may function as a passive element in which a first characteristic such as an inductance value between the pair of input / output terminals I / O is variable.

[0027] The variable device 100 includes an antisymmetric device 30 and a variable element 20. The variable device 100 may further include a control unit 22. The antisymmetric device 30 includes at least four terminals and is an element having an antisymmetric component in its electrical resistance. The antisymmetric device 30 in this example includes a first terminal 11, a second terminal 12, a third terminal 13, and a fourth terminal 14. The first terminal 11 and the second terminal 12 function as a pair of input / output terminals I / O.

[0028] A In the antisymmetric device 30, let the voltage between the first terminal 11 and the second terminal 12 be Vx, the current flowing from the first terminal 11 to the second terminal 12 be Ix, the voltage between the third terminal 13 and the fourth terminal 14 be Vy, and the current flowing from the third terminal 13 to the fourth terminal 14 be Iy. The voltages Vx, Vy, and the currents Ix, Iy are represented by Equation (1) using the antisymmetric component R Equation (1)

Number

[0029] The variable element 20 is connected to the third terminal 13 and the fourth terminal 14. The variable element 20 has two or more terminals including a terminal connected to the third terminal 13 and a terminal connected to the fourth terminal 14. The variable element 20 is an element in which an electrical second characteristic between the terminal connected to the third terminal 13 and the terminal connected to the fourth terminal 14 is variable.

[0030] The second characteristic is, for example, any one of an inductance value, a capacitance value, an impedance value, and an admittance value, but is not limited thereto. The first characteristic and the second characteristic may be different types of characteristics. For example, one of the first characteristic and the second characteristic may be an inductance value and the other may be a capacitance value. In another example, one of the first characteristic and the second characteristic may be an impedance value and the other may be an admittance value.

[0031] The control unit 22 controls the characteristic value of the second characteristic in the variable element 20 according to the target value of the first characteristic of the variable device 100. As will be described later, by using the anti-symmetric device 30, when the characteristic value of the second characteristic of the variable element 20 is changed, the characteristic value of the first characteristic of the variable device 100 is changed. The control unit 22 may be included in the variable device 100 or may be provided outside the variable device 100. The control unit 22 may control the characteristic value of the second characteristic of the variable element 20 by an electrical, optical, or magnetic signal, or may control the characteristic value by another signal.

[0032] The variable element 20 may be an element in which the second characteristic is variable without using a mechanical movable part. The variable element 20 may be an element in which the second characteristic changes according to the applied voltage, such as a varactor diode. Alternatively, the variable element 20 may include a switching element whose switching state changes according to a control signal, such as a transistor, and the second characteristic may change according to the switching state of the switching element. The variable element 20 may vary the second characteristic by using a switching element to switch the number of passive elements connected between the third terminal 13 and the fourth terminal 14.

[0033] FIG. 2 is a diagram showing a variable device 100 using a variable impedance element 24 as the variable element 20. The variable impedance element 24 is an element with a variable impedance value Z. The variable impedance element 24 may be a variable resistor or other variable passive element. The variable device 100 in this example is a device with a variable admittance value 1 / Z.

[0034] FIG. 3 is a diagram showing an equivalent circuit of the variable device 100 shown in FIG. 2. The impedance Zxx indicated by the first terminal 11 of the variable device 100 shown in FIG. 2 is expressed by Equation (2) using the anti-symmetric component R A and the diagonal component R. Equation (2)

Equation

[0035] The equivalent circuit in the upper part of FIG. 3 corresponds to the upper part (the first row) on the right side of Equation (2). The equivalent circuit in the lower part of FIG. 3 corresponds to the lower part (the second row) on the right side of Equation (2). As shown in FIG. 3 and Equation (2), the variable device 100 has a component of the admittance value 1 / Z corresponding to the impedance value Z of the variable element 20. Therefore, by controlling the impedance value Z of the variable element 20, the admittance value 1 / Z of the variable device 100 can be controlled.

[0036] As described with reference to FIGS. 2 and 3, by combining the anti-symmetric device 30 and the variable element 20, an inverse circuit for any variable element 20 can be generated. When the product of the impedances of the two circuits is constant regardless of the frequency, the two circuits are inverse circuits of each other.

[0037] FIG. 4 is a diagram showing a variable device 100 using a variable capacitor 26 as the variable element 20. In this example, the capacitance value C of the variable capacitor 26 is variable, and the inductance value L of the variable device 100 is variable. The variable capacitor 26 is, for example, a variable capacitance diode (also referred to as a varicap), but is not limited thereto. The variable capacitance diode is an element capable of controlling the capacitance by controlling the thickness of the depletion layer or the like by the reverse voltage applied between the anode and the cathode.

[0038] FIG. 5 is a diagram showing an equivalent circuit of the variable device 100 shown in FIG. 4. The impedance Zxx indicated by the first terminal 11 of the variable device 100 shown in FIG. 4 is obtained by replacing Z in Equation (2) with 1 / (iωC).

[0039] The upper equivalent circuit in FIG. 5 corresponds to the upper part of the right side of Equation (2) with Z replaced by 1 / (iωC). The lower equivalent circuit in FIG. 5 corresponds to the lower part of the right side of the said Equation (2). In the lower part of FIG. 5, the element whose impedance value is represented by iωCR A 2 functions as an inductor having an inductance value (CR A 2 ) proportional to C. Therefore, by controlling the capacitance value C of the variable capacitor 26, the inductance value of the variable device 100 can be controlled.

[0040] An inductance value is set as the first characteristic in the control unit 22 of this example. The control unit 22 controls the capacitance value of the variable capacitor 26 based on the set inductance value. Information indicating the relationship between the inductance value and the capacitance value may be preset in the control unit 22. A table showing the said relationship may be set in the control unit 22, a mathematical formula may be set, or other information may be set.

[0041] According to the variable device 100 of this example, a four-terminal device including an electric resistance and an inductor can be realized. The inductor in the variable device 100 is realized without using a coil-shaped electrical wiring. A coil formed by electrical wiring can be realized, for example, by forming a vortex structure in three-dimensional stacked wiring using an IC process. However, since wiring layers corresponding to the number of turns of the coil are formed, many manufacturing processes are required, leading to a significant increase in manufacturing costs. For this reason, it is difficult to implement an inductor function in an LSI chip for a logic circuit. According to the variable device 100, since an inductor can be realized using a capacitor, the inductor can also be easily implemented in an LSI chip.

[0042] Furthermore, by using the variable capacitor 26 as the variable capacitor, a variable device 100 with a variable inductor value can be realized. The variable capacitor 26 can be realized by a varactor diode as described above. For this reason, it can also be easily implemented in an LSI chip. By using the variable device 100 of this example, a variable inductor element can be mounted on an LSI chip for a logic circuit without significantly increasing the manufacturing cost. Therefore, an LSI chip for information processing having a high-frequency region reaching several GHz can be improved in performance and the high-performance improvement can be realized at low cost. The variable device 100 is particularly useful for an LSI chip for information processing mounted on a mobile terminal.

[0043] The variable device 100 may be mounted on a circuit so as to cancel out the capacitance component due to stray capacitance. For example, in a circuit transmitting a high-frequency signal of 1 GHz or more, the leakage due to the capacitance component increases. By using the variable device 100 of this example, the leakage due to the capacitance component of a high-frequency circuit can be easily suppressed.

[0044] The variable device 100 may be implemented in combination with other capacitors. Even when the capacitance values of the variable capacitor 26 and other capacitors vary due to temperature fluctuations or the like, one impedance value (e.g., iωC) of the variable capacitor 26 and other capacitors increases, and the other impedance value (e.g., 1 / iωC) decreases. Therefore, the fluctuations in the impedance values can be offset. The variable device 100 may be connected in series or in parallel with other capacitors. By using the variable device 100, both other capacitors and the inductor formed by the variable device 100 can be implemented only with capacitors.

[0045] FIG. 6 is a diagram showing a variable device 100 using a variable inductor 28 as the variable element 20. In this example, the variable inductor 28 has a variable inductance value L, and the variable device 100 has a variable capacitance value C.

[0046] FIG. 7 is a diagram showing an equivalent circuit of the variable device 100 shown in FIG. 6. The impedance Zxx indicated by the first terminal 11 of the variable device 100 shown in FIG. 6 is obtained by replacing Z in Equation (2) with iωL.

[0047] The upper equivalent circuit in FIG. 7 corresponds to the upper part of the right side of Equation (2) with Z replaced by iωL. The lower equivalent circuit in FIG. 7 corresponds to the lower part of the right side of the said Equation (2). In the lower part of FIG. 7, the element whose impedance value is represented by 1 / iω(L / R A 2 ) functions as a capacitor having a capacitance value (L / R A 2 ) proportional to L. Therefore, by controlling the inductance value L of the variable inductor 28, the capacitance value of the variable device 100 can be controlled. According to this example, by using the variable device 100, both other inductors and the capacitor formed by the variable device 100 can be implemented only with inductors.

[0048] In the control unit 22 of this example, a capacitance value may be set as the first characteristic. The control unit 22 controls the inductance value of the variable inductor 28 based on the set capacitance value. Information indicating the relationship between the inductance value and the capacitance value may be preset in the control unit 22. A table showing the relationship may be set in the control unit 22, a mathematical formula may be set, or other information may be set.

[0049] The angular frequency ω0 that gives the maximum Q value in the equivalent circuit shown in FIG. 5 is represented by Equation (3). Equation (3)

Number

Number

Number

[0050] As shown by Equation (5), the larger R A / R is, the larger Q max becomes. The absolute value of the antisymmetric component R A may be 5 times or more the absolute value of the diagonal component R. The absolute value of the antisymmetric component R A may be 10 times or more the absolute value of the diagonal component R, or may be 100 times or more. The absolute value of the antisymmetric component R A may be 1 / 1000 or less the absolute value of the diagonal component R, may be 1 / 500 or less, or may be 1 / 100 or less.

[0051] FIG. 8 is a perspective view showing an example of the antisymmetric device 30. The antisymmetric device 30 of this example has a Hall element 32 and a magnetic field generating unit 34. The Hall element 32 may have a thin film formed of a semiconductor material such as germanium, silicon, indium antimonide, indium arsenide, or gallium arsenide. A first terminal 11, a second terminal 12, a third terminal 13, and a fourth terminal 14 are connected to the thin film. The first terminal 11 and the second terminal 12 are connected to two sides facing each other on the main surface of the thin film. The third terminal 13 and the fourth terminal 14 are two sides facing each other on the main surface of the thin film and are connected to sides different from the first terminal 11 and the second terminal 12. In the thin film, the direction connecting the first terminal 11 and the second terminal 12 and the direction connecting the third terminal 13 and the fourth terminal 14 may be orthogonal to each other.

[0052] The magnetic field generating unit 34 applies a magnetic field B to the Hall element 32. The magnetic field generating unit 34 may generate a magnetic field B perpendicular to the main surface of the thin film. The magnetic field generating unit 34 is, for example, a permanent magnet, but other means may be used to generate the magnetic field.

[0053] The Hall element 32 of this example is not used for the purpose of measuring the intensity of the magnetic field B. The magnetic field generating unit 34 may apply a magnetic field B having a fixed intensity to the Hall element 32. By applying the magnetic field B to the Hall element 32, the Hall element 32 functions as the antisymmetric device 30 described by Equation (1). That is, the magnetic field B is a magnetic field for driving the Hall element 32 and is different from the magnetic field to be measured.

[0054] The first terminal 11 and the second terminal 12 of the Hall element 32 in this example function as a pair of input / output terminals I / O. The pair of input / output terminals I / O are, for example, two terminals in a passive element such as an inductor, a capacitor, or a resistor. The first terminal 11 and the second terminal 12 in this example are not connected to an external voltmeter and do not function as a magnetic sensor. A variable element 20 is connected to the third terminal 13 and the fourth terminal 14 in this example. A current source for causing the Hall element 32 to function as a magnetic sensor is not connected to the third terminal 13 and the fourth terminal 14 in this example. Thus, in this example, the Hall element 32 is used not as a magnetic sensor but as an antisymmetric device 30. Thereby, a variable device 100 can be realized.

[0055] The antisymmetric device 30 is not limited to the one using the Hall element 32. Any element that satisfies Equation (1) can be used as the antisymmetric device 30. For example, as the antisymmetric device 30, an element that generates a two-dimensional electron gas in an environment where a magnetic field is applied, or a magnetic material can be used. Also, as the antisymmetric device 30, a heterostructure or a superlattice structure in which a magnetic material is connected to a semiconductor, a metal, or a topological insulator can be used. Further, a device having a quantum Hall effect can be used as the antisymmetric device 30. An example of such a device is a Si-MOSFET.

[0056] When the magnetic field B generated by the magnetic field generation unit 34 is variable, the control unit 22 may control the magnetic field B generated by the magnetic field generation unit 34. By controlling the magnetic field B, the control unit 22 A may control the absolute value of the antisymmetric component R A . The control unit 22 may control the magnetic field B so that the absolute value of the antisymmetric component R A is 5 times or more the absolute value of the diagonal component R. Alternatively, the magnetic field generation unit 34 may generate a fixed magnetic field such that the absolute value of the antisymmetric component R

[0057] The maximum value Q of the Q value maxThe angular frequency ω0 that gives [it] depends on the electrical resistance R of the antisymmetric device 30 (in this example, the Hall element 32) and the capacitance C of the variable element 20. In the antisymmetric device 30, let the width between the first terminal 11 and the second terminal 12 be Wx, the width between the third terminal 13 and the fourth terminal 14 be Wy, and the thickness be Wz. In this example, let Wx = Wy. If the resistivity of the antisymmetric device 30 is ρ, the inductance value L of the variable device 100 is given by Equation (6), the angular frequency ω0 is given by Equation (7), and Q max is given by Equation (8).

Equation

Equation

Equation

[0058] If the magnetic field applied to the Hall element 32 is B, the electric field in the direction from the third terminal 13 to the fourth terminal 14 is Ey, and the Hall coefficient of the Hall element 32 is R H then the voltage Vy is expressed by the following equation.

Equation

Equation

[0059] The Hall angle θ of the Hall element 32 is expressed by the following equation.

Equation

[0060] When Wx = Wy, the current-voltage characteristics of the Hall element 32 are given by the above-described equation (1). I y When I x = 0, V x = RI y = R A I x and the Hall angle θ at this time is expressed by the following equation.

Equation

[0061] Consider the case where a magnetic field B is applied to the Hall element 32 formed of InSb. In the case of InSb, μ = 78000 cm 2 / (Vs). Also, let B = 10 kG (1 G = 10 8 Wb / cm 2 = 10 ―8 (VS) / cm 2 ). In this case, μB is μB = 78000 cm 2 / (Vs) × 10 × 10 3 × 10 ―8 (Vs) / cm 2 = 7.8. Also, Q max is 3.87.

[0062] Assuming an electrical resistivity ρ of 4 × 10 -3 Ωm and a volume of the Hall element 32 of 1 mm 3 (W x = W y = W z = 1 mm), the diagonal component R is R = 4 × 10 ―3 Ωcm × 1 mm / (1 mm × 1 mm) = 4 × 10 ―2 Ω. Also, the antisymmetric component R A is R A = 7.8 × 4 × 10 ―2 Ω = 31.2 × 10 ―2 Ω.

[0063] By selecting the capacitance C of the variable element 20, the inductance value L and the angular frequency ω0 can be calculated from equations (6) and (7). When C = 1 μF, L ≈ 0.1 μH and ω0 ≈ 3.2 MHz. When C = 1 nF, L ≈ 0.1 nH and ω0 ≈ 3.2 GHz. When C = 1 pF, L ≈ 0.1 pH and ω0 ≈ 3.2 THz.

[0064] The thickness W of the Hall element 32 z By adjusting the thickness W, the inductance value L and the angular frequency ω0 can also be adjusted. As shown in Equation (8), even if the thickness W z is changed, the value of Q max does not change. When C = 1 pF and W z = 1 μm, L ≈ 0.1 μH and ω0 ≈ 3.2 GHz. When C = 1 fF and W z = 10 nm, L ≈ 1 μH and ω0 ≈ 32 GHz. When C = 1 aF and W z = 10 nm, L ≈ 1 nH and ω0 ≈ 32 THz.

[0065] The inductance values achievable with the variable device 100 are important for implementation. For example, in mobile devices centered around smartphones, micro-sized inductor components with an L value of about 1 nH are used for impedance matching applications in high-frequency circuits used for wireless communication functions. The inductor is, for example, a high-frequency inductor component with a fine coil structure. In automotive autonomous driving as well, high-frequency inductor components are essential for communication devices required for automotive driving control. To miniaturize high-frequency inductors, multilayer wiring technology with a large process load used in LSIs is employed. For example, Murata Manufacturing's LQP01HQ0N3B02 has a size of about 0.25 mm × 0.125 mm × 0.2 mm and realizes an inductor element with L = 1 nH at the world's smallest level of miniaturization using multilayer wiring technology. When forming a coil within an LSI chip, even with multilayer wiring technology, a large coil area is required and it cannot be built into a signal processing LSI. The number of chips from a single silicon wafer decreases sharply. High-frequency inductors are limited to use as external components of signal processing LSI chips.

[0066] According to the variable device 100, a high-frequency inductor can be built into an LSI chip for signal processing of mobile devices or the like. For example, by adding the formation of rectangular parallel electrodes of 10 nm × 30 nm in the LSI process and setting the thickness of the silicon oxide film between the electrodes to 10 nm, a capacitor with C = 1 aF can be easily formed. A square with a length of 50 nm and a width of 50 nm and a thickness W z If the electrodes of the above capacitance are connected to the hole element 32 with a square shape of 50 nm in length and width and a thickness W = 10 nm, an inductor element with L = 1 nH that can be used up to an extremely high-frequency region up to the ω0 ≒ 5 THz region can be built into the signal processing LSI. The occupied area of the variable device 100 in the LSI is about 100 nm × 100 nm, and the thickness is about 500 nm. The variable device 100 having a high-frequency inductor function can be mounted in the LSI for signal processing of mobile devices. Therefore, the manufacturing cost of the LSI including the high-frequency inductor can be significantly reduced. In addition, the number of parts can be reduced, contributing to the reduction of the assembly man-hours. These facts indicate that the variable device 100 that can be realized by embedding a high-frequency inductor that does not use a coil structure in the LSI is an epoch-making technology without precedent.

[0067] Not only for DC-DC converters, but also for choke inductors with a large L value widely used for voltage conversion, a micro inductor using a coil structure including a metal thin film is used. In the variable device 100, for example, by using square parallel electrodes of 1 μm × 1 μm and setting the thickness of the silicon oxide film between the electrodes to 10 nm, a capacitor with C = 3.3 fF can be easily formed using the LSI manufacturing process. A square with a length and width of 10 nm and a thickness W z If this capacitance is connected to the hole element 32 with a square shape of 10 nm in length and width and a thickness W = 10 nm, the variable device 100 can realize an inductor having a large value of about L = 2.6 μH. It can be used up to the ω0 ≒ 1.7 GHz region. The variable device 100 is approximately 2 μm × 2 μm × 1 μm in thickness and can be used as a micro inductor for voltage conversion applications.

[0068] FIG. 9 is a diagram showing the relationship between the Q value of the variable device 100 and each frequency ω. In FIG. 9, similar to the example described in FIG. 8, R AThe case where / R = 7.8 is shown. The horizontal axis in Fig. 9 indicates the value of ωCR.

[0069] As shown in Fig. 9, the Q value varies according to the angular frequency ω of the variable device 100. The variable device 100 has a recommended region where the Q value changes linearly with respect to the angular frequency ω. The variable device 100 may be used at the angular frequency ω within the recommended region.

[0070] Fig. 10A is a cross-sectional view showing another example of the antisymmetric device 30. The antisymmetric device 30 in this example has a structure in which an antisymmetric layer 43 having an antisymmetric component in its electrical resistance and a magnetic field generating layer 44 for generating a magnetic field are laminated on one chip.

[0071] The antisymmetric device 30 in this example includes an antisymmetric layer 43, a magnetic field generating layer 44, a substrate 41, an insulating layer 42, and an insulating layer 45. The antisymmetric device 30 includes a first terminal 11, a second terminal 12, a third terminal 13, and a fourth terminal 14 in the same manner as the example in Fig. 8, but in Fig. 10A, the third terminal 13 and the fourth terminal 14 are omitted.

[0072] The antisymmetric layer 43 is a layer having an antisymmetric component in its electrical resistance. The antisymmetric layer 43 may have the same structure as the Hall element 32 shown in Fig. 8, or may have other structures. The antisymmetric layer 43 may be formed of a material with relatively large spin-orbit interaction. As an example, the antisymmetric layer 43 includes an indium antimonide layer (InSb layer).

[0073] The magnetic field generating layer 44 is laminated on the antisymmetric layer 43. The magnetic field generating layer 44 and the antisymmetric layer 43 may be in contact with each other. In other examples, other layers such as an insulating layer may be provided between the magnetic field generating layer 44 and the antisymmetric layer 43. The magnetic field generating layer 44 generates a magnetic field in the lamination direction. The magnetic field generating layer 44 may be formed of a material that magnetizes without using an external magnetic field, or may be formed of a material that is magnetized by an external magnetic field. As an example, the magnetic field generating layer 44 may contain neodymium. By laminating the magnetic field generating layer 44 and the antisymmetric layer 43, it becomes easier to apply a magnetic field in the direction perpendicular to the antisymmetric layer 43. Further, by forming the magnetic field generating layer 44 of a relatively hard material such as neodymium, the strain in the antisymmetric layer 43 can be reduced, the conductivity of the antisymmetric layer 43 can be improved, and the diagonal component R can be made smaller.

[0074] The substrate 41 supports the antisymmetric layer 43 and the magnetic field generating layer 44. The substrate 41 may be a semiconductor substrate such as silicon, or may be a substrate of other materials. At least a part of the variable element 20 and the control unit 22 (see FIG. 1) may be provided on the substrate 41.

[0075] The insulating layer 42 is provided between the substrate 41 and the antisymmetric layer 43. In other examples, the insulating layer 42 may not be provided, and the substrate 41 and the antisymmetric layer 43 may be in contact with each other. Also, in the example of FIG. 10A, the magnetic field generating layer 44 is laminated on the antisymmetric layer 43, but the antisymmetric layer 43 may be laminated on the magnetic field generating layer 44. In this case, the insulating layer 42 is provided between the substrate 41 and the magnetic field generating layer 44.

[0076] The insulating layer 45 covers the upper surface of the magnetic field generating layer 44. In other examples, the insulating layer 45 may not be provided. When the antisymmetric layer 43 is laminated on the magnetic field generating layer 44, the insulating layer 45 covers the upper surface of the antisymmetric layer 43.

[0077] The first terminal 11 and the second terminal 12 are connected to the antisymmetric layer 43. The first terminal 11 and the second terminal 12 may be connected to the upper surface of the antisymmetric layer 43 as shown in FIG. 10A, or may be connected to the side surface of the antisymmetric layer 43. When the first terminal 11 and the second terminal 12 are connected to the upper surface of the antisymmetric layer 43, a partial region of the upper surface of the antisymmetric layer 43 may be exposed without being covered by the magnetic field generation layer 44. The first terminal 11 and the second terminal 12 may be provided in the exposed region.

[0078] FIG. 10B is a cross-sectional view showing another example of the antisymmetric device 30. In the antisymmetric device 30 of this example, the arrangements of the first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14 are different from those in the example shown in FIG. 10A. The first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14 are connected to the side surface of the antisymmetric layer 43 in this example, while they are connected to the upper surface of the antisymmetric layer 43 in the example of FIG. 10A. In FIG. 10B, the third terminal 13 and the fourth terminal 14 are omitted.

[0079] FIG. 11 is a cross-sectional view showing another example of the antisymmetric device 30. The antisymmetric device 30 of this example has a stacked portion 50 in the structure of the antisymmetric device 30 shown in FIG. 10A or FIG. 10B, instead of the antisymmetric layer 43 and the magnetic field generation layer 44. Other structures are the same as those of the antisymmetric devices shown in FIG. 10A or FIG. 10B.

[0080] The stacked portion 50 is a stacked film having an electrical resistance with an antisymmetric component and generating a magnetic field in the stacking direction. Each layer of the stacked portion 50 is not distinguished into a layer having an antisymmetric component and a layer generating a magnetic field. The entire stacked portion 50 functions as a portion having an electrical resistance with an antisymmetric component and as a portion generating a magnetic field in the stacking direction.

[0081] The stacked portion 50 has at least two types of layers stacked thereon. The stacked portion 50 in the example of FIG. 11 has a stacked first layer 51 and second layer 52. The first layer 51 and the second layer 52 are stacked repeatedly two or more times. The first layer 51 is, for example, a cobalt layer (Co layer). The second layer 52 is, for example, a palladium layer (Pd layer). By stacking such layers, it is possible to form the stacked portion 50 having an antisymmetric component in the electrical resistance while generating a magnetic field in the stacking direction. However, the materials of the first layer 51 and the second layer 52 are not limited to these.

[0082] The stacked portion 50 may have an InSb layer as either the first layer 51 or the second layer 52, and may include an InSb layer in addition to the first layer 51 and the second layer 52. The stacked portion 50 may have a stack of a Co layer, a Pd layer, and an InSb layer. The stacked portion 50 may have a stack of a Co layer and an InSb layer.

[0083] The stacked portion 50 may have three or more types of layers stacked thereon. The stacked portion 50 may have a rare earth layer instead of the Co layer in any of the structures described above. The stacked portion 50 may have a stack of a Co layer, an Fe layer, and a B layer.

[0084] By stacking more of the above-described multiple types of layers, it becomes easier to align the direction of the magnetic field with the stacking direction. By setting the direction of the magnetic field to the stacking direction, the antisymmetric component R A can be increased.

[0085] The first terminal 11 and the second terminal 12 are connected to the stacked portion 50. The first terminal 11 and the second terminal 12 may be connected to the upper surface of the stacked portion 50, or may be connected to the side surface of the stacked portion 50 as shown in FIG. 11. When the first terminal 11 and the second terminal 12 are connected to the upper surface of the stacked portion 50, a partial region of the upper surface of the stacked portion 50 may be exposed without being covered by the insulating layer 45. The first terminal 11 and the second terminal 12 may be provided in the exposed region.

[0086] FIG. 12 is a cross-sectional view showing another example of the antisymmetric device 30. The antisymmetric device 30 in this example has a 2DEG device 33 instead of the Hall element 32 in the structure of the antisymmetric device 30 shown in FIG. 8. The magnetic field generating section 34 is the same as that in the example of FIG. 8.

[0087] The 2DEG device 33 has a structure that generates a two-dimensional electron gas in the plane to generate a conductive layer 63 that spreads in the plane. The 2DEG device in this example has a substrate 60, a lower layer 61, an upper layer 62, a control electrode 15, and an insulating layer 16. The 2DEG device includes a first terminal 11, a second terminal 12, a third terminal 13, and a fourth terminal 14 in the same manner as in the example of FIG. 8, but in FIG. 12, the third terminal 13 and the fourth terminal 14 are omitted.

[0088] The upper layer 62 is in surface contact with the lower layer 61. The lower layer 61 and the upper layer 62 may be semiconductor layers of different materials. As an example, the lower layer 61 is a neutral GaAs layer, and the upper layer 62 is an n-type AlGaAs layer. At the interface between the lower layer 61 and the upper layer 62, valleys of the conduction band with energy levels lower than the Fermi level are generated. Therefore, a conductive layer 63 with a large number of electrons is two-dimensionally generated at the interface between the lower layer 61 and the upper layer 62.

[0089] The substrate 60 supports the lower layer 61 and the upper layer 62. The substrate 60 may be a semiconductor substrate. For example, the substrate 60 is a GaAs substrate.

[0090] The first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14 are provided at different positions in the plane where the conductive layer 63 is provided. In the plane, they may be arranged such that a straight line connecting the first terminal 11 and the second terminal 12 is orthogonal to a straight line connecting the third terminal 13 and the fourth terminal 14. The first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14 may be provided on the upper surface of the upper layer 62.

[0091] The control electrode 15 is provided on the upper surface of the upper layer 62 via the insulating layer 16. The control electrode 15 may be provided between the first terminal 11 and the second terminal 12. The control electrode 15 may be provided in a region surrounded by the first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14. By adjusting the voltage applied to the control electrode 15, the thickness of the conductive layer 63 can be adjusted, and the diagonal component R of the electrical resistance can be adjusted.

[0092] FIG. 13 is a block diagram showing an example of a mobile terminal 200 according to another embodiment of the present invention. The mobile terminal 200 is a terminal that can be carried by a person. The mobile terminal 200 may be an information processing terminal having a communication function, or may be an information processing terminal without a communication function. The mobile terminal 200 may be a mobile phone or a personal computer, or may be another device.

[0093] The mobile terminal 200 in this example includes a communication unit 210, an information processing unit 212, a display unit 214, and an oscillator 216. However, one or more of the elements of the communication unit 210, the information processing unit 212, and the display unit 214 may not be provided in the mobile terminal 200.

[0094] The communication unit 210 transmits and receives signals to and from external devices. The communication unit 210 may communicate with external devices by wire or wirelessly. The information processing unit 212 performs predetermined processing on the input digital signal or analog signal and outputs it. The information processing unit 212 may also control other circuits of the mobile terminal 200. The display unit 214 displays information corresponding to the signal input from the information processing unit 212. The display unit 214 may have a liquid crystal display device or an organic EL display device.

[0095] The oscillator 216 is used to generate the operating clock of the mobile terminal 200. The operating clock is supplied to each circuit of the mobile terminal 200, such as the communication unit 210, the information processing unit 212, and the display unit 214. Each circuit of the mobile terminal 200 operates in response to each pulse of the operating clock. The oscillator 216 has a variable device 100. The variable device 100 in this example functions as a variable inductor with a variable inductance value. The variable device 100 may be used so that the frequency of the operating clock varies according to the inductance value. Also, as described above, the variable device 100 may be used in the information processing unit 212.

[0096] FIG. 14 is a diagram showing an example of the oscillator 216. However, the configuration of the oscillator 216 is not limited to the example of FIG. 14. The oscillator 216 may have a configuration in which the oscillation frequency is variable according to the inductance value of the variable device 100.

[0097] The oscillator 216 in this example has a power supply 218, a variable device 100, a transistor 220, a resistor 222, a capacitor 224, and a capacitor 226. The base terminal of the transistor 220 is connected to the positive terminal of the power supply 218. The variable device 100 connects the base terminal and the collector terminal of the transistor 220. The first terminal 11 and the second terminal 12 (see FIG. 1 etc.) of the variable device 100 are connected to the base terminal and the collector terminal of the transistor 220.

[0098] The resistor 222 connects the emitter terminal of the transistor 220 and the negative terminal of the power supply 218. The capacitor 224 is provided between the collector terminal and the emitter terminal of the transistor 220. The capacitor 226 is provided in parallel with the resistor 222 between the emitter terminal of the transistor 220 and the power supply 218. The connection point between the transistor 220 and the resistor 222 and the connection point between the capacitor 224 and the capacitor 226 are connected to each other, and the signal at these connection points is output as an oscillation signal.

[0099] An operating clock is generated based on the oscillation signal output by the oscillator 216. The oscillation signal itself may be used as the operating clock, or the operating clock may be generated using the oscillation signal as a source clock. For example, the crystal oscillator in a voltage controlled crystal oscillator (VCXO) may be replaced with the oscillator 216, or the crystal oscillator in a temperature compensated crystal oscillator (TCXO) may be replaced with the oscillator 216.

[0100] According to this example, since the variable inductor can be realized by the small variable device 100, in the small portable terminal 200, an operating clock with a variable frequency can be easily generated. Also, an oscillator 216 having a high Q max value can be easily realized.

[0101] FIG. 15 is a diagram showing an example of a DC-DC converter 300 according to another embodiment of the present invention. The DC-DC converter 300 outputs an output voltage Vo obtained by boosting or bucking the input voltage Vin by accumulating the input energy in an inductance component. The DC-DC converter 300 includes a variable device 100 that functions as the inductance component.

[0102] The DC-DC converter 300 in FIG. 15 includes a switch 302, a switch 304, a variable device 100, and a capacitor 306. The DC-DC converter 300 in FIG. 15 is a buck converter that steps down the input voltage Vin and outputs it, but it may be a boost converter that steps up the input voltage Vin and outputs it.

[0103] The switch 302 switches whether to apply the input voltage Vin to the variable device 100. The switch 304 switches whether to connect the input-side terminal of the variable device 100 to a reference potential such as a ground potential. The switch 302 and the switch 304 operate complementarily to each other. That is, when one of the switch 302 and the switch 304 is on, the other is off.

[0104] The voltage of the terminal on the output side of the variable device 100 is output as the output voltage Vo. The capacitor 306 is provided between the terminal on the output side of the variable device 100 and the reference potential. By providing the capacitor 306, the output voltage Vo is smoothed. In the DCDC converter 300 of this example, the shorter the period during which the switch 302 is on, the more the output voltage Vo is stepped down.

[0105] The variable device 100 of this example functions as a variable inductor with a variable inductance value. However, the variable device 100 may be used with a fixed inductance value.

[0106] Generally, a DCDC converter steps up or down the input voltage using a coil. Since a coil is an element formed by winding a wire, it is difficult to miniaturize. In particular, it is difficult to form a coil on a semiconductor chip. According to this example, the variable device 100 is used as an inductor. Therefore, the DCDC converter can be formed on a semiconductor chip. Thus, an ultra-small DCDC converter can be realized.

[0107] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

Explanation of Reference Numerals

[0108] 11 ··· First terminal, 12 ··· Second terminal, 13 ··· Third terminal, 14 ··· Fourth terminal, 15 ··· Control electrode, 16 ··· Insulating layer, 20 ··· Variable element, 22 ··· Control unit, 24 ··· Variable impedance element, 26 ··· Variable capacitor, 28 ··· Variable inductor, 30 ··· Antisymmetric device, 32 ··· Hall element, 33 ··· 2DEG device, 34 ··· Magnetic field generating section, 41 ··· Substrate, 42 ··· Insulating layer, 43 ··· Antisymmetric layer, 44 ··· Magnetic field generating layer, 45 ··· Insulating layer, 50 ··· Stacked section, 51 ··· First layer, 52 ··· Second layer, 60 ··· Substrate, 61 ··· Lower layer, 62 ··· Upper layer, 63 ··· Conductive layer, 100 ··· Variable device, 200 ··· Mobile terminal, 210 ··· Communication section, 212 ··· Information processing section, 214 ··· Display section, 216 ··· Oscillator, 218 ··· Power supply, 220 ··· Transistor, 222 ··· Resistor, 224, 226 ··· Capacitor, 300 ··· DC-DC converter, 302, 304 ··· Switch, 306 ··· Capacitor

Claims

1. A variable device having a pair of input / output terminals, wherein a first electrical characteristic between the pair of input / output terminals is variable, an antisymmetric device having a first terminal and a second terminal, and a third terminal and a fourth terminal, each of which functions as a pair of input / output terminals, and whose electrical resistance has an antisymmetric component; a variable element connected to the third terminal and the fourth terminal and having a variable second electrical characteristic; A variable device comprising:

2. The first characteristic and the second characteristic are different characteristics. The variable device according to claim 1 .

3. The variable element is a variable capacitor. The variable device according to claim 1 .

4. an inductance value is set as the first characteristic, and a control unit is further provided that controls a capacitance value of the variable element based on the set inductance value. The variable device according to claim 3 .

5. The variable element is a variable coil. The variable device according to claim 1 .

6. A capacitance value is set as the first characteristic, and a control unit is further provided that controls an inductance value of the variable element based on the set capacitance value. The variable device according to claim 5 .

7. The variable element is a variable resistor. The variable device according to claim 1 .

8. The antisymmetric device comprises: a Hall element having a pair of power supply terminals, the first terminal and the second terminal; A magnetic field generating unit that applies a magnetic field to the Hall element; A variable device according to any one of claims 1 to 7, comprising:

9. The magnetic field generating unit applies a fixed magnetic field to the Hall element. The variable device according to claim 8.

10. The antisymmetric device comprises: an antisymmetric layer having an antisymmetric component in electrical resistance; a magnetic field generating layer that is laminated with the antisymmetric layer and generates a magnetic field in the lamination direction; A variable device according to any one of claims 1 to 7, comprising:

11. The antisymmetric layer includes an InSb layer. The variable device according to claim 10.

12. The antisymmetric device has a laminated portion in which at least two types of layers are laminated, the electrical resistance has an antisymmetric component, and the laminated portion generates a magnetic field in the lamination direction. A variable device according to any one of claims 1 to 7.

13. The laminated portion includes a Co layer and a Pd layer. The variable device according to claim 12.

14. The antisymmetric device has an InSb layer. A variable device according to any one of claims 1 to 7.

15. The antisymmetric device has a structure that generates a two-dimensional electron gas in a plane to generate a conductive layer that extends in the plane; The first terminal, the second terminal, the third terminal, and the fourth terminal are provided at different positions in the plane of the conductive layer. A variable device according to any one of claims 1 to 7.

16. The voltage Vx at the first terminal, the current Ix flowing from the first terminal to the second terminal, the voltage Vy at the third terminal, and the current Iy flowing from the third terminal to the fourth terminal are expressed as an antisymmetric component R of the electrical resistance. Ａ and is expressed by equation (1) using diagonal component R, Formula (1) [0070] Antisymmetric component R Ａ The absolute value of is 5 times or more the absolute value of the diagonal component R A variable device according to any one of claims 1 to 7.

17. A mobile terminal including an oscillator for generating a clock, The oscillator comprises: a variable device having a pair of input / output terminals and an inductance value between the pair of input / output terminals being variable; The variable device is an antisymmetric device having a first terminal and a second terminal, and a third terminal and a fourth terminal, each of which functions as a pair of input / output terminals, and whose electrical resistance has an antisymmetric component; a variable capacitor connected to the third terminal and the fourth terminal, the variable capacitor having a variable capacitance value; A mobile terminal including

18. A DC-DC converter that outputs an input voltage by increasing or decreasing the input voltage by storing input energy in an inductance component, a variable device having a pair of input / output terminals, an inductance value between the pair of input / output terminals being variable, and functioning as the inductance component; The variable device is an antisymmetric device having a first terminal and a second terminal, and a third terminal and a fourth terminal, each of which functions as a pair of input / output terminals, and whose electrical resistance has an antisymmetric component; a variable capacitor connected to the third terminal and the fourth terminal, the variable capacitor having a variable capacitance value; A DC-DC converter including:

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