Printed circuit board, electronic module, electronic apparatus, and video display device

Abstract

To improve the quality of a waveform of a transmission signal in a build-up substrate.SOLUTION: A printed circuit board 101 has: a first layer 151 including a plurality of conductive layers 111 to 113; a second layer 152 on which the first layer is laminated; a plurality of first vias 104a-1 to 104a-3 formed on the first layer; a plurality of first pads 104b-1 to 104b-3 formed in correspondence with the plurality of conductive layers in the first layer and connected respectively to the first vias; a plurality of ground patterns formed on the plurality of conductive layers and each having an opening surrounding the first pad; a second via 105a formed on the second layer; and a second pad 105b-2 formed on a surface on the first layer side of the second layer and connected to the first and second vias. The plurality of first and second pads overlap each other in plan view seen in a lamination direction of the layers. A diameter of each of the plurality of openings in the plurality of ground patterns is larger than a diameter of the second pad. A diameter of the opening most distant from the second layer is smaller than a diameter of the opening closest to the second layer.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a printed wiring board, an electronic module, an electronic device, and a video display device.

Background Art

[0002] Due to the demand for miniaturization of electronic devices, the adoption of build-up substrates that enable high-density wiring and via placement in printed wiring boards mounted in electronic devices has been increasing. A build-up substrate has a core layer in which vias penetrating the core portion of the substrate are used, and a build-up layer formed by building up conductors one layer at a time on the outside of the core layer. The vias used in the build-up layer are advantageous in that they do not deteriorate the waveform quality of high-speed transmission signals because they have a smaller diameter and smaller parasitic components than the vias penetrating the core layer.

[0003] In recent years, data communication using digital signals with a transmission speed exceeding 10 Gbps has been performed between two semiconductor devices mounted on a printed circuit board. In order to ensure the waveform quality of the transmission signal, characteristic impedance matching of transmission lines formed by wiring and vias on the printed circuit board is required. Also, as the speed of the transmission signal increases, impedance mismatches at fine sites that could be ignored at low speeds become apparent, and as a result, the waveform quality of the transmission signal may deteriorate. Therefore, impedance matching is also required for the vias of build-up substrates, which have been advantageous for high-speed transmission. Patent Documents 1 and 2 disclose an impedance matching method for build-up substrates and a via structure for suppressing reflection when the characteristic impedances of signal wirings connected to signal vias are different.

[0004] In Patent Document 1, in order to suppress the parasitic capacitance caused by the overlap between the via pad of the build-up layer and the ground of the inner layer and achieve impedance matching, the opening diameter of the ground around the inner layer via pad and the opening diameter of the ground around the signal pad on the surface layer are made the same size. In Patent Document 2, when the characteristic impedances of the signal wirings connected to the signal vias are different, the impedance of the via is gradually changed to buffer the characteristic impedance mismatch between the signal wirings.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] When a higher density design is adopted, in a build-up substrate, the vias penetrating the core layer and the vias of the build-up layer may be arranged overlapping each other in plan view. In the case of this configuration, with the technologies disclosed in Patent Documents 1 and 2, it is difficult to suppress the impedance mismatch caused by the parasitic capacitance generated between the via of the build-up layer and the via of the core layer.

[0007] An object of the present invention is to provide a printed wiring board capable of improving the quality of the waveform of a transmission signal in a build-up substrate.

Means for Solving the Problems

[0008] According to one aspect of the present invention, there is provided a printed wiring board having: a first layer including a plurality of stacked conductor layers; a second layer on which the first layer is stacked; a plurality of first vias formed in the first layer; a plurality of first pads formed corresponding to the plurality of conductor layers of the first layer and each connected to the first via; a plurality of ground patterns formed in the plurality of conductor layers and each having an opening surrounding the first pad; a second via formed in the second layer; and a second pad formed on a surface of the second layer on the side of the first layer and connected to the first via and the second via, wherein the plurality of first pads and the second pad overlap in a plan view when viewed in a direction in which the first layer and the second layer are stacked, diameters of the plurality of openings of the plurality of ground patterns are larger than a diameter of the second pad, and a diameter of the opening farthest from the second layer is smaller than a diameter of the opening closest to the second layer.

Advantages of the Invention

[0009] According to the present invention, it is possible to improve the quality of the waveform of a transmission signal in a build-up substrate.

Brief Description of the Drawings

[0010]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 1F

Figure 1G

Figure 1H

Figure 2

Figure 3A

Figure 3B

Mode for Carrying Out the Invention

[0011] [First Embodiment] The printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1H. FIG. 1A is a cross-sectional view showing the printed wiring board 101 according to the present embodiment. FIG. 1B is a plan view showing the conductor layer 111 of the build-up layer 151 in the printed wiring board 101. FIG. 1C is a plan view showing the conductor layer 112 of the build-up layer 151 in the printed wiring board 101. FIG. 1D is a plan view showing the conductor layer 113 of the build-up layer 151 in the printed wiring board 101. FIG. 1E is a plan view showing the conductor layer 114 of the core layer 152 in the printed wiring board 101. FIG. 1F is a plan view showing the conductor layer 115 of the core layer 152 in the printed wiring board 101. FIG. 1G is a plan view showing the conductor layer 119 of the core layer 152 in the printed wiring board 101. FIGS. 1B to 1G are plan views in a plan view seen in the stacking direction of each conductor layer, which is a direction perpendicular to the board surface of the printed wiring board 101, that is, the direction in which the build-up layers 151, 153 and the core layer 152 are stacked. FIG. 1H is a cross-sectional view showing a modified example of the printed wiring board 101 according to the present embodiment.

[0012] As shown in FIGS. 1A to 1G, the printed wiring board 101 is a build-up substrate having 12 conductor layers 111 to 122. The conductor layers 111 to 122 are stacked via insulating layers 131 to 141 between one surface and the other surface of the printed wiring board 101.

[0013] Of the 12 layers, the conductor layers 111, 112, and 113 from the first layer to the third layer constitute the build-up layer 151. The conductor layers 114, 115, 116, 117, 118, and 119 from the fourth layer to the ninth layer constitute the core layer 152. The conductor layers 120, 121, and 122 from the tenth layer to the twelfth layer constitute the build-up layer 153. The build-up layer 151 is laminated on one surface of the core layer 152. The build-up layer 153 is laminated on the other surface of the core layer 152.

[0014] The conductor layers 111 to 122 are composed of conductors such as copper foils. An insulating layer 131 is formed between the conductor layer 111 and the conductor layer 112. An insulating layer 132 is formed between the conductor layer 112 and the conductor layer 113. An insulating layer 133 is formed between the conductor layer 113 and the conductor layer 114. An insulating layer 134 is formed between the conductor layer 114 and the conductor layer 115. An insulating layer 135 is formed between the conductor layer 115 and the conductor layer 116. An insulating layer 136 is formed between the conductor layer 116 and the conductor layer 117. An insulating layer 137 is formed between the conductor layer 117 and the conductor layer 118. An insulating layer 138 is formed between the conductor layer 118 and the conductor layer 119. An insulating layer 139 is formed between the conductor layer 119 and the conductor layer 120. An insulating layer 140 is formed between the conductor layer 120 and the conductor layer 121. An insulating layer 141 is formed between the conductor layer 121 and the conductor layer 122. The insulating layers 131 to 141 interposed between the conductor layers 111 to 122 are composed of insulators such as resins made of prepregs. On the outer surface of the conductor layer 111 of the first layer, which is the outermost layer of the build-up layer 151, and on the outer surface of the conductor layer 122 of the twelfth layer, which is the outermost layer of the build-up layer 153, resist layers (not shown) are formed as protective layers, respectively.

[0015] The printed wiring board 101 further includes wirings 102 and 103, build-up vias 104, and through vias 105. The build-up via 104 is a via formed in a build-up layer 151 including conductor layers 111, 112, and 113 from the first layer to the third layer. The through via 105 is a via formed in a core layer 152 including conductor layers 114, 115, 116, 117, 118, and 119 from the fourth layer to the ninth layer.

[0016] The wiring 102 is formed in the conductor layer 111 of the first layer. In the conductor layer 111, ground patterns 111a are formed on both sides of the wiring 102. On the other hand, the wiring 103 is formed in the conductor layer 119 of the ninth layer. In the conductor layer 119, ground patterns 119a are formed on both sides of the wiring 103. The wiring 102 and the wiring 103 are electrically connected to each other via the build-up via 104 and the through via 105. Note that the wirings 102 and 103 are not shown in FIG. 1A. High-speed signals such as digital signals having a transmission speed exceeding, for example, 10 Gbps are transmitted through the wirings 102 and 103.

[0017] The build-up via 104 has three-stage vias 104a-1, 104a-2, and 104a-3 and via pads 104b-1, 104b-2, and 104b-3, which are stacked to form it. The via 104a-1, the via pad 104b-2, the via 104a-2, the via pad 104b-2, the via 104a-3, and the via pad 104b-3 are stacked in this order from the inner layer side to the one surface side of the printed wiring board 101.

[0018] The first-stage via 104a-1 is a via formed by a hole formed in the conductor layer 113 and an insulating layer 133 between the conductor layer 113 and the conductor layer 114. The via 104a-1 is constituted by, for example, a conductor formed by copper plating or the like formed on the wall surface of the hole and further a conductor formed by copper plating or the like filled in the hole. The via 104a-1 has a circular planar shape in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101.

[0019] On the same layer as the conductor layer 113, a via pad 104b-1 is formed corresponding to the conductor layer 113 so as to overlap with the via 104a-1 in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The via pad 104b-1 is composed of a conductor such as a copper foil. The via pad 104b-1 is a pad having a circular planar shape with a diameter larger than that of the via 104a-1 in a plan view. The via pad 104b-1 is connected to the via 104a-1.

[0020] Also, a ground pattern 113a is formed on the conductor layer 113. A ground clearance 104e is formed in the ground pattern 113a. The ground clearance 104e is an opening in the conductor layer 113 where there is no conductor. The ground clearance 104e has a circular planar shape that surrounds the via pad 104b-1 in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The build-up via 104 including the via 104a-1 and the via pad 104b-1 is formed inside the ground clearance 104e.

[0021] The second-stage via 104a-2 is a via formed by a hole formed in the conductor layer 112 and the insulating layer 132 between the conductor layer 112 and the conductor layer 113. The via 104a-2 is composed of, for example, a conductor such as copper plating formed on the wall surface of the hole in the same manner as the via 104a-1, or further a conductor such as copper plating filled in the hole. The via 104a-2 has a circular planar shape in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The via 104a-2 is arranged so as to overlap with the via pad 104b-1 in a plan view and is connected to the via pad 104b-1.

[0022] On the same layer as the conductor layer 112, via pads 104b-2 are formed corresponding to the conductor layer 112 so as to overlap with the via 104a-2 in a plan view when viewed in a direction perpendicular to the plate surface of the printed wiring board 101. The via pad 104b-2 is composed of a conductor such as a copper foil. The via pad 104b-2 is a pad having a circular planar shape with a diameter larger than that of the via 104a-2 in a plan view. The via pad 104b-2 is connected to the via 104a-2. In a plan view, the diameter of the via 104a-2 is equal to the diameter of the via 104a-1, and the diameter of the via pad 104b-2 is equal to the diameter of the via pad 104b-1. Note that in a plan view, the diameter of the via 104a-2 may be different from the diameter of the via 104a-1, and the diameter of the via pad 104b-2 may be different from the diameter of the via pad 104b-1.

[0023] Also, a ground pattern 112a is formed on the conductor layer 112. A ground clearance 104d is formed in the ground pattern 112a. The ground clearance 104d is an opening in the conductor layer 112 where there is no conductor. The ground clearance 104d has a circular planar shape that surrounds the via pad 104b-2 in a plan view when viewed in a direction perpendicular to the plate surface of the printed wiring board 101. The built-up via 104 including the via 104a-2 and the via pad 104b-2 is formed inside the ground clearance 104d.

[0024] The third-stage via 104a-3 is a via formed by a hole formed in the conductor layer 111 and the insulating layer 131 between the conductor layer 111 and the conductor layer 112. The via 104a-3 is composed of, for example, a conductor such as copper plating formed on the wall surface of the hole, similar to the vias 104a-1 and 104a-2, or further a conductor such as copper plating filled in the hole. The via 104a-3 has a circular planar shape in a plan view when viewed in a direction perpendicular to the plate surface of the printed wiring board 101. The via 104a-3 is arranged so as to overlap with the via pad 104b-2 in a plan view and is connected to the via pad 104b-2.

[0025] On the same layer as the conductor layer 111, via pads 104b-3 are formed corresponding to the conductor layer 111 so as to overlap with via 104a-3 in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The via pad 104b-3 is composed of a conductor such as a copper foil. The via pad 104b-3 is a pad having a circular planar shape with a diameter larger than that of the via 104a-3 in a plan view. The via pad 104b-3 is connected to the via 104a-3. In a plan view, the diameter of the via 104a-3 is equal to the diameter of the via 104a-2, and the diameter of the via pad 104b-3 is equal to the diameter of the via pad 104b-2. Note that, in a plan view, the diameter of the via 104a-3 may be different from the diameter of the via 104a-2, and the diameter of the via pad 104b-3 may be different from the diameter of the via pad 104b-2.

[0026] Also, a ground pattern 111a is formed on the conductor layer 111. Ground clearances 102c and 104c are formed in the ground pattern 111a. The ground clearances 102c and 104c are openings in the conductor layer 111 where there is no conductor. The ground clearance 102c has a strip-shaped planar shape surrounding the wiring 102 in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The ground clearance 104c has a circular planar shape surrounding the via pad 104b-3 in a plan view. The ground clearances 102c and 104c are connected so as to surround the wiring 102 and the via pad 104b-3 connected to each other. The built-up via 104 including the via 104a-3 and the via pad 104b-3 is formed inside the ground clearance 104c.

[0027] Note that the vias 104a-1, 104a-2, and 104a-3 may have a planar shape other than circular in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. In this case, the diameter of the vias 104a-1, 104a-2, and 104a-3 is the diameter that is the maximum value of the distance between two points in the planar shape.

[0028] Also, the via pads 104b-1, 104b-2, and 104b-3 may have a planar shape other than circular in a plan view. In this case, the diameter of the via pads 104b-1, 104b-2, and 104b-3 is the diameter that is the maximum value of the distance between two points in the planar shape.

[0029] Also, the ground clearances 104c, 104d, and 104e may have a planar shape other than circular in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. In this case, the diameter of the ground clearances 104c, 104d, and 104e is the diameter that is the maximum value of the distance between two points in the planar shape.

[0030] The three vias 104a-1, 104a-2, and 104a-3 and the three via pads 104b-1, 104b-2, and 104b-3 described above are arranged so as to overlap in a plan view when the printed wiring board 101 is viewed in a direction perpendicular to the board surface of the printed wiring board 101. The wiring 102 is connected to the via pad 104b-3 formed corresponding to the conductor layer 111 in the same layer as the conductor layer 111. Comparing these with the diameter of the ground clearance 104c being Dc, the diameter of the ground clearance 104d being Dd, and the diameter of the ground clearance 104e being De, the diameters Dc, Dd, and De have the following magnitude relationship, and the diameter De is the largest. That is, the diameters Dc, Dd, and De of the ground clearances 104c, 104d, and 104e are smaller for the ground clearances farther from the core layer 152. Dc < Dd < De

[0031] Note that the diameters Dc, Dd, and De may increase stepwise in order from the build-up layer 151 toward the core layer 152, or may increase in a tapered shape as shown in FIG. 1H. In the case shown in FIG. 1H, the ground clearance 104c is formed such that the diameter Dc increases in a tapered shape from the minimum value Dc1 to the maximum value Dc2 in the direction from the build-up layer 151 toward the core layer 152. Also, the ground clearance 104d is formed such that the diameter Dd increases in a tapered shape from the minimum value Dd1 to the maximum value Dd2 in the direction from the build-up layer 151 toward the core layer 152. Further, the ground clearance 104e is formed such that the diameter De increases in a tapered shape from the minimum value De1 to the maximum value De2 in the direction from the build-up layer 151 toward the core layer 152.

[0032] Also, the magnitude relationship among the diameters Dc, Dd, and De is not limited to the above relationship, and two of these diameters may be equal to each other. Specifically, the diameter Dd and the diameter De may be equal, or the diameter Dc and the diameter Dd may be equal. That is, the diameters Dc, Dd, and De may have any of the following two magnitude relationships, as long as the diameter De is the largest. Dc < Dd = De Dc = Dd < De

[0033] Note that when the diameters Dc, Dd, and De shown in FIG. 1H increase in a tapered shape, the magnitude relationship can be expressed by the following equation using the respective minimum and maximum values. Dc1 < Dc2 ≤ Dd1 < Dd2 ≤ De1 < De2

[0034] Among the diameters Dc, Dd, and De of the ground clearances 104c, 104d, and 104e, it is preferable that the diameter Dc of the ground clearance 104c, which is the farthest from the core layer 152, is the smallest. The via pad 104b-3 surrounded by the ground clearance 104c, which is the farthest from the core layer 152, is located in the outermost layer of the build-up layer 151. Therefore, by minimizing the diameter Dc of the ground clearance 104c, it is possible to widely secure the area of the region where components can be arranged in the outermost layer of the build-up layer 151.

[0035] The through via 105 has a via 105a and via pads 105b-1 and 105b-2. The via 105a is a via formed by a through hole formed in the insulating layers 134 to 138 of the core layer 152 including from the conductor layer 114 to the conductor layer 119. The via pad 105b-2 is formed on the surface on the side of the build-up layer 151 of the core layer 152. That is, the via pad 105b-2 is formed corresponding to the conductor layer 114 in the same layer as the conductor layer 114 which is the outermost layer on the conductor layer 113 side of the core layer 152. The via pad 105b-1 is formed on the surface on the side of the build-up layer 153 opposite to the build-up layer 151 of the core layer 152. That is, the via pad 105b-1 is formed corresponding to the conductor layer 119 in the same layer as the conductor layer 119 which is the outermost layer on the conductor layer 120 side of the core layer 152. The via pads 105b-1 and 105b-3 are each connected to the via 105a.

[0036] The via 105a is constituted by a conductor such as copper plating formed on the wall surface of the through hole, and the through hole in which the conductor is formed is filled with an insulator such as resin. The via 105a has a circular planar shape in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101.

[0037] The via pad 105b-1 is arranged so as to overlap the via 105a in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The via pad 105b-1 is constituted by a conductor such as a copper foil. The via pad 105b-1 is a pad having a circular planar shape with a diameter larger than that of the via 105a in a plan view.

[0038] Via pad 105b-2 is arranged so as to overlap via 105a in a plan view when viewed in a direction perpendicular to the board surface of printed wiring board 101. Via pad 105b-2 is composed of a conductor such as a copper foil. Via pad 105b-2 is a pad having a circular planar shape with a diameter larger than that of via 105a in a plan view. In a plan view, the diameter of via pad 105b-2 is equal to the diameter of via pad 105b-1. Note that in a plan view, the diameter of via pad 105b-2 may be different from the diameter of via pad 105b-1.

[0039] As described above, the diameter of via 105a formed in core layer 152 is larger than the diameters of vias 104a-1, 104a-2, and 104a-3 formed in build-up layer 151. Also, the diameters of via pads 105b-1 and 105b-2 formed in core layer 152 are larger than the diameters of via pads 104b-1, 104b-2, and 104b-3 formed in build-up layer 151.

[0040] Each of the conductor layers 114 to 119 is formed with a ground pattern 114a to 119a, respectively. Each of the ground patterns 114a to 119a is formed with a ground clearance 105c. The ground pattern 119a is further formed with a ground clearance 103c. Each of the ground clearances 103c and 105c is an opening in which the conductor of the corresponding conductor layer 114 to 119 is absent. The ground clearance 105c of the ground pattern 114a has a circular planar shape surrounding the via pad 105b-2 in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The ground clearances 105c of the ground patterns 115a to 118a have a circular planar shape surrounding the via 105 in a plan view. The ground clearance 103c of the ground pattern 119a has a strip-shaped planar shape surrounding the wiring 103 in a plan view. The ground clearance 105c of the ground pattern 119a has a circular planar shape surrounding the via pad 105b-1 in a plan view. The ground clearances 103c and 105c of the ground pattern 119a are connected so as to surround the wiring 103 and the via pad 105b-1 connected to each other. Thus, the through via 105 is formed inside the ground clearances 105c of the respective ground patterns 114a to 119a in the core layer 152. The diameters of the ground clearances 105c of the ground patterns 114a to 119a are equal to each other. Note that the diameters of the ground clearances 105c of the ground patterns 114a to 119a may be different from each other.

[0041] Note that the via 105a may have a planar shape other than circular in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. In this case, the diameter of the via 105a is the diameter that is the maximum value of the distance between two points in the planar shape.

[0042] Also, the via pads 105b-1 and 105b-2 may have a planar shape other than circular in a plan view. In this case, the diameters of the via pads 105b-1 and 105b-2 are the diameters that are the maximum values of the distance between two points in the planar shape.

[0043] Also, the ground clearance 105c may have a planar shape other than circular in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. In this case, the diameter of the ground clearance 105c is the diameter that is the maximum value of the distance between two points in the planar shape.

[0044] The build-up via 104 and the through via 105 are arranged so as to overlap in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. That is, the vias 104a-1, 104a-2, 104a-3, the via pads 104b-1, 104b-2, 104b-3, the via 105a, and the via pads 105b-1, 1-5b-2 are arranged so as to overlap in a plan view. The wiring 103 provided in the conductor layer 119 is connected to the via pad 105b-1 formed corresponding to the conductor layer 119 in the same layer as the conductor layer 119.

[0045] Among the conductor layers 120 to 122 included in the build-up layer 153 on the side opposite to the build-up layer 151 in which the build-up via 104 is formed, a ground clearance 106 is formed in the conductor layer 120 closest to the core layer 152. The ground clearance 106 has a circular planar shape in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. The diameter of the ground clearance 106 is equal to the diameter of the ground clearance 105c of the conductor layer 119. The ground clearance 106 is arranged so as to overlap the ground clearance 105c of the ground pattern 119a in a plan view. Note that the diameter of the ground clearance 106 may be different from the diameter of the ground clearance 105c of the ground pattern 119a.

[0046] Note that the ground clearance 106 may have a planar shape other than circular in a plan view when viewed in a direction perpendicular to the board surface of the printed wiring board 101. In this case, the diameter of the ground clearance 105c is the diameter that is the maximum value of the distance between two points in the planar shape.

[0047] Taking the diameters of via pads 105b-1 and 105b-2 as Dp and comparing them with the diameters Dc, Dd, and De of ground clearances 104c, 104d, and 104e formed inside build-up via 104, they have the following magnitude relationships. Dp < Dc Dp < Dd Dp < De

[0048] As described above, in this embodiment, the diameters Dc, Dd, and De of ground clearances 104c, 104d, and 104e are larger than the diameter Dp of via pad 105b-2 in the same layer as conductor layer 114. Thereby, the parasitic capacitance generated between through via 105 in core layer 152 and build-up via 104 in build-up layer 151 can be reduced, and impedance mismatch due to parasitic capacitance can be suppressed.

[0049] Furthermore, in this embodiment, among ground clearances 104c, 104d, and 104e, the diameter Dc of ground clearance 104c farthest from core layer 152 is smaller than the diameter Dc of ground clearance 104e closest to core layer 152. Thereby, an increase in the characteristic impedance of wiring 102 wired in ground clearance 104c can be suppressed.

[0050] Thus, according to this embodiment, the quality of the waveform of the transmission signal in printed wiring board 101, which is a build-up substrate, can be improved.

[0051] In the above embodiment, the case where build-up layer 151 has three conductor layers 111 to 113, core layer 152 has six conductor layers 114 to 119, and build-up layer 153 has three conductor layers 120 to 122 has been described as an example, but it is not limited thereto. Each layer of build-up layer 151, core layer 152, and build-up layer 153 can have a plurality of conductor layers according to the design.

[0052] When each of the above layers has a plurality of conductor layers, the diameter of a plurality of ground clearances formed in a plurality of ground patterns in the plurality of conductor layers of the build-up layer 151 may be larger than the diameter of the via pad 105b-2 of the core layer 152. Also, among the plurality of ground clearances in the build-up layer 151, the diameter of the ground clearance farthest from the core layer 152 may be smaller than the diameter of the ground clearance closest to the core layer 152.

[0053] Also, in this case, among the plurality of ground clearances in the build-up layer 151, the diameter of the ground clearance farthest from the core layer 152 can be made the smallest. Also, in this case, the diameters of the plurality of ground clearances in the build-up layer 151 can be made smaller for ground clearances farther from the core layer 152.

[0054] [Embodiment] Regarding the printed wiring boards of the examples and comparative examples in which specific numerical values were set for the printed wiring board 101 according to the above first embodiment, the effect of suppressing impedance mismatch was confirmed by simulation.

[0055] (Example 1) In Example 1, the thicknesses of the conductor layers 111, 114, 119, and 122 were each 36 μm. The thicknesses of the conductor layers 112, 113, 120, and 121 were each 26 μm. The thicknesses of the conductor layers 115, 116, 117, and 118 were each 14 μm. The thicknesses of the insulating layers 131, 132, and 133 between the conductor layer 111 and the conductor layer 112, between the conductor layer 112 and the conductor layer 113, and between the conductor layer 113 and the conductor layer 114 were each 80 μm. The thicknesses of the insulating layers 139, 140, and 141 between the conductor layer 119 and the conductor layer 120, between the conductor layer 120 and the conductor layer 121, and between the conductor layer 121 and the conductor layer 122 were also each 80 μm. The thicknesses of the insulating layers 134 and 138 between the conductor layer 114 and the conductor layer 115 and between the conductor layer 118 and the conductor layer 119 were each 120 μm. The thicknesses of the insulating layers 135 and 137 between the conductor layer 115 and the conductor layer 116 and between the conductor layer 117 and the conductor layer 118 were each 200 μm. The thickness of the insulating layer 136 between the conductor layer 116 and the conductor layer 117 was 160 μm. The thicknesses of the solder resist layers formed outside the conductor layer 111 and outside the conductor layer 122 were each 30 μm.

[0056] The diameters of the holes of the vias 104a-1, 104a-2, and 104a-3 were each 150 μm. The diameters of the via pads 104b-1, 104b-2, and 104b-3 were each 275 μm. The diameter Dc of the ground clearance 104c of the conductor layer 111 was 675 μm. The diameter Dd of the ground clearance 104d of the conductor layer 112 was 775 μm. The diameter De of the ground clearance 104e of the conductor layer 113 was 875 μm.

[0057] The diameter of the hole of the via 105a was 300 μm. The diameters of the via pads 105b-1 and 105b-2 were each 500 μm. The diameter of the ground clearance 105c of the conductor layers 114 to 120 was 1300 μm.

[0058] The width of wiring 102 was 100 μm. The gaps between wiring 102 and the ground patterns on both of its sides were each 250 μm. The width of wiring 103 was 85 μm. The gaps between wiring 103 and the ground patterns on both of its sides were each 307.5 μm.

[0059] For the printed wiring board 101 of Example 1, the TDR (Time Domain Reflectometry) characteristics were analyzed by simulation. In the simulation, a step pulse signal was input to wiring 102, and the characteristic impedance was analyzed from the waveforms of the signals passing through build-up via 104, through via 105, and wiring 103. The modeling of the transmission line was performed using HFSS of Ansys. The analysis of the TDR characteristics was performed using HSPICE of Synopsys.

[0060] Similar to the printed wiring board 101 of Example 1, the TDR characteristics of the printed wiring boards of Comparative Examples 1 and 2 were also analyzed by simulation. In Comparative Example 1, all of the ground clearances 104c, 104d, and 104e of Example 1 were made to have the same diameter of 475 μm. In Comparative Example 2, the diameters of the ground clearances 104c, 104d, and 104e of Example 1 were made to be 875 μm, 675 μm, and 475 μm, respectively. Other points in Comparative Examples 1 and 2 were the same as those in Example 1.

[0061] Figure 2 is a graph showing the simulation results of analyzing the TDR characteristics for Example 1, Comparative Examples 1 and 2, and Example 2 and Example 3 described below. In the graph, the vertical axis represents the characteristic impedance (Ω), and the horizontal axis represents the time (ns). Also, in the graph, the solid line represents the simulation result of Example 1, the two-dot dashed line represents the simulation result of Comparative Example 1, and the one-dot dashed line represents the simulation result of Comparative Example 2. Also, the short dashed line represents the simulation result of Example 2, and the long dashed line represents the result of Simulation Example 3.

[0062] In the graph shown in FIG. 2, the vicinity of time 0 to 0.2 ns is the characteristic impedance of wiring 102. Also, the vicinity of time 0.2 to 0.23 ns is the range where the characteristic impedance decreases due to the via portion including build-up via 104 and through via 105. Further, the vicinity of time 0.23 to 0.43 ns is the characteristic impedance of wiring 103. Since the end of wiring 103 is terminated with a 50Ω resistor, the waveform continues even after time 0.43 ns.

[0063] As shown in FIG. 2, with respect to the characteristic impedance of 51Ω of wiring 102, the lowest value of the characteristic impedance of the via portion in Example 1 was 50.5Ω. On the other hand, in Comparative Example 1, the characteristic impedance of the via portion decreased to 45.4Ω, and in Comparative Example 2, it decreased to 46.7Ω. In Example 1, the characteristic impedance was within the range of 51Ω ± 5% (48.45 to 53.55Ω) based on the characteristic impedance of wiring 102. On the other hand, in Comparative Examples 1 and 2, the characteristic impedance deviated from 51Ω ± 5% due to the via portion.

[0064] In Example 1, the diameter of the ground clearance 104e of conductor layer 113 was 875μm, which was larger than the diameter of 500μm of via pad 105b-2 in the same layer as conductor layer 114. That is, in Example 1, in a plan view seen in the direction perpendicular to the board surface of printed wiring board 101, the ground pattern 113a of conductor layer 113 and the via pad 105b in the same layer as conductor layer 114 did not overlap. Therefore, in the structure including build-up via 104 and through via 105 stacked on each other, the distance between the ground pattern 113a of conductor layer 113 and the via pad 105b-2 of conductor layer 114 became longer. Thus, in Example 1, the parasitic capacitance between the ground pattern 113a of conductor layer 113 and the via pad 105b-2 of conductor layer 114 became smaller, and impedance mismatch could be suppressed.

[0065] On the other hand, in Comparative Examples 1 and 2, the diameter of the ground clearance 104e of the conductor layer 113 is 475 μm with respect to the diameter of 500 μm of the via pad 105b-2 in the same layer as the conductor layer 114. That is, in Comparative Examples 1 and 2, the diameter of the ground clearance 104e with respect to the build-up via 104 is smaller than the diameter of the via pad 105b-2 of the through via 105. For this reason, in Comparative Examples 1 and 2, in a plan view seen in a direction perpendicular to the plate surface of the printed wiring board 101, the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 overlap. Therefore, in a structure including the build-up via 104 and the through via 105 stacked on each other, the distance between the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 becomes shorter. Thus, in Comparative Examples 1 and 2, the parasitic capacitance between the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 becomes larger, and impedance mismatch could not be suppressed.

[0066] (Example 2) In Example 2, the diameter of the ground clearance 104e with respect to the build-up via 104 in Example 1 was changed. That is, in Example 2, the diameter of the ground clearance 104c of the conductor layer 111 was 675 μm. The diameter of the ground clearance 104d of the conductor layer 112 was 775 μm. The diameter of the ground clearance 104e of the conductor layer 113 was 775 μm. Other points in Example 2 were the same as those in Example 1.

[0067] Similar to the printed wiring board 101 of Example 1, the TDR characteristics of the printed wiring board 101 of Example 2 were also analyzed by simulation. In the graph shown in FIG. 2, the short dashed line indicates the simulation result of Example 2.

[0068] As shown in FIG. 2, the minimum value of the characteristic impedance of the via portion in Example 2 was 49.9 Ω. In Example 2, the characteristic impedance was within the range of 51 Ω ± 5% (48.45 to 53.55 Ω) based on the characteristic impedance of the wiring 102.

[0069] In Example 2, the diameter of the ground clearance 104e of the conductor layer 113 was 775 μm, which was larger than the diameter of 500 μm of the via pad 105b-2 in the same layer as the conductor layer 114. That is, in Example 2, in a plan view seen in the direction perpendicular to the board surface of the printed wiring board 101, the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 did not overlap. Therefore, in the structure including the build-up via 104 and the through via 105 stacked on each other, the distance between the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 became longer. Thus, in Example 2, the parasitic capacitance between the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 became smaller, and impedance mismatch could be suppressed.

[0070] (Example 3) In Example 3, the diameters of the ground clearances 104d and 104e with respect to the build-up via 104 in Example 1 were changed. That is, in Example 3, the diameter Dc of the ground clearance 104c of the conductor layer 111 was 675 μm. The diameter Dd of the ground clearance 104d of the conductor layer 112 was 675 μm. The diameter De of the ground clearance 104e of the conductor layer 113 was 775 μm. Other points in Example 3 were the same as those in Example 1.

[0071] Similar to the printed wiring board 101 of Example 1, the TDR characteristics of the printed wiring board 101 of Example 3 were also analyzed by simulation. In the graph shown in FIG. 2, the long dashed line indicates the simulation result of Example 3.

[0072] As shown in FIG. 2, the minimum value of the characteristic impedance of the via portion in Example 3 was 49.5 Ω. In Example 3, the characteristic impedance was within the range of 51 Ω ± 5% (48.45 to 53.55 Ω) based on the characteristic impedance of the wiring 102.

[0073] In Example 3, the diameter of the ground clearance 104e of the conductor layer 113 was 775 μm, which was larger than the diameter of 500 μm of the via pad 105b in the same layer as the conductor layer 114. That is, in Example 3, in a plan view seen in the direction perpendicular to the board surface of the printed wiring board 101, the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 did not overlap. Therefore, in the structure including the build-up via 104 and the through via 105 stacked on each other, the distance between the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 became longer. Thus, in Example 3, the parasitic capacitance between the ground pattern 113a of the conductor layer 113 and the via pad 105b-2 in the same layer as the conductor layer 114 became smaller, and impedance mismatch could be suppressed.

[0074] As common to Examples 1, 2, and 3, it is a necessary condition for impedance matching that the diameters of the ground clearances 104c, 104d, and 104e are larger than the diameter of the via pad 105b-2 in the same layer as the conductor layer 114.

[0075] Note that the diameters of the ground clearances 104c, 104d, and 104e do not necessarily have to be, in descending order as in Example 1, the diameter of the ground clearance 104e, the diameter of the ground clearance 104d, and the diameter of the ground clearance 104c. As in Examples 2 and 3, there may be ground clearances with the same diameter among the ground clearances 104c, 104d, and 104e. However, if the diameters of the ground clearances 104c and 104d are the same as the diameter of the ground clearance 104e, the distance from the wiring 102 wired in the ground clearance 104c in the conductor layer 111 to the ground becomes long. As a result, the characteristic impedance of the wiring 102 may increase excessively. Therefore, it is preferable that the diameters of the ground clearances 104c and 104d are smaller than the diameter of the ground clearance 104e. Also, if the diameters of all the ground clearances in the build-up layer 151 are increased, the area of the region where components can be arranged becomes narrow. For this reason, it is preferable that the outer ground clearances in the build-up layer 151 have a smaller diameter.

[0076] [Second Embodiment] The electronic device according to the second embodiment of the present invention will be described with reference to FIGS. 3A and 3B. FIGS. 3A and 3B are schematic views showing a head-mounted display (HMD) as an example of the electronic device according to the present embodiment. FIG. 3A is a side view of the HMD, and FIG. 3B is a front view of the HMD. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. In the present embodiment, an HMD, which is an example of an electronic device using the printed wiring board 101 according to the first embodiment, will be described. The HMD is used, for example, in cross-reality (XR) such as virtual reality (VR), augmented reality (AR), and mixed reality (MR).

[0077] As shown in FIGS. 3A and 3B, the HMD 200 includes a housing 201, a mounting tool 202, left-eye and right-eye display units 203, and a control unit 204. Each display unit 203 and the control unit 204 are housed and arranged inside the housing 201. The left-eye and right-eye display units 203 are display units that display left-eye and right-eye images, respectively. The control unit 204 is an electronic module that functions as a control unit for controlling the operation of the HMD 200 including each display unit 203 and the like.

[0078] The control unit 204 is a printed circuit board having the printed wiring board 101 according to the first embodiment and a semiconductor device 205 as a component mounted on the printed wiring board 101. The semiconductor device 205 controls each part of the HMD 200 such as the display unit 203, and transmits and receives signals such as video signals and control signals using signal wirings including wirings 102 and 103 that are electrically connected via build-up vias 104 and through vias 105 in the printed wiring board 101.

[0079] As in this embodiment, the printed wiring board 101 according to the first embodiment can be used for the HMD 200. Note that the printed wiring board 101 according to the first embodiment can also be used for electronic devices such as computers, displays, and video devices in addition to the HMD 200. In an electronic device, the printed wiring board 101 is used as a printed circuit board on which various components such as semiconductor devices are mounted.

[0080] The disclosure of this embodiment includes the following configurations. (Configuration 1) A first layer including a plurality of stacked conductor layers, A second layer on which the first layer is stacked, A plurality of first vias formed in the first layer, A plurality of first pads formed corresponding to the plurality of conductor layers of the first layer and each connected to the first via, A plurality of ground patterns formed in the plurality of conductor layers and each having an opening surrounding the first pad, The second via formed in the second layer, and a second pad formed on the surface of the second layer on the side of the first layer and connected to the first via and the second via. The plurality of first pads and the second pad overlap in a plan view when viewed in the direction in which the first layer and the second layer are laminated. The diameters of the plurality of openings of the plurality of ground patterns are larger than the diameter of the second pad. The diameter of the opening farthest from the second layer is smaller than the diameter of the opening closest to the second layer. A printed wiring board characterized by the above. (Configuration 2) Among the plurality of openings, the diameter of the opening farthest from the second layer is the smallest. The printed wiring board according to Configuration 1, characterized by the above. (Configuration 3) The diameters of the plurality of openings are smaller for the openings farther from the second layer. The printed wiring board according to Configuration 1 or 2, characterized by the above. (Configuration 4) Among the plurality of openings, the diameters of at least two of the openings are equal to each other. The printed wiring board according to any one of claims 1 to 3, characterized by the above. (Configuration 5) The diameter of the first pad is smaller than the diameter of the second pad. The printed wiring board according to any one of Configurations 1 to 4, characterized by the above. (Configuration 6) The diameter of the first via is smaller than the diameter of the second via. The printed wiring board according to any one of Configurations 1 to 5, characterized by the above. (Configuration 7) The second via is a via that penetrates the second layer. The printed wiring board according to any one of Configurations 1 to 6, characterized by the above. (Configuration 8) having a first wiring connected to the first pad surrounded by the opening farthest from the second layer The printed wiring board according to any one of Configurations 1 to 7, characterized in that. (Configuration 9) The opening farthest from the second layer is formed in the ground pattern located in the outermost layer of the first layer. The printed wiring board according to any one of Configurations 1 to 8, characterized in that. (Configuration 10) The second layer is a core layer, The second via is a through via penetrating the core layer. The printed wiring board according to any one of Configurations 1 to 9, characterized in that. (Configuration 11) The first layer is a build-up layer laminated on the core layer. The printed wiring board according to Configuration 10, characterized in that. (Configuration 12) A third pad formed on the surface of the second layer opposite to the first layer and connected to the second via, and having a second wiring connected to the third pad. The printed wiring board according to any one of Configurations 1 to 11, characterized in that. (Configuration 13) The printed wiring board according to any one of Claims 1 to 11, and components mounted on the printed wiring board. An electronic module characterized by having. (Configuration 14) A housing, The electronic module according to Configuration 13 disposed inside the housing. An electronic device characterized by having. (Configuration 15) A housing, A display unit disposed inside the housing and displaying an image, The printed wiring board according to any one of Configurations 1 to 11 disposed inside the housing, and A semiconductor device mounted on the printed wiring board and controlling the display unit, and A video display device characterized by comprising the same.

Explanation of Signs

[0081] 101: Printed wiring board 102, 103: Signal wiring 104: Build-up via 104a-1 to 104a-3: Via 104b-1 to 104b-3: Via pad 104c, 104d, 104e: Ground clearance 105: Through via 105a: Via 105b-1, 105b-2: Via pad 105c: Ground clearance 111 to 122: Conductor layer 111a to 119a: Ground pattern 131 to 141: Insulating layer 151, 153: Build-up layer 152: Core layer 200: HMD 201: Housing 202: Mounting tool 203: Display unit 204: Control unit 205: Semiconductor device

Claims

1. a first layer including a plurality of stacked conductor layers; a second layer on which the first layer is stacked; a plurality of first vias formed in the first layer; a plurality of first pads formed corresponding to the plurality of conductor layers of the first layer and each connected to the first via; a plurality of ground patterns formed in the plurality of conductor layers and each having an opening surrounding the first pad; a second via formed in the second layer; a second pad formed on a surface of the second layer on the side of the first layer and connected to the first via and the second via; the plurality of first pads and the second pad overlap in a plan view when viewed in a direction in which the first layer and the second layer are stacked; the diameters of the plurality of openings of the plurality of ground patterns are larger than the diameter of the second pad; the diameter of the opening farthest from the second layer is smaller than the diameter of the opening closest to the second layer A printed wiring board characterized by the above.

2. Among the plurality of openings, the diameter of the opening farthest from the second layer is the smallest The printed wiring board according to claim 1, characterized by the above.

3. The diameters of the plurality of openings are smaller for the openings farther from the second layer The printed wiring board according to claim 1 or 2, characterized by the above.

4. Among the plurality of openings, the diameters of at least two of the openings are equal to each other The printed wiring board according to claim 1 or 2, characterized by the above.

5. The diameter of the first pad is smaller than the diameter of the second pad The printed wiring board according to claim 1 or 2, characterized in that...

6. The diameter of the first via is smaller than the diameter of the second via The printed wiring board according to claim 1 or 2, characterized in that...

7. The second via is a via that penetrates the second layer The printed wiring board according to claim 1 or 2, characterized in that...

8. Having a first wiring connected to the first pad surrounded by the opening farthest from the second layer The printed wiring board according to claim 1 or 2, characterized in that...

9. The opening farthest from the second layer is formed in the ground pattern located in the outermost layer of the first layer The printed wiring board according to claim 1 or 2, characterized in that...

10. The second layer is a core layer, The second via is a through-via that penetrates the core layer The printed wiring board according to claim 1 or 2, characterized in that...

11. The first layer is a build-up layer laminated on the core layer The printed wiring board according to claim 10, characterized in that...

12. Formed on the surface of the second layer opposite to the first layer, having a third pad connected to the second via, and Having a second wiring connected to the third pad The printed wiring board according to claim 1 or 2, characterized in that...

13. The printed wiring board according to claim 1 or 2, and Components mounted on the printed wiring board An electronic module characterized by having... Claim 14 A housing, the electronic module according to claim 13 disposed inside the housing, and an electronic device characterized by comprising the same. Claim 15 A housing, a display unit disposed inside the housing for displaying an image, the printed wiring board according to claim 1 or 2 disposed inside the housing, a semiconductor device mounted on the printed wiring board for controlling the display unit, and a video display device characterized by comprising the same.

Images