Semiconductor structure and manufacturing method for the same

Abstract

To provide a semiconductor structure in which the difficulty of a process and the technology cost are reduced while the storage density is improved, and a manufacturing method for the same.SOLUTION: A semiconductor structure includes a base 10 and at least one layer of a memory device layer 20. The at least one layer of the memory device layer is stacked on the same side as the base along a vertical direction Z. The memory device layer includes at least a first signal line 20a, a transistor 20b, a second signal line 20c, and a selector line 20d. One of the first signal line and the second signal line is a reference voltage line while the other is a read-write line. A gate layer of the transistor is connected to the selector line. An active layer 201 of the transistor extends in the vertical direction and is disposed independently of the base. A bottom end of the active layer is connected to the first signal line and an upper end of the active layer is connected to the second signal line.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure belongs to the field of memory, and specifically relates to a semiconductor structure and a manufacturing method thereof.

Background Art

[0002] With the miniaturization of technology nodes, 1T0C (where T represents transistor and C represents capacitor) type DRAM (Dynamic Random Access Memory) has become a hot spot in research. However, the conventional 1T0C type DRAM uses the base as the active layer, and the active layers are arranged in a planar manner, that is, the entire active layer extends in the horizontal direction. By miniaturizing the size of the transistor, the memory density of the 1T0C type DRAM is increased, but this increases the difficulty of the process and the technical cost.

Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof that can improve the memory density while reducing the difficulty of the process and the technical cost.

[0004] A first aspect of the present disclosure provides a semiconductor structure including a base and at least one layer of memory device layer, wherein the at least one layer of memory device layer is stacked on the same side of the base along the vertical direction, and the memory device layer includes at least a first signal line, a transistor, a second signal line, and a selector line. One of the first signal line and the second signal line is a reference voltage line, and the other is a read / write line. Here, the gate layer of the transistor is connected to the selector line, the active layer of the transistor extends in the vertical direction and is independently arranged with respect to the base. The bottom end of the active layer is connected to the first signal line, and the upper end of the active layer is connected to the second signal line.

[0005] The second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, providing a base, forming at least one memory device layer vertically stacked on the base, wherein the method for forming the memory device layer includes forming a first signal line, a transistor, a second signal line, and a selector line on the base, one of the first signal line and the second signal line being a reference voltage line and the other being a read / write line, a gate layer of the transistor being connected to the selector line, an active layer of the transistor extending in a vertical direction and being disposed independently of the base, a bottom end of the active layer being connected to the first signal line, and a top end of the active layer being connected to the second signal line.

[0006] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: By disposing the active layer of the transistor independently of the base of the semiconductor structure, the present disclosure can reduce the design difficulty and technical cost of a three-dimensional transistor (i.e., the active layer of the present disclosure extends vertically as a whole) compared with a solution that uses a part of the base as the active layer, and can increase the number of transistors per unit area in the memory device layer. Therefore, the storage density can be increased. Furthermore, by stacking the memory device layers in multiple layers and along the vertical direction, the storage density can be further increased.

Brief Description of the Drawings

[0007] The drawings here are incorporated into the specification and form a part of the specification, conforming to the embodiments of the present disclosure and used to interpret the principles of the present disclosure together with the specification. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings based on these drawings without creative efforts.

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, exemplary embodiments will be described in more detail with reference to the drawings. However, the exemplary embodiments can be implemented in various forms and should not be limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to comprehensively convey the concept of the exemplary embodiments to those skilled in the art.

[0009] Furthermore, the described features, structures, or characteristics can be combined in any suitable way in one or more embodiments. In the following description, many specific details are provided for a complete understanding of the embodiments of the present application. However, those skilled in the art will come to realize that the technical means of the present application can be actually implemented without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, realizations, or operations are not shown or described in detail to avoid obscuring the aspects of the present application.

[0010] Hereinafter, the present application will be described in more detail with reference to the drawings and specific embodiments. Note that the technical features related to the embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the drawings are exemplary and are for interpreting the present application and should not be understood as a limitation to the present application.

[0011] The present disclosure provides a semiconductor structure, which may include, but is not limited to, a DRAM and is not overly limited herein.

[0012] The semiconductor structure of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0013] Referring to FIGS. 1 to 3, the semiconductor structure may include a base 10 and a memory device layer 20 formed on the base 10.

[0014] For example, the base 10 may include at least a single-crystalline semiconductor material layer 101 and an insulating isolation layer 102 formed between the memory device layer 20 and the single-crystalline semiconductor material layer 101. In this embodiment, the material of the single-crystalline semiconductor material layer 101 can include single-crystalline silicon, but is not limited thereto, and can also include single-crystalline semiconductor materials such as germanium (Ge). The material of the insulating isolation layer 102 may be silicon oxide, for example, silicon dioxide (SiO2), but is not limited thereto, and the insulating isolation layer 102 may use other insulating materials according to the actual situation.

[0015] Here, in the process of fabricating silicon dioxide as the insulating isolation layer 102, in the chemical vapor deposition method (abbreviated as CVD method), TEOS (Tetraethoxysilane) may be used as the silicon source. In the chemical vapor deposition method, on the surface of the single-crystalline semiconductor material layer 101, TEOS and oxygen react at a certain temperature and pressure to generate silicon dioxide and ethanol. In this process, the silicon atoms in the TEOS molecules react with oxygen to form silicon dioxide and release ethanol. This silicon dioxide is formed as a deposit on the surface of the single-crystalline semiconductor material layer 101 to form a silicon dioxide thin film as the insulating isolation layer 102.

[0016] It should be understood that the base 10 may be a peripheral base, a support base, or a bonding base.

[0017] This application will mainly be described below by taking an example in which the memory device layer 20 is formed on the base 10, that is, the base 10 is a support base.

[0018] The memory device layer 20 can include a first signal line 20a, a transistor 20b, a second signal line 20c, and a selector line 20d.

[0019] Referring to FIGS. 1 to 3, the transistor 20b includes at least an active layer 201, a gate layer 202, and a gate insulating layer 203 filled between the gate layer 202 and the active layer 201. The active layer 201 of the present embodiment may extend in the vertical direction Z, and this vertical direction Z may be a direction perpendicular or substantially perpendicular to the base 10, that is, the active layer 201 may be vertical or substantially vertical on the base 10.

[0020] Exemplarily, the transistor 20b referred to in the present embodiment can have an overall three-dimensional structure, which can improve the storage density per unit area, increase the channel width, increase the read / write current of the transistor 20b in the memory device layer 20, and improve the gate control ability by increasing the channel length in the vertical direction. Specifically, the transistor 20b includes a core layer and a sleeve layer. The sleeve layer surrounds at least the outer peripheral side of the core layer, and the core layer and the sleeve layer extend in the vertical direction Z as a whole. One of the core layer and the sleeve layer is the active layer 201 of the transistor 20b, and the other is the gate layer 202 of the transistor 20b. Here, when the sleeve layer is the gate layer 202 and the core layer is the active layer 201, referring to FIGS. 1 and 2, the transistor 20b is understood to have a gate surround structure. When the sleeve layer is the active layer 201 and the core layer is the gate layer 202, referring to FIG. 3, the transistor 20b is understood to have a channel surround structure.

[0021] In the present disclosure, the material of the active layer 201 is a semiconductor material. Specifically, it may be a polycrystalline semiconductor material, for example, a material such as polycrystalline (abbreviation: Poly) silicon. As long as the active layer 201 is a semiconductor material capable of full depletion, it is not limited to the above-described semiconductor material. Exemplarily, it should be understood that the active layer 201 may be IGZO. The material of the gate layer 202 may be a metal material such as copper or tungsten in order to improve conductivity, but is not limited thereto, and other materials having good conductivity can be used according to specific needs.

[0022] Also, in any embodiment, as shown in FIG. 1, the active layer 201 may be a junction active layer for enabling the transistor 20b to be a junction transistor. A junction transistor is a transistor having a junction structure in a semiconductor device by forming a channel region and source / drain regions using semiconductor materials of different conductivity types (i.e., different doping types). Specifically, the active layer 201 of the present embodiment may include a channel region 2011, a first electrode region 2012 and a second electrode region 2013 disposed on the opposite side of the channel region 2011 in the vertical direction Z. Note that one of the first electrode region 2012 and the second electrode region 2013 is a source region and the other is a drain region.

[0023] Here, the first electrode region 2012 may be formed between the first signal line 20a and the channel region 2011, that is, the upper end of the first electrode region 2012 contacts the lower end of the channel region 2011, and the lower end of the first electrode region 2012 contacts the upper end of the first signal line 20a. The second electrode region 2013 may be formed between the second signal line 20c and the channel region 2011, that is, the lower end of the second electrode region 2013 contacts the upper end of the channel region 2011, and the upper end of the second electrode region 2013 contacts the lower end of the second signal line 20c.

[0024] In this embodiment, the first electrode region 2012 and the second electrode region 2013 have the same conductivity type. For example, they are both N-type semiconductors or both P-type semiconductors. The conductivity types of the first electrode region 2012 and the second electrode region 2013 are both different from the conductivity type of the channel region 2011, thereby forming the junction-type active layer 201. For example, when the conductivity types of the first electrode region 2012 and the second electrode region 2013 are N-type semiconductors, the channel region 2011 is a P-type semiconductor. At this time, the transistor 20b may be an NMOS (N-Metal-Oxide-Semiconductor) transistor. When the conductivity types of the first electrode region 2012 and the second electrode region 2013 are P-type semiconductors, the channel region 2011 is an N-type semiconductor. At this time, the transistor 20b may be a PMOS (P-Metal-Oxide-Semiconductor) transistor. In this case, PN junctions are formed between the channel region 2011 and the first electrode region 2012, and between the channel region 2011 and the second electrode region 2013, respectively.

[0025] Here, when the active layer 201 of the transistor 20b is the aforementioned junction-type active layer, in order to realize the charge storage function of the transistor in the memory device layer 20, the gate layer 202 can be made to correspond to the channel region 2011 of the active layer 201. Specifically, as shown in FIG. 1, the upper surface of the first electrode region 2012 in the active layer 201 is higher than the lower surface of the gate layer 202, and the lower surface of the second electrode region 2013 is lower than the upper surface of the gate layer 202. As a result, the junction formed between the channel region 2011 and the first electrode region 2012 (i.e., the position where the channel region 2011 contacts the first electrode region 2012) and the junction formed between the channel region 2011 and the second electrode region 2013 (i.e., the position where the channel region 2011 contacts the second electrode region 2013) both correspond to the gate layer 202. Therefore, in the manufacture of the transistor 20b, in order to ensure the proper operation of the device, the design and position of the gate layer 202 need to correspond to the junctions of the active layer 201.

[0026] In another optional embodiment, the active layer 201 may also be a non-junction active layer. As shown in FIG. 2, the non-junction active layer refers to a semiconductor active layer without a PN junction, and usually consists of a continuous semiconductor thin film. When the active layer 201 is a non-junction active layer, the formed transistor 20b may be a non-junction transistor or a junction transistor. Compared with the junction active layer, the non-junction active layer does not require the step of patterning the source-drain region or the channel region, so the manufacturing process is relatively simple, the manufacturing cost can be reduced, and the production efficiency can be improved. When the active layer 201 is a non-junction active layer and the material is doped polycrystalline silicon, the signal line in contact with the active layer 201 may be composed of a semiconductor layer with doping of the opposite type to the active layer 201 so that the formed transistor 20b becomes a junction transistor.

[0027] Note that the performance of the non-junction transistor is affected by various factors such as the quality of the material, the thickness of the thin film, and the doping concentration. Therefore, in practice, in order to achieve optimal performance, it is necessary to optimize the design according to specific application scenarios and requirements.

[0028] Referring to FIG. 1 or FIG. 2, in the present disclosure, the active layer 201 may be formed at the upper end of the first signal line 20a, and the second signal line 20c may be formed at the upper end of the active layer 201. That is, the active layer 201 may be disposed between the first signal line 20a and the second signal line 20c. The upper end of the active layer 201 is connected to the second signal line 20c, and the lower end of the active layer 201 is connected to the first signal line 20a.

[0029] It should be noted that in the present disclosure, when referring to the upper end and the upper surface of a certain structure, it refers to one end away from the base 10 or the surface away from the base 10, and when referring to the lower end and the lower surface, it refers to one end close to the base 10 or the surface close to the base 10.

[0030] Here, one of the first signal line 20a and the second signal line 20c is a reference voltage line, and the other is a read / write line. The read / write line is connected to a peripheral circuit and inputs or outputs the stored signal. The selector line 20d is connected to the gate layer 202 of the transistor 20b, and different voltages are applied between the read / write line and the selector line 20d, enabling data reading and writing in the transistor 20b.

[0031] Exemplarily, the reference voltage line may be a ground line with a reference voltage of 0V. The following embodiments of the present invention will also be described by taking the case where the reference voltage is 0V as an example.

[0032] Exemplarily, taking the transistor 20b as an NMOS transistor as an example, the read / write operation of the transistor 20b will be described as follows: In the process of writing "1", a negative voltage is applied to the gate layer 202 of the transistor 20b via the selector line 20d, and a positive voltage is applied to the drain region of the transistor 20b via the read / write line. Holes due to GIDL (Gate Induced Drain Leakage) in the overlapping part of the drain region and the gate layer are accumulated in the floating body region.

[0033] Process of reading 「0」 or 「1」: Apply a positive voltage to the gate layer 202 of transistor 20b via selector line 20d, and apply an appropriate positive voltage to the drain region of transistor 20b via the read / write line. This appropriate positive voltage is a small voltage, enabling the NMOS transistor to operate in the linear region and preventing the occurrence of the HCI (Hot Carrier Injection effect, thermal carrier injection effect), thereby preventing the problem of ionization. If there is hole accumulation in the floating body, the threshold voltage of this transistor 20b is low, the drain current is large, and in this case, it becomes 「1」. If there is no hole accumulation in the floating body, the threshold voltage of this transistor 20b is high, and the drain current is small, and at this time, it becomes 「0」. Here, the difference between the drain current for reading 「1」 and the drain current for reading 「0」 is the sense margin.

[0034] Process of writing 「0」: Apply a positive voltage to the gate layer 202 of transistor 20b via selector line 20d, and apply a negative voltage to the drain region of transistor 20b via the read / write line, forward-bias the PN junction from the drain region to the channel region, and recombine electrons and holes to remove holes.

[0035] In the process of selectively writing 「0」, a small positive voltage is applied to the selector line 20d connected to the selected transistor 20b that is 「1」, so the potential of the floating body of this transistor 20b rises. Assuming that the turn-on voltage of the PN junction from the drain region to the channel region of transistor 20b is 0.7V, apply a small voltage to the gate layer 202 of the selected transistor 20b to make the turn-on voltage of the PN junction from the drain region to the channel region 0.5V. By applying a negative voltage to the read / write line connected to the selected transistor 20b, not only is the drain end of the selected transistor surely turned on, but also the transistor with no voltage applied to its gate layer is surely turned off, and the write 「0」 operation is completed.

[0036] The process of "Hold": The drain region of the transistor is connected to 0V by the read / write line.

[0037] In the above process, the source region of each transistor 20b is connected to the reference voltage through the reference voltage line. The reference voltage can be a fixed voltage or ground. Also, the above "Hold" is an operation to prevent the state of the transistor from changing so that the stored data can be correctly obtained in the subsequent reading process.

[0038] From the above, in the present disclosure, each transistor 20b can function as a memory unit by itself without the need for an additional storage capacitor. That is, the memory unit of the memory device layer 20 in the present disclosure can be a 1T0C type memory unit.

[0039] Exemplarily, as shown in conjunction with FIGS. 1 and 2, when the transistor 20b has a gate surround structure, the selector line 20d may be formed on the second signal line 20c closer to the base 10. That is, the selector line 20d may be formed between the first signal line 20a and the second signal line 20c. Such a design may utilize a part of the selector line 20d as the gate layer 202 of the transistor 20b. That is, the manufacture of the gate layer 202 of the transistor 20b can be achieved simultaneously with the production of the selector line 20d in order to save manufacturing steps and reduce the manufacturing difficulty and cost. As shown with reference to FIGS. 1 and 2, the selector line 20d needs to be provided insulated from the first signal line 20a and the second signal line 20c. Therefore, it should be understood that the first insulating medium layer 204 may be formed between the selector line 20d and the first signal line 20a, and the second insulating medium layer 205 may be formed between the selector line 20d and the second signal line 20c.

[0040] Exemplarily, as shown in FIG. 3, when the transistor 20b has a channel surround structure, since the gate layer 202 of the transistor 20b is surrounded by the active layer 201, in order to facilitate the connection of the selector line 20d to the gate layer 202 of the corresponding transistor 20b, the selector line 20d may be formed on the upper end or the lower end side of the gate layer 202. When the selector line 20d is formed on the upper end side of the gate layer 202, the selector line 20d is located on the second signal line 20c on the side away from the base 10. When the selector line 20d is formed on the lower end side of the gate layer 202, the selector line 20d can be located on the first signal line 20a on the side close to the base 10.

[0041] In the present disclosure, since the material of the active layer 201 is a semiconductor material, when designing the first signal line 20a and the second signal line 20c, as shown with reference to FIGS. 1 and 2, the first signal line 20a and the second signal line 20c may be designed to include at least a semiconductor material layer 206. The lower end of the active layer 201 is in direct contact with the semiconductor material layer 206 of the first signal line 20a, and the upper end of the active layer 201 is in direct contact with the semiconductor material layer 206 of the second signal line 20c. For example, when the semiconductor material is polycrystalline silicon, the contact area between the polycrystalline silicon and the metal silicide in the first signal line 20a and the second signal line 20c can be increased, and the impedance can be reduced. The setting of the metal silicide in the first signal line 20a and the second signal line 20c will be described later.

[0042] Here, as described above, when the active layer 201 is a non-junction active layer, the conductivity type of this active layer 201 may be made the same as the conductivity type of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c to form a non-junction memory unit. For example, both the active layer 201 and the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c are N-type semiconductors, or both the active layer 201 and the semiconductor material layer 206 of the first signal line 20a and the second signal line 20c are P-type semiconductors, thereby reducing the manufacturing cost and improving the production efficiency.

[0043] However, without being limited thereto, when the active layer 201 is the non-junction active layer as described above, in order to form a junction transistor as the memory unit, the conductivity type of the active layer 201 may be made different from the conductivity type of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c. In the embodiment where the transistor 20b has a gate surround structure as shown in FIG. 3, when the active layer 201 is an N-type semiconductor, the conductivity types of the semiconductor material layers 206 in the first signal line 20a and the second signal line 20c may both be P-type semiconductors, or when the active layer 201 is a P-type semiconductor, the conductivity types of the semiconductor material layers 206 in the first signal line 20a and the second signal line 20c may both be N-type semiconductors. Thereby, a PN junction structure is formed between the semiconductor material layer 206 of the first signal line 20a and the active layer 201, and between the semiconductor material layer 206 of the second signal line 20c and the active layer 201. In this case, however, it is necessary to oppose the gate layer 202 to the PN junction structure. When the selector line 20d is formed on the upper end side of the gate layer 202, the lower surface of the active layer 201 is higher than the lower surface of the gate layer 202, that is, the lower end of the gate layer 202 in the transistor 20b is at a position closer to the base 10 than the lower end of the active layer 201. When the selector line 20d is formed on the lower end side of the gate layer 202, the upper surface of the active layer 201 is lower than the upper surface of the gate layer 202, that is, the upper end of the gate layer 202 in the transistor 20b is further away from the base 10 than the upper end of the active layer 201. In the orthographic projection on the base 10, the selector line 20d covers at least a part of the outer boundary of the active layer 201, and preferably, the selector line 20d completely covers the outer boundary of the active layer 201. The outer boundary refers to the boundary between the active layer 201 and the second signal line 20c. Alternatively, when the second signal line 20c functions as a read / write line, it can be understood that the channel of the transistor 20b forms a PN junction with the drain.

[0044] Also, when the active layer 201 is a junction-type active layer as described above, the semiconductor material layer 206 of the first signal line 20a may have the same conductivity type as the first electrode region 2012 of the active layer 201, the semiconductor material layer 206 of the first signal line 20a may be in contact with the first electrode region 2012 of the active layer 201, the semiconductor material layer 206 of the second signal line 20c has the same conductivity type as the second electrode region 2013 of the active layer 201, and the semiconductor material layer 206 of the second signal line 20c is in contact with the second electrode region 2013 of the active layer 201. Taking the case where the semiconductor material is polycrystalline silicon as an example, the contact area between the polycrystalline silicon and the metal silicide of the first signal line 20a and the second signal line 20c may be increased to reduce the impedance. In other embodiments, it is understood that the semiconductor material layer 206 may not be formed between the metal silicides of the first signal line 20a and the second signal line 20c and the first electrode region 2012 and the second electrode region 2013 in order to simplify the process. This may be done on a case-by-case basis.

[0045] Note that the junction formed in the source region, that is, the junction on the ground line side, may or may not be covered by the gate layer 202, but the junction formed in the drain region, that is, the junction on the read / write line side, must be covered by the gate layer 202.

[0046] In the present disclosure, when the material of the active layer 201 is a polycrystalline semiconductor material, the material of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c may also be a polycrystalline semiconductor material. For example, when the material of the active layer 201 is polycrystalline silicon, the material of the semiconductor material layer 206 is also polycrystalline silicon.

[0047] Exemplarily, in order to improve the conductivity of the first signal line 20a and the second signal line 20c, as shown with reference to FIGS. 1 and 2, the first signal line 20a and the second signal line 20c may further include a metal conductive material layer 207, and the metal conductive material layer 207 is disposed on the semiconductor material layer 206 on the side away from the source layer 201. Further, in order to reduce the contact resistance between the metal conductive material layer 207 and the semiconductor material layer 206, as shown with reference to FIGS. 1 and 2, the first signal line 20a and the second signal line 20c may further include a transition conductive material layer 208 formed between the semiconductor material layer 206 and the metal conductive material layer 207, and the material of the transition conductive material layer 208 includes a metal element in the metal conductive material layer 207 and a semiconductor material element in the semiconductor material layer 206.

[0048] For example, when the semiconductor material of the semiconductor material layer 206 is polycrystalline silicon, the material of the transition conductive material layer 208 may be a metal silicide as described above. For example, when the metal material of the metal conductive material layer 207 is tungsten, the material of the transition conductive material layer 208 may be tungsten silicide (WSi2) in order to reduce the contact resistance between the semiconductor material layer 206 of the polycrystalline silicon material and the metal conductive material layer 207.

[0049] It should be understood that when the material of the active layer 201 is not polycrystalline silicon, the transition conductive material layer 208 may not be provided with a metal silicide material as long as it is practical. For example, when the material of the active layer 201 is an oxide semiconductor such as IGZO, the materials of the first signal line 20a and the second signal line 20c may not include the transition conductive material layer 208 and may include only the metal conductive material layer 207, and the active layer 201 is in direct contact with the metal conductive material layer 207.

[0050] Also, as shown with reference to FIG. 3, it should be noted that when the resistivity of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c meets the requirements, the first signal line 20a and the second signal line 20c may be made of only the semiconductor material.

[0051] Exemplarily, the selector line 20d may be made of a metal material such as copper or tungsten to improve conductivity, but is not limited thereto, and other materials with good conductivity may be used according to specific needs.

[0052] In the present disclosure, in order to improve the storage density of the memory device layer 20, in this embodiment, the memory device layer 20 is provided with a plurality of transistors 20b, and the plurality of transistors 20b may be arranged in a first horizontal direction X and a second horizontal direction Y as shown with reference to FIGS. 4 and 5. A plurality of read / write lines (i.e., the first signal line 20a or the second signal line 20c) and selector lines 20d may also be provided as shown in combination with FIGS. 1 and 4. The selector line 20d may extend in the first horizontal direction X, and the read / write line may extend in the second horizontal direction Y. Also, a plurality of read / write lines may be arranged at intervals in the first horizontal direction X, and a plurality of selector lines 20d may be arranged at intervals in the second horizontal direction Y.

[0053] Here, as shown in FIGS. 1 to 3, the active layers 201 of the plurality of transistors 20b arranged in the second horizontal direction Y are connected to the same read / write line. As shown in combination with FIGS. 1 and 4, the gate layers 202 of the respective transistors 20b arranged in the first horizontal direction X may be connected to the same selector line 20d. With such a design, while independently controlling the memory unit to perform read / write operations, by reducing the number of read / write lines and selector lines 20d, the planar space occupied thereby can be reduced, and in order to further increase the storage density, the number of transistors 20b can be increased within the limited planar space.

[0054] It should be noted that the first horizontal direction X and the second horizontal direction Y are directions parallel or substantially parallel to base 10. And the first horizontal direction X intersects with the second horizontal direction Y. Exemplarily, the first horizontal direction X and the second horizontal direction Y are perpendicular or substantially perpendicular to each other. In other embodiments, the angle between the first horizontal direction X and the second horizontal direction Y may be an acute angle or an obtuse angle.

[0055] Furthermore, since the active layer 201 of the transistor 20b in the memory device layer 20 is arranged independently of the base 10, that is, the active layer 201 of the transistor 20b in the memory device layer 20 in the present disclosure does not need to be formed using a part of the base 10, the entire memory device layer 20 can be arranged independently of the base 10. As a result, the memory device layer 20 can be arranged to have multiple layers on the same base 10. As shown in FIGS. 1 to 3, by stacking multiple memory device layers 20 on the same side of the base 10 along the vertical direction Z, the storage density of the entire semiconductor structure can be increased.

[0056] Furthermore, the design relationship between the multiple memory device layers 20 may be different for different structures of the transistor 20b, as described in Solution 1 and Solution 2 below.

[0057] 〔Solution 1〕 In this Solution 1, referring to FIGS. 1, 2, and 4, the transistor 20b is shown as a gate-all-around structure as described above, and the selector line 20d is arranged between the first signal line 20a and the second signal line 20c. Therefore, in order to reduce the manufacturing difficulty, when manufacturing the multiple memory device layers 20, the selector lines 20d of any two memory device layers 20 can be arranged independently of each other. As a result, any two memory device layers 20 are controlled independently of each other.

[0058] Based on this, in order to simplify the manufacturing process, when manufacturing the multi-layer memory device layer 20, at least two adjacent memory device layers 20 may share signal lines. Specifically, in two adjacent memory device layers 20, the memory device layer 20 on the side away from the base 10 is defined as the upper-layer memory device layer, and the memory device layer 20 on the side close to the base 10 is defined as the lower-layer memory device layer. Referring to FIGS. 1 and 2, at least a part of the second signal line 20c in the lower-layer memory device layer is shared as at least a part of the first signal line 20a in the upper-layer memory device layer. That is, the first signal line 20a of the upper-layer memory device layer and the second signal line 20c of the lower-layer memory device layer can be used as the same signal line, for example, the same reference voltage line or the same read / write line. In other embodiments, it will be understood that there is no shared portion of the read / write signal line and / or the reference voltage line.

[0059] For example, in any two adjacent memory device layers 20, if the first signal line 20a of the upper-layer memory device layer and the second signal line 20c of the lower-layer memory device layer are shared as the reference voltage line, then the second signal line 20c of the upper-layer memory device layer and the first signal line 20a of the lower-layer memory device layer both become read / write lines. In any two adjacent memory device layers 20, if the first signal line 20a of the upper-layer memory device layer and the second signal line 20c of the lower-layer memory device layer are shared as the read / write line, then the second signal line 20c of the upper-layer memory device layer and the first signal line 20a of the lower-layer memory device layer both become the reference voltage line.

[0060] Here, when the first signal line 20a and the second signal line 20c include the aforementioned semiconductor material layer 206, transition conductive material layer 208, and metal conductive material layer 207 as shown with reference to FIGS. 1 and 2, the metal conductive material layer 207 of the first signal line 20a in the upper memory device layer can be shared as the metal conductive material layer 207 of the second signal line 20c in the lower memory device layer. After forming this shared metal conductive material layer 207, the transition conductive material layer 208 and the semiconductor material layer 206 of the first signal line 20a in the upper memory device layer are formed. When the first signal line 20a and the second signal line 20c include only the semiconductor material layer 206, the first signal line 20a in the upper memory device layer may be completely shared as the second signal line 20c in the lower memory device layer.

[0061] In this solution, in order to further simplify the manufacturing process, when manufacturing the multi-layer memory device layer 20, in any two adjacent memory device layers 20, the first signal line 20a in the upper memory device layer and the second signal line 20c in the lower memory device layer may be used as the same signal line.

[0062] 〔Solution 2〕 In this solution 2, as shown with reference to FIGS. 3 and 5, the transistor 20b has the channel surround structure as described above, and the selector line 20d is formed on the upper end or the lower end side of the gate layer 202 in the transistor 20b. In order to simplify the manufacturing process, when manufacturing the multi-layer memory device layer 20, as shown in FIG. 3, the transistors 20b of at least two adjacent memory device layers 20 are provided corresponding to each other in the vertical direction Z. In other words, by the orthographic projection of the transistors 20b adjacent in the vertical direction Z onto the base 10 overlapping or substantially overlapping, at least a part of the gate layer 202 of the transistors 20b adjacent in the vertical direction Z can be easily shared by the same selector line 20d, reducing the total number of signal lines, simplifying the manufacturing process, and reducing the manufacturing cost.

[0063] Referring to FIG. 3, the multi-layer memory device layer 20 may be divided into at least one shared unit GG along the vertical direction Z. This shared unit GG includes two adjacent memory device layers 20. For the convenience of later description, the memory device layer 20 on the side away from the base 10 in the shared unit GG is defined as the upper-layer memory device layer, and the memory device layer 20 on the side close to the base 10 may be defined as the lower-layer memory device layer. Here, in the shared unit GG, the gate layers 202 of the two transistors 20b arranged in the vertical direction Z share the same selector line 20d. The second signal line 20c of the upper-layer memory device layer and the first signal line 20a of the lower-layer memory device layer are both read / write lines. By being arranged independently of each other, independent control of the read / write states of the two memory device layers 20 in the shared unit GG can be realized. It should be understood that when the second signal line 20c of the upper-layer memory device layer and the first signal line 20a of the lower-layer memory device layer are both read / write lines, the first signal line 20a of the upper-layer memory device layer and the second signal line 20c of the lower-layer memory device layer are both reference voltage lines.

[0064] Referring further to FIG. 3, in the shared unit GG, the gate layers 202 of two transistors 20b arranged in the vertical direction Z are directly connected to form a shared gate layer, and the shared selector line 20d is arranged on the upper end side of the shared gate layer, but is not limited thereto, and may be arranged on the lower end side of the shared gate layer. Further, in other embodiments, in the shared unit GG, the shared selector line 20d is also arranged between the upper memory device layer and the lower memory device layer, and the gate layers 202 of two transistors 20b arranged in the vertical direction Z may be indirectly connected via the shared selector line 20d. Specifically, in the shared unit GG, the selector line 20d of the upper memory device layer is formed on the lower end side of the gate layer 202 of the upper memory device layer, and the select line 20d of the lower memory device layer is formed on the upper end side of the gate layer 202 of the lower memory device layer. The select line 20d of the lower memory device layer and the selector line 20d of the upper memory device layer are at least partially shared to form a shared select line. For example, the select line 20d of the lower memory device layer may be completely shared with the selector line 20d of the upper memory device layer for cost reduction.

[0065] In some embodiments, at least a part of the second signal line 20c in the lower memory device layer is shared with at least a part of the first signal line 20a in the upper memory device layer in the shared unit GG. Therefore, the first signal line 20a of the upper memory device layer and the second signal line 20c of the lower memory device are used together as the reference voltage line of the shared unit GG, thereby simplifying the process and reducing the cost. However, it is not limited thereto, and the first signal line 20a of the upper memory device layer and the second signal line 20c of the lower memory device layer may be provided independently and used as the reference voltage line or the read / write line of the shared unit GG.

[0066] In any embodiment, as shown in FIG. 6, a plurality of shared units GG may be provided. Here, in two adjacent shared units GG, one read / write line and the other read / write line are provided independently of each other. Thereby, the read / write lines of any two memory device layers 20 are designed to be independent of each other, facilitating the realization of independent control of the read / write states of each memory device layer 20.

[0067] In any embodiment, as shown with reference to FIG. 6, in two adjacent shared units GG, the gate layer 202 of the transistor 20b of one shared unit GG and the gate layer 202 of the transistor 20b of the other shared unit GG are provided insulated from each other by an insulating isolation layer 218. In two adjacent shared units GG, one selector line 20d and the other selector line 20d are provided independently of each other. Thereby, independent control between adjacent shared units GG becomes possible, reducing the difficulty of control.

[0068] It will be understood that at least one of the read / write line and the selector line may be set independently of each other between different shared units GG in order to realize independent operations between different shared units GG. Thus, when the selector lines 20d connected to the gate layer 202 are provided independently of each other between two adjacent shared units GG, for example, in two adjacent shared units GG, the selector line 20d of the shared unit GG closer to base 10 is located between base 10 and the selector line 20d of the shared unit GG farther from base 10 is located on the side of the shared unit GG away from base 10, or when the shared selector line 20d in the shared unit GG is located between the upper memory device layer and the lower memory device layer, the read / write lines may be partially shared between the two, for example, the upper read / write line of the shared unit GG closer to base 10 and the lower read / write line of the shared unit GG farther from base 10 may be at least partially shared. In other words, the adjacent read / write lines in two adjacent shared units GG share at least a part.

[0069] In another optional embodiment, as shown in FIG. 7, the multi-layer memory device layer 20 may be divided into at least one shared group G along the vertical direction Z. This shared group G may include shared units GG of two adjacent layers. For the convenience of later description, in the shared group G, the shared unit GG on the side away from the base 10 is defined as the upper-layer shared unit, and the shared unit GG on the side close to the base 10 is defined as the lower-layer shared unit. Here, in the shared group G, the two-layer shared unit GG shares the same selector line 20d. The selector line 20d is formed at the lower end side of the shared gate layer of the upper-layer shared unit and the upper end side of the shared gate layer of the lower-layer shared unit. Since the read / write lines of the upper-layer shared unit and the read / write lines of the lower-layer shared unit are independent of each other, while realizing independent control of each layer of the memory device layer 20 in the shared group G, the fabrication of the selector line 20d can be further saved, and the fabrication cost can be reduced.

[0070] Optionally, as shown in FIG. 8, a plurality of shared groups G may be provided. In two adjacent shared groups G, the lowermost read / write line of the shared group G on the side away from the base 10 is at least partially provided in a shared manner with the uppermost read / write line of the shared group G on the side close to the base 10. The selector line 20d of the shared group G on the side away from the base 10 is arranged independently of the selector line 20d of the shared group G on the side close to the base 10. By doing so, while realizing independent control of each memory device layer 20, the fabrication of the read / write lines can be further saved, and the fabrication cost can be reduced.

[0071] Here, based on any of the above-described embodiments of the present disclosure, by arranging the active layer 201 of the transistor 20b independently of the base 10 of the semiconductor structure, compared with the method of using a part of the base 10 as the active layer 201, by making the memory device layer 20 multi-layered and stacking it along the vertical direction Z, the storage density can be increased, and the design difficulty and technical cost of the transistor 20b can be reduced.

[0072] In addition, the present disclosure also provides a method for manufacturing a semiconductor structure for manufacturing the semiconductor structure described in any of the foregoing embodiments. However, for the structure, shape, positional relationship with other layers, connection relationship, etc. of each layer in the semiconductor structure, reference may be made to the foregoing content and will not be repeated here.

[0073] Here, the method for manufacturing the semiconductor structure of the present disclosure may include the following steps: Step S100: Provide a base 10, which may be, for example, a stacked structure as shown in FIG. 9. The base 10 may include a single-crystalline semiconductor material layer 101 and an insulating isolation layer 102 formed on the single-crystalline semiconductor material layer 101. Step S200: As shown with reference to FIGS. 1 to 3 and FIGS. 6 to 8, form at least one memory device layer 20 stacked along the vertical direction Z on the base 10. The method for forming the memory device layer 20 may include the following: Form a first signal line 20a, a transistor 20b, a second signal line 20c, and a selector line 20d on the base 10. One of the first signal line 20a and the second signal line 20c is a reference voltage line, and the other is a read / write line. Connect the gate layer 202 of the transistor 20b to the selector line 20d, extend the active layer 201 of the transistor 20b in the vertical direction Z, and arrange it independently of the base 10. The lower end of the active layer 201 is connected to the first signal line 20a, and the upper end of the active layer 201 is connected to the second signal line 20c.

[0074] In the present disclosure, the step of forming the first signal line 20a of the bottommost memory device layer 20 on the base 10 may include the following: Step S2001: Sequentially form a thin film of a metal conductive material and a thin film of a semiconductor material that cover the entire surface on the base 10 to form a composite conductive thin film. Here, in step S2001, a transition conductive material thin film may be formed between the metal conductive material thin film and the semiconductor material thin film. The transition conductive material thin film may be fabricated by vapor deposition or may be formed by a silicidation reaction between the metal conductive material thin film and the semiconductor material thin film. The composite conductive thin film may include a metal conductive material thin film, a semiconductor material thin film, and a transition conductive material thin film formed between the metal conductive material thin film and the semiconductor material thin film.

[0075] Step S2002: Pattern the composite conductive thin film to form a plurality of slits penetrating the composite conductive thin film. The composite conductive thin film is divided into a plurality of first signal lines 20a arranged at intervals by the slits. The first signal line 20a may include a metal conductive material layer 207, a transition conductive material layer 208, and a semiconductor material layer 206 that are sequentially stacked.

[0076] In another embodiment, the step of forming the first signal line 20a of the bottom layer memory device layer 20 on the base 10 may include sequentially forming a thin film of a semiconductor material that covers the entire surface on the base 10, and then patterning the semiconductor material thin film to form a plurality of slits penetrating the semiconductor material thin film. The semiconductor material thin film may be divided into a plurality of first signal lines 20a arranged at intervals by the slits. The first signal line 20a may include a semiconductor material layer 206.

[0077] In another embodiment, optionally, when forming the material layer of the first signal line 20a, it may not be necessary to form the semiconductor material thin film or the transition conductive material thin film in step S2001.

[0078] Note that the first signal line 20a manufactured according to the present disclosure may be used as a read / write line, but is not limited thereto, and may also be used as a reference voltage line. Here, when the first signal line 20a is used as a reference voltage line, by using the manufacturing method described above, it is not limited to forming a plurality of reference voltage lines arranged at intervals, and the entire surface of the composite conductive thin film may be directly used as a reference voltage line without performing a patterning process on the composite conductive thin film.

[0079] In addition to the first signal line 20a in the bottommost memory device layer 20 that can be fabricated according to the above steps, it should also be understood that the first signal line 20a in other memory device layers 20 can also be fabricated according to the above steps or by other methods that can be selected according to the actual situation.

[0080] In the present disclosure, for transistors 20b with different structures, there are different manufacturing methods, for example, as described in Solution 3 and Solution 4 below.

[0081] 〔Solution 3〕 In this Solution 3, after forming the first signal line 20a, a GAA-type transistor 20b may be formed on the base 10, and the step of forming the GAA-type transistor 20b may include the following: Step S2003: Form a first insulating medium layer 204 on the base 10. As shown in FIG. 10, this first insulating medium layer 204 covers at least the upper surface of the first signal line 20a. Note that as shown in FIGS. 10 and 12 together, when a plurality of first signal lines 20a are installed and arranged at intervals, the first insulating medium layer 204 can also be formed in the slit between adjacent first signal lines 20a. In this embodiment, the surface of the first insulating medium layer 204 away from the base 10 may be polished by a CMP (Chemical Mechanical Polishing) device to form a plane parallel to the base 10, and the flat surface is advantageous for the fabrication of subsequent film layers. As shown with reference to FIG. 13, step S2004 forms a conductive thin film layer 211 and a second insulating medium layer 205 that are sequentially stacked along the vertical direction Z on the upper surface of the first insulating medium layer 204. In this embodiment, the conductive thin film layer 211 and the second insulating medium layer 205 are a film layer structure that covers the first insulating medium layer 204 entirely. The conductive thin film layer 211 is patterned in a subsequent step S2008. However, in other embodiments, after forming the conductive thin film layer 211, it may be patterned as a selector line, and then, a second insulating medium layer 205 covering the entire surface may be fabricated; Step S2005 forms a filling hole S1 that penetrates the second insulating medium layer 205, the conductive thin film layer 211, and the first insulating medium layer 204 along the vertical direction Z. As shown with reference to FIG. 14, this filling hole S1 exposes a part of the first signal line 20a. It should be understood that a plurality of such filling holes S1 may be provided in the first horizontal direction X and the second horizontal direction Y and arranged at intervals; Step S2006 forms a gate insulating layer 203 on the inner wall of the filling hole S1, and the inner wall of the gate insulating layer 203 forms a through hole S2 that penetrates along the vertical direction Z and exposes a part of the first signal line 20a as shown with reference to FIG. 15; Step S2007 forms an active layer 201 in the through hole S2 of the gate insulating layer 203; Step S2008 performs a patterning process on the conductive thin film layer 211 to form a plurality of selector lines 20d arranged at intervals. These selector lines 20d intersect the extending direction of the read / write lines. For example, the selector lines 20d extend along the first horizontal direction X, and the read / write lines extend along the second horizontal direction Y. Here, the selector line 20d includes at least one gate layer 202, and each gate layer 202 is provided at least partially around the active layer 201. Specifically, as shown with reference to FIGS. 4 and 16, each gate layer 202 may be provided entirely around the active layer 201.

[0082] Exemplarily, in step S2005, in addition to penetrating the second insulating medium layer 205, the conductive thin film layer 211, and the first insulating medium layer 204, the filling hole S1 may be over-etched on the first signal line 20a. Exemplarily, as shown with reference to FIG. 14, the lower end of this filling hole S1 may be embedded in the semiconductor material layer 206 of the first signal line 20a. That is, in some embodiments, the filling hole S1 is recessed on the surface of the first signal line 20a, and in other embodiments, when the first signal line 20a includes a metal conductive material layer 207, a transition conductive material layer 208, and a semiconductor material layer 206 that are sequentially stacked, or when the first signal line 20a includes the semiconductor material layer 206, the filling hole S1 is recessed on the surface of the semiconductor material layer 206 but does not penetrate the semiconductor material layer 206.

[0083] Exemplarily, in step S2006, the specific steps may include the following: Step S20061, sequentially form a silicon oxide thin film and a silicon nitride thin film. A part of the silicon oxide thin film and the silicon nitride thin film are sequentially stacked to cover the surface of the second insulating medium layer 205 away from the base 10. Another part of the silicon oxide thin film and the silicon nitride thin film are respectively disposed in their corresponding filling holes S1. The silicon oxide thin film and the silicon nitride thin film disposed in the filling holes S1 may have a groove-like structure, and the groove-like structure of the silicon nitride thin film is disposed within the groove-like structure of the silicon oxide thin film; Step S20062, remove the bottom of the groove-like structure of the silicon nitride thin film and the silicon oxide thin film to expose the first signal line 20a; Step S20063, remove the remaining part of the groove-like structure in the silicon nitride thin film disposed in the filling hole S1, that is, remove the groove sidewalls of the groove-like structure in the silicon nitride thin film, so that the part of the silicon oxide thin film remaining in the filling hole S1 is formed as the gate insulating layer 203.

[0084] In the present solution 3, in the process of fabricating the gate insulating layer 203, by forming a silicon nitride thin film, the gate insulating layer 203 formed of a silicon oxide thin film can be protected, the quality of the gate insulating layer can be improved, and current leakage can be reduced. In the present embodiment, the gate insulating layer 203 is formed using a silicon oxide thin film, but the material of the actual gate insulating layer 203 can be set according to specific needs, and it can be understood that the silicon nitride thin film can be replaced as the material layer according to specific needs.

[0085] In addition, in the process of forming the gate insulating layer 203, it is also possible to omit step S20063, that is, the groove side walls of the groove-like structure in the silicon nitride thin film are left in the filling hole S1, and the gate insulating layer 203 may be formed together with the portion of the silicon oxide thin film remaining in the filling hole S1. Further, in step S2006, the gate insulating layer 203 may be formed using other methods known in the art, and the present invention is not particularly limited.

[0086] Exemplarily, in step S2007, the specific steps are as shown with reference to FIG. 16. In the through hole S2 of the gate insulating layer 203, the first electrode region 2012, the channel region 2011, and the second electrode region 2013 are sequentially formed. The upper surface of the first electrode region 2012 is higher than the lower surface of the gate layer 202, and the lower surface of the second electrode region 2013 is lower than the upper surface of the gate layer 202. The first electrode region 2012 can have the same conductivity type as the second electrode region 2013 and a different conductivity type from the channel region 2011, that is, the active layer 201 formed in step S2007 is a junction-type active layer.

[0087] In the present solution 3, as described above, the first signal line 20a may include the semiconductor material layer 206, and the semiconductor material layer 206 of the first signal line 20a may be exposed in the through hole S2. Based on this, the step of forming the first electrode region 2012 in the through hole S2 of the gate insulating layer 203 includes the step of epitaxially growing on the semiconductor material layer 206 of the first signal line 20a exposed in the through hole S2 to form the first electrode region 2012. In the present embodiment, epitaxially growing the semiconductor material layer 206 of the first signal line 20a exposed in the through hole S2 to form the first electrode region 2012 is regarded as constituting an integral structure with the semiconductor material layer 206 of the first signal line 20a. Without being limited thereto, a semiconductor material of the same conductivity type as the semiconductor material layer 206 of the first signal line 20a may be directly deposited in the through hole S2. After a semiconductor material of the same conductivity type as the semiconductor material layer 206 of the first signal line 20a is deposited, as shown with reference to FIG. 17, in order to form the first electrode region 2012, it should be understood that it is also necessary to remove a part of the semiconductor material on the inner wall of the through hole S2 and on the upper part of the second medium layer 205.

[0088] For example, in the present solution 3, the step of forming the channel region 2011 in the through hole S2 of the gate insulating layer 203 may include, after forming the first electrode region 2012, laminating a semiconductor thin film of a conductivity type different from that of the first electrode region 2012, and then performing a back etching process on this semiconductor thin film to form the channel region 2011 disposed in the through hole S2. As shown with reference to FIG. 18, the upper surface of this channel region 2011 is lower than the upper surface of the gate layer 202.

[0089] In this solution 3, when the second signal line 20c includes the semiconductor material layer 206, the semiconductor material layer 206 of the second signal line 20c may be formed as an integral structure with the second electrode region 2013 of the active layer 201. Specifically, after forming the channel region 2011 of the active layer 201, a semiconductor thin film layer 212 having the same conductivity type as the semiconductor material layer 206 of the first signal line 20a may be formed on the base 10. As shown with reference to FIG. 19, it covers the channel region 2011, the gate insulating layer 203, and the second insulating medium layer 205. Then, the semiconductor thin film layer 212 may be patterned to form a plurality of semiconductor portions arranged at intervals. This semiconductor portion includes the second electrode region 2013 of the active layer 201 and the semiconductor material layer 206 of the second signal line 20c. The second electrode region 2013 of the active layer 201 is filled in the through hole S2, and the semiconductor material layer 206 of the second signal line 20c covers the second electrode region 2013, the gate insulating layer 203, and the second insulating medium layer 205.

[0090] Also, in other embodiments, the semiconductor material layer 206 of the second signal line 20c and the second electrode region 2013 of the active layer 201 may be separately fabricated, so that they may have different doping concentrations, or after fabricating the semiconductor material layer 206 of the second signal line 20c and the second electrode region 2013 of the active layer 201 integrally, the semiconductor material layer 206 of the second signal line 20c may be further doped. It will be understood that the impedance can be reduced by giving the semiconductor material layer 206 a high doping concentration.

[0091] In other embodiments, when the transistor 20b is a non-junction transistor, the active layer 201 and the semiconductor material layer 206 of the second signal line 20c can be formed by epitaxial growth on the upper surface of the semiconductor material layer 206 of the first signal line 20a, which can be specified depending on the case.

[0092] In the present disclosure, the second signal line 20c may be a reference voltage line or a read / write line. When the second signal line 20c fabricated in the present disclosure is used as the reference voltage line, the semiconductor thin film layer 212 may be patterned by the method described above. The patterned reference voltage line may have the same extending direction as the selector line 20d or a different extending direction from the selector line 20d, which is specifically determined according to the case. Also, without patterning the semiconductor thin film layer 212, by directly connecting the electrode regions for grounding all the transistors 20b of the entire memory device layer 20 using the entire surface of the semiconductor thin film layer 212, the patterning step can be reduced and the manufacturing cost can be lowered. When the second signal line 20c fabricated in the present disclosure is used as the read / write line, not only the semiconductor thin film layer needs to be patterned, but it is also necessary to make the extending direction of the entire patterned second signal line 20c different from the extending direction of the selector line 20d. For example, while the selector line extends in the first horizontal direction X, the read / write line may extend in the second horizontal direction Y as a whole.

[0093] For example, in the present solution 3, when the second signal line 20c is used as the read / write line, the step of forming the second signal line 20c may specifically include step S2009, step S2010, step S2011, and step S2012.

[0094] In step S2009, a semiconductor thin film layer 212 having the same conductivity type as the semiconductor material layer 206 of the first signal line 20a is formed. As shown with reference to FIG. 19, the semiconductor thin film layer 212 covers the channel region 2011, the gate insulating layer 203, and the second insulating medium layer 205. In other embodiments, the semiconductor thin film layer 212 may be filled only with the through hole S2 whose upper surface is flush with the upper surface of the second insulating medium layer 205. The semiconductor material layer 206 of the second signal line 20c is fabricated in the subsequent step S2012.

[0095] In step S2010, a first slit extending in the first horizontal direction X and a second slit extending in the second horizontal direction Y are formed. The first slit sequentially penetrates the semiconductor thin film layer 212, the second insulating medium layer 205, and the conductive thin film layer 211 along the vertical direction Z, and is disposed between adjacent filling holes S1 in the second horizontal direction Y. The second slit penetrates the semiconductor thin film layer 212 and is disposed between adjacent filling holes S1 in the first horizontal direction X. The conductive thin film layer 211 forms a plurality of selector lines 20d extending in the first horizontal direction X under the action of the first slit. The semiconductor thin film layer 212 forms a plurality of semiconductor portions spaced apart in the first horizontal direction X and the second horizontal direction Y under the action of the first slit and the second slit. The semiconductor portion has a second electrode region 2013 and a semiconductor material layer 206 of the second signal line 20c. The second electrode region 2013 is filled in the through hole S2, and the semiconductor material layer 206 of the second signal line 20c covers the second electrode region 2013, the gate insulating layer, and the second insulating medium layer 205. That is, step S2010 may include the aforementioned step S2008. Specifically, in the process of forming the first slit, the primary patterning process of the semiconductor thin film layer 212 is achieved and the patterning process of the conductive thin film layer 211 is completed, so that the process steps can be reduced. Also, in this solution, the formation order of the first slit and the second slit is not specified. The first slit can be formed before the second slit, or after the second slit. It should be noted that the first slit and the second slit can also be simultaneously implemented within the range allowed by the etching process.

[0096] In other embodiments, when the semiconductor thin film layer 212 is filled only in the through hole S2, the step of forming the second slit in step S2010 may be omitted, and other steps related to the second slit may be deleted in the subsequent step S2011.

[0097] In other embodiments, before fabricating the second insulating medium layer 205, the conductive thin film layer 211 may be patterned as a selector line, and the semiconductor material layer 206 may be patterned simultaneously with the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20c.

[0098] In step S2011, as shown with reference to FIG. 16, an insulation filling portion 209 is formed in the first slit and the second slit. The upper surface of the insulation filling portion 209 is flush with the upper surface of the semiconductor portion. The insulation filling portions 209 in the first slit and the second slit may be filled simultaneously or sequentially. For example, after forming the second slit and before forming the first slit, the insulation filling portion 209 may be filled in the second slit. Then, after forming the first slit, the insulation filling portion 209 may be filled in the first slit. However, the present invention is not limited thereto. First, the first slit may be formed, then the insulation filling portion 209 may be filled in the first slit, then the second slit may be formed, and then the insulation filling portion 209 may be filled in the second slit. Or, it should be noted that after forming the first slit and the second slit, the insulation filling portion 209 may be formed simultaneously in the first slit and the second slit.

[0099] In step S2012, a transition conductive material layer 208 of a plurality of second signal lines 20c arranged at intervals in the first horizontal direction X and extending along the second horizontal direction Y, and a metal conductive material layer 207 of the plurality of second signal lines 20c arranged at intervals in the first horizontal direction X and extending along the second horizontal direction Y are formed. In the second signal line 20c: the metal conductive material layer 207 and the transition conductive material layer 208 correspond one-to-one in the vertical direction Z, and each transition conductive material layer 208 is in contact with the upper surfaces of a plurality of semiconductor portions arranged in the second horizontal direction Y. For example, as shown in FIG. 20, the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20c may be simultaneously patterned to form an elongated structure extending along the second horizontal direction Y. For example, a transition conductive material thin film and a metal conductive material thin film may be first formed to entirely cover the base 10, and then the transition conductive material thin film and the metal conductive material thin film are patterned to simultaneously cut out the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20c, thereby reducing the manufacturing cost. Further, in other embodiments, when the semiconductor thin film layer 212 fills only the through hole S2, in step S2012, a semiconductor material layer 206 may be fabricated as the second signal line 20c, or the semiconductor material layer 206, the transition conductive material thin film, and the metal conductive material thin film may be sequentially deposited to fabricate the second signal line 20c, or the second signal line 20c may be obtained by sequentially depositing the semiconductor material layer 206 and the metal conductive material thin film and then subjecting both to a silicidation reaction to form a transition conductive material thin film, which is determined by circumstances and will not be elaborated with many examples. In this solution, in any two adjacent memory device layers 20: at least a part of the second signal line 20c in the lower memory device layer is shared as at least a part of the first signal line 20a in the upper memory device layer. For example: the metal conductive material layer 207 of the second signal line 20c in the lower memory device layer can be shared by the first signal line 20a in the upper memory device layer. Here, the first signal line 20a of the upper memory device layer may be formed simultaneously with the transition conductive material layer 208 and the metal conductive material layer 207 of the second signal line 20c, and the specific steps may include the following: First, on a base 10, a first transition conductive material thin film, a metal conductive material thin film, a second transition conductive material thin film, and a semiconductor material thin film that are comprehensively covered and sequentially laminated are formed. This first transition conductive material thin film is used to form the transition conductive material layer 208 of the second signal line 20c in the lower layer memory device layer through subsequent patterning processing. The metal conductive material thin film forms the metal conductive material layer 207 shared by the second signal line 20c in the lower layer memory device layer and the first signal line 20a in the upper layer memory device layer through subsequent patterning processing. The second transition conductive material thin film and the semiconductor material thin film are patterned to form the transition conductive material layer 208 and the semiconductor material layer 206 of the first signal line 20a in the upper layer memory device layer; Then, the first transition conductive material thin film, the metal conductive material thin film, the second transition conductive material thin film, and the semiconductor material thin film are simultaneously patterned to form a composite linear structure as shown in FIG. 21. The composite linear structure includes the metal conductive material layer 207 and the transition conductive material layer 208 of the second signal line 20c in the lower layer memory device layer, and the metal conductive material layer 207, the transition conductive material layer 208, and the semiconductor material layer 206 of the first signal line 20a in the upper layer memory device layer. The metal conductive material layer 207 of the second signal line 20c in the lower layer memory device layer and the metal conductive material layer 207 of the first signal line 20a in the upper layer memory device layer are shared layers.

[0100] In other embodiments, the composite linear structure includes only the semiconductor material layer 206, or includes the semiconductor material layer 206, the metal conductive material layer 207, and the transition conductive material layer 208 of the second signal line 20c, and the metal conductive material layer 207, the transition conductive material layer 208, and the semiconductor material layer 206 of the first signal line 20a in the upper layer memory device layer, or the metal conductive material layer 207 of the second signal line 20c in the lower layer memory device layer and the metal conductive material layer 207 of the first signal line 20a in the upper layer memory device layer are different from each other as desired, and are electrically connected to each other or insulated from each other.

[0101] In other embodiments, after forming the conductive thin film layer 211, it is also possible to directly pattern the conductive thin film layer 211 to form a plurality of selector lines 20d arranged at intervals. Then, an insulating medium layer is deposited to cover the upper surface of the selector lines 20d and fill the gaps between adjacent selector lines 20d. After that, this insulating medium layer is planarized and stopped at the upper surface of the selector lines 20d. That is, the portion of the insulating medium layer covering the upper surface of the selector lines 20d is removed, and only the portion filled between adjacent selector lines 20d is retained, and this portion is defined as the isolation part. Then, it is understood that a second insulating medium layer 205 may be formed to entirely cover the isolation part and the selector lines 20d, and the second insulating medium layer 205 and the isolation part may be integrally fabricated. Then, again, the aforementioned steps S2005, S2006, and S2007 are executed. The filling hole S1 formed in step S2005 penetrates the second insulating medium layer 205, the selector lines 20d, and the first insulating medium layer 204 along the vertical direction Z. After executing step S2007, a semiconductor thin film layer, a transition conductive material thin film, and a metal conductive material thin film covering the entire surface can be sequentially formed. Then, the whole is patterned to form a second signal line 20c intersecting the extending direction of the selector lines 20d, and at the same time, a column of the second electrode regions 2013 of the transistors 20b is formed. The column mentioned here means a plurality of transistors 20b arranged along the extending direction of the second signal line (20c). That is, the column of the second electrode regions 2013 of the transistors 20b may be integrally formed with the second semiconductor material layer 206 of the second signal line 20c.

[0102] In this embodiment, in any two adjacent memory device layers 20, the second signal line 20c of the lower memory device layer and the first signal line 20a of the upper memory device layer are shared, and the entire shared signal line is defined as a shared composite signal line. When three or more memory device layers 20 of the semiconductor structure according to this solution are provided, there may be a plurality of shared composite signal lines. One of the shared composite signal lines adjacent in the vertical direction Z is a reference voltage line, and the other is a read / write line.

[0103] After forming the memory device layer 20 of the last layer (i.e., the memory device layer 20 farthest from the base 10), as shown in FIG. 1, an insulating cover layer 210 is formed to cover the second signal line 20c of the memory device layer 20 of the last layer. After forming the insulating cover layer 210, an overhaul structure (not shown) is designed to facilitate the extraction of the signal lines of each memory device layer 20, which will not be described in detail here.

[0104] 〔Solution 4〕 In Solution 4, after forming the first signal line 20a, a CAA-type transistor 20b may be formed on the base 10. The step of forming the CAA-type transistor 20b may include the following: Step S2100, forming a first insulating medium layer 204 on the base 10. The first insulating medium layer 204 covers at least the upper surface of the first signal line 20a as shown with reference to FIG. 11. When a plurality of first signal lines 20a are provided and arranged at intervals as shown in FIGS. 11 and 12 in combination, it should be noted that the first insulating medium layer 204 can also be formed in the slit between adjacent first signal lines 20a. In this embodiment, the surface of the first insulating medium layer 204 away from the base 10 may be planarized by a CMP (Chemical Mechanical Polishing) apparatus to form a plane parallel to the base 10, which is advantageous for the fabrication of subsequent film layers; Step S2101, forming a filling hole S1 that penetrates the first insulating medium layer 204 in the vertical direction Z. The filling hole S1 exposes a part of the first signal line 20a as shown with reference to FIG. 22. Step S2102, forming an annular active layer 201 on the inner wall of the filling hole S1. The inner wall of the annular active layer 201 forms a through hole S2 that penetrates in the vertical direction Z. The through hole S2 exposes a part of the first signal line 20a as shown with reference to FIG. 23. Step S2103, forming a groove-shaped gate insulating layer 203 in the through hole S2. The groove-shaped gate insulating layer 203 covers the region of the first signal line 20a exposed by the inner wall of the annular active layer 201 and the through hole S2 as shown in FIG. 24. In step S2104, as shown with reference to FIG. 25, a gate layer 202 is formed in the groove of the groove-shaped gate insulating layer 203.

[0105] Steps S2103 and S2104 may be executed sequentially, but are not limited thereto. After step S2102, the gate insulating thin film material layer 214 and the gate thin film material layer 215 may also be sequentially formed first. The gate insulating thin film material layer 214 includes a planar portion disposed on the upper surface of the first insulating medium layer 204 and a groove-shaped portion disposed in the filling hole S1. The gate thin film material layer 215 includes a planar portion disposed on the upper surface of the gate insulating thin film material layer 214 and a columnar portion filled in the filling hole S1, as shown with reference to FIG. 26. Then, in order to form the gate layer 202 and the gate insulating layer 203 simultaneously, the portions of the gate insulating thin film material layer 214 and the gate thin film material layer 215 disposed on the upper surface of the first insulating medium layer 204 are removed. As shown in FIG. 25, by protruding the upper portion of the gate layer 202, the second signal line 20c formed thereafter includes a semiconductor material layer, and this semiconductor material layer contacts the upper surface of the active layer 201. In the case of different conductivity types, the junction formed between the active layer 201 and the semiconductor material layer of the second signal line 20c can be covered by the gate layer 202. In some embodiments, when the active layer 201 is a non-junction active layer and the conductivity types of the semiconductor material layers 206 of the first signal line 20a and the second signal line 20c in contact with the active layer 201 are different from the conductivity type of the active layer 201, it is necessary to design the gate layer 202 such that the lower end of the gate layer 202 is lower than the lower end of the active layer 201. That is, it is necessary to embed the lower end of the through hole S2 mentioned in step S2102 into the semiconductor material layer 206 of the first signal line 20a. Since the groove bottom of the gate insulating layer 203 in step S2103 also needs to be lower than the lower end of the active layer 201, the lower end of the gate layer 202 formed in the subsequent step S2104 can be made lower than the lower end of the active layer 201, and the upper end of the gate layer 202 needs to be higher than the upper end of the active layer 201.As a result, the junctions formed between the active layer 201 and the semiconductor material layer 206 of the first signal line 20a, and between the active layer 201 and the semiconductor material layer 206 of the second signal line 20c are all covered by the gate layer 202. One of the semiconductor material layer 206 of the first signal line 20a and the semiconductor material layer 206 of the second signal line 20c can be regarded as the source region of the transistor 20b, and the other can be regarded as the drain region of the transistor 20b.

[0106] It should be noted that the junction formed in the source region may or may not be covered by the gate layer 202, but the junction formed in the drain region must be covered by the gate layer 202.

[0107] In some embodiments, the gate insulating layer 203 is fabricated by vapor deposition. In some embodiments, the gate insulating layer 203 is formed, for example, by an oxidation method such as ISSG (In Situ Steam Generation) or thermal oxidation, by oxidizing a part of the inner wall of the active layer 201 and the surface of the semiconductor material layer 206 (not shown) in the first signal line 20a.

[0108] Here, after forming the gate layer 202 and before forming the second signal line 20c, the manufacturing method further includes the following steps: Step S2105, forming the insulation isolation part 216. As shown in FIG. 27, the insulation isolation part 216 completely covers the upper surface of the gate layer 202 and exposes at least a part of the upper surface of the annular active layer 201, so that the second signal line 20c formed later can be insulated from the gate layer 202 while contacting the upper surface of the annular active layer 201.

[0109] It should be noted that the CAA transistor has a simple manufacturing process and low manufacturing cost.

[0110] In Solution 4, the multi-layer memory device layer 20 may be divided into at least one shared unit GG. The shared unit GG includes two layers of adjacent memory device layers 20. In the shared unit GG, the memory device layer 20 on the side away from the base 10 is defined as the upper-layer memory device layer, and the memory device layer 20 on the side close to the base 10 is defined as the lower-layer memory device layer. The specific relationship between the layers of the shared unit GG can refer to the foregoing content and will not be repeatedly described here.

[0111] Here, when manufacturing the shared unit GG, the manufacturing method further includes the following steps: Step S2106: After forming the reference voltage lines of the shared unit GG (i.e., the first signal line 20a of the upper-layer memory device layer and the second signal line 20c of the lower-layer memory device layer), sequentially form the third insulating medium layer and the upper-layer read / write line. As shown with reference to FIG. 28, the third insulating medium layer refers to the first insulating medium layer 204 of the upper-layer memory device layer of the shared unit GG, and the upper-layer read / write line refers to the second signal line 20c of the upper-layer memory device layer of the shared unit GG; Step S2107: Form a first alignment hole penetrating the upper-layer read / write line and the third insulating medium layer. The first alignment hole corresponds one-to-one to the filling hole S1, exposing a part of the reference voltage line. The size and manufacturing method of this first alignment hole can refer to the manufacturing method of the filling hole S1 in FIG. 22. The orthographic projection of the first alignment hole on the base 10 of this solution overlaps at least partially with the orthographic projection of the filling hole S1 on the base 10; Step S2108: Form a groove-shaped active layer on the inner wall of the first alignment hole. The groove-shaped active layer covers the hole surface of the upper-layer read / write line and the third insulating medium layer, and the region corresponding to the first alignment hole in the reference voltage line; In step S2109, a second alignment hole S3 is formed. As shown with reference to FIG. 29, the second alignment hole S3 penetrates from the inner wall of the groove-shaped active layer to the bottom of the groove-shaped active layer, the reference voltage line, and the insulation isolation part 216, and the second alignment hole S3 exposes the upper surface of the lower gate layer that points to the gate layer 202 of the transistor 20b in the lower-layer memory device layer in the shared unit GG; In step S2110, an annular gate insulating layer 203 is formed on the inner wall of the second alignment hole S3. The inner wall of the annular gate insulating layer 203 is formed as a third alignment hole. The third alignment hole exposes the upper surface of the lower gate layer, and an upper gate layer is formed in the third alignment hole. The upper gate layer fills the inside of the third alignment hole and contacts the upper surface of the lower gate layer. As shown with reference to FIG. 30, this upper gate layer points to the gate layer 202 of the transistor 20b in the upper-layer memory device layer in the shared unit GG; In other embodiments, the second alignment hole S3 does not extend to the insulation isolation part 216, and extends at least through the reference voltage line or extends to the insulation isolation part 216 without penetrating the insulation isolation part 216. When the third alignment hole is formed in step S2110, it penetrates the insulation isolation part 216 to expose the upper surface of the lower gate layer.

[0112] In step S2111, as shown with reference to FIG. 31, a fourth insulating medium layer 217 that covers the groove-shaped active layer and the upper read / write line is formed, and the fourth insulating medium layer 217 exposes the upper surface of the upper gate layer; In step S2112, as shown with reference to FIG. 32, a selector line 20d that contacts the upper surface of the upper gate layer is formed on the upper surface of the fourth insulating medium layer 217. The selector line 20d contacts the upper surface of the upper gate layer and insulates the upper active layer (i.e., the active layer 201 of the upper-layer memory device layer) and the upper read / write line through the fourth insulating medium layer 217.

[0113] Exemplarily, in the shared unit GG: the active layer 201 is one of an N-type semiconductor and a P-type semiconductor, the upper layer read / write line (i.e., the second signal line 20c of the upper layer memory device layer) and the lower layer read / write line (i.e., the first signal line 20a of the lower layer memory device layer) both include a semiconductor material layer, and the semiconductor material layers of the upper layer read / write line and the lower layer read / write line are both the other of the N-type semiconductor and the P-type semiconductor; the bottom of the groove of the groove-shaped gate insulating layer of the lower layer memory device layer is embedded in the semiconductor material layer of the lower layer read / write line, and the upper surface of the bottom of the groove of the groove-shaped gate insulating layer is made lower than the bottom surface of the active layer 201 of the lower layer memory device layer, so that the bottom surface of the shared gate layer is lower than the bottom surface of the active layer 201 of the lower layer memory device layer, whereby the PN junction formed by the lower active layer (i.e., the active layer 201 of the lower layer memory device layer) and the semiconductor material layer of the lower layer read / write line is covered by the shared gate layer.

[0114] Here, in the orthographic projection on the base 10: the selector line 20d covers the boundary of the first alignment hole such that the PN junction formed by the lower active layer (i.e., the active layer 201 of the upper layer memory device layer) and the semiconductor material layer of the upper layer read / write line is covered by the selector line 20d; in this embodiment, the fourth insulating medium layer 217 may be disposed between the selector line 20d and the semiconductor material layer of the upper layer read / write line, step S2111 is executed during step S2110, and the fourth insulating medium layer 217 is fabricated in the same layer as the annular gate insulating layer to form a continuous film layer with a uniform thickness, and then the step of fabricating the upper gate layer in step S2110 is executed.

[0115] In other embodiments, the fourth insulating medium layer 217 may not be fabricated in the same layer as the annular gate insulating layer. For example, after sequentially forming the annular gate insulating layer and the upper gate layer, a fourth insulating medium layer 217 covering the upper gate layer, the annular gate insulating layer 203, the groove-shaped active layer, and the upper layer read / write line is formed, and then the fourth insulating medium layer 217 is patterned to expose the upper surface of the upper gate layer, and then step S2112 is executed.

[0116] In other embodiments, after step S2112, the manufacturing method of the shared unit GG may further include the following steps: Step S2113, as shown with reference to FIG. 32, form an insulating layer 218 that covers at least the fourth insulating medium layer 217 and fills the space between adjacent selector lines 20d.

[0117] In other embodiments, the first signal line 20a of the lower memory device layer and the second signal line 20c of the upper memory device layer are read / write lines, and include a composite line layer formed by a semiconductor material layer, a metal material layer, and a transition metal material layer having a conductivity type different from that of the active layer 201. The semiconductor material layer is in contact with the active layer 201 to form a PN junction.

[0118] Here, a plurality of the shared units GG of this solution 4 may be provided, and two adjacent shared units GG may be formed completely independently. That is, after step S2114 is completed, steps S2106 to S2114 may be repeated a plurality of times to fabricate more layers of the shared units GG.

[0119] Also, the multi-layer shared unit GG is not limited to the independent formation described above, and may form at least one of the aforementioned shared groups G. It should be understood that the manufacturing method of the shared group G includes the aforementioned steps S2106 to S2114, and after step S2114 is formed, an upper-layer shared unit may be formed. Since the first signal line 20a of the lower memory device layer in the upper-layer shared unit needs to be provided insulated from the selector line 20d, it should be noted that the insulating isolation layer 218 fabricated in step S2114 may cover the upper surface of the selector line 20d in addition to covering the fourth insulating medium layer 217 and filling the space between adjacent selector lines 20d.

[0120] In this embodiment, although the overall formation steps of the upper shared unit and the lower shared unit in the shared group G may be the same, since the upper shared unit needs to share the selector line 20d with the lower shared unit, when forming the filling hole S1 in the lower memory device layer of the upper shared unit, this filling hole S1 penetrates the first signal line 20a in the lower memory device layer of the upper shared unit and the insulating layer 218 in the lower shared unit to expose the selector line 20d of the lower shared unit. This is necessary to facilitate the subsequent fabrication of the gate layer 202 of the upper shared unit. By making the gate layer 202 of the upper shared unit in contact connection with this selector line 20d, a solution is realized in which two layers of the shared unit GG in the shared group G share the same selector line 20d. Also, for the remaining steps of the upper shared unit, the manufacturing methods of each layer of the lower shared unit in Solution 4 can be referred to, and detailed descriptions are omitted here.

[0121] Here, when there is no shared structure in the adjacent memory device layer 20, as a manufacturing method of the single-layer memory device layer 20, after sequentially forming the first signal line 20a, the first insulating medium layer 204, and the second signal line 20c, a through hole penetrating the second signal line 20c, the first insulating medium layer 204, and the first signal line 20a is formed. An active layer 201 and a gate insulating layer 203 are sequentially formed in this through hole. Then, the gate layer 202 and the selector line 20d are formed. The gate layer 202 and the selector line 20d may be integrally formed or separately formed. It should be understood that the manufacturing method of the single-layer memory device layer 20 is not limited to this as long as the CAA structure of this embodiment can be fabricated.

[0122] In the present disclosure, terms such as "first", "second", "third", "fourth", etc. are merely for the purpose of explanation and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the "first", "second", "third", "fourth" features can include one or more features explicitly or implicitly. In the description of this application, "a plurality" means two or more unless otherwise specified.

[0123] In the description of this specification, the description referring to terms such as "some embodiments", "exemplary", etc. means that the specific features, structures, materials or characteristics described in the embodiments or exemplified are included in at least one embodiment or example of the present application. In this specification, the schematic expressions for the above terms are not necessarily the same embodiments or examples. Also, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Further, as long as they do not conflict with each other, those skilled in the art may combine and combine the different embodiments or examples and the features of different embodiments or examples described in this specification.

[0124] As described above, the embodiments of the present application have been shown and described. However, the above embodiments are exemplary and cannot be understood as limitations on the present application. Those skilled in the art can make changes, modifications, substitutions and deformations to the above embodiments within the scope of the present application. However, any changes or modifications according to the claims and the specification of the present application all belong to the scope of the claims of the present application.

Claims

1. A semiconductor structure including a base and at least one memory device layer, the at least one memory device layer is stacked on the same side of the base along a vertical direction, the memory device layer including at least a first signal line, a transistor, a second signal line, and a selector line, one of the first signal line and the second signal line being a reference voltage line and the other being a read / write line; The gate layer of the transistor is connected to the selector line; an active layer of the transistor extends vertically and is disposed independently of the base, and a bottom end of the active layer is connected to the first signal line; The upper end of the active layer is connected to the second signal line.

1. A semiconductor structure comprising:

2. In the memory device layer, The transistors are arranged in a plurality of pieces and are arrayed in a first horizontal direction and a second horizontal direction, the first horizontal direction and the second horizontal direction intersect with each other, The read / write lines are arranged in a plurality of pieces and are arranged at intervals in a first horizontal direction, the read / write lines extend in a second horizontal direction and are connected to active layers of the plurality of transistors arranged in the second horizontal direction, A plurality of the selector lines are arranged at intervals in a second horizontal direction, the selector lines extend in a first horizontal direction, and are connected to the gate layers of the transistors arranged in the first horizontal direction.

2. The semiconductor structure of claim 1.

3. the transistor includes a core layer, a sleeve layer, and a gate insulating layer; The core layer extends in a vertical direction, the sleeve layer surrounds at least an outer periphery of the core layer, one of the core layer and the sleeve layer being an active layer of the transistor, and the other being a gate layer of the transistor; The gate insulating layer is filled between the gate layer and the active layer.

2. The semiconductor structure of claim 1.

4. the core layer is the active layer, the sleeve layer is the gate layer, The selector line is formed on a side of the second signal line close to the base, a first insulating medium layer is formed between the selector line and the first signal line, a second insulating medium layer is formed between the selector line and the second signal line, and a gate layer of the transistor belongs to a part of the selector line.

4. The semiconductor structure of claim 3.

5. the active layer includes a channel region, a first electrode region, and a second electrode region; the first electrode region is formed between the first signal line and the channel region, a top surface of the first electrode region is higher than a bottom surface of the gate layer, one of the first electrode region and the channel region is an N-type semiconductor and the other is a P-type semiconductor; The second electrode region is formed between the second signal line and the channel region, a bottom surface of the second electrode region is lower than an upper surface of the gate layer, and the second electrode region has the same conductivity type as the first electrode region.

5. The semiconductor structure of claim 4.

6. the first signal line and the second signal line include a layer of semiconductor material; a semiconductor material layer of the first signal line has the same conductivity type as the first electrode region, and the semiconductor material layer of the first signal line is in contact with the first electrode region or is integral with the first electrode region; The semiconductor material layer of the second signal line has the same conductivity type as the second electrode region, and the semiconductor material layer of the second signal line is in contact with the second electrode region or is integral with the second electrode region.

5. The semiconductor structure of claim 4.

7. The memory device layer is multi-layered, and selector lines of any two of the memory device layers are arranged independently of each other, and in at least two adjacent memory device layers, A memory device layer farther from the base is defined as an upper memory device layer, and a memory device layer closer to the base is defined as a lower memory device layer, and at least a part of a second signal line of the lower memory device layer is shared as at least a part of a first signal line of the upper memory device layer.

5. The semiconductor structure of claim 4.

8. the core layer is the gate layer, the sleeve layer is the active layer, The selector line is formed on the top or bottom side of the gate layer.

4. The semiconductor structure of claim 3.

9. The memory device layer is multi-layered, and the multi-layered memory device layer is divided into at least one shared unit along a vertical direction, the shared unit includes two adjacent memory device layers, a memory device layer away from the base of the shared unit is defined as an upper memory device layer, and a memory device layer closer to the base is defined as a lower memory device layer, and in the shared unit, The gate layers of two transistors arranged in the vertical direction share the same selector line, and the second signal line of the upper memory device layer and the first signal line of the lower memory device layer are both the read / write lines and are arranged independently of each other.

9. The semiconductor structure of claim 8.

10. In the shared unit, At least a portion of a second signal line of the lower memory device layer is shared as at least a portion of a first signal line of the upper memory device layer such that a first signal line of the upper memory device layer and a second signal line of the lower memory device layer are used together as a reference voltage line of the shared unit; or A first signal line of the upper memory device layer and a second signal line of the lower memory device layer are arranged independently of each other so as to be used as a reference voltage line of the shared unit.

10. The semiconductor structure of claim 9.

11. In the shared unit, the gate layers of two vertically arranged transistors are directly connected to form a shared gate layer, and the selector line is disposed on the top or bottom side of the shared gate layer; or In the shared unit, the selector line of the upper memory device layer is formed on a bottom end side of a gate layer of the upper memory device layer, and the selector line of the lower memory device layer is formed on an upper end side of a gate layer of the lower memory device layer, and the selector line of the lower memory device layer and the selector line of the upper memory device layer are at least partially shared.

10. The semiconductor structure of claim 9.

12. the shared unit is a plurality of In two adjacent shared units, the read / write lines of one unit are arranged independently of the read / write lines of the other unit.

12. The semiconductor structure of claim 11.

13. In two adjacent shared units, a gate layer of one transistor is arranged to be insulated from a gate layer of the other transistor, in two adjacent shared units, a selector line of one selector line is arranged independently from a selector line of the other, and in two adjacent shared units, adjacent read / write lines share at least a portion.

12. The semiconductor structure of claim 11.

14. In the shared unit, the gate layers of two transistors arranged in a vertical direction are directly connected to form a shared gate layer, and the selector line is disposed on the top or bottom side of the shared gate layer; The memory device layer of multiple layers is divided into at least one shared group along a vertical direction, the shared group includes the shared units of two adjacent layers, the shared unit of the shared group that is farther from the base is defined as an upper layer shared unit, and the shared unit of the shared group that is closer to the base is defined as a lower layer shared unit, the shared units of the two layers in the shared group share the same selector line, the selector line is formed on a bottom end side of the shared gate layer in the upper layer shared unit and on a top end side of the shared gate layer in the lower layer shared unit, and the read / write line of the upper layer shared unit and the read / write line of the lower layer shared unit are arranged independently of each other.

12. The semiconductor structure of claim 11.

15. A plurality of the shared groups are arranged, and in two adjacent shared groups, at least a part of the read / write line in the bottom layer of the shared group farther from the base and the read / write line in the top layer of the shared group closer to the base are arranged in common, and the selector line of the shared group farther from the base and the selector line of the shared group closer to the base are arranged independently of each other.

15. The semiconductor structure of claim 14.

16. the first signal line and the second signal line include a semiconductor material layer, a bottom end of the active layer is in direct contact with the semiconductor material layer of the first signal line, and a top end of the active layer is in direct contact with the semiconductor material layer of the second signal line; the active layer is one of an N-type semiconductor and a P-type semiconductor, the semiconductor material layers of the first signal line and the second signal line are of the same conductivity type and are the other of an N-type semiconductor and a P-type semiconductor, and in an orthogonal projection on the base, the selector line covers at least a portion of an outer boundary of the active layer; When the selector line is formed on the upper end side of the gate layer, a bottom surface of the active layer is higher than a bottom surface of the gate layer, When the selector line is formed on the bottom end side of the gate layer, the upper surface of the active layer is lower than the upper surface of the gate layer.

9. The semiconductor structure of claim 8.

17. the semiconductor material layers in the first signal line and the second signal line and the material of the active layer are polycrystalline semiconductor materials; and / or the first signal line and the second signal line further include a metal conductive material layer and a transition conductive material layer, the transition conductive material layer being formed between the semiconductor material layer and the metal conductive material layer; The material of the transition conductive material layer includes a metal element in the metal conductive material layer and a semiconductor element in the semiconductor material layer.

20. The semiconductor structure of claim 16.

18. 1. A method for making a semiconductor structure, comprising the steps of: Providing a base; forming at least one vertically stacked memory device layer on the base; The method for forming the memory device layer includes: forming a first signal line, a transistor, a second signal line and a selector line on the base, one of the first signal line and the second signal line being a reference voltage line and the other being a read / write line, a gate layer of the transistor being connected to the selector line, an active layer of the transistor extending in a vertical direction and being disposed independently with respect to the base, a bottom end of the active layer being connected to the first signal line, and a top end of the active layer being connected to the second signal line.

1. A method for producing a semiconductor structure comprising:

19. forming a transistor on the base, forming a first insulating medium layer on the base covering at least an upper surface of the first signal line; forming a conductive thin film layer and a second insulating medium layer in sequence on an upper surface of the first insulating medium layer in a vertical direction; forming a fill hole vertically through the second insulating medium layer, the conductive thin film layer, and the first insulating medium layer, the fill hole exposing a portion of the first signal line; forming an annular gate insulating layer on an inner wall of the filling hole, the inner wall of the gate insulating layer forming a through hole that penetrates in a vertical direction, the through hole exposing a portion of the first signal line; forming an active layer in the through hole of the gate insulating layer; patterning the conductive thin film layer to form a plurality of spaced apart selector lines, the selector lines intersecting the extension direction of the read / write lines; The selector lines include at least one gate layer, each of the gate layers being disposed at least partially around the active layer.

20. A method for producing a semiconductor structure according to claim 18.

20. The step of forming an active layer includes the steps of sequentially forming a first electrode region, a channel region, and a second electrode region in the through hole of the gate insulating layer; An upper surface of the first electrode region is higher than a bottom surface of the gate layer, and a bottom surface of the second electrode region is lower than an upper surface of the gate layer. The first electrode region has the same conductivity type as the second electrode region and has a different conductivity type from the channel region.

20. A method for producing a semiconductor structure according to claim 19.

21. the first signal line includes a semiconductor material layer, the semiconductor material layer of the first signal line being exposed at the through hole; The step of forming a first electrode region in the through hole of the gate insulating layer includes: depositing a semiconductor material of the same conductivity type as the semiconductor material layer of the first signal line in the through hole to form the first electrode region; or performing an epitaxial growth process on the semiconductor material layer of the first signal line exposed at the through hole to form the first electrode region.

21. A method for producing a semiconductor structure according to claim 20.

22. The second signal line includes a layer of semiconductor material, the layer of semiconductor material of the second signal line being in direct contact with or integrally formed with the second electrode region of the active layer.

21. A method for producing a semiconductor structure according to claim 20.

23. The second signal line includes the semiconductor material layer, a metal conductive material layer, and a transition conductive material layer disposed between the semiconductor material layer and the metal conductive material layer, which are stacked on the base. When the second signal line is used as a read / write line, the step of forming the second signal line includes: forming a semiconductor thin film layer of the same conductivity type as the semiconductor material layer of the first signal line, the semiconductor thin film layer covering the channel region, the gate insulating layer and the second insulating medium layer; forming a first slit extending in a first horizontal direction and a second slit extending in a second horizontal direction, the first slit penetrating the semiconductor thin film layer, the second insulating medium layer and the conductive thin film layer in order along a vertical direction and located between the filling holes adjacent in the second horizontal direction, the second slit penetrating the semiconductor thin film layer and located between the filling holes adjacent in the first horizontal direction, the conductive thin film layer forming a plurality of the selector lines extending in the first horizontal direction under the action of the first slit, the semiconductor thin film layer forming a plurality of semiconductor portions arranged at intervals in the first horizontal direction and the second horizontal direction under the action of the first slit and the second slit, the semiconductor portions including the second electrode region and a semiconductor material layer of the second signal line, the second electrode region being filled in a through hole, and the semiconductor material layer of the second signal line covering the second electrode region, the gate insulating layer and the second insulating medium layer; forming an insulating fill in the first slit and the second slit, a top surface of the insulating fill being flush with a top surface of the semiconductor portion; A transition conductive material layer of a plurality of second signal lines arranged at intervals in a first horizontal direction and extending in a second horizontal direction is formed, and a metal conductive material layer of a plurality of second signal lines arranged at intervals in the first horizontal direction and extending in a second horizontal direction is formed, in the second signal lines, the metal conductive material layer has a one-to-one correspondence with the transition conductive material layer in a vertical direction, and each of the transition conductive material layers is in contact with an upper surface of a plurality of the semiconductor portions arranged in the second horizontal direction.

23. A method for producing a semiconductor structure according to claim 22.

24. forming a transistor on the base, forming a first insulating medium layer on the base, the first insulating medium layer covering at least a top surface of the first signal line; forming a fill hole vertically through the first insulating medium layer, the fill hole exposing a portion of the first signal line; forming an annular active layer on an inner wall of the filling hole, and forming a through hole that penetrates the inner wall of the annular active layer in a vertical direction, the through hole exposing a portion of the first signal line; forming a groove-shaped gate insulating layer in the through hole, the groove-shaped gate insulating layer covering an inner wall of the annular active layer and a region of the first signal line exposed by the through hole; forming a gate layer in the groove of the grooved gate insulating layer.

20. A method for producing a semiconductor structure according to claim 18.

25. After forming the gate layer and before forming the second signal line, the manufacturing method further includes: forming an isolation insulating portion, the isolation insulating portion completely covering an upper end of the gate layer and exposing at least a portion of an upper surface of the annular active layer; 25. A method for producing a semiconductor structure according to claim 24.

26. The memory device layers of the multiple layers divide at least one shared unit, the shared unit including two adjacent memory device layers, the memory device layer away from the base of the shared unit being defined as an upper memory device layer, and the memory device layer closer to the base being defined as a lower memory device layer; In the shared unit, gate layers of two transistors arranged in a vertical direction are connected to form a shared gate layer, and the same selector line is shared between the gate layers of the upper memory device layer and the lower memory device layer. At least a part of a first signal line of the upper memory device layer and at least a part of a second signal line of the lower memory device layer are arranged in common. The first signal line of the upper memory device layer and the second signal line of the lower memory device layer are shared as a reference voltage line of the shared unit. The second signal line of the upper memory device layer and the first signal line of the lower memory device layer are both read / write lines and are arranged independently of each other. In manufacturing the shared unit, the manufacturing method further comprises: forming a reference voltage line of the shared unit, and then sequentially forming a third insulating medium layer and an upper layer read / write line; forming a first alignment hole penetrating the upper layer read / write line and the third insulating medium layer, the first alignment hole corresponding to the filling hole one-to-one, and exposing a portion of the reference voltage line; forming a groove-shaped active layer on an inner wall of the first alignment hole, the groove-shaped active layer covering the upper read / write line and the hole surface of the third insulating medium layer, and covering an area of ​​the reference voltage line corresponding to the first alignment hole; forming a second alignment hole, the second alignment hole penetrating at least an inner sidewall of the groove-shaped active layer, a groove bottom of the groove-shaped active layer, and the reference voltage line; forming an annular gate insulating layer on an inner wall of the second alignment hole, the inner wall of the annular gate insulating layer being formed as a third alignment hole, the third alignment hole exposing an upper surface of the lower gate layer, and an upper gate layer being formed in the third alignment hole, the upper gate layer contacting an upper surface of the lower gate layer; forming a fourth insulating medium layer covering the groove-shaped active layer and the upper layer read / write line, the fourth insulating medium layer exposing an upper surface of the upper layer gate layer; forming a selector line on an upper surface of the fourth insulating medium layer in contact with an upper surface of the upper gate layer.

26. A method for producing a semiconductor structure according to claim 25.

27. In the shared unit, the active layer is one of an N-type semiconductor and a P-type semiconductor, the upper layer read / write line and the lower layer read / write line each include a semiconductor material layer, and the semiconductor material layers of the upper layer read / write line and the lower layer read / write line each are the other of an N-type semiconductor and a P-type semiconductor; a groove bottom of the groove-shaped gate insulating layer of the lower memory device layer is embedded in the semiconductor material layer of the lower read / write line, an upper surface of the groove bottom of the groove-shaped gate insulating layer is lower than a bottom surface of the active layer of the lower memory device layer, and a bottom surface of the shared gate layer is lower than a bottom surface of the active layer of the lower memory device layer; the selector line in an orthogonal projection of the base covers a boundary of the first alignment hole; The fourth insulating medium layer is located between the selector line and the semiconductor material layer of the upper read / write line, and the fourth insulating medium layer and the annular gate insulating layer are fabricated in the same layer to be a continuous and equal thickness film layer.

27. A method for producing a semiconductor structure according to claim 26.

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