Semiconductor device

Abstract

To further improve the radiation resistance of a solid-state imaging element.SOLUTION: A multiple pixel circuit 10 provided in a semiconductor device 100 include a photodiode PPD, an amplifying transistor Mdrv, a selection transistor Msel, and a reset transistor Mfdr, and the threshold voltages of the reset transistor Mfdr and the selection transistor Msel are 15% or more of the power supply voltages (VRR, VDD) of the reset transistor Mfdr and the selection transistor Msel, respectively.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] The decommissioning work of nuclear facilities includes, for example, work carried out in an environment with a high radiation dose such as fuel debris removal. Work in such an environment is carried out completely remotely while grasping the situation inside the facility by referring to images taken by a radiation-resistant camera attached to, for example, the tip of a robotic arm. Conventionally, an imaging tube with high radiation resistance has been used as the imaging device of the above-mentioned radiation-resistant camera, but the imaging tube is large and has low image quality. For this reason, in recent years, there has been a demand for a radiation-resistant camera equipped with a solid-state imaging device that is small, lightweight, and has high image quality.

[0003] Here, it is known that the characteristics of a solid-state imaging device formed on a semiconductor substrate deteriorate due to the total dose effect of radiation such as gamma rays. For example, in a solid-state imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor, the dark current increases in a photodiode serving as a photosensor due to the ionization action of gamma rays by the total dose effect, resulting in a malfunction due to whiteout. The whiteout due to the total dose effect also causes the shortening of the life of the solid-state imaging device and, by extension, the camera. For example, the cumulative dose, which is an index of the radiation resistance of the imaging tube, is several mega Gy, while the cumulative dose of the solid-state imaging device is several kilo Gy to 100 kilo Gy. In addition, secondary electrons generated by the ionization action of radiation in the semiconductor constituting the photodiode enter the photodiode, resulting in false signals in the captured image and a decrease in the S / N ratio of the image like sandstorm.

[0004] Patent Documents 1 and 2 below disclose solid-state imaging devices with improved radiation resistance. For example, Patent Document 1 below discloses a solid-state imaging device including a photodiode formed on a semiconductor substrate, a semiconductor region formed so as to surround the photodiode, and an overflow transistor formed between the photodiode and the semiconductor region in plan view for discharging the charge accumulated in the photodiode.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] By the way, although the solid-state imaging devices disclosed in Patent Documents 1 and 2 described above have improved radiation resistance, further improvement in radiation resistance is required. By further improving the radiation resistance of the solid-state imaging device, high-quality images can be obtained even in an environment with a higher radiation dose, which is considered to contribute to shortening the time required for the decommissioning of nuclear facilities.

[0007] The present invention has been made in view of the above circumstances, and an object thereof is to further improve the radiation resistance of a solid-state imaging device.

Means for Solving the Problems

[0008] To solve the above problems, a semiconductor device (100) according to a first aspect of the present invention includes a semiconductor substrate (1) and a pixel circuit (10) having a photodiode (PPD) formed on the semiconductor substrate. The pixel circuit includes an amplification transistor (Mdrv) that amplifies a signal corresponding to the charge of the photodiode, a selection transistor (Msel) that switches whether to output the signal amplified by the amplification transistor to a signal line (OUT), and a reset transistor (Mfdr) that discharges the charge accumulated in the photodiode. The threshold voltages of the reset transistor and the selection transistor are each a voltage of 15% or more of the power supply voltages (VRR, VDD) of the reset transistor and the selection transistor.

[0009] Further, a semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect of the present invention, wherein the amplification transistor, the selection transistor, and the reset transistor have a well structure insulated by an element isolation oxide film layer (STI). The impurity concentration in the wells (20) of the reset transistor and the selection transistor is higher than the impurity concentration in the well of the amplification transistor, and the wells of the reset transistor and the selection transistor are formed to have a depth equal to or greater than the depth of the element isolation oxide film layer.

[0010] Further, a semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect of the present invention, wherein the pixel circuit further includes a transfer transistor (Mtg) that transfers the charge of the photodiode and a charge accumulation unit (FD) that accumulates the charge transferred by the transfer transistor. The reset transistor discharges the charge transferred by the transfer transistor by resetting the voltage of the charge accumulation unit.

[0011] Further, a semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect of the present invention, wherein the pixel circuit further includes an overflow transistor (Mpdr) that discharges the charge accumulated in the photodiode.

[0012] Further, in the semiconductor device according to the fifth aspect of the present invention, in the semiconductor device according to the third or fourth aspect of the present invention, the amplification transistor, the selection transistor, the reset transistor, and the transfer transistor are transistors having an SLT structure.

[0013] Further, in the semiconductor device according to the sixth aspect of the present invention, in the semiconductor device according to the fourth aspect of the present invention, the photodiode is composed of a first semiconductor region (2) of a first conductivity type formed on the semiconductor substrate and a second semiconductor region (3) of a second conductivity type formed on the first semiconductor region. The overflow transistor is composed of the second semiconductor region, a third semiconductor region (6, 7) of the second conductivity type formed on the semiconductor substrate so as to be separated from the second semiconductor region so as to surround the photodiode in a plan view, and a gate region (5) formed between the second semiconductor region and the third semiconductor region when viewed from a direction perpendicular to the plane of the semiconductor substrate.

[0014] Further, in the semiconductor device according to the seventh aspect of the present invention, in the semiconductor device according to the sixth aspect of the present invention, the photodiode is formed in a polygonal shape in a plan view, the third semiconductor region is formed in a form surrounding at least other sides of the polygonal photodiode except one side in a plan view, and the gate region is formed between the second semiconductor region and the third semiconductor region so as to surround at least the other sides of the photodiode in a plan view.

[0015] Further, in the semiconductor device according to the eighth aspect of the present invention, in the semiconductor device according to the sixth or seventh aspect of the present invention, a plurality of the pixel circuits are provided, and the plurality of pixel circuits are arranged side by side in a column direction which is a predetermined direction in the plane of the semiconductor substrate and a row direction which is a direction perpendicular to the column direction in a plan view. The pixel circuits adjacent to each other in the row direction have the third semiconductor region common to each other in the row direction.

Advantages of the Invention

[0016] According to the present invention, there is an effect that the radiation resistance of the solid-state imaging device can be further improved.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Embodiments for Carrying Out the Invention

[0018] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals are given to common components, and repeated descriptions are omitted. Also, the drawings are schematic, and it should be noted that the dimensional relationships between elements, the ratios of the elements, etc. may be different from reality. There may also be portions where the dimensional relationships and ratios are different between the drawings. In this specification, as an example, the first conductivity type is described as P-type and the second conductivity type is described as N-type, but it is not limited thereto.

[0019] FIG. 1 is a circuit diagram of a pixel circuit constituting a solid-state imaging device as a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 according to the present embodiment is, for example, a CMOS image sensor as a solid-state imaging device, and is formed on a single semiconductor substrate such as silicon using, for example, a known CMOS LSI manufacturing technology.

[0020] The semiconductor device 100 has a plurality of pixel circuits 10 formed on a semiconductor substrate. The pixel circuit 10 is, for example, a 5-transistor type pixel circuit in which an overflow transistor Mpdr is further added to a 4-transistor type pixel circuit also called APS (Active Pixel Sensor). Specifically, the pixel circuit 10 includes a photodiode PPD, a transfer transistor Mtg, a charge accumulation section FD, a reset transistor Mfdr, an amplification transistor Mdrv, a selection transistor Msel, and an overflow transistor Mpdr.

[0021] The photodiode PPD is, for example, a pinned photodiode as described later. The anode electrode of the photodiode PPD is connected to the ground potential GND, and the cathode electrode is connected to the transfer transistor Mtg.

[0022] The transfer transistor Mtg is an element for transferring the charge of the photodiode PPD. The transfer transistor Mtg is, for example, an MOS transistor of the second conductivity type (N type). The source electrode of the transfer transistor Mtg is connected to the cathode electrode of the photodiode PPD, and the drain electrode is connected to the gate electrode of the amplification transistor Mdrv and the source electrode of the reset transistor Mfdr. A binary signal φTG is input to the gate electrode of the transfer transistor Mtg. The on / off of the transfer transistor Mtg is switched by the signal φTG. That is, the signal φTG is a control signal for controlling the on / off of the transfer transistor Mtg.

[0023] The charge storage section (Floating Diffusion) FD stores the charge transferred by the transfer transistor Mtg. The charge storage section FD is formed at a node to which the drain electrode of the transfer transistor Mtg, the gate electrode of the amplification transistor Mdrv, and the source electrode of the reset transistor Mfdr are commonly connected. The charge storage section FD is realized, for example, by a parasitic capacitance or a floating capacitance existing at the above node.

[0024] The reset transistor Mfdr is a charge discharge element that resets the voltage of the charge storage section FD. The reset transistor (charge discharge transistor) Mfdr is, for example, an MOS transistor of the second conductivity type (N-channel type). The source electrode of the reset transistor Mfdr is connected to the charge storage section FD, and the drain electrode is connected to the power supply voltage VRR. A binary signal φFDR is input to the gate electrode of the reset transistor Mfdr. The on / off of the reset transistor Mfdr is switched by the signal φFDR. That is, the signal φFDR is a control signal that controls the on / off of the reset transistor Mfdr.

[0025] The amplification transistor Mdrv is an element that amplifies a signal corresponding to the charge stored in the charge storage section FD. The amplification transistor Mdrv is, for example, an MOS transistor of the second conductivity type (N-channel type) and constitutes a source follower circuit. The drain electrode of the amplification transistor Mdrv is connected to the power supply voltage VDD, and the gate electrode is connected to the charge storage section FD. The source electrode of the amplification transistor Mdrv is connected to the output signal line OUT via the selection transistor Msel.

[0026] The selection transistor Msel is an element that switches whether to output the signal amplified by the amplification transistor Mdrv to the output signal line OUT. The selection transistor Msel is, for example, a MOS transistor of the second conductivity type (N-channel type). The drain electrode of the selection transistor Msel is connected to the source electrode of the amplification transistor Mdrv, and the source electrode is connected to the output signal line OUT. A signal φSEL is input to the gate electrode of the selection transistor Msel. The on / off state of the selection transistor Msel is switched by the signal φSEL. That is, the signal φSEL is a control signal that controls the on / off state of the selection transistor Msel.

[0027] The overflow transistor Mpdr is an element that discharges the charge accumulated in the photodiode PPD. The overflow transistor Mpdr is, for example, a MOS transistor of the second conductivity type (N-channel type). The overflow transistor Mpdr is connected between the power supply voltage VRR and the cathode electrode of the photodiode PPD. Specifically, the drain electrode of the overflow transistor Mpdr is connected to the power supply voltage VRR, and the source electrode is connected to the cathode electrode of the photodiode PPD. A binary signal φPDR is input to the gate electrode of the overflow transistor Mpdr. The on / off state of the overflow transistor Mpdr is switched by the signal φPDR. That is, the signal φPDR is a control signal that controls the on / off state of the overflow transistor Mpdr.

[0028] Here, the power supply voltage VDD is the power supply for the source follower circuit (amplification transistor Mdrv), and the power supply voltage VRR is the power supply for resetting the charge storage unit FD and the photodiode PPD. By separating the power supply voltage VDD and the power supply voltage VRR, it becomes possible to optimize the operating conditions of the pixel. Note that the power supply voltage for resetting the charge storage unit FD and the power supply voltage for resetting the photodiode PPD may be separated. In addition, in this embodiment, the case where the power supply voltage VDD and the power supply voltage VRR are separated is illustrated, but the present invention is not limited to this, and the power supply voltage VDD and the power supply voltage VRR may be made common.

[0029] The photodiode PPD accumulates charges in response to the received optical signal. The transfer transistor Mtg turns on when the signal φTG is in the enabled state and transfers the charges accumulated by the photodiode PPD to the charge accumulation section FD. The amplification transistor Mdrv amplifies the signal corresponding to the charges stored in the charge accumulation section FD and outputs it to the node N1. The selection transistor Msel turns on when the signal φSEL is in the enabled state and outputs the signal of the node N1 to the output signal line OUT. The reset transistor Mfdr turns on when the signal φFDR is in the enabled state and connects the power supply voltage VRR and the charge accumulation section FD. Thereby, the electrons accumulated in the charge accumulation section FD are discharged to the power supply voltage VRR, and the charge accumulation section FD is reset.

[0030] The overflow transistor Mpdr turns on when the signal φPDR is in the enabled state and connects the power supply voltage VRR higher than the depletion voltage of the photodiode and the cathode electrode of the photodiode PPD in which charges are accumulated. Thereby, the electrons accumulated in the photodiode PPD are discharged to the power supply voltage VRR, and the photodiode PPD is reset. In this way, the overflow transistor Mpdr can function as an electron shutter of the photodiode PPD.

[0031] FIG. 2A is a plan view showing a layout configuration of a pixel circuit of a semiconductor device according to an embodiment of the present invention. FIG. 2B is a cross-sectional view taken along the line B-B′ of the pixel circuit shown in FIG. 2A. In FIGS. 2A and 2B, the positional relationship of each member will be described while referring to the XYZ orthogonal coordinate system set in the figure as needed. This XYZ orthogonal coordinate system is set such that the XY plane is parallel to the plane of the semiconductor substrate 1, and the X axis is parallel to the line B-B′. However, for convenience of explanation, the origin of the XYZ orthogonal coordinate system shown in each figure is not fixed, and its position is appropriately changed for each figure.

[0032] FIG. 2A shows the layout configuration of the pixel circuit 10 as viewed from a direction perpendicular to the plane (XY plane) of the semiconductor substrate 1 constituting the semiconductor device 100. In FIGS. 2A and 2B, the display of the uppermost wiring layer among the wiring layers connecting circuit elements is omitted.

[0033] The semiconductor substrate 1 is, for example, a P-type substrate doped with B (boron) in silicon. A P-well 2 as a first semiconductor region of the first conductivity type (P-type) is formed in this semiconductor substrate 1. The P-well 2 is formed by doping the P-type substrate 1 with a low concentration of P-type impurities.

[0034] An N-well 3 as a second semiconductor region of the second conductivity type (N-type) is formed on the P-well 2. A PN junction type photodiode is formed by the P-well 2 and the N-well 3.

[0035] In the present embodiment, further, a pinning layer 4 as a P-type semiconductor layer (P+ region) having a higher P-type impurity concentration than the P-well 2 is formed on the N-well 3. The pinning layer 4 is formed, for example, by doping the surface of the P-type substrate 1 with P-type impurities. By forming the pinning layer 4, the photodiode becomes an embedded type photodiode PPD. In the present embodiment, the embedded type photodiode PPD is simply also referred to as the "photodiode PPD". Note that the pinning layer 6 and the P-well 2 are grounded by a contact portion 9. The contact portion 9 has a higher P-type impurity concentration (P++) than the pinning layer 4 in order to make an ohmic contact with the metal.

[0036] As shown in FIG. 2A, in a plan view as viewed from a direction perpendicular to the plane of the semiconductor substrate 1 (the positive side of the Z axis), an N-well 6 and an N-type diffusion region 7 as a third semiconductor region of the second conductivity type (N-type) are formed separated from the N-well 3 so as to surround the photodiode PPD.

[0037] More specifically, the photodiode PPD is formed, for example, in a polygonal shape in plan view. Here, the polygonal shape refers to a shape having three or more corners, and examples thereof include a triangular shape, a rectangular shape (square shape), a pentagonal shape, a hexagonal shape, and the like. In the present embodiment, as an example, the photodiode PPD is described as being formed in a rectangular shape, but it is not limited thereto.

[0038] The N-well 6 is formed in a form that at least surrounds the sides of the polygonal photodiode PPD other than one side in plan view. For example, when the photodiode PPD is rectangular, the N-well 6 is formed in a form that surrounds at least three of the four sides of the photodiode PPD.

[0039] An N-type diffusion region (N++ region) 7 having an N-type impurity concentration higher than that of the N-well 6 is formed on the N-well 6 so as to overlap the N-well 6 in plan view. Here, the N-well 6 and the N-type diffusion region 7 extend, for example, in contact with a pixel boundary line A that defines the region of one pixel circuit 10.

[0040] Note that in the present embodiment, the case where the N-well 6 and the N-type diffusion region 7 are formed as the third semiconductor region is exemplified, but it is not limited thereto, and at least the N-type diffusion region 7 may be formed as the third semiconductor region.

[0041] Furthermore, in plan view, a gate region 5 is formed on the P-well 2 between the N-well 3 as the second semiconductor region and the N-well 6 and the N-type diffusion region 7 as the third semiconductor region. The gate region 5 is, for example, a gate portion of a MOS (Metal Oxide Semiconductor) structure formed of a gate oxide film (for example, SiO2) and an electrode (for example, polysilicon, etc.) formed on the gate oxide film. Specifically, the gate region 5 is formed between the N-well 3 and the N-well 6 in a form that at least surrounds three sides of the N-well 3 of the photodiode PPD in plan view.

[0042] Here, an overflow transistor Mpdr is configured with N-well 3 as the source electrode, N-well 6 and N-type diffusion region 7 as the drain electrodes, and gate region 5 as the gate electrode.

[0043] As shown in FIG. 2A, in a plan view, circuit elements constituting a pixel circuit 10 other than the overflow transistor Mpdr are formed in a region on one side (a side other than the three sides) of the rectangular photodiode PPD. That is, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplification transistor Mdrv, and a selection transistor Msel are formed in a region on one side of the photodiode PPD on the negative Y-axis side.

[0044] Furthermore, as shown in FIG. 2B, a PMD (PMD: Pre Metal Dielectric) 8, which is a transparent insulating film such as SiO2, is formed on the surface of the semiconductor substrate 1, for example, by a CVD (Chemical Vapor Deposition) method.

[0045] As described above, the pixel circuit 10 in the semiconductor device 100 according to the present embodiment has a structure in which the transfer transistor Mtg connected to the photodiode PPD and the overflow transistor Mpdr surrounds the periphery of the photodiode PPD except for the contact portion (P++) for connecting the pinning layer 4 to the ground potential. As a result, an element isolation oxide film layer (STI) is not formed in the X-axis direction of the pixel boundary line A and in the positive Y-axis direction of the pixel boundary line A.

[0046] FIG. 3A is a plan view schematically showing the configuration of transistors other than the overflow transistor provided in the pixel circuit of the semiconductor device according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line A-A' of the transistor shown in FIG. 3A.

[0047] Transistors other than the overflow transistor Mpdr (transfer transistor Mtg, reset transistor Mfdr, amplification transistor Mdrv, and selection transistor Msel) are, as described above, for example, MOS transistors of the second conductivity type (N-channel type). Therefore, as shown in FIG. 3A, a gate region 11 is formed on the P well 20, and a source region 12 and a drain region 13 are formed so as to sandwich the gate region 11 in plan view.

[0048] As shown in FIG. 3B, the gate region 11 is, for example, a gate portion of a MOS (Metal Oxide Semiconductor) structure formed from a gate oxide film 21 (e.g., SiO2) and an electrode 122 (e.g., polysilicon, etc.) formed on the gate oxide film. The gate oxide film 21 has a thickness of, for example, about 5 to 10 nm. When the thickness of the gate oxide film 21 is of this order, charge-up in the gate oxide film 21 is less likely to occur, and leakage current is less likely to occur compared to the case where the gate oxide film is thick.

[0049] On the other hand, the thickness of the element isolation oxide film layer (STI) is, for example, about 400 nm, which is extremely large compared to the thickness of the gate oxide film 21. Therefore, among the electron-hole pairs generated by the ionization action due to the total dose effect of gamma rays, electrons are swept to the nearby electrodes because the mobility in the element isolation oxide film layer (STI) is relatively high, while holes have low mobility and are trapped by the charge traps in the element isolation oxide film layer (STI) to become fixed positive charges. As a result, the Si (P-) near the element isolation oxide film layer (STI) is inverted to N-type to form a channel, and the leakage current indicated by the arrow in FIG. 3A increases.

[0050] In this embodiment, in order to suppress the leakage current caused by the total dose effect of such radiation, among the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel, the reset transistor Mfdr and the selection transistor Msel are enhancement-type transistors with a threshold voltage VT higher than that of the other transistors. Specifically, the threshold voltage VT of the reset transistor Mfdr and the selection transistor Msel is set to a voltage of 15% or more of the power supply voltage of the reset transistor Mfdr and the selection transistor Msel.

[0051] That is, for the reset transistor Mfdr, the threshold voltage VT is a voltage of 15% or more of the power supply voltage VRR, and for the selection transistor Msel, the threshold voltage VT is a voltage of 15% or more of the power supply voltage VDD. For example, assuming that the power supply voltage VDD is 3.3V, the threshold voltage VT of the selection transistor Msel is about 0.5V or more.

[0052] Note that the threshold voltage VT of the reset transistor Mfdr and the selection transistor Msel can be set to any voltage (for example, 20%, 25%, etc. of the power supply voltage) as long as it is 15% or more of the power supply voltage. However, since the dynamic range decreases as the threshold voltage VT of the reset transistor Mfdr and the selection transistor Msel is increased, it is desirable to set an appropriate voltage in consideration of the leakage current and the dynamic range.

[0053] The concentration of P-type impurities in the P-well 20 (see FIG. 3B) of the reset transistor Mfdr and the selection transistor Msel is increased compared to the concentration of P-type impurities in the P-well 20 (see FIG. 3B) of the transfer transistor Mtg and the amplification transistor Mdrv, for example, by p-type ion implantation or the like. Also, by setting the P-well concentration to increase such a threshold voltage VT, generation of an N-type inversion layer due to the total dose effect at the interface between the element isolation oxide film layer (STI) and Si(p-) can be suppressed, and the leakage current can be suppressed. Further, the p-well with this increased concentration is formed to have a depth equal to or greater than the depth of the element isolation oxide film layer (STI). Thereby, the threshold voltage VT of the reset transistor Mfdr and the selection transistor Msel is higher than the threshold voltage VT of the transfer transistor Mtg and the amplification transistor Mdrv.

[0054] Here, when the leakage current of the reset transistor Mfdr increases, the charge accumulated in the charge storage unit FD is discharged. Also, when the leakage current of the selection transistor Msel increases, the signal amplified by the amplification transistor Mdrv is output to the output signal line OUT at an unintended timing. For this reason, the threshold voltage VT of the reset transistor Mfdr and the selection transistor Msel is increased to suppress the leakage current. Although it is ideal that the transfer transistor Mtg and the amplification transistor Mdrv do not generate a leakage current, even if a somewhat leakage current occurs, it does not cause much of a problem.

[0055] FIG. 4A is a plan view showing an arrangement example of pixel circuits in a semiconductor device according to an embodiment of the present invention. FIG. 4B is a cross-sectional view taken along the line C-C' of the semiconductor device in FIG. 4A. In FIGS. 4A and 4B, as in FIGS. 2A and 2B, the positional relationship of each member will be described while referring to the XYZ orthogonal coordinate system set in the figure as necessary. Note that in FIGS. 4A and 4B, the display of the uppermost wiring layer among the wiring layers connecting circuit elements to each other is omitted. In the plane of the semiconductor substrate 1 shown in FIG. 4A, the Y-axis direction, which is a predetermined direction, is the column direction, and the X-axis direction is the row direction.

[0056] As shown in FIG. 4A, in the semiconductor device 100, a plurality of pixel circuits 10 are formed side by side in the row direction and the column direction on a semiconductor substrate. Specifically, for example, when the uppermost row on the positive Y-axis side in FIG. 4A is defined as the first row, in the pixel circuits 10 of the odd-numbered rows, the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel are arranged on one side in the column direction (the positive side in the Y-axis direction). Further, in the pixel circuits 10 of the even-numbered rows, the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel are arranged on the other side in the column direction (the negative side in the Y-axis direction).

[0057] Overflow transistors Mpdr of pixel circuits 10 adjacent to each other in the row direction (X-axis direction) have drain electrodes (N-well 6 and N-type diffusion region 7 as the third semiconductor region) that are common to each other in the row direction.

[0058] Here, as shown in FIG. 4A, it is preferable to adjust the ranges of the N-well 6 and the N-type diffusion region 7 in the row direction so that the distances between adjacent photodiodes PPDs in the row direction (X-axis direction) are equal. Thereby, the resolution of the pixels in the horizontal direction can be made uniform.

[0059] Further, as shown in FIG. 4B, in two pixel circuits 10 in which overflow transistors Mpdr are adjacent to each other in the column direction (Y-axis direction), they have a third semiconductor region (N-well 6 and N-type diffusion region 7) that is common to each other in the column direction. For example, between the pixel circuit 10 in the first row and the pixel circuit in the second row, the drain electrodes of the overflow transistors Mpdr are common in the Y-axis direction, and between the pixel circuit 10 in the third row and the pixel circuit in the fourth row, the drain electrodes of the overflow transistors Mpdr are common in the Y-axis direction.

[0060] By arranging a plurality of pixel circuits 10 as shown in Fig. 4A, among the four sides of the photodiode PPD formed in a rectangular shape of each pixel circuit 10, in the regions around the three sides other than the side where the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel are formed, the N-well 6 and the N-type diffusion region 7 serving as the drain electrodes of the overflow transistor Mpdr of each pixel circuit 10 are common. That is, in the regions on the three sides of the four sides of the photodiode PPD, an element isolation oxide film layer such as STI is not formed.

[0061] As described above, in this embodiment, among the four transistors other than the overflow transistor Mpdr provided in the pixel circuit 10, the reset transistor Mfdr and the selection transistor Msel are of enhancement type to increase the threshold voltage VT. Specifically, the threshold voltage VT of the reset transistor Mfdr and the selection transistor Msel is set to a voltage of 15% or more of the power supply voltage of the reset transistor Mfdr and the selection transistor Msel. Therefore, the leakage current of the reset transistor Mfdr and the selection transistor Msel can be suppressed, and the radiation resistance of the solid-state imaging device as the semiconductor device 100 can be further improved.

[0062] Here, if the transistor used in the solid-state imaging device has an ELT (Enclosed Layout Transistor) structure, it is possible to improve the radiation resistance of the solid-state imaging device. The ELT structure is, for example, a structure in which the drain (or source) of a MOS transistor is surrounded by a gate electrode, and the edge of the element isolation oxide film layer (STI) and the diffusion layer region of the drain (source) are separated.

[0063] However, if the transistor used in the solid-state imaging device has an ELT structure, the layout of the gate electrode becomes large, resulting in an increase in the layout area of the transistor. As a result, the area of the photodiode PPD is reduced. Also, if the amplification transistor Mdrv has an ELT structure, an increase in the gate capacitance leads to a decrease in the conversion gain (charge-voltage conversion efficiency) of the charge storage section FD. As a result, demerits such as a decrease in sensitivity occur.

[0064] In contrast, in this embodiment, a transistor having a normal SLT (Stripe Layout Transistor) structure is used as the transistor of the solid-state imaging device. Among the four transistors other than the overflow transistor Mpdr provided in the pixel circuit 10, the reset transistor Mfdr and the selection transistor Msel are of the enhancement type to increase the threshold voltage VT. As a result, the radiation resistance of the solid-state imaging device as the semiconductor device 100 can be further improved without causing demerits such as a decrease in sensitivity.

[0065] As described above, a semiconductor device according to an embodiment of the present invention has been described. However, the present invention is not limited to the above embodiment and can be freely changed within the scope of the present invention. For example, in the above embodiment, an example in which the first conductivity type is P-type and the second conductivity type is N-type has been described. However, each transistor may be formed with the first conductivity type being N-type and the second conductivity type being P-type. However, such a transistor becomes a P-type MOS transistor. In a P-type MOS transistor, the threshold voltage VT increases due to the total dose effect, so there is no merit in increasing the concentration of the first conductivity type (N-type).

[0066] In addition, in the above-described embodiment, an example was given in which the pixel circuit 10 is a 5-transistor type pixel circuit in which an overflow transistor Mpdr is further added to a 4-transistor type pixel circuit also called an APS (Active Pixel Sensor). However, the pixel circuit 10 may be a 4-transistor type pixel circuit (a circuit including a transfer transistor Mtg, a reset transistor Mfdr, an amplification transistor Mdrv, and a selection transistor Msel). Alternatively, the pixel circuit 10 may be a 3-transistor type pixel circuit in which the transfer transistor and the charge accumulation part FD in the 4-transistor type pixel circuit are omitted, and the cathode of the photodiode is directly connected to the gate of the amplification transistor Mdrv and the source of the reset transistor Mfdr. This 3-transistor type pixel circuit includes an amplification transistor Mdrv, a selection transistor Msel, and a reset transistor Mfdr, and the reset transistor Mfdr is used to discharge the charge accumulated in the photodiode.

Explanation of Reference Numerals

[0067] 1…Semiconductor substrate, 2…P well, 3…N well, 5…Gate region, 6…N well, 7…N-type diffusion region, 10…Pixel circuit, 100…Semiconductor device, FD…Charge accumulation part, Mdrv…Amplification transistor, Mfdr…Reset transistor, Mpdr…Overflow transistor, Msel…Selection transistor, Mtg…Transfer transistor, OUT…Output signal line, PPD…Photodiode, VDD…Power supply voltage, VRR…Power supply voltage.

Claims

1. A semiconductor substrate, a pixel circuit having a photodiode formed on the semiconductor substrate, and comprising, the pixel circuit includes, an amplification transistor that amplifies a signal corresponding to the charge of the photodiode, a selection transistor that switches whether to output the signal amplified by the amplification transistor to a signal line, a reset transistor that discharges the charge accumulated in the photodiode, and has, the threshold voltages of the reset transistor and the selection transistor are each a voltage of 15% or more of the power supply voltages of the reset transistor and the selection transistor, a semiconductor device.

2. the amplification transistor, the selection transistor, and the reset transistor have a well structure insulated by an element isolation oxide film layer, the impurity concentrations in the wells of the reset transistor and the selection transistor are higher than the impurity concentration in the well of the amplification transistor, the wells of the reset transistor and the selection transistor are formed to have a depth equal to or greater than the depth of the element isolation oxide film layer, the semiconductor device according to claim 1.

3. the pixel circuit includes, a transfer transistor that transfers the charge of the photodiode, a charge accumulation unit that accumulates the charge transferred by the transfer transistor, and further comprises, the reset transistor discharges the charge transferred by the transfer transistor by resetting the voltage of the charge accumulation unit, the semiconductor device according to claim 1 or claim 2.

4. The pixel circuit further includes an overflow transistor that discharges the charge stored in the photodiode, the semiconductor device according to claim 3.

5. The amplification transistor, the selection transistor, the reset transistor, and the transfer transistor are transistors of an SLT structure, the semiconductor device according to claim 3.

6. The photodiode is composed of a first semiconductor region of a first conductivity type formed in the semiconductor substrate and a second semiconductor region of a second conductivity type formed on the first semiconductor region. The overflow transistor is composed of the second semiconductor region, a third semiconductor region of the second conductivity type formed in the semiconductor substrate and separated from the second semiconductor region so as to surround the photodiode in a plan view, and a gate region formed between the second semiconductor region and the third semiconductor region when viewed from a direction perpendicular to the plane of the semiconductor substrate. The semiconductor device according to claim 4.

7. The photodiode is formed in a polygonal shape in a plan view. The third semiconductor region is formed in a form that surrounds at least the other sides of the polygonal photodiode excluding one side in a plan view. The gate region is formed between the second semiconductor region and the third semiconductor region in a form that surrounds at least the other sides of the photodiode in a plan view. The semiconductor device according to claim 6.

8. Having a plurality of the pixel circuits. The plurality of pixel circuits are respectively arranged side by side in a column direction which is a predetermined direction in the plane of the semiconductor substrate and a row direction which is a direction perpendicular to the column direction in a plan view. The pixel circuits adjacent to each other in the row direction have the third semiconductor region common to each other in the row direction. The semiconductor device according to claim 6.

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