Light-emitting device

Abstract

To suppress variations in luminescence of light-emitting elements due to variations in threshold voltages of transistors, and suppress degradation in luminescence of the light-emitting element due to degradation of an electroluminescent layer.SOLUTION: A light-emitting device includes a light-emitting element, a first transistor having a source electrically connected to an anode of the light-emitting element, a second transistor that controls whether an image signal is inputted to a gate of the first transistor, a third transistor that controls whether the gate of the first transistor is electrically connected to a drain thereof, a fourth transistor that controls whether a first power-supply potential is supplied to the drain of the first transistor, a fifth transistor that controls whether a second power-supply potential is supplied to the anode of the light-emitting element, a first capacitor that retains voltage across the gate of the first transistor and the source thereof, and a second capacitor that is electrically connected to the first capacitor in series and electrically connected to the light-emitting element in series.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a light-emitting device in which a transistor is provided for each pixel. [Background technology]

[0002] Display devices using light-emitting elements have high visibility and are ideal for making them thin, but they also have no limitations on the viewing angle. Since there is no LCD, it is used as an alternative to CRT (Cathode Ray Tube) and LCD displays. Active matrix display devices using light-emitting elements are attracting attention. The specific configurations proposed vary by manufacturer, but usually include at least a light emitting element and A transistor (switching transistor) that controls the input of a video signal to the pixel; A transistor (drive transistor) that controls the current value supplied to the light emitting element is provided for each pixel. It is provided in the base.

[0003] By making all the transistors in the pixel have the same polarity, In the above, a process of adding an impurity element that gives one conductivity to the semiconductor layer is partially omitted. In the following Patent Document 1, a pixel is composed of only n-channel transistors. A light-emitting device display having a light-emitting element is described. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-195810 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, in a light-emitting device, since the drain current of the driving transistor is supplied to the light-emitting element, if there is a variation in the threshold voltage of the driving transistor between pixels, the variation will be reflected in the luminance of the light-emitting element. Therefore, a proposal for a pixel configuration capable of correcting the current value of the driving transistor in anticipation of the variation in the threshold voltage is an important issue in improving the image quality of the light-emitting device. Also, generally, the conductive film used as the anode of the light-emitting element is less likely to have its surface oxidized in the atmosphere than the conductive film used as the cathode of the light-emitting element. In addition, since the conductive film used as the anode of the light-emitting element is usually formed by sputtering, when an anode is formed on an electroluminescent layer containing an electroluminescent material, the electroluminescent layer is likely to be damaged by sputter damage. Therefore, a light-emitting element having a structure in which an anode, an electroluminescent layer, and a cathode are laminated in this order has a simple manufacturing process and is likely to obtain high luminous efficiency. However, when an n-channel type driving transistor is combined with the light-emitting element having the above structure, the source of the driving transistor is connected to the anode of the light-emitting element. Therefore, as the electroluminescent material deteriorates and the voltage between the anode and the cathode of the light-emitting element increases, the potential of the source in the driving transistor rises, and the voltage between the gate and the source (gate voltage) decreases. For this reason, the drain current of the driving transistor, that is, the current supplied to the light-emitting element decreases, and the luminance of the light-emitting element decreases. In view of the above problems, one of the problems of the present invention is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. Alternatively, the present invention is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. is an important issue in improving the image quality of the light-emitting device.

[0006] Also, generally, the conductive film used as the anode of the light-emitting element is less likely to have its surface oxidized in the atmosphere than the conductive film used as the cathode of the light-emitting element. Moreover, the conductive film used as the anode of the light-emitting element is usually formed by sputtering. Therefore, when an anode is formed on an electroluminescent layer containing an electroluminescent material, the electroluminescent layer is likely to be damaged by sputter damage. Thus, a light-emitting element having a structure in which an anode, an electroluminescent layer, and a cathode are laminated in this order has a simple manufacturing process and is likely to obtain high luminous efficiency. However, when an n-channel type driving transistor is combined with the light-emitting element having the above structure, the source of the driving transistor is connected to the anode of the light-emitting element. Therefore, as the electroluminescent material deteriorates and the voltage between the anode and the cathode of the light-emitting element increases, the potential of the source in the driving transistor rises, and the voltage between the gate and the source (gate voltage) decreases. As a result, the drain current of the driving transistor, that is, the current supplied to the light-emitting element decreases, and the luminance of the light-emitting element decreases. In view of the above problems, one of the problems of the present invention is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. Alternatively, the present invention is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. For this reason, the drain current of the driving transistor, that is, the current supplied to the light-emitting element decreases, and the luminance of the light-emitting element decreases. In view of the above problems, one of the problems of the present invention is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed.

[0007] In view of the above problems, one of the problems of the present invention is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. Providing a light-emitting device capable of suppressing a decrease in the luminance of a light-emitting element due to deterioration of an electroluminescent layer is one of the problems.

Means for Solving the Problems

[0008] In one aspect of the present invention, in order to solve the above problems, a first capacitor element that holds a voltage between the gate and the source of a driving transistor, and a second capacitor element that is connected in series to the first capacitor element and is also connected in series to a light-emitting element are provided in a pixel. Further, the capacitance value of the first capacitor element is configured to be smaller than the capacitance value of a combined capacitance composed of the light-emitting element and the second capacitor element. In the above pixel, with the gate and the drain of the driving transistor connected, a voltage greater than the threshold voltage is applied between the gate and the source of the driving transistor. Next, while keeping the gate and the drain connected, the source is set to a floating state, whereby the threshold voltage of the driving transistor is held in the first capacitor element. Then, while keeping the source in a floating state, when a voltage of an image signal is applied to the gate, a voltage obtained by adding the threshold voltage to the voltage of the image signal is applied between the gate and the source of the driving transistor. The light-emitting element is supplied with a current corresponding to the gate voltage of the driving transistor and performs grayscale display. and connected in series to the light-emitting element, are provided in the pixel. Also, the capacitance value of the first capacitor element is smaller than the capacitance value of the combined capacitance composed of the light-emitting element and the second capacitor element. In the above pixel, with the gate and the drain of the driving transistor connected a voltage greater than the threshold voltage is applied between the gate and the source of the driving transistor. Next, while keeping the gate and the drain connected, the source is set to a floating state, whereby the threshold voltage of the driving transistor is held in the first capacitor element. Then, while keeping the source in a floating state, when a voltage of an image signal is applied to the gate, a voltage obtained by adding the threshold voltage to the voltage of the image signal is applied between the gate and the source of the driving transistor. The light-emitting element is supplied with a current corresponding to the gate voltage of the driving transistor and performs grayscale display. is held in the first capacitor element. And, while keeping the source in a floating state, when a voltage of an image signal is applied to the gate, a voltage obtained by adding the threshold voltage to the voltage of the image signal is applied between the gate and the source of the driving transistor. The light-emitting element is supplied with a current corresponding to the gate voltage of the driving transistor and performs grayscale display. is applied between the gate and the source of the driving transistor. The light-emitting element is supplied with a current corresponding to the gate voltage of the driving transistor and performs grayscale display. is supplied and grayscale display is performed.

[0009] In one aspect of the present invention, with the above configuration, even if the threshold voltage of the driving transistor shifts, its gate voltage can be determined according to the magnitude of the threshold voltage. Also, in one aspect of the present invention, with the above configuration, even if the voltage between the anode and the cathode of the light-emitting element increases due to deterioration of the electroluminescent material, no change occurs in the gate voltage of the driving transistor. Also, in one aspect of the present invention, with the above configuration, even if the voltage between the anode and the cathode of the light-emitting element increases due to deterioration of the electroluminescent material, no change occurs in the gate voltage of the driving transistor. In one aspect of the present invention, with the above configuration, even if the voltage between the anode and the cathode of the light-emitting element increases due to deterioration of the electroluminescent material, no change occurs in the gate voltage of the driving transistor. occurs in the gate voltage of the driving transistor. ​

[0010] Specifically, a light emitting device according to one aspect of the present invention includes a light emitting element and a source that is an anode of the light emitting element. a first transistor electrically connected to the first transistor and configured to control a current flowing through the light emitting element; a second transistor for controlling whether or not an image signal is input to the gate of the first transistor; A third transistor that controls whether the gate and drain of the first transistor are electrically connected to each other. a second transistor for controlling whether or not a first power supply potential is supplied to the drain of the first transistor; The transistor 4 controls whether or not to supply a second power supply potential to the anode of the light-emitting element. a fifth transistor and a first transistor for holding a voltage between the gate and the source of the first transistor; The first capacitance element is electrically connected in series to the first capacitance element, and the second capacitance element is electrically connected in series to the light emitting element. and a second capacitance element electrically connected to the first transistor to the fifth transistor. Each of the transistors is a light-emitting device that is an n-channel transistor.

[0011] In the light-emitting device according to an embodiment of the present invention, a second electrode is connected to the drain of the second transistor. A sixth transistor may be provided to control whether or not the source potential is supplied.

[0012] In the light-emitting device according to the above embodiment of the present invention, the first to sixth transistors In the transistor, a channel formation region provided between a source and a drain is made of an oxide semiconductor. Alternatively, it may be single crystal silicon. Effect of the Invention

[0013] In one embodiment of the present invention, the above-described structure prevents a variation in threshold voltage of a driving transistor. The variation in luminance between pixels is suppressed. This can suppress a decrease in the luminance of the light-emitting element.

Brief Description of the Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0016] (Embodiment 1) The light-emitting device in this embodiment includes a pixel portion. Further, an example of the pixel portion in the light-emitting device of this embodiment will be described with reference to FIG. 1.

[0017] As shown in FIG. 1(A), the pixel portion includes a signal line S1, a power supply line VA, a power supply line VB, a power supply line VC, a scanning line G1, a scanning line G2, a scanning line G3, a scanning line G4, and a light-emitting element 101 and a transistor 102, a transistor 103, a transistor 104, transistors 105, a transistor 106, a capacitor element 107, a capacitor element 108, and a transistor 109.

[0018] In the light-emitting device shown in FIG. 1(A), the transistor is a field-effect transistor. Also, in the above transistor, depending on the structure, operating conditions, etc., the source and the drain may be interchanged with each other.

[0019] For example, a circuit including a light-emitting element 101, a transistor 102, a transistor 103, a transistor 10 4, a transistor 105, a transistor 106, a capacitor element 107, a capacitor element 108, and a transistor 109 may be regarded as one pixel circuit, and one pixel may be constituted by one pixel circuit. The above pixel circuits are provided in a plurality in the matrix direction in the pixel portion. Also, one pixel may be constituted by two or more of the above pixel circuits. In that case, the pixel circuits in one pixel are also referred to as sub-pixels.

[0020] The light-emitting element 101 has an anode and a cathode, and emits light with a luminance corresponding to the amount of current flowing between the anode and the cathode. Therefore, gradation display can be performed by the light-emitting element 101.

[0021] As the light-emitting element 101, for example, an electroluminescence element or a light-emitting diode can be used. For example, the structure of the light-emitting element 101 can be a structure including an electroluminescent layer containing an electroluminescent material between a conductive film used as an anode and a conductive film used as a cathode.

[0022] The source of transistor 102 is electrically connected to the anode of light-emitting element 101. The transistor 102 functions as a driving transistor that controls the current flowing through light-emitting element 101.

[0023] One of the source and drain of transistor 103 is electrically connected to signal line S1, and the other of the source and drain of transistor 103 is electrically connected to the gate of transistor 102. Signal line S1 is a wiring to which an image signal (video signal) is supplied. Also, in FIG. 1(A), the gate of transistor 103 is electrically connected to scanning line G1. Scanning line G1 is a wiring to which scanning signal SCN1 is supplied, and transistor 103 becomes on or off according to scanning signal SCN1. Transistor 103 functions as a switching transistor that controls whether or not to input an image signal to the gate of transistor 102.

[0024] One of the source and drain of transistor 104 is electrically connected to the drain of transistor 102, and the other of the source and drain of transistor 104 is electrically connected to the gate of transistor 102. Also, in FIG. 1(A), the gate of transistor 104 is electrically connected to scanning line G2. Scanning line G2 is a wiring to which scanning signal SCN2 is supplied, and transistor 104 becomes on or off according to scanning signal SCN2. Transistor 104 has a function of controlling whether or not to electrically connect the gate and drain of transistor 102.

[0025] One of the source and drain of transistor 105 is electrically connected to power supply line VA, and the ​​​​​​​​​​​​​The other of the source and drain of transistor 105 is electrically connected to the drain of transistor 102. The power supply line VA is a wiring to which the power supply potential V1 is supplied, and the power supply potential V1 is a potential higher than the reference potential (for example, the ground potential). Also, in FIG. 1(A), the gate of transistor 105 is electrically connected to the scanning line G3. The scanning line G3 is a wiring to which the scanning signal S CN3 is supplied, and transistor 105 becomes on or off according to the scanning signal SCN3. Transistor 105 has a function of controlling whether to supply the power supply potential V1 to the drain of transistor 102.

[0026] One of the source and drain of transistor 106 is electrically connected to the power supply line VB, and the other of the source and drain of transistor 106 is electrically connected to the anode of the light emitting element 101. The power supply line VB is a wiring to which the power supply potential V2 is supplied, and the power supply potential V2 is a potential lower than the reference potential. Also, in FIG. 1(A), the gate of transistor 106 is electrically connected to the scanning line G4. The scanning line G4 is a wiring to which the scanning signal SCN4 is supplied, and transistor 106 becomes on or off according to the scanning signal SCN4. Transistor 106 has a function of controlling whether to supply the power supply potential V2 to the anode of the light emitting element 101. Also, by setting the voltage of the cathode of the light emitting element 101 to a potential higher than the power supply potential V2, for example, during the initialization period, the amount of current flowing through the light emitting element 101 can be reduced. One of the pair of electrodes of the capacitor element 107 is electrically connected to the gate of transistor 102, and the other of the pair of electrodes of the capacitor element 107 is electrically connected to the source of transistor 102

[0027] ​ It can be achieved. The capacitive element 107 has a function of holding the voltage between the gate and the source of the transistor 102. It has the function.

[0028] One of the pair of electrodes of the capacitive element 108 is electrically connected to the other of the pair of electrodes of the capacitive element 107 and the anode of the light-emitting element 101, and the other of the pair of electrodes of the capacitive element 108 is electrically connected to the power supply line VB. The capacitive element 108 is electrically connected in series with the capacitive element 107 and is electrically connected in series with the light-emitting element 101. Note that the capacitance value of the capacitive element 107 is preferably smaller than the capacitance value of the combined capacitance composed of the light-emitting element 101 and the capacitive element 108. Thereby, it is possible to suppress the decrease in the voltage between the gate and the source of the transistor 102 due to the capacitance in the light-emitting element 101. It can be achieved.

[0029] Note that the capacitance value of the capacitive element 107 is preferably smaller than the capacitance value of the combined capacitance composed of the light-emitting element 101 and the capacitive element 108. Thereby, it is possible to suppress the decrease in the voltage between the gate and the source of the transistor 102 due to the capacitance in the light-emitting element 101. Note that the capacitance value of the capacitive element 107 is preferably smaller than the capacitance value of the combined capacitance composed of the light-emitting element 101 and the capacitive element 108. Thereby, it is possible to suppress the decrease in the voltage between the gate and the source of the transistor 102 due to the capacitance in the light-emitting element 101. Note that the capacitance value of the capacitive element 107 is preferably smaller than the capacitance value of the combined capacitance composed of the light-emitting element 101 and the capacitive element 108. Thereby, it is possible to suppress the decrease in the voltage between the gate and the source of the transistor 102 due to the capacitance in the light-emitting element 101. It can be achieved.

[0030] One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. One of the source and the drain of the transistor 109 is electrically connected to the power supply line VC, and the other of the source and the drain of the transistor 109 is electrically connected to the drain of the transistor 102. The power supply line VC is a wiring to which the power supply potential V3 is supplied, and the power supply potential V3 is lower than the power supply potential V1, higher than the power supply potential V2, and higher than the potential of the cathode of the light-emitting element 101. Note that it is not limited to this, and the cathode of the light-emitting element 101 may be electrically connected to the power supply line VC. Also, the potential difference between the power supply potential V3 and the power supply potential V2 is larger than the threshold voltage of the transistor 102. Also, the other of the source and the drain of the transistor 109 may be electrically connected to the gate of the transistor 102 instead of the drain of the transistor 102. Also, in FIG. 1(A), the gate of the transistor 109 is electrically connected to the scanning line G2. 、The transistor 109 becomes on or off according to the scanning signal SCN2. The transistor 109 has a function of controlling whether to supply the power supply potential V3 to the drain of the transistor 102 or not. By providing the transistor 109, during the initialization period, a power supply potential V3 lower than the power supply potential V1 is supplied to the gate and drain of the transistor 102, and the value of the current flowing between the source and drain of the transistor 102 can be reduced. Thus, the power consumption can be reduced.

[0031] As the transistor 102, an n-channel type transistor can be used. Also, as the transistor 103, transistor 104, transistor 105, transistor 106, and transistor 109, an n-channel type transistor or a p-channel type transistor can be used. For example, by using n-channel type transistors as the transistor 102, transistor 103, transistor 104, transistor 105, transistor 106, and transistor 109, the number of manufacturing steps can be reduced.

[0032] Also, as the transistor 102, transistor 103, transistor 104, transistor 1 05, transistor 106, and transistor 109, for example, transistors in which the channel formation region provided between the source and drain is a wide-gap semiconductor such as an oxide semiconductor can be used, or transistors in which the channel formation region is a semiconductor such as amorphous, microcrystalline, polycrystalline or single-crystalline silicon or germanium can be used. The transistors using the above-mentioned oxide semiconductor may use conventional semiconductors such as silicon. ​​​​​​​​​The off-state current of the transistor is lower than that of the transistor using an oxide semiconductor. , it has a wider band gap than silicon and a lower intrinsic carrier density than silicon. Therefore, the off-state current of the transistor using the oxide semiconductor can be extremely low. The off-state current of the transistor is 10 aA (1 × 10 -17 A) Below , preferably 1 aA (1×10 -18 A) The following is more preferable: Approximately 10zA (1×10 -20 A) The following is more preferably 1zA (1×10 -21 A) or less, more preferably a channel width of 1 μm 100yA per m (1×10 -22 A) The following:

[0033] Next, an example of a method for driving the light emitting device in this embodiment will be described with reference to the timing chart shown in FIG. The following description will be given with reference to the timing chart and Figs. 2 and 3. transistor 102, transistor 103, transistor 104, transistor 105, The transistor 106 and the transistor 109 are all n-channel transistors. The capacitance of the capacitance element 107 is a composite capacitance formed by the light emitting element 101 and the capacitance element 108. The combined capacitance between the gate and source of the transistor 102 is much smaller than the capacitance of the There is no voltage drop between the

[0034] In the embodiment, the driving method of the light emitting device is an initialization period T11, a threshold voltage data acquisition period T21, and a threshold voltage data acquisition period T31. It is roughly divided into a period T12, an image signal input period T13, and a display period T14.

[0035] First, in the initialization period T11, as shown in FIGS. 1(B) and 2(A), turn on transistor 104, transistor 106, and transistor 109. At this time, the potentials of the gate and drain of transistor 102 become the power supply potential V3.

[0036] Also, the potential of the source of transistor 102 becomes the power supply potential V2. As a result, transistor 102 turns on, and the voltage between the gate and source of transistor 102 ( also referred to as voltage Vgs102) becomes the value obtained by subtracting the power supply potential V2 from the power supply potential V3 (V3 - V2 ). )

[0037] Next, in the threshold voltage data acquisition period T12, as shown in FIGS. 1(B) and 2(B), turn off transistor 106.

[0038] At this time, with transistor 102 remaining on, a current flows between the source and drain of transistor 102, causing the potential of the source of transistor 102 to rise. When the voltage between the gate and source of transistor 102 becomes equal to or lower than the threshold voltage of transistor 102 ( also referred to as voltage Vth102), transistor 102 turns off. Thereafter, by turning off transistor 104 and transistor 109, the voltage between the gate and source of transistor 102 is held.

[0039] Next, in the image signal input period T13, as shown in FIGS. 1(B) and 3(A), turn on transistor 103.

[0040] At this time, an image signal is input to the gate of transistor 102, and the ​The potential of the gate of the transistor 102 changes according to the image signal. The voltage between the transistors is the threshold voltage of the transistor 102 plus the voltage Vs (Vth102+Vs). The value of the voltage Vs varies depending on the amount of change in the potential of the gate of the transistor 102 due to the image signal. In FIG 3A, it is assumed, as an example, that the transistor 102 is turned on.

[0041] Next, in the display period T14, as shown in FIG. 1(B) and FIG. 3(B), 103 is turned off and transistor 105 is turned on.

[0042] At this time, the drain potential of the transistor 102 becomes the power supply potential V1, and the transistor 1 A current flows between the source and drain of the light emitting element 102. When a current flows between the electrodes, the light emitting element 101 emits light. .

[0043] At this time, the value of the current flowing through the light emitting element 101 is the value between the source and drain of the transistor 102. The current flowing between the transistors (also called Ids102) is determined by the current flowing between the transistors (Ids102) and saturates the transistor 102. When the transistor 102 is operated in the MOSFET region, the current flowing between the source and drain of the transistor 102 is It can be expressed by the following formula (1).

[0044]

number

[0045] β is a constant calculated from the mobility, channel length, channel width, etc. of the transistor 102. be.

[0046] In the display period T14, the voltage between the gate and source of the transistor 102 (Vgs10 Since it is Vth102 + Vs, substituting it into the above formula (1) gives the following formula (2). It becomes as follows.

[0047] [Number]

[0048] Therefore, the current value (Ids102) flowing between the source and drain of transistor 102 is determined according to the value of the image signal, regardless of the threshold voltage of transistor 102.

[0049] By performing all of the above operations in all pixel circuits, an image is displayed in the light-emitting device. Further by repeatedly performing the above operations in each pixel circuit, the display image of the light-emitting device can be rewritten This is possible.

[0050] The above is an example of a driving method of the light-emitting device in this embodiment.

[0051] Note that in the light-emitting device in this embodiment, transistor 109 may not be provided as shown in FIG. 4. At this time, in initialization period T11, transistor 105 is turned on to supply the power supply potential V1 to the drain of transistor 102. By adopting a configuration without providing transistor 109 the number of transistors can be reduced, and the circuit area can be reduced This is possible. As described with reference to FIGS. 1 to 4, in the light-emitting device in this embodiment, a threshold voltage data

[0052] acquisition period is provided, and the voltage between the gate and source of the driving transistor is set to a value corresponding to the threshold voltage of the driving transistor using a capacitive element. Thereby, during the display period using a capacitive element, the voltage between the gate and source of the driving transistor is set to a value corresponding to the threshold voltage of the driving transistor. As a result, during the display period it is set to a value corresponding to the threshold voltage of the driving transistor. Thereby, during the display period Thus, the amount of current flowing between the source and drain of the driving transistor can be determined regardless of the threshold voltage of the driving transistor, and variations in the luminance between pixels due to variations in the threshold voltage of the driving transistor can be suppressed.

[0053] In addition, in the light-emitting device according to the present embodiment, during the initialization period, by supplying an initialization power supply potential to the anode of the light-emitting element, changes in the voltage applied between the anode and cathode of the light-emitting element due to deterioration of the electroluminescent layer in the light-emitting element can be suppressed. Therefore, it is possible to suppress a decrease in the luminance of the light-emitting element due to deterioration of the electroluminescent layer.

[0054] In addition, in the light-emitting device according to the present embodiment, by configuring all the transistors in the pixel portion with n-channel transistors, the number of manufacturing steps can be reduced.

[0055] This embodiment can be implemented in appropriate combination with other embodiments.

[0056] (Embodiment 2) In this embodiment, a specific configuration of a pixel of a light-emitting device according to an aspect of the present invention will be described.

[0057] FIG. 5 shows a top view of the pixel shown in FIG. 1(A) as an example. In FIG. 5, various insulating films are omitted to clearly show the layout of the pixel, and a top view of the pixel is shown. Also, in FIG. 5, in order to clearly show the layout of the transistors and capacitor elements included in the pixel, the anode, the electroluminescent layer, and the cathode are omitted, and a top view of the pixel is shown.

[0058] Further, FIG. 6 shows cross-sectional views taken along broken lines A1 - A2 and A3 - A4 of the top view shown in FIG. 5. is shown.

[0059] Transistor 103 has, on a substrate 800 having an insulating surface, a conductive film that functions as a gate 801, a gate insulating film 802 on the conductive film 801, and a semiconductor layer 803 located on the gate insulating film 802 at a position overlapping the conductive film 801, and conductive films 804 and 805 located on the semiconductor layer 803 that function as a source or a drain. The conductive film 801 also functions as a scanning line G1. The conductive film 804 also functions as a signal line S1.

[0060] Transistor 102 has, on a substrate 800 having an insulating surface, a conductive film that functions as a gate 806, a gate insulating film 802 on the conductive film 806, and a semiconductor layer 807 located on the gate insulating film 802 at a position overlapping the conductive film 806, and conductive films 808 and 809 located on the semiconductor layer 807 that function as a source or a drain. The conductive film 806 is connected to the conductive film 805 via a contact hole.

[0061] Transistor 104 has, on a substrate 800 having an insulating surface, a conductive film that functions as a gate 810, a gate insulating film 802 on the conductive film 810, and a semiconductor layer 811 located on the gate insulating film 802 at a position overlapping the conductive film 810, and conductive films 805 and 808 located on the semiconductor layer 811 that function as a source or a drain. The conductive film 810 also functions as a scanning line G2.

[0062] Transistor 105 has, on a substrate 800 having an insulating surface, a conductive film that functions as a gate 812, a gate insulating film 802 on the conductive film 812, and at a position overlapping the conductive film 812 A semiconductor layer 813 located on the gate insulating film 802 and functioning as a source or a drain and a conductive film 808 and a conductive film 814 located on the semiconductor layer 813. The conductive film 812 also functions as a scanning line G3. The conductive film 814 also functions as a power supply line VA.

[0063] The transistor 106 has, on a substrate 800 having an insulating surface, a conductive film 815 functioning as a gate, a gate insulating film 802 on the conductive film 815, and a semiconductor layer 816 located on the gate insulating film 802 at a position overlapping the conductive film 815 and functioning as a source or a drain and a conductive film 809 and a conductive film 817 located on the semiconductor layer 816. The conductive film 815 also functions as a scanning line G4.

[0064] The capacitor element 107 has, on a substrate 800 having an insulating surface, a conductive film 806, a gate insulating film 802 on the conductive film 806, and a conductive film 809 located on the gate insulating film 802 at a position overlapping the conductive film 806.

[0065] The capacitor element 108 has, on a substrate 800 having an insulating surface, a conductive film 818, a gate insulating film 802 on the conductive film 818, and a conductive film 809 located on the gate insulating film 802 at a position overlapping the conductive film 818. The conductive film 818 also functions as a power supply line VB and is connected to the conductive film 817 through a contact hole.

[0066] The transistor 109 has, on a substrate 800 having an insulating surface, a conductive film 819 functioning as a gate, a gate insulating film 802 on the conductive film 819, and a semiconductor layer 820 located on the gate insulating film 802 at a position overlapping the conductive film 819 and functioning as a source or a drain ​、It has a conductive film 808 and a conductive film 821 located on the semiconductor layer 820. The conductive film 819 also functions as a scanning line G2. Further, the conductive film 821 is connected to a conductive film 822 that functions as a power source line VC via a contact hole.

[0067] Also, an insulating film 823 and an insulating film 824 are sequentially formed on the conductive film 804, the conductive film 805, the conductive film 808, the conductive film 809, the conductive film 814, the conductive film 817, and the conductive film 821. And, a conductive film 825 that functions as an anode is provided on the insulating film 824. The conductive film 825 is connected to the conductive film 809 via a contact hole 826 formed in the insulating film 823 and the insulating film 824.

[0068] Also, an insulating film 827 having an opening through which a part of the conductive film 825 is exposed is provided on the insulating film 82 4. An electroluminescent layer 828 and a conductive film 829 that functions as a cathode are provided so as to be sequentially laminated on a part of the conductive film 825 and the insulating film 827. The region where the conductive film 825, the electroluminescent layer 828, and the conductive film 829 overlap corresponds to the light-emitting element 1 01.

[0069] Note that in FIG. 5, the case where both the conductive film 810 and the conductive film 819 also function as the scanning line G2 is illustrated, but the conductive film 810 and the conductive film 819 may be composed of one conductive film.

[0070] Next, FIG. 7 shows a top view of the pixel shown in FIG. 4 as an example. Note that in FIG. 7, for the purpose of clearly showing the layout of the pixel, various insulating films are omitted and a top view of the pixel is shown. Also in FIG. 7, for the purpose of clearly showing the layout of the transistor and the capacitor element included in the pixel, the a ​​​​​​ The top view of the pixel is shown with the node, the electroluminescent layer, and the cathode omitted.

[0071] The pixel shown in FIG. 7 is different from the pixel shown in FIG. 5 in that it does not have the conductive film 819 that functions as the gate of the transistor 109, the conductive film 822 that functions as the power supply line VC, and the conductive film 821 connected to the conductive film 822. Note that in FIGS. 5 to 7, the case where a wide-gap semiconductor such as an oxide semiconductor is used for the semiconductor layers 803, 807, 811, 813, 816, and 820 is illustrated. The oxide semiconductor has a wider bandgap and a lower intrinsic carrier density than silicon. Therefore, as described above, a transistor using an oxide semiconductor has an extremely low off-current compared to a transistor using a semiconductor such as ordinary silicon or germanium.

[0072]

[0073]

[0074]

[0075] ​​​​​​​​​​​​​​Also, as other stabilizers, any one or more of lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) may be included.

[0076] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides , In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides , In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, I n-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In -Lu-Zn-based oxides, quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, I n-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used.

[0077] Here, for example, an In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be included in addition to In, Ga, and Zn.

[0078] Also, as the oxide semiconductor, a material represented by InMO3(ZnO) m (m > 0 and m is not an integer) may be used. Here, M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Also, as the oxide semiconductor, In3SnO5 (ZnO) (ZnO) n (n > 0 and n is an integer) may be used.

[0079] Also, as the oxide semiconductor, an In-Ga-Zn-based oxide with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3 ) or In:Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) or an oxide near its composition can be used. Alternatively, an In-Sn-Zn-based oxide with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1 :3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4: 1 / 8:5 / 8) or an oxide near its composition may be used.

[0080] However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal element and oxygen, interatomic bond distance, density, etc. appropriate.

[0081] For example, in an In-Sn-Zn oxide-based material, a relatively high mobility can be obtained relatively easily. However, even in an In-Ga-Zn oxide-based material, the mobility can be increased by reducing the density of defects within the bulk.

[0082] Note that, for example, when the atomic ratio of In, Ga, and Zn in an oxide is In:Ga:Zn = a:b:c (a + b + c = 1), the composition of the oxide is in the vicinity of the composition of an oxide with an atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, and c satisfy (a - A) 2 + (b - B) 2 + (c - C) 2 ≤ r 2 . For r, for example, 0.05 may be used. The same applies to other oxides.

[0083] The oxide semiconductor may be single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. Moreover, it may have a structure including a crystalline portion within the amorphous state, or may be non-amorphous.

[0084] An oxide semiconductor in an amorphous state can relatively easily obtain a flat surface. Therefore, when a transistor is fabricated using this, interface scattering can be reduced, and relatively easily, a relatively high mobility can be obtained.

[0085] In addition, in a crystalline oxide semiconductor, more defects within the bulk can be reduced, and if the flatness of the surface is enhanced, a mobility higher than that of an amorphous oxide semiconductor can be obtained. To enhance the flatness of the surface, it is preferable to form the oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably​​ It is preferably formed on a surface of 0.1 nm or less.

[0086] Note that Ra is the center line average roughness defined in JIS B0601 extended three-dimensionally so as to be applicable to a surface, and can be expressed as "a value obtained by averaging the absolute values of the deviations from the reference surface to the specified surface", and is defined by the following formula. and can be expressed as "a value obtained by averaging the absolute values of the deviations from the reference surface to the specified surface", and is defined by the following formula. and is defined by the following formula.

[0087]

Equation

[0088] In the above, S0 refers to the area of the measurement surface (a rectangular area surrounded by four points represented by coordinates (x1, y1), (x1, y2), (x2, y1 )(x2, y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope). Microscope).

[0089] Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or less with the potential of the source as a reference in a state where the drain is at a higher potential than the source and the gate. Or, the off-current means, in a p-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or more with the potential of the source as a reference in a state where the drain is at a lower potential than the source and the gate. Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or less with the potential of the source as a reference in a state where the drain is at a higher potential than the source and the gate. Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or less with the potential of the source as a reference in a state where the drain is at a higher potential than the source and the gate. Note that, unless otherwise specified, in this specification, the off-current means, in an n-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or less with the potential of the source as a reference in a state where the drain is at a higher potential than the source and the gate. Or, the off-current means, in a p-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or more with the potential of the source as a reference in a state where the drain is at a lower potential than the source and the gate. Or, the off-current means, in a p-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or more with the potential of the source as a reference in a state where the drain is at a lower potential than the source and the gate. Or, the off-current means, in a p-channel type transistor, the current flowing between the source and the drain when the potential of the gate is 0 or more with the potential of the source as a reference in a state where the drain is at a lower potential than the source and the gate.

[0090] Note that a semiconductor having a wider bandgap and a lower intrinsic carrier density than silicon As an example of a conductor material, in addition to oxide semiconductors, there are silicon carbide (SiC), gallium nitride (Ga N), and the like. Compound semiconductors such as silicon carbide and gallium nitride must be single crystals. To obtain a single crystal material, crystal growth at a temperature significantly higher than the process temperature of oxide semiconductors, epitaxial growth on a special substrate, or the like is required. The manufacturing conditions are strict, and film formation on easily available silicon wafers or glass substrates with a low heat resistance temperature is difficult. However, oxide semiconductors can be manufactured by sputtering or wet methods, and have the advantage of excellent mass productivity. In addition, since oxide semiconductors can be film-formed even at room temperature, film formation on a glass substrate or on an integrated circuit using semiconductor elements is possible, and it is also possible to cope with the increase in the size of the substrate. Therefore, oxide semiconductors have the merit of high mass productivity. Also, even when trying to obtain a crystalline oxide semiconductor to improve the performance of a transistor (for example, field-effect mobility), a crystalline oxide semiconductor can be obtained by heat treatment at 200°C to 800°C.

[0091] Also, various conductive films such as conductive film 801, conductive films 804 to 806, conductive films 808 to 810, conductive film 812, conductive film 814, conductive film 815, conductive films 817 to 819, conductive film 8 21, and conductive film 822 can use an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy film containing the above-described elements as components, or an alloy film combining the above-described elements. Also, a configuration in which a high melting point metal film such as chromium, tantalum, titanium, molybdenum, or tungsten is laminated on the lower side or the upper side of a metal film such as aluminum or copper may be used. Also, aluminum or copper has a resistance ​​​​​​​​​​​ To avoid problems such as heat and corrosion, it is advisable to use it in combination with a high melting point metal material. High As the high melting point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, yttrium, etc. can be used. Also, Cu-Mg-Al alloy, Mo-Ti alloy, Ti, Mo have high adhesion to the oxide film. Therefore, when the gate insulating film 8 02 is an oxide, it is desirable to use a material with high adhesion to the oxide film on the gate insulating film 802 for the conductive films 804, 805, 808, 809, 814, 817, 821. For example, for the conductive films 804, 805, 808, 809, 814, 817, 821, a conductive film composed of Cu-Mg-Al alloy, Mo-Ti alloy, Ti, or Mo in the lower layer and a conductive film composed of Cu with a low resistance value in the upper layer are laminated and used, so that the adhesion to the gate insulating film 802 which is an oxide can be increased and the resistance value can be decreased. For example, for the conductive films 804, 805, 808, 809, 814, 817, 821, a conductive film composed of Cu-Mg-Al alloy, Mo-Ti alloy, Ti, or Mo in the lower layer and a conductive film composed of Cu with a low resistance value in the upper layer are laminated and used, so that the adhesion to the gate insulating film 802 which is an oxide can be increased and the resistance value can be decreased. A conductive film composed of Cu-Mg-Al alloy, Mo-Ti alloy, Ti, or Mo in the lower layer and a conductive film composed of Cu with a low resistance value in the upper layer are laminated and used, so that the adhesion to the gate insulating film 802 which is an oxide can be increased and the resistance value can be decreased. When using an oxide semiconductor layer for the semiconductor layers 803, 807, 811, 813, 816, 820, the film formation of the oxide semiconductor layer can be carried out by holding the substrate in a processing chamber maintained in a reduced pressure state, introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the processing chamber, and using a target. During film formation, the substrate temperature can be set to 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower. By forming the film while heating the substrate, the impurity concentration contained in the formed oxide semiconductor layer can be reduced. Also, the damage due to sputtering can be reduced. The residual

[0092] When using an oxide semiconductor layer for the semiconductor layers 803, 807, 811, 813, 816, 820, the film formation of the oxide semiconductor layer can be carried out by holding the substrate in a processing chamber maintained in a reduced pressure state, introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the processing chamber, and using a target. During film formation, the substrate temperature can be set to 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower. By forming the film while heating the substrate, the impurity concentration contained in the formed oxide semiconductor layer can be reduced. Also, the damage due to sputtering can be reduced. The residual When using an oxide semiconductor layer for the semiconductor layers 803, 807, 811, 813, 816, 820, the film formation of the oxide semiconductor layer can be carried out by holding the substrate in a processing chamber maintained in a reduced pressure state, introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the processing chamber, and using a target. During film formation, the substrate temperature can be set to 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower. By forming the film while heating the substrate, the impurity concentration contained in the formed oxide semiconductor layer can be reduced. Also, the damage due to sputtering can be reduced. The residual When using an oxide semiconductor layer for the semiconductor layers 803, 807, 811, 813, 816, 820, the film formation of the oxide semiconductor layer can be carried out by holding the substrate in a processing chamber maintained in a reduced pressure state, introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the processing chamber, and using a target. During film formation, the substrate temperature can be set to 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower. By forming the film while heating the substrate, the impurity concentration contained in the formed oxide semiconductor layer can be reduced. Also, the damage due to sputtering can be reduced. The residual When using an oxide semiconductor layer for the semiconductor layers 803, 807, 811, 813, 816, To remove moisture, it is preferable to use an adsorption type vacuum pump. It is preferable to use an opto-pump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump with a cold trap added. When the processing chamber is evacuated using a lion pump, hydrogen atoms such as hydrogen and water (H2O) are released. Since compounds containing atoms (and more preferably compounds containing carbon atoms) are exhausted, By using this method, the concentration of impurities contained in the oxide semiconductor layer formed in the treatment room can be reduced.

[0093] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m 3 / second or less By doing so, it is possible to prevent the alkali from being added to the oxide semiconductor layer during the film formation by the sputtering method. It is possible to reduce the inclusion of impurities such as metals and hydrides. By using an adsorption type vacuum pump, alkali metals, hydrogen atoms, hydrogen molecules, The backflow of impurities such as water, hydroxyl radicals, or hydrides can be reduced.

[0094] In addition, by setting the purity of the target to 99.99% or more, the amount of the target mixed into the oxide semiconductor layer can be reduced. It is possible to reduce alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, etc. In addition, by using the target, lithium, sodium, and the like can be easily formed in the oxide semiconductor layer. The concentration of alkali metals such as sodium and potassium can be reduced.

[0095] Note that moisture or hydrogen (water) as an impurity is contained in the oxide semiconductor layer formed by sputtering or the like. Water or hydrogen tends to form donor levels. Therefore, for an oxide semiconductor, it is an impurity. Thus, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor layer (dehydration or dehydrogenation), the oxide semiconductor layer is subjected to heat treatment in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra-dry air (the moisture content measured using a dew point meter of the CRDS (Cavity Ring Down Laser Spectroscopy) method is 20 ppm or less (dew point conversion of -55 °C) , preferably 1 ppm or less, more preferably 10 ppb or less of air) atmosphere. It is desirable to perform heat treatment.

[0096] By subjecting the oxide semiconductor layer to heat treatment, moisture or hydrogen in the oxide semiconductor layer can be desorbed. Specifically, heat treatment may be performed at a temperature of 250 °C or higher and 750 °C or lower, preferably 400 °C or higher and lower than the distortion point of the substrate. For example, it may be performed at about 500 °C for 3 minutes or more and 6 minutes or less. If the RTA method is used for heat treatment, dehydration or dehydrogenation can be performed in a short time, so that treatment can be performed even at a temperature exceeding the distortion point of the glass substrate.

[0097] In addition to an electric furnace, the heat treatment apparatus may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. . The GRTA device is a device for performing heat treatment using high-temperature gas. As the gas, noble gases such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used.

[0098] In heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain moisture or water element, etc. Alternatively, the purity of nitrogen or noble gases such as helium , neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7 N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 p pm or less).

[0099] Note that oxide semiconductors are insensitive to impurities, and even if a considerable amount of metal impurities are contained in the film, there is no problem, and it is pointed out that inexpensive soda lime glass containing a large amount of alkali metals such as sodium can be used (Kamiya, Nomura, Hosono, "Physical Properties of Amorphous Oxide Semiconductors and Current Status of Device Development", Solid State Physics, September 2009 issue, Vol. 44, pp. 62 1-633.). However, such a statement is inappropriate. Since alkali metals are not elements that make up oxide semiconductors, they are impurities. Alkaline earth metals also become impurities when they are not elements that make up oxide semiconductors. In particular, among alkali metals, Na diffuses into the insulating film when the insulating film in contact with the oxide semiconductor layer is an oxide and becomes Na . Also, Na breaks or interrupts the bond between the metal and oxygen that make up the oxide semiconductor within the oxide semiconductor layer. As a result, for example, characteristics of the transistor such as non-normal ionization due to a negative shift in the threshold voltage and a decrease in mobility + become Na. Moreover . Also, Na breaks or interrupts the bond between the metal and oxygen that make up the oxide semiconductor within the oxide semiconductor layer, or interrupts during the bond. As a result, for example, characteristics of the transistor such as non-normal ionization due to a negative shift in the threshold voltage and a decrease in mobility deteriorate.​​ In addition, the transistor characteristics may vary. The deterioration and variation in characteristics occur when the hydrogen concentration in the oxide semiconductor layer is sufficiently low. Therefore, the hydrogen concentration in the oxide semiconductor layer is more pronounced when the hydrogen concentration is 1×10 18 / cm 3 below, More preferably, 1×10 17 / cm 3 If it is less than 100%, reduce the concentration of the impurity. Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5×10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 More preferably, 1×10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 below, Preferably 1 x 10 15 / cm 3 Similarly, the measured value of the K concentration should be 5 x 1 0 15 / cm 3 Less than or equal to 1×10 15 / cm 3 The following should be used.

[0100] The concentration of hydrogen in the oxide semiconductor layer is reduced and the oxide semiconductor layer is highly purified, thereby stabilizing the oxide semiconductor layer. In addition, the carrier density is extremely low when the material is heated below the glass transition temperature. Therefore, an oxide semiconductor layer having a wide band gap can be formed without using a large-area A transistor can be manufactured using the substrate, which improves mass productivity. By using the oxide semiconductor layer in which the hydrogen concentration is reduced and which is highly purified, A transistor with extremely low off-current can be fabricated. The above heat treatment can be carried out at any time after the formation of the oxide semiconductor layer.

[0101] In this embodiment, an oxide containing a phase (also referred to as CAAC: C Axis Aligned Crystal) will be described, which is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, with metal atoms arranged in layers along the c-axis or metal atoms and oxygen atoms arranged in layers, and the directions of the a-axis or b-axis being different (rotated around the c-axis as the center) in the ab-plane.

[0102] An oxide containing CAAC, in a broad sense, is a non-single crystal that has a triangular, hexagonal, equilateral triangular, or regular hexagonal atomic arrangement when viewed from a direction perpendicular to the ab-plane, and contains a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis direction.

[0103] CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, CAAC contains crystallized portions (crystalline portions), but in some cases, the boundaries between one crystalline portion and another cannot be clearly distinguished.

[0104] When oxygen is contained in CAAC, a part of the oxygen may be substituted with nitrogen. Also, the c-axes of the individual crystalline portions constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal lines of the ab-planes of the individual crystalline portions constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). ​​​​​​​​​​​​​​

[0105] Depending on its composition and the like, the CAAC can be a conductor, a semiconductor, or an insulator. Also, depending on its composition and the like, it can be transparent or opaque to visible light.

[0106] As an example of such a CAAC, a crystal is formed in a film shape, and when observed from a direction perpendicular to the film surface or the surface of the supporting substrate, a triangular or hexagonal atomic arrangement is observed, and when the film cross-section is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed.

[0107] An example of the crystal structure included in the CAAC will be described in detail with reference to FIGS. 15 to 17. Unless otherwise specified, in FIGS. 15 to 17, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is the ab-plane. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab-plane as the boundary. Also, in FIG. 15, the O surrounded by a circle indicates a 4-coordinate O, and the O surrounded by a double circle indicates a 3-coordinate O.

[0108] FIG. 15(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter 4-coordinate O) adjacent to the In. Here, the structure showing only the adjacent oxygen atoms for one metal atom is called a small group. The structure of FIG. 15(A) has an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are three 4-coordinate O each in the upper half and the lower half of FIG. 15(A). The small group shown in FIG. 15(A) has a charge of 0.

[0109] FIG. 15(B) shows one 5-coordinate Ga and three 3-coordinate oxygen atoms (hereinafter 3-coordinate O) adjacent to the Ga. ​​​​​​​​​​​​It shows a structure having coordinated O), two 4 - coordinated O's close to Ga. The 3 - coordinated O's are all present on the ab plane. There is one 4 - coordinated O each in the upper half and the lower half of Fig. 15(B). Also, since In also takes a 5 - coordinate state, it can have the structure shown in Fig. 15(B). The small group shown in Fig. 15(B) has a charge of 0. All are present on the ab plane. There is one 4 - coordinated O each in the upper half and the lower half of Fig. 15(B). Since In also takes a 5 - coordinate state, it can have the structure shown in Fig. 15(B). The small group shown in Fig. 15(B) has a charge of 0.

[0110] Fig. 15(C) shows a structure having one 4 - coordinated Zn and four 4 - coordinated O's close to Zn. There is one 4 - coordinated O in the upper half of Fig. 15(C) and three 4 - coordinated O's in the lower half. The small group shown in Fig. 15(C) has a charge of 0. There is one 4 - coordinated O in the upper half of Fig. 15(C) and three 4 - coordinated O's in the lower half. The small group shown in Fig. 15(C) has a charge of 0.

[0111] Fig. 15(D) shows a structure having one 6 - coordinated Sn and six 4 - coordinated O's close to Sn. There are three 4 - coordinated O's in the upper half of Fig. 15(D) and three 4 - coordinated O's in the lower half. The small group shown in Fig. 15(D) has a charge of +1. There are three 4 - coordinated O's in the upper half of Fig. 15(D) and three 4 - coordinated O's in the lower half. The small group shown in Fig. 15(D) has a charge of +1.

[0112] Fig. 15(E) shows a small group containing two Zn's. There is one 4 - coordinated O in the upper half of Fig. 15(E) and one 4 - coordinated O in the lower half. The small group shown in Fig. 15(E) has a charge of -1. There is one 4 - coordinated O in the upper half of Fig. 15(E) and one 4 - coordinated O in the lower half. The small group shown in Fig. 15(E) has a charge of -1.

[0113] Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also called a unit cell). Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also called a unit cell).

[0114] Here, the rule for the combination of these small groups will be explained. The three O's in the upper half of the 6 - coordinated In shown in Fig. 15(A) each have three adjacent In's downward, and the three O's in the lower half each have three adjacent In's upward. The 5 - coordinated Ga shown in Fig. 15(B) The three O's in the upper half of the 6 - coordinated In shown in Fig. 15(A) each have three adjacent In's downward, and the three O's in the lower half each have three adjacent In's upward. The three O's in the lower half each have three adjacent In's upward. The 5 - coordinated Ga shown in Fig. 15(B) One O in the upper half has one adjacent Ga downward, and one O in the lower half has one adjacent Ga upward. One O in the upper half of the four-coordinate Zn shown in Fig. 15(C) has one adjacent Zn downward, and the three Os in the lower half have three adjacent Zns upward. Thus, the number of four-coordinate Os above the metal atom is equal to the number of adjacent metal atoms below that O. Similarly, the number of four-coordinate Os below the metal atom is equal to the number of adjacent metal atoms above that O. Since O is four-coordinate, the sum of the number of adjacent metal atoms below and the number of adjacent metal atoms above is 4. Therefore, when the sum of the number of four-coordinate Os above one metal atom and the number of four-coordinate Os below another metal atom is 4, two small groups with metal atoms can bond to each other. For example, when a six-coordinate metal atom (In or Sn) bonds through the four-coordinate Os in the upper half, since there are three four-coordinate Os, it

[0115] will bond to either a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn). Metal atoms with these coordination numbers bond through four-coordinate Os in the c-axis direction. Also, in addition, multiple small groups combine to form a medium group so that

[0116] the total charge of the layer structure is 0. Fig. 16(A) shows a model diagram of the medium group that constitutes the layer structure of the In-Sn-Zn-O system. Fig. 16(B) shows a large group composed of three medium groups. Note that Fig. 16(C) shows the atomic arrangement

[0117] when observing the layer structure of Fig. 16(B) from the c-axis direction. In Fig. 16(A), for , for example, there are three 4 - coordinate O atoms each in the upper and lower halves of Sn, which are shown as 3 in the round frame . Similarly, in Fig. 16(A), there is one 4 - coordinate O atom each in the upper and lower halves of In, which is shown as 1 in the round frame. Also, similarly, in Fig. 16 (A), there is one 4 - coordinate O atom in the lower half and three 4 - coordinate O atoms in the upper half of Zn, and there is one 4 - coordinate O atom in the upper half and three 4 - coordinate O atoms in the lower half of Zn are shown.

[0118] In Fig. 16(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system, in order from the top, is Sn with three 4 - coordinate O atoms each in the upper and lower halves, which combines with In with one 4 - coordinate O atom each in the upper and lower halves. That In combines with Zn with three 4 - coordinate O atoms in the upper half. Through one 4 - coordinate O atom in the lower half of that Zn, it combines with In with three 4 - coordinate O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn with one 4 - coordinate O atom in the upper half. Through one 4 - coordinate O atom in the lower half of this small group, it combines with Sn with three 4 - coordinate O atoms each in the upper and lower halves. This middle group loop combines multiple times to form a large group.

[0119] Here, for 3 - coordinate O and 4 - coordinate O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinate or 5 - coordinate), Zn (4 - coordinate), and Sn (5 - coordinate or 6 - coordinate) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. So, to form a layer structure containing Sn, a charge of - 1 to cancel out the charge + 1 is required. As a structure with a charge of - 1, Fig. 1 ​ As shown in 5(E), a small group containing two Zn's can be mentioned. For example, a group containing Sn If there is one small group containing Sn and one small group containing two Zn's, the charges will cancel out so that the total charge of the layer structure can be made zero.

[0120] Specifically, by repeating the large group shown in Fig. 16(B), a crystal of the In-Sn-Zn -O system (In2SnZn3O8) can be obtained. Note that the obtained In-Sn -Zn-O system layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be represented by a composition formula of. Note that for the crystal of the In-Sn-Zn-O system, as the value of m increases the crystallinity improves, which is preferable.

[0121] In addition to this, there are also In-Sn-Ga-Zn system oxides which are quaternary metal oxides, and ternary metal oxides such as In-Ga-Zn system oxides (also denoted as IGZO), In- Al-Zn system oxides, Sn-Ga-Zn system oxides, Al-Ga-Zn system oxides, Sn-A l-Zn system oxides, In-Hf-Zn system oxides, In-La-Zn system oxides, In-C e-Zn system oxides, In-Pr-Zn system oxides, In-Nd-Zn system oxides, In-Sm -Zn system oxides, In-Eu-Zn system oxides, In-Gd-Zn system oxides, In-Tb- Zn system oxides, In-Dy-Zn system oxides, In-Ho-Zn system oxides, In-Er-Z n system oxides, In-Tm-Zn system oxides, In-Yb-Zn system oxides, In-Lu-Zn system oxides, and binary metal oxides such as In-Zn system oxides, Sn-Zn system oxides, Al -Zn system oxides, Zn-Mg system oxides, Sn-Mg system oxides, In-Mg system oxides, and I n-Ga-based oxides, In-based oxides which are monometallic oxides, Sn-based oxides, Zn-based oxides, etc. are the same when used. The same applies when using substances such as zinc oxides.

[0122] For example, Fig. 17(A) shows a model diagram of the middle group constituting the layer structure of the In-Ga-Zn-O system. is shown.

[0123] In Fig. 17(A), the middle group constituting the layer structure of the In-Ga-Zn-O system has, in order from the top, In with three 4-coordinate O atoms each in the upper and lower halves, Zn with one 4-coordinate O atom in the upper half bonded to it, and through the three 4-coordinate O atoms in the lower half of that Zn, Ga with one 4-coordinate O atom each in the upper and lower halves is bonded, and through the one 4-coordinate O atom in the lower half of that Ga it is bonded to In with three 4-coordinate O atoms each in the upper and lower halves. This is the structure where the middle group is bonded to form a large group. This middle group is bonded in multiple to form a large group. This middle group combines in multiple to form a large group.

[0124] Fig. 17(B) shows a large group composed of three middle groups. Note that Fig. 17(C) shows the atomic arrangement when observing the layer structure of Fig. 17(B) from the c-axis direction.

[0125] Here, since the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3 respectively, a small group containing any of In, Zn, and Ga has a charge of 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0. is always zero.

[0126] Also, the middle group constituting the layer structure of the In-Ga-Zn-O system is not limited to the middle group shown in Fig. 17(A), and large groups formed by combining middle groups with different arrangements of In, Ga, and Zn are also possible. groups are also possible.

[0127] The oxide semiconductor layer composed of CAAC can also be fabricated by a sputtering method. To obtain CAAC by the sputtering method, it is necessary to form hexagonal crystals at the initial stage of deposition of the oxide semiconductor layer, and to grow crystals using the crystals as seeds. For this purpose, it is preferable to increase the distance between the target and the substrate (for example, about 150 mm to 200 mm), and set the substrate heating temperature to 100°C to 500°C, preferably 20 0°C to 400°C, and more preferably 250°C to 300°C. In addition, by heat-treating the deposited oxide semiconductor layer at a temperature higher than the substrate heating temperature during film formation, microscopic defects contained in the film and defects at the lamination interface can be repaired.

[0128] In addition, the composition ratio of the target used for forming the In-Sn-Zn-based oxide layer is such that In:Sn: Zn is in an atomic ratio of 1:2:2, 2:1:3, 1:1:1, or 20:45:35, etc., and an oxide target is used.

[0129] Compared with an amorphous oxide semiconductor, the bonds between metal and oxygen are ordered in CAAC. That is, when the oxide semiconductor is amorphous, the coordination number of oxygen atoms may vary depending on individual metal atoms, but in CAAC, the coordination number of oxygen atoms in metal atoms is almost constant. Therefore, microscopic oxygen deficiencies are reduced, and it has the effect of reducing charge movement and instability due to the desorption of hydrogen atoms (including hydrogen ions) and alkali metal atoms.

[0130] Therefore, by fabricating a transistor using an oxide semiconductor layer composed of CAAC, ​​​After performing light irradiation on the transistor or adding bias - thermal stress (BT), the change amount of the threshold voltage of the transistor can be reduced. Therefore, a transistor having stable electrical characteristics can be fabricated.

[0131] Also, when an oxide semiconductor layer is used for semiconductor layer 803, semiconductor layer 807, semiconductor layer 811, semiconductor layer 8 13, semiconductor layer 816, semiconductor layer 820, insulating films such as gate insulating film 802 and insulating film 823 in contact with the oxide semiconductor layer are formed by using methods such as plasma CVD method or sputtering method, and are made of silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide or tantalum oxide, yttrium oxide, hafnium silicate (HfSi O x O y (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSi x O y (x > 0, y > 0 ), hafnium aluminate with nitrogen added (HfAl x O y (x > 0, y > 0)), etc. The film can be formed by using a single film or multiple stacked films. By using an inorganic material containing oxygen for the above - mentioned insulating film, even if oxygen deficiency occurs in the oxide semiconductor layer due to heat treatment for reducing moisture or hydrogen, oxygen can be supplied to the oxide semiconductor layer from the above - mentioned

[0132] insulating film, and the oxygen deficiency serving as a donor can be reduced to form a composition that satisfies the stoichiometric composition ratio. Therefore, the channel formation region can be made closer to the i - type, and the variations in the electrical characteristics of transistors 103, 104, 105, 106, 109 due to oxygen deficiency can be reduced, and the improvement of electrical characteristics can be realized. can appear.

[0133] In addition, insulating films such as the gate insulating film 802 and the insulating film 823 in contact with the oxide semiconductor layer may use an insulating material containing a Group 13 element and oxygen. Many oxide semiconductors contain a Group 13 element, and an insulating material containing a Group 13 element has good compatibility with the oxide semiconductor. By using this for the insulating film in contact with the oxide semiconductor layer, the state of the interface with the oxide semiconductor layer can be kept good. The insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, and gallium aluminum oxide. Here, aluminum gallium oxide means that the content (atomic%) of aluminum is more than the content (atomic%) of gallium, and gallium aluminum oxide means that the content (atomic%) of gallium is equal to or more than the content (atomic%) of aluminum. For example, when forming an insulating film in contact with a gallium-containing oxide semiconductor layer, using a material containing gallium oxide for the insulating film can keep the interface characteristics between the oxide semiconductor layer and the insulating film good. For example, by providing the oxide semiconductor layer in contact with the insulating film containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating film can be reduced. When an element of the same group as the component element of the oxide semiconductor is used for the insulating film, the same effect can be obtained. For example, using a material containing aluminum oxide for the insulating film.

[0134]

[0135] It is also effective to form. Aluminum oxide has the property of being difficult to permeate water. Therefore, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0136] In FIGS. 5 to 7, a semiconductor such as amorphous, microcrystalline, or polycrystalline silicon or germanium may be used for the semiconductor layer 803, semiconductor layer 807, semiconductor layer 811, semiconductor layer 813, semiconductor layer 816, and semiconductor layer 820. However, when a semiconductor such as amorphous, microcrystalline, or polycrystalline silicon or germanium is used for the semiconductor layer 803, semiconductor layer 807, semiconductor layer 811, semiconductor layer 813, semiconductor layer 816, and semiconductor layer 820, an impurity element for imparting conductivity is added to the semiconductor layer to form an impurity region that functions as a source or a drain. For example, by adding phosphorus or arsenic to the semiconductor layer, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the above semiconductor layer, an impurity region having p-type conductivity can be formed.

[0137] Next, FIG. 8 shows a top view of the pixel shown in FIG. 1(A) as another example. In FIG. 8, for the sake of clearly showing the layout of the pixel, various insulating films are omitted, and a top view of the pixel is shown. Also, in FIG. 8, for the sake of clearly showing the layout of the transistor and the capacitive element included in the pixel, the anode, the electroluminescent layer, and the cathode are omitted, and a top view of the pixel is shown.

[0138] Further, FIG. 9 shows cross-sectional views taken along broken lines A1 - A2 and A3 - A4 of the top view shown in FIG. 8.

[0139] ​​​​​​​​​​​​​​ The transistor 103 includes a semiconductor layer 903 and a semiconductor layer The gate insulating film 902 on the semiconductor layer 903 and the gate insulating film 9 A conductive film 901 that is located on the gate electrode 902 and functions as a gate electrode, and a source or drain electrode The semiconductor layer 903 includes a conductive film 904 and a conductive film 905 which function as a conductive film and are located over the semiconductor layer 903 . The conductive film 901 also functions as a scanning line G1. The conductive film 904 also functions as a signal line S1. do.

[0140] The transistor 102 includes a semiconductor layer 907 and a semiconductor layer The gate insulating film 902 on the semiconductor layer 907 and the gate insulating film 9 A conductive film 906 which is located on the gate electrode 902 and functions as a gate, and a source or drain electrode 903 which is located on the gate electrode 902 and functions as a gate. The semiconductor layer 907 includes a conductive film 908 and a conductive film 909 which function as a conductive film and are located over the semiconductor layer 907 . The conductive film 906 is connected to the conductive film 905 through a contact hole.

[0141] The transistor 104 includes a semiconductor layer 907 and a semiconductor layer The gate insulating film 902 on the semiconductor layer 907 and the gate insulating film 9 A conductive film 910 is located on the gate electrode 902 and functions as a gate electrode, and a source or drain electrode 910 is located on the gate electrode 902. The semiconductor layer 907 includes a conductive film 911 and a conductive film 908 which function as a conductive film. The conductive film 910 also functions as a scanning line G2. 8, the transistor 102 and the transistor 903 are connected to the conductive film 906. The transistor 102 and the transistor 104 share a semiconductor layer 907. 104 may have semiconductor layers independent of each other.

[0142] Transistor 105 has, on a substrate 900 having an insulating surface, a semiconductor layer 913, and a semiconductor layer a gate insulating film 902 on the semiconductor layer 913, and a conductive film 912 that is located on the gate insulating film 9 02 and that functions as a gate, and a conductive film 908 and a conductive film 914 that function as a source or a drain and that are located on the semiconductor layer 913. The conductive film 912 also functions as a scanning line G3. The conductive film 914 also functions as a power supply line VA and functions.

[0143] Transistor 106 has, on a substrate 900 having an insulating surface, a semiconductor layer 916, and a semiconductor layer a gate insulating film 902 on the semiconductor layer 916, and a conductive film 915 that is located on the gate insulating film 9 02 and that functions as a gate, and a conductive film 909 and a conductive film 917 that function as a source or a drain and that are located on the semiconductor layer 916. The conductive film 915 also functions as a scanning line G4.

[0144] Capacitor element 107 has, on a substrate 900 having an insulating surface, a semiconductor layer 907, and a semiconductor layer 90 a gate insulating film 902 on the semiconductor layer 907, and a conductive film 906 that is located on the gate insulating film 902 at a position overlapping the semiconductor layer 907. In FIG. 8, the capacitor element 107 and the transistor 102 share one semiconductor layer 907, but the capacitor element 107 and the transistor 1 02 may have semiconductor layers independent of each other.

[0145] Capacitor element 108 has, on a substrate 900 having an insulating surface, a semiconductor layer 918, and a semiconductor layer 91 a gate insulating film 902 on the semiconductor layer 918, and a conductive film 902 that is located on the gate insulating film 902 The semiconductor layer 918 is connected to a power supply through the conductive film 917. It is connected to a conductive film 930 which also functions as line VB.

[0146] The transistor 109 includes a semiconductor layer 913 and a semiconductor layer The gate insulating film 902 on the semiconductor layer 913 and the gate insulating film 9 A conductive film 919 which is located on the gate electrode 910 and functions as a gate electrode and a source or drain electrode The conductive film 908 and the conductive film 921 function as a conductive film and are located over the semiconductor layer 913 . The conductive film 919 also functions as a scanning line G2. 8, the power supply line VC is connected to the conductive film 922 via the The transistor 105 and the transistor 109 share a single semiconductor layer 913. The transistor 105 and the transistor 109 may have semiconductor layers independent of each other. .

[0147] In addition, a conductive film 904, a conductive film 905, a conductive film 908, a conductive film 909, a conductive film 911, a conductive film An insulating film 923 is formed over the conductive film 914, the conductive film 917, and the conductive film 921. A conductive film 925 functioning as an anode is provided over the insulating film 923. A contact hole 926 is formed in the insulating film 923, and the contact hole 925 is connected to the conductive film 909. Connected.

[0148] In addition, an insulating film 927 having an opening through which a part of the conductive film 925 is exposed is formed on the insulating film 92. An electroluminescent layer 928 is provided on a part of the conductive film 925 and the insulating film 927. A conductive film 929 functioning as a cathode and a conductive film 928 functioning as a cathode are laminated in this order. The region where the electrofilm 925, the electroluminescent layer 928, and the conductive film 929 overlap corresponds to the light-emitting element 1 corresponds to 01.

[0149] In addition, in FIG. 8, when both the conductive film 910 and the conductive film 919 also function as the scanning line G2 is illustrated, but the conductive film 910 and the conductive film 919 may be composed of one conductive film. .

[0150] In addition, for the semiconductor layers 903, 907, 913, 916, and semiconductor layer 9 18, a semiconductor such as silicon or germanium, which is a single crystal, is used.

[0151] When the semiconductor layers 903, 907, 913, 916, and semiconductor layer 91 8 are single-crystal silicon, first, a bond substrate, which is a single-crystal semiconductor substrate, is prepared. Then, an ion beam composed of ions accelerated by an electric field is injected into the bond substrate, and a brittle layer that is locally weakened due to the disruption of the crystal structure is formed in a region with a certain depth from the surface of the bond substrate. The depth of the region where the brittle layer is formed can be adjusted by the acceleration energy of the ion beam and the incident angle of the ion beam. Then, the bond substrate and the substrate 900 having an insulating surface are bonded together. The bonding is performed by overlapping the bond substrate and the substrate 900, and then applying a pressure of 1 N / cm or more and 500 N / cm or less, preferably 11 N / cm 2 or more and 20 N / cm 2 or less, to a part of the bond substrate and the substrate 900. When the pressure is applied, 2 bonding starts between the bond substrate and the insulating surface of the substrate 900 at that part, and finally spreads to the entire adhered surface. 2 Next, by performing a heat treatment, the minute voids existing in the brittle layer are removed, and the bond substrate and the substrate 900 are firmly bonded together. are removed, and the bond substrate and the substrate 900 are firmly bonded together. The volume of the void increases, and the micro voids combine with each other. As a result, in the embrittlement layer, the bonding groups A single-crystalline semiconductor layer, which is a part of the plate, separates from the bonding substrate. The temperature of the heat treatment is set to a temperature not exceeding the strain point of the substrate 900. Then, by processing the single-crystalline semiconductor layer into a desired shape by etching or the like, semiconductor layers 903, 907, 913, 916, and semiconductor layer 918 can be formed. 916, and semiconductor layer 918 can be formed. 916, and semiconductor layer 918 can be formed.

[0152] Semiconductor layers 903, 907, 913, 916, and semiconductor layer 91 8 may be doped with a p-type conductive impurity element such as boron, aluminum, or gallium, or an n-type conductive impurity element such as phosphorus or arsenic in order to control the threshold voltage. The addition of the impurity element for controlling the threshold voltage may be performed on the semiconductor layer before patterning, or may be performed on the semiconductor layers 903, 907, 913, 916, and semiconductor layer 918 formed after patterning

[0153] A crystalline, microcrystalline, or amorphous semiconductor layer may be used, or the semiconductor layer may be crystallized by a known technique. Known crystallization methods include a laser crystallization method using a laser beam and a crystallization method using a catalyst element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method may be combined and used. Further, when a substrate having excellent heat resistance such as quartz is used as substrate 900, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalyst element, a high-temperature annealing method at about 950° C., or the like may be used. In addition, a wide-gap semiconductor such as an oxide semiconductor may be used for semiconductor layers 903, 907, 913, 916, and 918. When an oxide semiconductor is used for semiconductor layers 903, 907, 913, 916, and 918, a dopant is added to the semiconductor layer to form an impurity region that functions as a source or a drain. The dopant may be added by using an ion implantation method. The dopant may be, for example, a noble gas such as helium, argon, or xenon, or a group 15 atom such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is desirably 5×10 / cm or more and 1×10 / cm or less. Note that in the light-emitting device according to one aspect of the present invention, a color filter method of displaying a full-color image is performed by combining a light-emitting element that emits monochromatic light such as white light and a color filter. Also, when using a substrate with excellent heat resistance like quartz as substrate 900, methods such as thermal crystallization using an electric furnace, lamp annealing crystallization using infrared light, crystallization using a catalyst element, high-temperature annealing around 950 °C, etc. can be used. Moreover, for semiconductor layers 903, 907, 913, 916, and semiconductor layer 918, a wide-gap semiconductor such as an oxide semiconductor can be used. When using an oxide semiconductor for semiconductor layers 903, 907, 913, 916, and semiconductor layer 918, a dopant is added to the semiconductor layer to form an impurity region that functions as a source or a drain. The addition of the dopant can use the ion implantation method.

[0154] The dopant can be, for example, noble gases such as helium, argon, xenon, or group 15 atoms such as nitrogen, phosphorus, arsenic, antimony, etc. For example, when using nitrogen as the dopant, the concentration of nitrogen atoms in the impurity region is desirably 5×10 / cm or more and 1×10 / cm or less. In the light-emitting device according to one aspect of the present invention, a color filter method for displaying a full-color image is achieved by combining a light-emitting element that emits monochromatic light such as white light and a color filter. Also, a crystalline, microcrystalline, or amorphous semiconductor layer can be used, or the semiconductor layer can be crystallized by known techniques. Known crystallization methods include laser crystallization using a laser beam and crystallization using a catalyst element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method can be combined and used. When using a substrate with excellent heat resistance like quartz as substrate 900, methods like thermal crystallization using an electric furnace, lamp annealing crystallization using infrared light, crystallization using a catalyst element, high-temperature annealing around 950 °C, etc. can be used. Furthermore, for semiconductor layers 903, 907, 913, 916, and semiconductor layer 918, a wide-gap semiconductor such as an oxide semiconductor can be used. 19 / cm 3 When using an oxide semiconductor for semiconductor layers 903, 907, 913, 916, and semiconductor layer 918, a dopant is added to the semiconductor layer to form an impurity region that functions as a source or a drain. 0 22 / cm 3 The addition of the dopant can use the ion implantation method.

[0155] Note that in the light-emitting device according to one aspect of the present invention, a color filter method of displaying a full-color image is performed by combining a light-emitting element that emits monochromatic light such as white light and a color filter. can be adopted. Alternatively, a method of using a plurality of light-emitting elements that emit lights of different hues can be adopted to perform full-color image display. In this method, in order to separately apply an electroluminescent layer provided between a pair of electrodes of the light-emitting element for each corresponding color, it is called the separation method. In the case of the separation method, the separation of the electroluminescent layer is usually performed by vapor deposition using a mask such as a metal mask. Therefore, the pixel size depends on the

[0156] precision of the separation of the electroluminescent layer by vapor deposition. On the other hand, in the case of the color filter method, unlike the separation method, it is not necessary to separate the electroluminescent layer. Therefore, it is easier to reduce the pixel size than in the case of the separation method, and a high-definition pixel portion can be realized. In addition, the light-emitting device has a bottom emission structure that extracts the light of the light-emitting element from the element substrate side, such as a substrate 800 or a substrate 900 on which a transistor is formed, and a top emission

[0157] structure that extracts the light of the light-emitting element from the side opposite to the element substrate. In the case of the top emission structure, the light emitted from the light-emitting element is not blocked by various elements such as wirings, transistors, and storage capacitors. Therefore, compared with the bottom emission structure, the extraction efficiency of light from the pixel can be increased. Therefore, the top emission structure is advantageous for extending the lifespan of the light-emitting element because high luminance can be obtained even when the current value supplied to the light-emitting element is kept low.

[0158] Further, the light-emitting device according to one aspect of the present invention may have a microcavity (micro-optical resonator) structure that resonates the light emitted from the electroluminescent layer within the light-emitting element.​​​​​ Due to the cavity structure, the extraction efficiency of light of a specific wavelength from the light-emitting element can be increased, so that the luminance and color purity of the pixel portion can be improved.

[0159] FIG. 10 shows, as an example, a cross-sectional view of a pixel having a microcavity structure. Note that in FIG. 10, a part of the cross-section of the pixel corresponding to red, a part of the cross-section of the pixel corresponding to blue, and a part of the cross-section of the pixel corresponding to green are shown.

[0160] Specifically, in FIG. 10, a pixel 140r corresponding to red, a pixel 140g corresponding to green, and a pixel 140b corresponding to blue are shown. The pixel 140r, the pixel 140g, and the pixel 140b each have anodes 715r, 715g, and 715b. The above anodes 715r, 715g, and 715b are provided on the insulating film 750 formed on the substrate 740 in each of the pixel 140r, the pixel 140g , and the pixel 140b.

[0161] And, on the anodes 715r, 715g, and 715b, a partition wall 730 having an insulating film is provided. The partition wall 730 has an opening, and in the above opening, the anodes 715r, 715g, and 715b are partially exposed . Further, on the partition wall 730 so as to cover the exposed region, an electroluminescent layer 731 and a cathode 732 having translucency to visible light are laminated in order. The overlapping portion of the anode 715r, the electroluminescent layer 731, and the cathode 732 corresponds to the light-emitting element 741r corresponding to red. The anode 715g, the electroluminescent layer 731, and the cathode

[0162] 732 corresponds to the light-emitting element 741g corresponding to green. The anode 715g, the electroluminescent layer 731, and the cathode ​​​​The overlapping portion with 732 corresponds to the light-emitting element 741g corresponding to green. Anode 715b The overlapping portion of the anode 715b, the electroluminescent layer 731, and the cathode 732 corresponds to the light-emitting element 74 1b corresponding to blue.

[0163] Also, the substrate 742 faces the substrate 740 so as to sandwich the light-emitting element 741r, the light-emitting element 741g, and the light-emitting element 741b therebetween. On the substrate 742, there are provided a coloring layer 743r corresponding to the pixel 140r, a coloring layer 743g corresponding to the pixel 140g, and a coloring layer 743b corresponding to the pixel 140b. The coloring layer 743r is a layer having a higher transmittance of light in the wavelength region corresponding to red than the transmittance of light in other wavelength regions, and the coloring layer 743g is a layer having a higher transmittance of light in the wavelength region corresponding to green than the transmittance of light in other wavelength regions, and the coloring layer 743b is a layer having a higher transmittance of light in the wavelength region corresponding to blue than the transmittance of light in other wavelength regions. Furthermore, an overcoat 744 is provided on the substrate 742 so as to cover the coloring layer 743r, the coloring layer 743g, and the coloring layer 743b. The overcoat 744 is a layer having light transmittance with respect to visible light for protecting the coloring layer 743 r, the coloring layer 743g, and the coloring layer 743b, and it is preferable to use a resin material having high flatness. The coloring layer 743r, the coloring layer 743 g, and the coloring layer 743b and the overcoat 744 may be regarded as a color filter together, or each of the coloring layer 743r, the coloring layer 743g, and the coloring layer 743b may be regarded as a color filter.

[0164] And in FIG. 10, on the anode 715r, a conductive film 745r having a high reflectance of visible light and a visible

[0165] ​​​​​​​​A conductive film 746r having a higher light transmittance in the visible light range than the above conductive film 745r is laminated and used in this order. . Further, on the anode 715g, a conductive film 745g having a high reflectance of visible light and a visible light transmittance higher than that of the above conductive film 745g, namely a conductive film 746g, are laminated and used in this order. The film thickness of the conductive film 74 6g is made smaller than the film thickness of the conductive film 746r. Further, on the anode 715b , a conductive film 745b having a high reflectance of visible light is used.

[0166] Therefore, in the light-emitting device shown in FIG. 10, in the light-emitting element 741r, the optical path length of the light emitted from the electroluminescent layer 731 can be adjusted by the distance between the conductive film 745r and the cathode 732. Also, in the light-emitting element 741g, the optical path length of the light emitted from the electroluminescent layer 731 can be adjusted by the distance between the conductive film 745g and the cathode 732. Further, in the light-emitting element 741b, the optical path length of the light emitted from the electroluminescent layer 731 can be adjusted by the distance between the conductive film 745b and the cathode 732.

[0167] In one aspect of the present invention, a microcavity structure may be provided in which the optical path lengths are adjusted in accordance with the wavelengths of the light corresponding to the light-emitting element 741r, the light-emitting element 741g, and the light-emitting element 741b respectively, so as to resonate the light emitted from the electroluminescent layer 731 within each of the above light-emitting elements. For example, in the case of FIG. 10, if the distance between the conductive film 745r, the conductive film 745g, or the conductive film 745 b and the cathode 732 is L, the refractive index of the electroluminescent layer 731 is n, and the wavelength of the light to be resonated is λ, it is preferable that the product of the distance L and the refractive index n is (2N - 1) / 4 times the wavelength λ (N is a natural number).

[0168] By adopting the above microcavity structure in the light-emitting device according to one aspect of the present invention, in the light emitted from the light-emitting element 741r, the intensity of the light having a wavelength corresponding to red is increased by resonance. Therefore, the color purity and luminance of the red light obtained through the coloring layer 743r are increased. Also, in the light emitted from the light-emitting element 741g, the intensity of the light having a wavelength corresponding to green is increased by resonance. Therefore, the color purity and luminance of the green light obtained through the coloring layer 743g are increased. In addition, in the light emitted from the light-emitting element 741b, the intensity of the light having a wavelength corresponding to blue is increased by resonance. Therefore, the color purity and luminance of the blue light obtained through the coloring layer 743b are increased.

[0169] In FIG. 10, a configuration using pixels corresponding to three colors of red, green, and blue is shown. However, in one aspect of the present invention, the configuration is not limited thereto. The combination of colors used in one aspect of the present invention is , for example, four colors of red, green, blue, and yellow, or three colors of cyan, magenta, and yellow may be used. Alternatively, the combination of the above colors may be six colors of light red, green, and blue, and dark red, green, and blue. Alternatively, the combination of the above colors may be six colors of red, green, blue, cyan, magenta, and yellow.

[0170] Note that, for example, the colors that can be expressed using pixels of red, green, and blue are limited to the colors shown inside the triangle drawn by three points corresponding to the respective emission colors on the chromaticity diagram. Therefore, as in the case of using pixels of red, green, blue, and yellow, by separately adding a light-emitting element having an emission color outside the triangle on the chromaticity diagram, the color gamut that can be expressed in the light-emitting device can be expanded, and the color reproducibility can be enriched.

[0171] ​​ Also, in FIG. 10, among the light-emitting elements 741r, 741g, and 741b, for the light-emitting element 741b with the shortest light wavelength λ, a conductive film 745b with a high reflectance of visible light is used as the anode, and for the other light-emitting elements 741r and 741g, by using conductive films 746r and 746g with different film thicknesses from each other, the optical path length is adjusted. In one aspect of the present invention, even for the light-emitting element 741b with the shortest wavelength λ, a conductive film such as the conductive films 746r and 746g with a high transmittance of visible light may be provided on the conductive film 745b with a high reflectance of visible light. However, as shown in FIG. 10, in the case where the conductive film 745b with a high reflectance of visible light constitutes the anode in the light-emitting element 741b with the shortest wavelength λ, for all the light-emitting elements, compared with the case of using a conductive film with a high transmittance of visible light for the anode, since the manufacturing process of the anode is simplified, it is preferable. Note that the conductive film 745b with a high reflectance of visible light often has a smaller work function compared to the conductive films 746r and 746g with a high transmittance of visible light. Therefore, in the light-emitting element 741b with the shortest light wavelength λ, compared with the light-emitting elements 741r and 741g, hole injection from the anode 71 5b to the electroluminescent layer 731 is difficult, and thus the luminous efficiency tends to be low. Therefore, in one aspect of the present invention, in the light-emitting element 741b with the shortest light wavelength λ, in the layer of the electroluminescent layer 731 that contacts the conductive film 745b with a high reflectance of visible light, it is preferable to use a composite material in which a substance with high hole-transporting properties contains a substance that exhibits acceptor properties (electron-accepting properties) with respect to the substance with high hole-transporting properties. The above composite material is used for the anode 71 5b. 5b to the electroluminescent layer 731 is difficult, and thus the luminous efficiency tends to be low. Therefore, in one aspect of the present invention, in the light-emitting element 741b with the shortest light wavelength λ, in the layer of the electroluminescent layer 731 that contacts the conductive film 745b with a high reflectance of visible light, it is preferable to use a composite material in which a substance with high hole-transporting properties contains a substance that exhibits acceptor properties (electron-accepting properties) with respect to the substance with high hole-transporting properties. The above composite material is used for the anode 71 5b. 5b.

[0172] Note that the conductive film 745b with a high reflectance of visible light often has a smaller work function compared to the conductive films 746r and 746g with a high transmittance of visible light. Therefore, in the light-emitting element 741b with the shortest light wavelength λ, compared with the light-emitting elements 741r and 741g, hole injection from the anode 71 5b to the electroluminescent layer 731 is difficult, and thus the luminous efficiency tends to be low. Therefore, in one aspect of the present invention, in the light-emitting element 741b with the shortest light wavelength λ, in the layer of the electroluminescent layer 731 that contacts the conductive film 745b with a high reflectance of visible light, it is preferable to use a composite material in which a substance with high hole-transporting properties contains a substance that exhibits acceptor properties (electron-accepting properties) with respect to the substance with high hole-transporting properties. The above composite material is used for the anode 71 5b. 5b to the electroluminescent layer 731 is difficult, and thus the luminous efficiency tends to be low. Therefore, in one aspect of the present invention, in the light-emitting element 741b with the shortest light wavelength λ, in the layer of the electroluminescent layer 731 that contacts the conductive film 745b with a high reflectance of visible light, it is preferable to use a composite material in which a substance with high hole-transporting properties contains a substance that exhibits acceptor properties (electron-accepting properties) with respect to the substance with high hole-transporting properties. The above composite material is used for the anode 71 5b. 5b. 5b. 5b. By forming in contact with 5b, hole injection from the anode 715b to the electroluminescent layer 731 is facilitated, and the luminous efficiency of the light-emitting element 741b can be increased.

[0173] Examples of the substance showing acceptor properties include 7,7,8,8-tetracyano-2,3,5,6- tetrafluoroquinodimethane (abbreviation: F4-TCNQ), chloranil, etc. In addition, transition metal oxide compounds can be mentioned. Also, oxides of metals belonging to Group 4 to Group 8 in the periodic table of elements can be mentioned. Specifically, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide are preferable because of their high acceptor properties. Among them, molybdenum oxide is preferable because it is stable in the atmosphere, has low hygroscopicity, and is easy to handle.

[0174] Examples of the substance having high hole transport properties used for the composite material include aromatic amine compounds, carbazole derivatives, conductors, aromatic hydrocarbons, polymer compounds (oligomers, dendrimers, polymers, etc.), and various compounds can be used. Note that as the organic compound used for the composite material, it is preferably an organic compound having high hole transport properties. Specifically, 10 cm -6 cm 2 / Vs or more It is preferably a substance having a hole mobility of. However, as long as it is a substance having higher hole transport properties than electrons, other substances may be used.

[0175] In addition, as the conductive films 745r, 745g, and 745b having high reflectance of visible light, for example, aluminum, silver, or an alloy containing these metal materials, etc., are used as a single layer, or can be formed by laminating. Also, the conductive film 745r, the conductive film 745g, and the conductive film 745b may be formed by laminating a conductive film with a high visible light reflectance and a conductive film with a thin film thickness (preferably 20 nm or less, more preferably 10 nm or less). For example, a thin titanium film or molybdenum film is laminated on a conductive film with a high visible light reflectance to form the conductive film 745b , thereby preventing the formation of an oxide film on the surface of a conductive film with a high visible light reflectance (such as aluminum, an alloy containing aluminum, or silver).

[0176] Also, for the conductive film 746r and the conductive film 746g with high visible light transmittance, for example, indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide, etc. can be used.

[0177] Also, the cathode 732 can be formed by laminating a conductive film that is thin enough to transmit light (preferably 20 nm or less, more preferably 10 nm or less) and a conductive film composed of a conductive metal oxide. The conductive film that is thin enough to transmit light can be formed by a single layer or by laminating silver, magnesium, or an alloy containing these metal materials. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide, or a material obtained by adding silicon oxide to these metal oxide materials can be used.

[0178] This embodiment can be implemented in appropriate combination with other embodiments.

[0179] (Embodiment 3) In this embodiment, an example of a specific configuration of the light-emitting device of the present invention will be described. In FIG. 11 、As an example, a block diagram of the light-emitting device according to this embodiment is shown. Note that in the block diagram shown in FIG. 11 the circuit in the light-emitting device is classified by function and shown as independent blocks from each other. However, in an actual circuit, it is difficult to completely separate the circuit by function, and one circuit may be related to multiple functions

[0180] The light-emitting device shown in FIG. 11 includes a pixel section 500 having a plurality of pixels, a scanning line driving circuit 510 that selects each pixel line by line, and a signal line driving circuit 520 that controls the input of an image signal to the pixels of the selected line

[0181] As the configuration of the pixel section 500, for example, the configuration of the pixel section in the light-emitting device shown in Embodiment 1 above can be applied

[0182] The signal line driving circuit 520 includes a shift register 521, a first storage circuit 522, a second storage circuit 523, and a DA conversion circuit 524. A clock signal S-CLK and a start pulse signal S-SP are input to the shift register 521. The shift register 521 generates a timing signal in which pulses are sequentially shifted according to these clock signal S-CLK and start pulse signal S-SP, and outputs the timing signal to the first storage circuit 522. The order in which the pulses of the timing signal appear may be switched according to the scanning direction switching signal

[0183] When the timing signal is input to the first storage circuit 522, the image signal is sequentially written and held in the first storage circuit 522 according to the pulses of the timing signal. Note that the image signal may be sequentially written to a plurality of storage circuits included in the first storage circuit 522, but the first storage ​​​​​​​​​​​​Divide the plurality of memory circuits included in circuit 522 into several groups, and perform so-called divided driving in which the image signals are input in parallel for each group. This may be performed.

[0184] Until the writing of the image signal to all the memory circuits of the first memory circuit 522 is completed once. The time is called a line period. Actually, the horizontal blanking period may be included in the line period.

[0185] When one line period ends, according to the pulse pattern of the latch signal S-LS input to the second memory circuit 523, the image signal held in the first memory circuit 522 is simultaneously written to the second memory circuit 523 and held. After the image signal has been sent to the second memory circuit 523, the first memory circuit 522 writes the next image signal sequentially according to the timing signal from the shift register 521 again. During this second line period, the image signal written and held in the second memory circuit 523 is input to the DA conversion circuit 524.

[0186] Then, the DA conversion circuit 524 converts the input digital image signal into an analog image signal and inputs it to each pixel in the pixel unit 500 via the signal line.

[0187] Note that the signal line driving circuit 520 may use another circuit that can output a signal in which pulses are sequentially shifted instead of the shift register 521.

[0188] Also, in FIG. 11, the pixel unit 500 is directly connected to the subsequent stage of the DA conversion circuit 524, but the present invention is not limited to this configuration. In front of the pixel unit 500, from the output of the DA conversion circuit 524 ​​​​​​​​​A circuit for performing signal processing on the obtained image signal can be provided. An example of a circuit for performing signal processing includes, for example, a buffer, a level shifter, and the like.

[0189] Next, the operation of the scanning line driving circuit 510 will be described. The scanning line driving circuit 510 generates a selection signal that sequentially shifts pulses, and inputs the selection signal to a plurality of scanning lines, thereby selecting pixels line by line. When a pixel is selected by the selection signal, a plurality of transistors each having a gate electrically connected to one of the scanning lines are appropriately turned on or off, and each signal or the supply of the power supply potential is performed. Note that the pixel portion 500, the scanning line driving circuit 510, and the signal line driving circuit 520 can be formed on the same substrate, but any of them can also be formed on a different substrate.

[0190] This embodiment can be implemented in appropriate combination with the above embodiment.

[0191]

[0192] (Embodiment 4) In this embodiment, an example of a specific configuration of the light-emitting device of the present invention will be described. FIG. 12 shows , as an example, a block diagram of the light-emitting device in this embodiment. Note that in the block diagram shown in FIG. 12, the circuits in the light-emitting device are classified by function and shown as independent blocks from each other. However, in an actual circuit, it is difficult to completely separate the circuits by function, and one circuit may be related to multiple functions as well.

[0193] The light-emitting device of the present invention shown in FIG. 12 includes a pixel portion 600 having a plurality of pixels, a scanning line driving circuit 610 that selects the plurality of pixels line by line, and an image signal to the pixels in the selected line ​​​​​It has a signal line driving circuit 620 for controlling the input.

[0194] As the configuration of the pixel portion 600, for example, the configuration of the pixel portion in the light-emitting device shown in the above-described Embodiment 1 can be applied. It can be applied.

[0195] The signal line driving circuit 620 includes at least a shift register 621, a sampling circuit 622, and a storage circuit 623 capable of storing an analog signal. The shift register 621 receives a clock signal S-CLK and a start pulse signal S-SP. The shift register 621 generates a timing signal in which pulses are sequentially shifted according to these clock signal S-CLK and start pulse signal S-SP, and inputs it to the sampling circuit 622. In the sampling circuit 622, according to the input timing signal, an analog image signal for one line period input to the signal line driving circuit 620 is sampled. When all the image signals for one line period are sampled, the sampled image signals are output to the storage circuit 623 all at once according to the latch signal S-LS and held. The image signal held in the storage circuit 623 is input to the pixel portion 600 via a signal line. It has at least a shift register 621, a sampling circuit 622, and a storage circuit 623 capable of storing an analog signal. The shift register 621 receives a clock signal S-CLK and a start pulse signal S-SP. The shift register 621 generates a timing signal in which pulses are sequentially shifted according to these clock signal S-CLK and start pulse signal S-SP, and inputs it to the sampling circuit 622. In the sampling circuit 622, according to the input timing signal, an analog image signal for one line period input to the signal line driving circuit 620 is sampled. When all the image signals for one line period are sampled, the sampled image signals are output to the storage circuit 623 all at once according to the latch signal S-LS and held. The image signal held in the storage circuit 623 is input to the pixel portion 600 via a signal line. The shift register 621 receives a clock signal S-CLK and a start pulse signal S-SP. The shift register 621 generates a timing signal in which pulses are sequentially shifted according to these clock signal S-CLK and start pulse signal S-SP, and inputs it to the sampling circuit 622. The shift register 621 generates a timing signal in which pulses are sequentially shifted according to these clock signal S-CLK and start pulse signal S-SP, and inputs it to the sampling circuit 622. According to these clock signal S-CLK and start pulse signal S-SP, it generates a timing signal in which pulses are sequentially shifted, and inputs it to the sampling circuit 622. In the sampling circuit 622, according to the input timing signal, an analog image signal for one line period input to the signal line driving circuit 620 is sampled. In the sampling circuit 622, according to the input timing signal, an analog image signal for one line period input to the signal line driving circuit 620 is sampled. When all the image signals for one line period are sampled, the sampled image signals are output to the storage circuit 623 all at once according to the latch signal S-LS and held. When all the image signals for one line period are sampled, the sampled image signals are output to the storage circuit 623 all at once according to the latch signal S-LS and held. The image signal held in the storage circuit 623 is input to the pixel portion 600 via a signal line.

[0196] In this embodiment, the case where, after sampling all the image signals for one line period in the sampling circuit 622, the sampled image signals are input to the lower-stage storage circuit 623 all at once is taken as an example for explanation, but the present invention is not limited to this configuration. After sampling the image signal corresponding to each pixel in the sampling circuit 622, without waiting for one line period, the sampled image signal may be input to the lower-stage storage circuit 623 each time. In this embodiment, the case where, after sampling all the image signals for one line period in the sampling circuit 622, the sampled image signals are input to the lower-stage storage circuit 623 all at once is taken as an example for explanation, but the present invention is not limited to this configuration. After sampling the image signal corresponding to each pixel in the sampling circuit 622, without waiting for one line period, the sampled image signal may be input to the lower-stage storage circuit 623 each time. In this embodiment, the case where, after sampling all the image signals for one line period in the sampling circuit 622, the sampled image signals are input to the lower-stage storage circuit 623 all at once is taken as an example for explanation, but the present invention is not limited to this configuration. After sampling the image signal corresponding to each pixel in the sampling circuit 622, without waiting for one line period, the sampled image signal may be input to the lower-stage storage circuit 623 each time. After sampling the image signal corresponding to each pixel in the sampling circuit 622, without waiting for one line period, the sampled image signal may be input to the lower-stage storage circuit 623 each time. After sampling the image signal corresponding to each pixel in the sampling circuit 622, without waiting for one line period, the sampled image signal may be input to the lower-stage storage circuit 623 each time. It may be.

[0197] Also, the sampling of the image signal may be performed sequentially for each corresponding pixel, or the pixels within one line may be divided into several groups, and sampling may be performed in parallel for each pixel corresponding to each group.

[0198] In FIG. 12, the pixel unit 600 is directly connected to the subsequent stage of the memory circuit 623, but the present invention is not limited to this configuration. A circuit for performing signal processing may be provided in the previous stage of the pixel unit 600 on the analog image signal output from the memory circuit 623. Examples of the circuit for performing signal processing include a buffer that can, for example, shape the waveform.

[0199] And, in parallel with the input of the image signal from the memory circuit 623 to the pixel unit 600, the sampling ring circuit 622 can sample the image signal corresponding to the next line period again.

[0200] Next, the operation of the scanning line driving circuit 610 will be described. The scanning line driving circuit 610 generates a selection signal whose pulses shift sequentially, and inputs the selection signal to a plurality of scanning lines to select pixels line by line. When a pixel is selected by the selection signal, a plurality of transistors each having its gate electrically connected to one of the scanning lines are appropriately turned on or off, and each signal or power supply potential is supplied.

[0201] Note that the pixel unit 600, the scanning line driving circuit 610, and the signal line driving circuit 620 can be formed on the same substrate, but any of them can also be formed on a different substrate.

[0202] This embodiment can be implemented in appropriate combination with the above-described embodiment.

[0203] ​(Embodiment 5) FIG. 13 is an example of a perspective view of a light-emitting device according to an aspect of the present invention. In FIG. 13, the light-emitting device in the above-described embodiment is illustrated when used in a display unit.

[0204] The light-emitting device shown in FIG. 13 includes a display unit 1601, a circuit board 1602, and a connection unit 1603. It has.

[0205] An image processing unit is provided on the circuit board 1602, and various signals and a power supply potential are input to the display unit 1601 via the connection unit 1603. The connection unit 1603 can use an FPC (Flexible Printed Circuit), etc. Also, when a COF tape is used for the connection unit 16 03, a part of the circuit of the image processing unit or a part of the driving circuit included in the display unit 1601 is formed on a separately prepared chip, and the COF (Chip On Film) method may be used to connect the chip to the COF tape. This embodiment can be implemented in combination with the above-described embodiment.

[0206] This embodiment can be implemented in combination with the above embodiment.

[0207] (Embodiment 6) Not limited to oxide semiconductors, the field-effect mobility of an actually measured insulated-gate type transistor is lower than the original mobility for various reasons. As factors that reduce mobility there are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. However, using the Levinson model it is possible to theoretically derive the field-effect mobility when it is assumed that there are no defects inside the semiconductor. Therefore, in this embodiment, the field effect mobility of an ideal oxide semiconductor without defects inside the semiconductor is theoretically derived, and using such an oxide semiconductor, a fine transistor is formed. The calculation results of the characteristics when a dister is fabricated are shown.

[0208] Assuming that the intrinsic mobility of the semiconductor is μ0 and the measured field-effect mobility is μ, and that there is some potential barrier (such as grain boundaries) in the semiconductor, it can be expressed by the following formula. Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature.

[0209]

Equation

[0210] Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, assuming that the potential barrier is due to defects, in the Levinson model, it is expressed by the following formula.

[0211]

Equation

[0212] Here, e is the elementary charge, N is the average defect density per unit area in the channel, ε is the dielectric constant of the semiconductor, n is the number of carriers contained in the channel per unit area, C is the capacitance per unit area ox , Vg is the gate voltage, and t is the thickness of the channel. Note that for a semiconductor layer with a thickness of 30 nm or less, the thickness of the channel can be regarded as the same as the thickness of the semiconductor layer without problem. In the linear region, the drain current I is as follows. Here, L is the channel length, W is the channel width, and here, L = W = 10 μm. d is given by the following formula.

[0213]

Equation

[0214] Here, L is the channel length, W is the channel width, and here, L = W = 10 μm. Also, V dis the drain voltage. Divide both sides of the above equation by V g and then take the logarithm of both sides, we get as follows.

[0215]

Equation

[0216] The right side of Equation 7 is a function of V g . As can be seen from this equation, the defect density N can be obtained from the slope of the straight line with the vertical axis being ln(Id / V g ), the horizontal axis being 1 / V g . That is, the defect density can be evaluated from the I -V d characteristics of the transistor. As for the oxide semiconductor, when the ratio of indium (I g n), tin (Sn), and zinc (Zn) is In:Sn:Zn = 1:1:1, the defect density N is about 1×10 / cm 12 . 2

[0217] Based on the defect density obtained in this way, from Equations 4 and 5, μ0 = 120 cm 2 / Vs is derived. The mobility measured in the defective In-Sn-Zn-based oxide is about 35 cm 2 / Vs. However, even if there are no defects inside the semiconductor, the transport characteristics of the transistor are affected by scattering at the interface between the channel and the gate insulator. That is, the mobility μ1 at a location x away from the gate insulator interface is expressed by the following equation. The mobility μ0 of the oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film can be predicted to be 120 cm 2 / Vs.

[0218] However, even if there are no defects inside the semiconductor, the transport characteristics of the transistor are affected by scattering at the interface between the channel and the gate insulator. That is, the mobility μ1 at a location x away from the gate insulator interface is expressed by the following equation. The mobility μ1 at a location x away from the gate insulator interface is expressed by the following equation.

[0219] [Number]

[0220] Here, D is the electric field in the gate direction, and B and G are constants. B and G can be obtained from actual measurement results. From the above measurement results, B = 4.75×10 cm / s, G = 10 7 nm (depth affected by interface scattering). As D increases (i.e., the gate voltage increases), the second term in Equation (8) increases, so it can be seen that the mobility μ1 decreases.

[0221] Figure 18 shows the results of calculating the mobility μ2 of a transistor using an ideal oxide semiconductor without defects in the channel as the channel. Note that for the calculation, the device simulation software Sentaurus Device manufactured by Synopsys was used, and the bandgap, electron affinity, relative permittivity, and thickness of the oxide semiconductor were set to 2.8 electron volts, 4.7 electron volts, 15, and 15 nm, respectively. These values were obtained by measuring a thin film formed by sputtering. Furthermore, the work functions of the gate, source, and drain were set to 5.5 electron volts, 4.6 electron volts, and 4.6 electron volts, respectively. Also, the thickness of the gate insulator was 100 nm and the relative permittivity was 4.1. Both the channel length and channel width were 10 μm, and the drain voltage V

[0222] was 0 .1 V. d .1 V.

[0223] As shown in Figure 18, a peak with a mobility of 100 cm 2 / Vs or more appears at a gate voltage 1 V higher, but as the gate voltage further increases, interface scattering increases and the mobility decreases. In order to reduce interface scattering, it is desirable to flatten the surface of the semiconductor layer at the atomic level (Atomic Layer Flatness). omic Layer Flatness)

[0224] The characteristics when a fine transistor is fabricated using an oxide semiconductor having such mobility are shown in FIGS. 19 to 21. Note that the cross-sectional structure of the transistor used in the calculation is shown in FIG. 22. The transistor shown in FIG. 22 has semiconductor regions 8103a and 8103c that exhibit an n-type conductivity type in the oxide semiconductor layer. The resistivity of the semiconductor regions 8103a and 8103c is set to 2×10 Ωcm. + type conductivity in the oxide semiconductor layer. The transistor shown in FIG. 22(A) is formed on an embedded insulator 8102 made of aluminum oxide formed so as to be embedded in a base insulator 8101. The transistor has semiconductor regions 8103a, 8103c, a true semiconductor region 8103b that is sandwiched between them and serves as a channel formation region, and a gate 8105. -3 Ωcm.

[0225] The transistor shown in FIG. 22(A) is formed on a base insulator 8101 and on an embedded insulator 8102 made of aluminum oxide formed so as to be embedded in the base insulator 8101. The transistor has semiconductor regions 8103a, 8103c, a true semiconductor region 8103b that is sandwiched between them and serves as a channel formation region, and a gate 8105. The width of the gate 8105 is 33 nm. There is a gate insulator 8104 between the gate 8105 and the semiconductor region 8103b. Also, sidewall insulators 8106a and 8106b are provided on both side surfaces of the gate 8105, and an insulator 8107 for preventing a short circuit between the gate 8105 and other wirings is provided on the upper part of the gate 8105. The width of the sidewall insulator is 5 nm. Also, a source 8108a and a drain 8108b are provided in contact with the semiconductor regions 8103a and 8103c. Note that the channel width in this transistor is 40 nm. The width of the gate 8105 is 33 nm.

[0226] There is a gate insulator 8104 between the gate 8105 and the semiconductor region 8103b. Sidewall insulators 8106a and 8106b are provided on both side surfaces of the gate 8105, and an insulator 8107 for preventing a short circuit between the gate 8105 and other wirings is provided on the upper part of the gate 8105. The width of the sidewall insulator is 5 nm. Also, a source 8108a and a drain 8108b are provided in contact with the semiconductor regions 8103a and 8103c. Note that the channel width in this transistor is 40 nm. There are a source 8108a and a drain 8108b in contact with the semiconductor regions 8103a and 8103c. Note that the channel width in this transistor is 40 nm.

[0227] The transistor shown in Fig. 22(B) includes a base insulator 8101 and an embedded insulator 8102 made of aluminum oxide. It is formed on the embedded insulator 8102 and has a semiconductor region 8103a, a semiconductor region 8103c, a true semiconductor region 8103b sandwiched therebetween, a gate 8105 with a width of 33 nm, a gate insulator 8104, sidewall insulators 8106a and 8106b, an insulator 8107, a source 8108a, and a drain 8108b, and is the same as the transistor shown in Fig. 22(A) in this regard. and a gate insulator 8104, sidewall insulators 8106a and 8106b, an insulator 8107, a source 8108a, and a drain 8108b. The difference between the transistor shown in Fig. 22(A) and the transistor shown in Fig. 22(B) lies in the conductivity type of the semiconductor region under the sidewall insulators 8106a and 8106b. In the transistor shown in Fig. 22(A), the semiconductor regions under the sidewall insulators 8106a and 8106b are semiconductor regions 8103a and 8103c having an n-type conductivity type, while in the transistor shown in Fig. 22(B), it is the true semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b).

[0228] The difference between the transistor shown in Fig. 22(A) and the transistor shown in Fig. 22(B) is the conductivity type of the semiconductor region under the sidewall insulators 8106a and 8106b. In the transistor shown in Fig. 22(A), the semiconductor regions under the sidewall insulators 8106a and 8106b are semiconductor regions 8103a and 8103c having an n-type conductivity type, while in the transistor shown in Fig. 22(B), it is the true semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). type semiconductor regions 8103a and 8103c, + while in the transistor shown in Fig. 22(B), it is the true semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). while in the transistor shown in Fig. 22(B), it is the true semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much is formed. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b).

[0229] Other parameters used in the calculation are as described above. Sentaurus Device, a device simulation software manufactured by Synopsys, was used for the calculation. Fig. 19 shows the drain current (Id, solid line) and mobility of the transistor having the structure shown in Fig. 22(A). Other parameters used in the calculation are as described above. Sentaurus Device, a device simulation software manufactured by Synopsys, was used for the calculation. Fig. 19 shows the drain current (Id, solid line) and mobility of the transistor having the structure shown in Fig. 22(A). of the transistor having the structure shown in Fig. 22(A) (Id, solid line) and mobility (μ, dotted line) shows the gate voltage (Vg, potential difference between the gate and the source) dependence. The drain current Id is calculated with the drain voltage (potential difference between the drain and the source) set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V.

[0230] Figure 19(A) shows a gate insulating film with a thickness of 15nm, Figure 19(B) shows one with a thickness of 10n m, and Figure 19(C) shows one with a thickness of 5nm. The thinner the gate insulating film, especially the drain current Id (off-current) in the off-state decreases significantly. On the other hand, there is no obvious change in the peak value of the mobility μ and the drain current Id (on-current) in the on-state. It was shown that it exceeds 10 μA around the gate voltage of 1V.

[0231] Figure 20 shows the gate voltage Vg dependence of the drain current Id (solid line) and the mobility μ (dotted line) of a transistor with the structure shown in Figure 22(B), where the offset length Loff is 5n m. The drain current Id is calculated with the drain voltage set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. Figure 20(A) shows a gate insulating film with a thickness of 15nm, Figure 20(B) shows one with a thickness of 10nm, and Figure 20(C) shows one with a thickness of 5nm.

[0232] Also, Figure 21 shows the gate voltage dependence of the drain current Id (solid line) and the mobility μ (dotted line) of a transistor with the structure shown in Figure 22(B), where the offset length Loff is 15nm. The drain current Id is calculated with the drain voltage set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. Figure 21(A) shows a gate insulating film with a thickness of 15n m. was set to m, FIG. 21(B) was set to 10 nm, and FIG. 21(C) was set to 5 nm is what is obtained by setting it to this value.

[0233] In all cases, as the gate insulating film becomes thinner, the off-current decreases significantly, while the peak value of the mobility μ and the on-current do not show a noticeable change. There is no significant change in the peak value of the mobility μ and the on-current.

[0234] The peak of the mobility μ is about 80 cm 2 / Vs in FIG. 19, but about 60 cm 2 / Vs in FIG. 20, and about 40 cm 2 / Vs in FIG. 21, and it decreases as the offset length Loff increases. Also, the off-current shows a similar tendency. On the other hand, the on-current decreases as the offset length L off increases, but it is much gentler compared to the decrease in the off-current. Moreover, it was shown that in all cases, it exceeds 10 μA around a gate voltage of 1 V.

[0235] (Embodiment 7) For a transistor having an oxide semiconductor containing In, Sn, and Zn as main components in the channel formation region, good characteristics can be obtained by heating the substrate during film formation of the oxide semiconductor, or by performing a heat treatment after forming the oxide semiconductor film. Here, the main component refers to an element contained at 5 atomic% or more in terms of the composition ratio. Therefore, in this embodiment, the case where the field-effect mobility of the transistor is improved by intentionally heating the substrate after forming the oxide semiconductor film will be described with reference to FIGS. 23 to 29. By intentionally heating the substrate after forming the oxide semiconductor film, it becomes possible to improve the field-effect mobility of the transistor. Also, for the transistor

[0236] After forming the oxide semiconductor film containing In, Sn, and Zn as main components, intentionally heating the substrate makes it possible to improve the field-effect mobility of the transistor. It becomes possible to shift the threshold voltage in the positive direction and achieve normally-off operation.

[0237] For example, FIGS. 23(A) to (C) show the characteristics of a transistor using an oxide semiconductor film containing In, Sn, and Zn as main components, with a channel length L of 3 μm and a channel width W of 10 μm, and a gate insulating film with a thickness of 100 nm. Note that Vd was set to 10 V.

[0238] FIG. 23(A) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by sputtering without intentionally heating the substrate. At this time, the field-effect mobility is 18.8 cm / Vsec. On the other hand, when the substrate is intentionally heated to form an oxide semiconductor film containing In, S 2 n, and Zn as main components, it becomes possible to improve the field-effect mobility. FIG. 23(B) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by heating the substrate to 200°C. The field-effect mobility is 32.2 cm / Vsec. The field-effect mobility can be further increased by performing heat treatment after forming an oxide semiconductor film containing In, Sn, and Zn as main components. FIG. 23(C) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by sputtering at 200°C and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm cm 2 / Vsec.

[0239] By intentionally heating the substrate, moisture during sputtering film formation is incorporated into the oxide semiconductor film. The field-effect mobility can be further increased. FIG. 23(C) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by sputtering at 200°C and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm / V sec. 2 / V sec.

[0240] By intentionally heating the substrate, moisture during sputtering film formation is incorporated into the oxide semiconductor film. An effect of reducing the occurrence can be expected. Also, by performing a heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field effect mobility can be improved as described above. Such an improvement in the field effect mobility is presumed to be due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, crystallization can be achieved by removing impurities from the oxide semiconductor to increase its purity. The non-single crystal oxide semiconductor thus purified to a high purity is ideally estimated to be capable of achieving a field effect mobility exceeding 100 cm / Vsec. Oxygen ions are implanted into an oxide semiconductor containing In, Sn, and Zn as main components, and hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor is released by heat treatment, and the oxide semiconductor may be crystallized by the heat treatment simultaneously with or after that. By such a crystallization or recrystallization treatment, a non-single crystal oxide semiconductor with good crystallinity can be obtained. The effects of intentionally heating the substrate during film formation and / or performing a heat treatment after film formation contribute not only to the improvement of the field effect mobility but also to making the transistor normally off. For a transistor having an oxide semiconductor film containing In, Sn, and Zn as main components formed without intentionally heating the substrate, the threshold voltage tends to shift negatively. However, in the case of using an oxide semiconductor film formed by intentionally heating the substrate, this negative shift of the threshold voltage is eliminated. That is, the threshold voltage moves in the direction of making the transistor normally off, and such a tendency is shown in FIGS. 23(A) and 23(B). 2

[0241]

[0242] ​ It can also be confirmed from the comparison with (1).

[0243] Note that the threshold voltage can also be controlled by changing the ratios of In, Sn, and Zn. It is possible, and by setting the composition ratio to In:Sn:Zn = 2:1:3, normal-off of the transistor can be expected. Also, by setting the target composition ratio to In:Sn:Zn = 2:1:3, a highly crystalline oxide semiconductor film can be obtained.

[0244] The intentionally set substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher, more preferably 400°C or higher. By depositing the film or performing heat treatment at a higher temperature, normal-off of the transistor can be achieved.

[0245] Also, by intentionally heating the substrate during film deposition and / or performing heat treatment after film deposition, the stability against gate bias stress can be enhanced. For example, under the conditions of applying 2 MV / cm, at 150°C for 1 hour, the drift can be less than ±1.5 V, preferably less than 1.0 V.

[0246] Actually, a BT test was performed on the transistors of sample 1 that was not heat-treated after depositing the oxide semiconductor film and sample 2 that was heat-treated at 650°C.

[0247] First, the substrate temperature was set to 25°C, Vd was set to 10 V, and the Vg-Id characteristics of the transistor were measured. Next, the substrate temperature was set to 150°C and Vd was set to 0.1 V. Next, 20 V was applied as Vg so that the electric field strength applied to the gate insulating film became 2 MV / cm, and it was held for 1 hour. Next, Vg was set to 0 V. Next, the substrate temperature was set to 25°C and Vd was set to 10 V. ​ The Vg-Id measurement of the transistor was performed. This is called the plus BT test.

[0248] Similarly, first, the substrate temperature was set to 25 °C, Vd was set to 10 V, and the Vg-Id characteristics of the transistor were measured. Next, the substrate temperature was set to 150 °C and Vd was set to 0.1 V. Next, -20 V was applied to Vg so that the electric field strength applied to the gate insulating film became -2 MV / cm, and it was held for 1 hour as it was. Next, Vg was set to 0 V. Next, the substrate temperature was set to 25 °C and Vd was set to 1 0 V, and the Vg-Id measurement of the transistor was performed. This is called the minus BT test.

[0249] The results of the plus BT test of Sample 1 are shown in Fig. 24(A), and the results of the minus BT test are shown in Fig. 24(B ). Also, the results of the plus BT test of Sample 2 are shown in Fig. 25(A), and the results of the minus BT test of Sample 2 are shown in Fig. 25(B).

[0250] The variations in the threshold voltage due to the plus BT test and the minus BT test of Sample 1 were 1.80 V and -0.42 V, respectively. Also, the variations in the threshold voltage due to the plus BT test and the minus BT test of Sample 2 were 0.79 V and 0.76 V, respectively. It can be seen that both Sample 1 and Sample 2 have small variations in the threshold voltage before and after the BT test, indicating high reliability.

[0251] The heat treatment can be performed in an oxygen atmosphere, but it may also be performed first in a nitrogen or inert gas atmosphere, or under reduced pressure and then in an atmosphere containing oxygen. By first performing dehydration and dehydrogenation and then adding oxygen to the oxide semiconductor, the effect of the heat treatment can be further enhanced. Also, to add oxygen later, oxygen ions can be accelerated by an electric field to the oxide semiconductor film Alternatively, a method of injecting the material into the cavity may be applied.

[0252] Defects due to oxygen vacancies are easily generated in oxide semiconductors and at the interface with the stacked films. By making the oxide semiconductor contain excess oxygen through such heat treatment, The excess oxygen is mainly contained in the interstitial The oxygen concentration is 1×10 16 / cm 3 More than 2×10 20 / cm 3 If the content is set to the above range, the oxide semiconductor can contain the metal oxide without causing distortion or the like to the crystal.

[0253] In addition, by making the oxide semiconductor contain crystals at least in part through heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. The oxide film was sputtered using a 1:1 target without intentionally heating the substrate. The semiconductor film was found to have a halo pattern by X-ray diffraction (XRD). The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be selected as desired, but for example, by performing heat treatment at 650°C, X-ray A clear diffraction peak can be observed by diffraction.

[0254] In fact, we performed XRD analysis of the In-Sn-Zn-O film. Using the AXS X-ray diffraction device D8 ADVANCE, the out-of-plane method was used. Measured.

[0255] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0256] An In-Sn-Zn-O film was formed on a dehydrogenated quartz substrate to a thickness of 100 nm. 。

[0257] The In-Sn-Zn-O film was formed using a sputtering apparatus with a power of 100 W ( DC) in an oxygen atmosphere. The target used was an In-Sn-Zn-O target with an atomic ratio of In:Sn:Zn = 1:1:1. The substrate heating temperature during film formation was 200 °C. 。The sample thus prepared was designated as Sample A.

[0258] Next, heat treatment was performed on the sample prepared in the same manner as Sample A at a temperature of 650 °C. The heat treatment was carried out by first heating in a nitrogen atmosphere for 1 hour and then further heating in an oxygen atmosphere for 1 hour without lowering the temperature. The sample thus prepared was designated as Sample B.

[0259] Fig. 28 shows the XRD spectra of Sample A and Sample B. In Sample A, no peaks derived from crystals were observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg - 38 deg. 。

[0260] Thus, the characteristics of transistors can be improved by intentionally heating during film formation and / or performing heat treatment after film formation for oxide semiconductors mainly composed of In, Sn, and Zn. 。

[0261] This substrate heating and heat treatment serve to prevent hydrogen and hydroxyl groups, which are harmful impurities to oxide semiconductors, from being included in the film or to remove them from the film. That is, high purity can be achieved by removing hydrogen, which becomes a donor impurity in the oxide semiconductor, The transistor can be made normally-off, and the oxide semiconductor can be purified to a high purity. As a result, the off-current can be reduced to 1 aA / μm or less. Here, the unit of the above off-current value indicates the current value per 1 μm of channel width.

[0262] Specifically, as shown in FIG. 29, when the substrate temperature is 125 °C, it is 1 aA / μm (1×1 0 -18 A / μm) or less, when it is 85 °C, it is 100 zA / μm (1×10 -19 A / μm ) or less, and when it is at room temperature (27 °C), it can be made 1 zA / μm (1×10 -21 A / μm) or less. Preferably, at 125 °C, it can be 0.1 aA / μm (1×10 -19 A / μ m) or less, at 85 °C, it can be 10 zA / μm (1×10 -20 A / μm) or less, and at room temperature it can be 0.1 zA / μm (1×10 -22 A / μm) or less.

[0263] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during film formation, it is preferable to sufficiently suppress leakage from outside the film formation chamber and outgassing from the inner wall of the film formation chamber, and to purify the sputtering gas. For example, it is preferable to use a gas with a dew point of -70 °C or lower so that no moisture is contained in the sputtering gas. Also, it is preferable to use a highly purified target so that the target itself does not contain impurities such as hydrogen and moisture. Oxide semiconductors mainly composed of In, Sn, and Zn can remove moisture in the film by heat treatment, but since the moisture release temperature is higher than that of oxide semiconductors mainly composed of In, Ga, and Zn, it is preferable to form a film that does not contain moisture from the beginning.

[0264] ​​​​​ In addition, in the transistors of the samples that were heat-treated at 650°C after the formation of the oxide semiconductor film, the relationship between the substrate temperature and the electrical characteristics was evaluated.

[0265] The transistors used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, Lov of 3 μm on one side (total 6 μm), and dW of 0 μm. Note that Vd was set to 10 V. Note that the substrate temperature was -40°C, -25°C, 25°C, 75°C, 125°C, and 150°C. Here, in the transistor, the overlapping width between the gate electrode and the pair of electrodes is called Lov, and the overhang of the pair of electrodes with respect to the oxide semiconductor film is called dW.

[0266] Fig. 26 shows the Vg dependence of Id (solid line) and the field-effect mobility (dotted line). Also, Fig. 2 7(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 27(B) shows the relationship between the substrate temperature and the field-effect mobility of the transistor.

[0267] From Fig. 27(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. Note that the range was 1.09 V to -0.23 V at -40°C to 150°C.

[0268] Also, from Fig. 27(B), it can be seen that the higher the substrate temperature, the lower the field-effect mobility. Note that the range was 36 cm 2 / Vs to 32 cm 2 / Vs at -40°C to 150°C. Therefore, it can be seen that the variation in the electrical characteristics is small in the above temperature range.

[0269] For a transistor having an oxide semiconductor containing In, Sn, and Zn as main components in the channel formation region as described above, while maintaining the off-current at 1 aA / μm or less, the field-effect mobility is 30 c m2 Above / Vsec, preferably 40 cm 2 Above / Vsec, more preferably 60 cm 2 Above / Vsec, and the on-current value required by the LSI can be satisfied. For example, In an FET with L / W = 33 nm / 40 nm, when the gate voltage is 2.7 V and the drain voltage is 1.0 V an on-current of 12 μA or more can flow. Also, sufficient electrical characteristics can be ensured even within the temperature range required for the operation of the transistor. With such characteristics, even if a transistor formed of an oxide semiconductor is mixed in an integrated circuit made of an Si semiconductor, it is possible to realize an integrated circuit having a new function without sacrificing the operating speed.

Example

[0270] In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film will be described with reference to FIG. 30 and the like.

[0271] FIG. 30 is a top view and a cross-sectional view of a transistor having a coplanar top-gate and top-contact structure. FIG. 30(A) shows the top view of the transistor. Also, FIG. 30( B) shows a cross-section A-B corresponding to the dashed line A-B in FIG. 30(A). The transistor shown in FIG. 30(B) includes a substrate 2100, an underlying insulating film 2102 provided on the substrate 2100, a protective insulating film 2104 provided around the underlying insulating film 2102, and an oxide semiconductor film 2106 having a high-resistance region 2106a and a low

[0272] resistance region 2106b provided on the underlying insulating film 2102 and the protective insulating film 2104, and a gate electrode 2108 provided on the oxide semiconductor film 2106. The oxide semiconductor film 2106 and the gate electrode 2108 are covered with a gate insulating film 2110, and a source electrode 2112 and a drain electrode 2114 are provided on the gate insulating film 2110. ​The formed gate insulating film 2108, the gate electrode 2110 provided to overlap with the oxide semiconductor film 210 6, the sidewall insulating film 2112 provided in contact with the side surface of the gate electrode 2110, and at least a pair provided in contact with the low resistance region 2106b of electrodes 2114, the interlayer insulating film 2116 provided to cover at least the oxide semiconductor film 2106, the gate electrode 2110, and the pair of electrodes 2114, and the wiring 21 provided to be connected to at least one of the pair of electrodes 2114 through an opening provided in the interlayer insulating film 2116 18, and has. Although not shown, a protective film provided to cover the interlayer insulating film 2116 and the wiring 2118 may be provided. By providing the protective film, the minute leakage current caused by the surface conduction of the interlayer insulating film 2116 can be reduced, and the off-current of the transistor can be reduced

[0273] This can be done.

Example

Example

[0274] In this example, another example of a transistor using an In-Sn-Zn-O film different from the above as an oxide semiconductor film is shown. This is shown.

[0275] FIG. 31 is a top view and a cross-sectional view showing the structure of the transistor manufactured in this example. FIG. 31(A) is a top view of the transistor. Further, FIG. 31(B) is a cross-sectional view corresponding to the dashed line A-B in FIG. 31(A). This is shown.

[0276] The transistor shown in FIG. 31(B) includes a substrate 3600, an underlying insulating film 3602 provided on the substrate 3600, an oxide semiconductor film 3606 provided on the underlying insulating film 3602, and oxidation insulating film 3602, and an oxide semiconductor film 3606 provided on the underlying insulating film 3602, and oxidation A pair of electrodes 3614 in contact with the oxide semiconductor film 3606, the oxide semiconductor film 3606, and a pair of the gate insulating film 3608 provided on the electrodes 3614, and through the gate insulating film 3608 the gate electrode 3610 provided to overlap the oxide semiconductor film 3606, and the gate insulating film 36 08 and the interlayer insulating film 3616 provided to cover the gate electrode 3610, and through the opening provided in the interlayer insulating film 3616 to connect to the pair of electrodes 3614, the wiring 3618, and the interlayer insulating film 3616 and the protective film 3620 provided to cover the wiring 3618.

[0277] As the substrate 3600, a glass substrate is used. As the underlying insulating film 3602, a silicon oxide film is used. As the oxide semiconductor film 3606, an In - Sn - Zn - O film is used. As the pair of electrodes 3614, a tungsten film is used. As the gate insulating film 3608, a silicon oxide film is used. As the gate electrode 361 0, a stacked structure of a tantalum nitride film and a tungsten film is used. As the interlayer insulating film 3616 a stacked structure of a silicon oxynitride film and a polyimide film is used. As the wiring 3618, a stacked structure in which a titanium film, an aluminum film, and a titanium film are formed in this order is used. As the protective film 3620, a poly imide film is used respectively.

[0278] In the transistor having the structure shown in Fig. 31(A), the overlapping width between the gate electrode 3610 and the pair of electrodes 3614 is called Lov. Similarly, the overhang of the pair of electrodes 3614 with respect to the oxide semiconductor film 3606 is called dW.

Example

[0279] The light - emitting device according to one aspect of the present invention is an image - emitting device, a notebook personal computer, a recording An image playback device equipped with a recording medium (typically a DVD: Digital Versatile Disc or other recording medium that can play back the recording medium and has a display capable of displaying the image) can be used. In addition, an electronic device that can use the light-emitting device according to one aspect of the present invention includes a mobile phone, a portable game machine, a portable information terminal, an e-book, a video camera, a digital still camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.) , a copying machine, a facsimile machine, a printer, a printer multifunction machine, an automated teller machine (A TM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 14.

[0280] FIG. 14(A) shows a portable game machine, which includes a housing 5001, a housing 5002, an image display unit 500 3, an image display unit 5004, a microphone 5005, a speaker 5006, an operation key 500 7, a stylus 5008, and the like. The light-emitting device according to one aspect of the present invention can be used for the image display unit 50 03 or the image display unit 5004. By using the light-emitting device according to one aspect of the present invention for the image display unit 5003 or the image display unit 5004, a high-quality portable game machine can be provided. Note that the portable game machine shown in FIG. 14(A) has two image display units 5003 and 5004, but the number of image display units of the portable game machine is not limited to this.

[0281] FIG. 14(B) shows a notebook personal computer, which includes a housing 5201, an image display unit 52 02, a keyboard 5203, a pointing device 5204, and the like. One aspect The light-emitting device according to the present invention can be used for the image display unit 5202. In the image display unit 5202 By using the light-emitting device according to one aspect of the present invention, a high-quality notebook personal computer can be provided.

[0282] FIG. 14(C) shows a portable information terminal, which includes a housing 5401, an image display unit 5402, operation keys 54 03, etc. The light-emitting device according to one aspect of the present invention can be used for the image display unit 5402. By using the light-emitting device according to one aspect of the present invention for the image display unit 5402, a high-quality portable information terminal can be provided.

[0283] As described above, the application scope of the present invention is extremely wide and can be used for electronic devices in all fields. It is possible.

[0284] This embodiment can be implemented in appropriate combination with the above-described embodiment.

Explanation of Reference Numerals

[0285] 101 Light-emitting element 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Capacitor element 108 Capacitor element 109 Transistor 140b Pixel 140g Pixel 140r Pixel 500 Pixel section 510 Scanning line drive circuit 520 Signal line drive circuit 521 Shift register 522 Memory circuit 523 Memory circuit 524 DA conversion circuit 600 Pixel section 610 Scanning line drive circuit 620 Signal line drive circuit 621 Shift register 622 Sampling circuit 623 Memory circuit 715b Anode 715g Anode 715r Anode 730 Partition wall 731 Electroluminescent layer 732 Cathode 740 Substrate 741b Light-emitting element 741g Light-emitting element 741r Light-emitting element 742 Substrate 743b Coloring layer 743g Coloring layer 743r Coloring layer 744 Overcoat 745b Conductive film 745g Conductive film 745r Conductive film 746g Conductive film 746r Conductive film 750 Insulating film 800 Substrate 801 Conductive film 802 Gate insulating film 803 Semiconductor layer 804 Conductive film 805 Conductive film 806 Conductive film 807 Semiconductor layer 808 Conductive film 809 Conductive film 810 Conductive film 811 Semiconductor layer 812 Conductive film 813 Semiconductor layer 814 Conductive film 815 Conductive film 816 Semiconductor layer 817 Conductive film 818 Conductive film 819 Conductive film 820 Semiconductor layer 821 Conductive film 822 Conductive film 823 Insulating film 824 Insulating film 825 Conductive film 826 Contact hole 827 Insulating film 828 Electroluminescent layer 829 Conductive film 900 Substrate 901 Conductive film 902 Gate insulating film 903 Semiconductor layer 904 Conductive film 905 Conductive film 906 Conductive film 907 Semiconductor layer 908 Conductive film 909 Conductive film 910 Conductive film 911 Conductive film 912 Conductive film 913 Semiconductor layer 914 Conductive film 915 Conductive film 916 Semiconductor layer 917 Conductive film 918 Semiconductor layer 919 Conductive film 921 Conductive film 922 Conductive film 923 Insulating film 925 Conductive film 926 Contact hole 927 Insulating film 928 Electroluminescent layer 929 Conductive film 930 Conductive film 1601 Display section 1602 Circuit board 1603 Connection section 2100 Substrate 2102 Underlying insulating film 2104 Protective insulating film 2106a High-resistance region 2106b Low-resistance region 2106 Oxide semiconductor film 2108 Gate insulating film 2110 Gate electrode 2112 Sidewall insulating film 2114 Pair of electrodes 2116 Interlayer insulating film 2118 Wiring 3600 Substrate 3602 Underlying insulating film 3606 Oxide semiconductor film 3608 Gate insulating film 3610 Gate electrode 3614 Pair of electrodes 3616 Interlayer insulating film 3618 Wiring 3620 Protective film 5001 Housing 5002 Housing 5003 Image display unit 5004 Image display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Housing 5202 Image display unit 5203 Keyboard 5204 Pointing device 5401 Housing 5402 Image display unit 5403 Operation key 8101 Underlying insulator 8102 Embedded insulator 8103a Semiconductor region 8103b Semiconductor region 8103c Semiconductor region 8104 Gate insulator 8105 Gate 8106a Sidewall insulator 8106b Sidewall insulator 8107 Insulator 8108a Source 8108b Drain

Claims

1. A first transistor, a second transistor, and a light-emitting element, the first transistor has a function of controlling supply of a current to the light-emitting element in accordance with an image signal; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the first transistor; a light-emitting device, wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, A first semiconductor film; a first conductive film having a region disposed above the first semiconductor film; the first semiconductor film has a first region that overlaps with the first conductive film and functions as a channel formation region of the first transistor, and a second region that overlaps with the first conductive film and functions as a first electrode of a first capacitor; the first conductive film has a function as a gate of the first transistor and a function as a second electrode of the first capacitor; The first region and the second region are spaced apart from each other and arranged side by side in a first direction, Each of the first region and the second region has a region whose width in a second direction intersecting the first direction is longer than its width in the first direction. Light emitting device.

2. A first transistor, a second transistor, and a light-emitting element, the first transistor has a function of controlling supply of a current to the light-emitting element in accordance with an image signal; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the first transistor; a light-emitting device, wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, A first semiconductor film; a first conductive film having a region disposed above the first semiconductor film; the first semiconductor film has a first region that overlaps with the first conductive film and functions as a channel formation region of the first transistor, and a second region that overlaps with the first conductive film and functions as a first electrode of a first capacitor; the first conductive film has a function as a gate of the first transistor and a function as a second electrode of the first capacitor; The first region and the second region are spaced apart from each other and arranged side by side in a first direction, the first region and the second region are electrically connected via a third region of the first semiconductor film that does not overlap with the first conductive film; Each of the first region and the second region has a region whose width in a second direction intersecting the first direction is longer than its width in the first direction. Light emitting device.

3. A first transistor, a second transistor, and a light-emitting element, the first transistor has a function of controlling supply of a current to the light-emitting element in accordance with an image signal; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the first transistor; a light-emitting device, wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, A first semiconductor film; a first conductive film having a region disposed above the first semiconductor film; the first semiconductor film has a first region that overlaps with the first conductive film and functions as a channel formation region of the first transistor, and a second region that overlaps with the first conductive film and functions as a first electrode of a first capacitor; the first conductive film has a function as a gate of the first transistor and a function as a second electrode of the first capacitor; The first region and the second region are spaced apart from each other and arranged side by side in a first direction, the first region and the second region are electrically connected via a third region of the first semiconductor film that does not overlap with the first conductive film; the third region has a curved shape; Each of the first region and the second region has a region whose width in a second direction intersecting the first direction is longer than its width in the first direction. Light emitting device.

4. In any one of claims 1 to 3, A second semiconductor film is provided. the second semiconductor film has a third region which overlaps with the first conductive film and functions as a first electrode of a second capacitor; the first conductive film functions as a second electrode of the second capacitor element; Light emitting device.

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