Semiconductor device, debug system, control method for semiconductor device and debug method

Abstract

To check a function execution history of a CPU mounted on a semiconductor device while reducing the cost of the semiconductor device.SOLUTION: A semiconductor device comprises a CPU for executing instructions included in a program, a first register for storing an address of an instruction currently being executed by the CPU, a second register for storing a return destination address when a function branch occurs as a result of the execution of the instruction by the CPU, and a generation circuit for generating and outputting function branch information indicating a branch destination address of the function when the function branch occurs as a result of the execution of the instruction by the CPU. The generation circuit determines whether or not the function branch has occurred based on values of the first register and the second register before and after the instruction execution by the CPU, and if it determines that the function branch has occurred, outputs the value of the first register after the instruction execution by the CPU as the function branch information.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a debug system, a control method for a semiconductor device, and a debug method, and can be suitably used, for example, for a semiconductor device equipped with a CPU (Central Processing Unit).

Background Art

[0002] There is a demand to check the function execution history of a function executed by a CPU mounted on a semiconductor device. As a technique for recording the function execution history of a computer such as a CPU, for example, the technique described in Patent Document 1 can be cited.

[0003] According to the technique described in Patent Document 1, a debugger initially stores in an ID memory the instruction address of an instruction included in a program to be debugged and the function ID (identifier) corresponding to the instruction address. When the computer starts executing the program, the debugger reads, for each instruction, the function ID corresponding to the instruction address of the instruction from the ID memory and compares the current function ID with the previous function ID. When the current function ID is different from the previous function ID, the debugger records the current function ID in a trace memory. Thereby, the function execution history of the computer can be recorded.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the technique described in Patent Document 1 requires an ID memory for storing an instruction address and a function ID. Mounting the ID memory on a semiconductor device increases the cost of the semiconductor device. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device includes a CPU (Central Processing Unit) that executes instructions included in a program, a first register that stores an address of an instruction currently being executed by the CPU, a second register that stores a return address when a function branch occurs due to the execution of an instruction by the CPU, and a generation circuit that generates and outputs function branch information indicating an address of a function branch destination when a function branch occurs due to the execution of an instruction by the CPU. The generation circuit determines whether a function branch has occurred based on the values of the first register and the second register before and after the execution of an instruction by the CPU. When it is determined that a function branch has occurred, the generation circuit outputs the value of the first register after the execution of the instruction by the CPU as the function branch information.

[0007] According to one embodiment, a debug system includes a semiconductor device, an emulator that adds a timestamp to function branch information output from the semiconductor device and outputs the function branch information with the timestamp added, and a debugger that displays an execution history of a function executed by the CPU based on the function branch information with the timestamp added output from the emulator.

[0008] According to one embodiment, there is provided a method for controlling a semiconductor device. The semiconductor device includes a CPU (Central Processing Unit) that executes instructions included in a program, a first register that stores the address of the instruction currently being executed by the CPU, and a second register that stores the return address when a function branch occurs due to the execution of an instruction by the CPU. The control method includes determining whether a function branch has occurred based on the values of the first register and the second register before and after the instruction execution by the CPU, and when it is determined that a function branch has occurred, outputting the value of the first register after the instruction execution by the CPU as function branch information indicating the branch destination address of the function.

[0009] According to one embodiment, there is provided a debugging method executed by a debugging system. The debugging system includes a semiconductor device including a CPU (Central Processing Unit) that executes instructions included in a program, a first register that stores the address of the instruction currently being executed by the CPU, and a second register that stores the return address when a function branch occurs due to the execution of an instruction by the CPU, an emulator, and a debugger. The debugging method includes the semiconductor device determining whether a function branch has occurred based on the values of the first register and the second register before and after the instruction execution by the CPU, the semiconductor device outputting, when it is determined that a function branch has occurred, the value of the first register after the instruction execution by the CPU as function branch information indicating the branch destination address of the function, the emulator adding a timestamp to the function branch information output from the semiconductor device and outputting the function branch information with the timestamp added, and the debugger displaying the execution history of the function executed by the CPU based on the function branch information with the timestamp added output from the emulator.

Advantages of the Invention

[0010] According to the above-described embodiment, it is possible to provide a semiconductor device, a debug system, a control method for a semiconductor device, and a debug method that can confirm the function execution history of a CPU mounted on the semiconductor device while reducing the cost of the semiconductor device.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be narrowly interpreted based on the description of these drawings. Also, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0013] In the following embodiments, for convenience, when necessary, they are divided and described in a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a modification example, application example, detailed description, supplementary description, etc. of a part or all of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and in cases where it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0014] Furthermore, in the following embodiments, the constituent elements (including operation steps, etc.) are not necessarily essential unless otherwise specified and in cases where they are clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and in cases where it is clearly not the case in principle, those substantially approximating or similar to the shape, etc. are included. This also applies to the above-mentioned numbers, etc. (including the number, numerical value, quantity, range, etc.).

[0015] [Embodiment 1] First, with reference to FIG. 1, a configuration example of the debug system according to Embodiment 1 will be described. FIG. 1 is a block diagram showing the configuration of a debug system 1 according to Embodiment 1. As shown in FIG. 1, the debug system 1 according to Embodiment 1 includes a semiconductor device 10, an emulator 20, and a debugger 30.

[0016] The semiconductor device 10 includes a CPU 11 and a generation circuit 12. The semiconductor device 10 is realized by a SoC (System On Chip) or an MPU (Micro Processing Unit), etc.

[0017] The CPU 11 executes instructions included in the program to be debugged. The CPU 11 includes a program counter 111, a link register 112, and an exception link register 113. In the figure, the program counter is appropriately denoted as PC (Program Counter), the link register is appropriately denoted as LR (Link Register), and the exception link register is appropriately denoted as ELR (Exception Link Register).

[0018] The program counter 111 is a register that stores the address of the instruction currently being executed by the CPU 11. The link register 112 is a register that stores the return address when a function is called by the execution of an instruction by the CPU 11. The exception link register 113 is a register that stores the return address when an exception occurs by the execution of an instruction by the CPU 11.

[0019] Before executing an instruction, the CPU 11 outputs the values of the program counter 111, the link register 112, and the exception link register 113 before instruction execution to the generation circuit 12. Also, after executing an instruction, the CPU 11 outputs the values of the program counter 111, the link register 112, and the exception link register 113 after instruction execution to the generation circuit 12.

[0020] The generation circuit 12 generates and outputs function branch information indicating the branch destination address of a function when a function branch occurs due to the execution of an instruction by the CPU 11. Here, a function branch refers to an operation indicating a processing transition in units of functions and exceptions. In Embodiment 1, the generation circuit 12 is assumed to detect a function call, a function return, an exception call, and an exception return as function branches.

[0021] Specifically, the generation circuit 12 determines whether a function branch has occurred based on the values of the program counter 111, the link register 112, and the exception link register 113 before and after the execution of an instruction by the CPU 11.

[0022] When it is determined that a function branch has occurred, the generation circuit 12 outputs the value of the program counter 111 after the execution of the instruction by the CPU 11 to the emulator 20 as function branch information.

[0023] The emulator 20 includes a trace memory 21 and a timestamp circuit 22. The timestamp circuit 22 adds timestamp information to the function branch information at the timing when the function branch information is input from the generation circuit 12 of the semiconductor device 10. The trace memory 21 stores the function branch information to which the timestamp information is added. The function branch information to which the timestamp information is added and stored in the trace memory 21 is output to the debugger 30.

[0024] Based on the function branch information to which the timestamp information is added and output from the trace memory 21 of the emulator 20, the debugger 30 displays the function execution history of the function executed by the CPU 11 on a display (not shown) or the like.

[0025] Subsequently, with reference to FIG. 2, a schematic operation example when a function call and a function return occur in the semiconductor device 10 will be described. FIG. 2 is a diagram for explaining a schematic operation example when a function call and a function return occur in the semiconductor device 10 according to the first embodiment. In FIG. 2, "Y" indicates "Yes" (the same in FIG. 4).

[0026] In the example of FIG. 2, a function call that branches from the function A, which is the main function, to the function B, which is the sub-function, occurs due to the execution of an instruction by the CPU 11. At this time, the value of the program counter 111 is the address of the function A before the instruction execution and the address of the function B after the instruction execution.

[0027] Also, in the operation of a function call, when the CPU 11 branches from function A to function B, at the same time, the CPU 11 stores, in the link register 112, an added value obtained by adding the value of the instruction length to the value of the program counter 111 before instruction execution. That is, the CPU 11 stores, in the link register 112, the address of the instruction immediately following the current instruction in function A.

[0028] As a result, the value of the link register 112 after instruction execution becomes a value corresponding to the value of the program counter 111 when returning to function A in a subsequent function return. In the following description, it is assumed that the instruction length is "4", but the instruction length is not limited to "4" and can be set to other values.

[0029] In this way, in the example of FIG. 2, a function call occurs as a function branch due to the execution of an instruction by the CPU 11. Therefore, the generation circuit 12 determines whether a function call has occurred by performing the function call determination operation shown in FIG. 2.

[0030] In the function call determination operation, the generation circuit 12 compares an added value obtained by adding the value "4" of the instruction length to the value of the program counter 111 before instruction execution with the value of the link register 112 after instruction execution (step S101). When the two match (Y in step S101), the generation circuit 12 determines that a function call has occurred. Here, since the two match, the generation circuit 12 determines that a function call has occurred.

[0031] When the generation circuit 12 determines that a function call has occurred by the above-described function call determination operation, the generation circuit 12 outputs the value of the program counter 111 after instruction execution to the emulator 20 as function branch information (step S102).

[0032] Also, in the example of FIG. 2, subsequently, a function return occurs in which the CPU 11 branches from function B, which is a sub-function, to function A, which is the main function, due to the execution of an instruction.

[0033] In the operation of function return, before branching from function B to function A, the CPU 11 stores the value of the link register 112 in the program counter 111. Then, the CPU 11 branches from function B to function A.

[0034] As a result, both the value of the program counter 111 and the value of the link register 112 after instruction execution become values corresponding to the value of the program counter 111 when returning to function A.

[0035] In this way, in the example of FIG. 2, due to the execution of instructions by the CPU 11, a function return occurs as a function branch. Therefore, the generation circuit 12 determines whether a function return has occurred by performing the function return determination operation shown in FIG. 2.

[0036] In the function return determination operation, the generation circuit 12 compares the value of the link register 112 before instruction execution with the value of the program counter 111 after instruction execution (step S111). When the two match (Y in step S111), the generation circuit 12 determines that a function return has occurred. Here, since the two match, the generation circuit 12 determines that a function return has occurred.

[0037] When the generation circuit 12 determines that a function return has occurred by the above-described function return determination operation, it outputs the value of the program counter 111 after instruction execution to the emulator 20 as function branch information (step S112).

[0038] Here, an example of the function execution history of the CPU 11 displayed by the debugger 30 in the case of the example of FIG. 2 will be described. FIG. 3 is a diagram showing an example of the function execution history displayed by the debugger 30 according to Embodiment 1. According to FIG. 3, it can be confirmed that functions A, B, and A have been executed in this order in time series by the CPU 11.

[0039] Although not shown in the example of FIG. 2, depending on the execution of instructions by the CPU 11, as a function branch, an exception call that branches from function A, which is the main function, to an exception, or an exception return that branches from an exception to function A, which is the main function, may occur.

[0040] FIG. 4 is a diagram for explaining a schematic operation example of an exception call determination operation and an exception return determination operation executed by the generation circuit 12 according to Embodiment 1. As shown in FIG. 4, the generation circuit 12 determines whether an exception call or an exception return has occurred by performing the exception call determination operation and the exception return determination operation.

[0041] In the exception call determination operation, the generation circuit 12 compares the added value obtained by adding the value "4" of the instruction length to the value of the program counter 111 before instruction execution with the value of the exception link register 113 after instruction execution (step S121). When the two match (Y in step S121), the generation circuit 12 determines that an exception call has occurred.

[0042] When the generation circuit 12 determines that an exception call has occurred by the above-described exception call determination operation, it outputs the value of the program counter 111 after instruction execution to the emulator 20 as function branch information (step S122).

[0043] In the exception return determination operation, the generation circuit 12 compares the value of the exception link register 113 before instruction execution with the value of the program counter 111 after instruction execution (step S131). When the two match (Y in step S131), the generation circuit 12 determines that an exception return has occurred.

[0044] When the generation circuit 12 determines that an exception return has occurred by the above-described exception return determination operation, it outputs the value of the program counter 111 after instruction execution to the emulator 20 as function branch information (step S132).

[0045] Next, with reference to FIGS. 5 to 7, a configuration example and an operation example of the semiconductor device 10 will be described in more detail. FIG. 5 is a diagram showing a configuration example of the generation circuit 12 according to the first embodiment. FIG. 6 is a diagram for explaining an operation example when a function call and a function return occur in the CPU 11 according to the first embodiment. FIG. 7 is a diagram for explaining an operation example when a function call and a function return occur in the generation circuit 12 according to the first embodiment.

[0046] First, with reference to FIG. 5, a configuration example of the generation circuit 12 will be described. As shown in FIG. 5, the generation circuit 12 includes latch circuits 121 and 122, a comparison value calculation circuit 123, a function / exception call determination circuit 124, a function / exception return determination circuit 125, and an output unit 126.

[0047] As described above, before executing an instruction, the CPU 11 outputs the values of the program counter 111, link register 112, and exception link register 113 before instruction execution to the generation circuit 12. Also, after executing an instruction, the CPU 11 outputs the values of the program counter 111, link register 112, and exception link register 113 after instruction execution to the generation circuit 12.

[0048] When the values of the program counter 111, link register 112, and exception link register 113 before instruction execution are output from the CPU 11, the latch circuit 121 holds those values.

[0049] When the values of the program counter 111, link register 112, and exception link register 113 after instruction execution are output from the CPU 11, the latch circuit 122 holds those values.

[0050] The comparison value calculation circuit 123 calculates an addition value obtained by adding the value “4” of the instruction length to the value of the program counter 111 before instruction execution held in the latch circuit 121, and holds the calculated addition value.

[0051] The function / exception call determination circuit 124 performs the above-described function call determination operation and exception call determination operation by using the value held by the comparison value calculation circuit 123 and the values of the link register 112 and the exception link register 113 after instruction execution held in the latch circuit 122.

[0052] In the function call determination operation, the function / exception call determination circuit 124 compares the value held by the comparison value calculation circuit 123 with the value of the link register 112 after instruction execution. If both values match, it is determined that a function call has occurred.

[0053] Also, in the exception call determination operation, the function / exception call determination circuit 124 compares the value held by the comparison value calculation circuit 123 with the value of the exception link register 113 after instruction execution. If both values match, it is determined that an exception call has occurred.

[0054] The function / exception call determination circuit 124 outputs a determination result indicating whether a function call or an exception call has occurred to the output unit 126.

[0055] The function / exception return determination circuit 125 performs the above-described function return determination operation and exception return determination operation by using the values of the link register 112 and the exception link register 113 before instruction execution held in the latch circuit 121 and the value of the program counter 111 after instruction execution held in the latch circuit 122.

[0056] In the function return determination operation, the function / exception return determination circuit 125 compares the value of the link register 112 before instruction execution with the value of the program counter 111 after instruction execution. If both values match, it is determined that a function return has occurred.

[0057] Also, in the exception return determination operation, the function / exception return determination circuit 125 compares the value of the exception link register 113 before instruction execution with the value of the program counter 111 after instruction execution. If both values match, it is determined that an exception return has occurred.

[0058] The function / exception return determination circuit 125 outputs a determination result indicating whether a function return or an exception return has occurred to the output unit 126.

[0059] Based on the determination results output from the function / call determination circuit 124 and the function / exception return determination circuit 125, the output unit 126 determines whether any function branch of function call, exception call, function return, or exception return has occurred. When it is determined that any function branch has occurred, the output unit 126 outputs the value of the program counter 111 after instruction execution held in the latch circuit 122 as function branch information to the emulator 20.

[0060] Subsequently, with reference to FIGS. 6 and 7, an operation example of the semiconductor device 10 will be described. First, with reference to FIG. 6, an operation example when a function call and a function return occur in the CPU 11 will be described.

[0061] FIG. 6 shows the addresses and codes of the instructions executed for the function A which is the main function, and also shows the addresses and codes of the instructions executed for the function B which is the sub-function. Further, in the examples of FIGS. 6 and 7, similar to FIG. 2, a function call that branches from the function A which is the main function to the function B which is the sub-function occurs, and subsequently, a function return that branches from the function B which is the sub-function to the function A which is the main function is assumed to occur.

[0062] In the initial state, the value of the program counter 111 (the value before instruction execution) is "0x1000". Therefore, the CPU 11 executes the instruction at the address "0x1000" (operation (a)). At this time, the instruction at the address "0x1000" includes a function call instruction (bl instruction). The bl instruction is an instruction that calls a function located at the address "0x2000".

[0063] Therefore, the CPU 11 executes the operation of a function call that branches from function A to function B. In the operation of the function call, when the CPU 11 branches from function A to function B, it simultaneously stores the address of the instruction one below the current instruction in the link register 112. Here, since the instruction length is "4", the address of the instruction one below the current instruction address "0x1000" is "0x1004" obtained by adding the instruction length "4" to the current instruction address "0x1000". Therefore, the CPU 11 stores "0x1004" in the link register 112. As a result, the value of the link register 112 after the execution of the function call instruction corresponds to the value of the program counter 111 when returning to function A in the subsequent function return.

[0064] Here, the value of the program counter 111 after the execution of the function call instruction is the address of function B, "0x2000". Therefore, the CPU 11 executes the instruction at the address "0x2000" (operation (b)). At this time, the instruction at the address "0x2000" includes a no-operation instruction (nop instruction). Therefore, after executing the nop instruction, the CPU 11 transitions the value of the program counter 111 to the placement address of the next instruction. As a result, the value of the program counter 111 becomes "0x2004".

[0065] Next, the CPU 11 executes the instruction one below, that is, the instruction at the address "0x2004" (operation (c)). At this time, the instruction at the address "0x2004" includes a function return instruction (ret instruction).

[0066] Therefore, the CPU 11 executes the operation of a function return that branches from function B to function A. In the operation of the function return, before the CPU 11 branches from function B to function A, it stores the value "0x1004" of the link register 112 in the program counter 111. After that, the CPU 11 branches from function B to function A.

[0067] Here, the value of the program counter 111 after the execution of the function return instruction is the address of function A, "0x1004". Therefore, the CPU 11 executes the instruction at the address "0x1004" (operation (d)). At this time, the instruction at the address "0x1004" contains a nop instruction. Therefore, the CPU 11 executes the nop instruction.

[0068] Subsequently, referring to FIG. 7, an operation example when a function call and a function return occur in the generation circuit 12 will be described. Note that the operation example of the CPU 11 shown in FIG. 7 is the same as the operation example of the CPU 11 shown in FIG. 6.

[0069] As shown in FIG. 7, whether a function call has occurred is determined by the function / exception call determination circuit 124 executing a function call determination operation. Here, the comparison value calculation circuit 123 holds an addition value "0x1004" obtained by adding the value "4" of the instruction length to the value "0x1000" of the program counter 111 in (1) before the execution of the function call instruction.

[0070] Therefore, in the function call determination operation, the function / exception call determination circuit 124 compares the value "0x1004" of the link register 112 in (2) after the execution of the function call instruction with the value "0x1004" held by the comparison value calculation circuit 123. Here, since the two match, the function / exception call determination circuit 124 determines that a function call has occurred.

[0071] Therefore, the output unit 126 outputs the value "0x2000" of the program counter 111 in (3) after the execution of the function call instruction to the emulator 20 as function branch information.

[0072] Also, whether a function return has occurred is determined by the function / exception return determination circuit 125 executing a function return determination operation. In the function return determination operation, the function / exception return determination circuit 125 compares the value "0x1004" of the link register 112 in (4) before the execution of the function return instruction with the value "0x1004" of the program counter 111 in (5) after the execution of the function return instruction. Here, since the two values match, the function / exception return determination circuit 125 determines that a function return has occurred.

[0073] Therefore, the output unit 126 outputs the value "0x1004" of the program counter 111 in (5) after the execution of the function return instruction to the emulator 20 as function branch information.

[0074] Subsequently, with reference to FIG. 8, an example of the operation flow of the generation circuit 12 will be described. FIG. 8 is a diagram for explaining an example of the operation flow of the generation circuit 12 according to Embodiment 1. In FIG. 8, "Y" indicates "Yes" and "N" indicates "No". As shown in FIG. 8, the latch circuit 121 holds the values of the program counter 111, link register 112, and exception link register 113 before the instruction execution by the CPU 11 (step S201).

[0075] When an instruction is executed by the CPU 11 (step S202), the latch circuit 122 holds the values of the program counter 111, link register 112, and exception link register 113 after the instruction execution by the CPU 11 (step S203).

[0076] Next, the comparison value calculation circuit 123 calculates an addition value obtained by adding the value "4" of the instruction length to the value of the program counter 111 before the instruction execution held in the latch circuit 121, and holds the calculated addition value (step S204).

[0077] Next, the function call determination operation is performed. Specifically, the function / exception call determination circuit 124 compares the value held by the comparison value calculation circuit 123 with the value of the link register 112 after instruction execution held in the latch circuit 122 (step S205). When the two match (Y in step S205), the function / exception call determination circuit 124 determines that a function call has occurred.

[0078] Next, the exception call determination operation is performed. Specifically, the function / exception call determination circuit 124 compares the value held by the comparison value calculation circuit 123 with the value of the exception link register 113 after instruction execution held in the latch circuit 122 (step S206). When the two match (Y in step S206), the function / exception call determination circuit 124 determines that an exception call has occurred.

[0079] Next, the function return determination operation is performed. Specifically, the function / exception return determination circuit 125 compares the value of the link register 112 before instruction execution held in the latch circuit 121 with the value of the program counter 111 after instruction execution held in the latch circuit 122 (step S207). When the two match (Y in step S207), the function / exception return determination circuit 125 determines that a function return has occurred.

[0080] Next, the exception return determination operation is performed. Specifically, the function / exception return determination circuit 125 compares the value of the exception link register 113 before instruction execution held in the latch circuit 121 with the value of the program counter 111 after instruction execution held in the latch circuit 122 (step S208). When the two match (Y in step S208), the function / exception return determination circuit 125 determines that an exception return has occurred.

[0081] In step S205 to step S208, the output unit 126 determines whether any function branch such as a function call, an exception call, a function return, or an exception return has occurred. When it is determined that any function branch has occurred, the output unit 126 outputs the value of the program counter 111 after instruction execution held in the latch circuit 122 as function branch information to the emulator 20 (step S209).

[0082] As described above, according to the first embodiment, the semiconductor device 10 determines whether a function branch has occurred based on the values of the program counter 111, the link register 112, and the exception link register 113 before and after instruction execution. When the semiconductor device 10 determines that a function branch has occurred, the semiconductor device 10 outputs the value of the program counter 111 after instruction execution as function branch information. Therefore, since the semiconductor device 10 does not require the ID memory that was necessary in Patent Document 1, it is possible to avoid an increase in the cost of the semiconductor device 10 due to the mounting of the ID memory. Thereby, while reducing the cost of the semiconductor device 10, it is possible to check the function execution history of the CPU 11 mounted on the semiconductor device 10.

[0083] [Modification Example of the First Embodiment] Subsequently, with reference to FIG. 9, a configuration example of a debug system according to a modification example of the first embodiment will be described. FIG. 9 is a diagram showing a configuration example of a debug system 1A according to a modification example of the first embodiment. This modification example is an example in which a plurality of CPUs 11 are mounted on the semiconductor device 10A.

[0084] As shown in FIG. 9, the debug system 1A according to this modification example includes a semiconductor device 10A, an emulator 20A, and a debugger 30A. The semiconductor device 10A is different from the above-described semiconductor device 10 in that it includes a plurality of the above-described CPUs 11 and a plurality of the above-described generation circuits 12.

[0085] Each of the plurality of generation circuits 12 is provided in relation to any one of the plurality of CPUs 11. Further, to each of the plurality of CPUs 11, a CPU number is associated as a number for identifying the CPU. When each of the plurality of generation circuits 12 determines that an instruction has been executed by the associated CPU 11 and a function branch has occurred, the CPU number of the associated CPU 11 is added to the function branch information, and the function branch information with the CPU number added is output to the emulator 20A.

[0086] The emulator 20A is similar in configuration itself to the emulator 20 described above. The timestamp circuit 22 adds timestamp information to the function branch information with the CPU number added at the timing when the function branch information with the CPU number added is input from the generation circuit 12 of the semiconductor device 10A. The trace memory 21 stores the function branch information with the CPU number and the timestamp information added. The function branch information with the CPU number and the timestamp information added, stored in the trace memory 21, is output to the debugger 30A.

[0087] Based on the function branch information with the CPU number and the timestamp information added, output from the trace memory 21 of the emulator 20A, the debugger 30A displays, for each CPU 11, the function execution history of that CPU 11 on a display (not shown) or the like.

[0088] As described above, according to this modification example, the semiconductor device 10A, similar to the semiconductor device 10 described above, does not require the ID memory that was necessary in Patent Document 1. Therefore, it is possible to avoid an increase in the cost of the semiconductor device 10A due to the mounting of the ID memory. Further, since the function branch information output from the semiconductor device 10A is limited to function branches related to function calls, function returns, exception calls, and exception returns, information on function branches other than these, for example, information on branches by if statements and while statements, is not included, and the amount of information is small. Therefore, the semiconductor device 10A can output all function branch information of a plurality of CPUs 11 mounted on the semiconductor device 10A. As a result, while reducing the cost of the semiconductor device 10A, it is possible to check all function execution histories of a plurality of CPUs 11 mounted on the semiconductor device 10A.

[0089] [Embodiment 2] Embodiment 2 corresponds to an embodiment in which the above-described Embodiment 1 is conceptually generalized. With reference to FIG. 10, a configuration example of the debug system according to Embodiment 2 will be described. FIG. 10 is a diagram showing a configuration example of the debug system 2 according to Embodiment 2.

[0090] As shown in FIG. 10, the debug system 2 according to Embodiment 2 includes a semiconductor device 40, an emulator 50, and a debugger 60.

[0091] The semiconductor device 40 includes a CPU 41 and a generation circuit 42. The semiconductor device 40 corresponds to the semiconductor device 10. The CPU 41 executes instructions included in the program to be debugged. Further, the CPU 41 includes a first register 411 and a second register 412. The CPU 41 corresponds to the CPU 11.

[0092] The first register 411 stores the address of the instruction currently being executed by the CPU 41. The first register 411 corresponds to the program counter 111. The second register 412 stores the return address when a function branch occurs due to the execution of an instruction by the CPU 41. The second register 412 corresponds to the link register 112 or the exception link register 113.

[0093] The generation circuit 42 generates and outputs function branch information indicating the address of the branch destination of a function when a function branch occurs due to the execution of an instruction by the CPU 41. The generation circuit 42 corresponds to the generation circuit 12.

[0094] Specifically, the generation circuit 42 determines whether a function branch has occurred based on the values of the first register 411 and the second register 412 before and after the execution of an instruction by the CPU 41. When the generation circuit 42 determines that a function branch has occurred, it outputs the value of the first register 411 after the execution of the instruction by the CPU 41 as function branch information to the emulator 50.

[0095] The emulator 50 adds a timestamp to the function branch information output from the semiconductor device 40 and outputs the function branch information with the timestamp added to the debugger 60. The emulator 50 corresponds to the emulator 20.

[0096] The debugger 60 displays the function execution history of the function executed by the CPU 41 based on the function branch information with the timestamp added output from the emulator 50. The debugger 60 corresponds to the debugger 30.

[0097] As described above, according to the second embodiment, the semiconductor device 40 determines whether a function branch has occurred based on the values of the first register 411 and the second register 412 before and after the execution of an instruction. When the semiconductor device 40 determines that a function branch has occurred, it outputs the value of the first register 411 after the execution of the instruction as function branch information. Therefore, since the semiconductor device 40 does not require the ID memory that was necessary in Patent Document 1, it is possible to avoid an increase in the cost of the semiconductor device 40 due to the mounting of the ID memory. Thereby, while reducing the cost of the semiconductor device 40, it is possible to confirm the function execution history of the CPU 41 mounted on the semiconductor device 40.

[0098] Also, when the second register 412 is a link register, the generation circuit 42 may determine that a function call has occurred as a function branch when the added value obtained by adding a predetermined value corresponding to the instruction length to the value of the program counter before the execution of the instruction by the CPU 41 matches the value of the link register after the execution of the instruction by the CPU 41.

[0099] Also, when the second register 412 is a link register, the generation circuit 42 may determine that a function return has occurred as a function branch when the value of the link register before the execution of the instruction by the CPU 41 matches the value of the program counter after the execution of the instruction by the CPU 41.

[0100] Also, when the second register 412 is an exception link register, the generation circuit 42 may determine that an exception call has occurred as a function branch when the added value obtained by adding a predetermined value corresponding to the instruction length to the value of the program counter before the execution of the instruction by the CPU 41 matches the value of the exception link register after the execution of the instruction by the CPU 41.

[0101] Also, when the second register 412 is an exception link register, the generation circuit 42 may determine that an exception return has occurred as a function branch when the value of the exception link register before the execution of the instruction by the CPU 41 matches the value of the program counter after the execution of the instruction by the CPU 41.

[0102] Further, the semiconductor device 40 may include a plurality of CPUs 41 and a plurality of generation circuits 42. That is, the semiconductor device 40 may include a plurality of first registers 411 and a plurality of second registers 412. Also, when each of the plurality of generation circuits 42 determines that a function branch has occurred due to the execution of an instruction by the associated CPU 41, the generation circuit 42 may add the CPU number of the associated CPU 41 to the function branch information and output the function branch information with the CPU number added to the emulator 50. Further, the semiconductor device 40 may be a SoC or an MPU.

[0103] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

[0104] Furthermore, the present disclosure can be realized by causing a CPU to execute a computer program for part or all of the processing of the semiconductor devices 10, 10A, 40, the emulators 20, 20A, 50, and the debuggers 30, 30A, 60.

[0105] In addition, when the above-described program is loaded into a computer, it includes a set of instructions (or software code) for causing the computer to perform one or more functions described in the embodiments. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or tangible storage medium includes RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive) or other memory technologies, CD (Compact Disc)-ROM, DVD (Digital Versatile Disc), Blu-ray (registered trademark) disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted on a transitory computer-readable medium or communication medium. By way of example and not limitation, the transitory computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

Explanation of Reference Numerals

[0106] 1, 1A, 2 Debugging system 10, 10A, 40 Semiconductor device 11, 41 CPU 111 Program counter 112 Link register 113 Exception link register 411 First register 412 Second register 12,42 Generation circuit 121,122 Latch circuit 123 Comparison value calculation circuit 124 Function / exception call determination circuit 125 Function / exception return determination circuit 126 Output section 20,20A,50 Emulator 21 Trace memory 22 Timestamp circuit 30,30A,60 Debugger

Claims

1. A CPU (Central Processing Unit) that executes instructions included in a program, a first register that stores the address of the instruction currently being executed by the CPU, a second register that stores the return address when a function branch occurs due to the execution of an instruction by the CPU, and a generation circuit that generates and outputs function branch information indicating the branch destination address of a function when the function branch occurs due to the execution of an instruction by the CPU. The generation circuit, determines whether the function branch has occurred based on the values of the first register and the second register before and after the instruction execution by the CPU, and when it is determined that the function branch has occurred, outputs the value of the first register after the instruction execution by the CPU as the function branch information. A semiconductor device.

2. The first register is a program counter, and the second register is a link register that stores the return address when a function is called due to the execution of an instruction by the CPU, or an exception link register that stores the return address when an exception occurs due to the execution of an instruction by the CPU. The semiconductor device according to claim 1.

3. When the second register is the link register, the generation circuit determines that a function call has occurred as the function branch when a sum value obtained by adding a predetermined value corresponding to the instruction length to the value of the program counter before the instruction execution by the CPU matches the value of the link register after the instruction execution by the CPU. The semiconductor device according to claim 2.

4. When the second register is the link register, the generation circuit determines that a function return has occurred as the function branch when the value of the link register before the instruction execution by the CPU matches the value of the program counter after the instruction execution by the CPU. The semiconductor device according to claim 2.

5. When the second register is the exception link register, the generation circuit determines that an exception call has occurred as the function branch when a sum value obtained by adding a predetermined value corresponding to the instruction length to the value of the program counter before the instruction execution by the CPU matches the value of the exception link register after the instruction execution by the CPU. The semiconductor device according to claim 2.

6. When the second register is the exception link register, if the value of the exception link register before the execution of the instruction by the CPU matches the value of the program counter after the execution of the instruction by the CPU, the generation circuit determines that an exception return has occurred as the function branch. The semiconductor device according to claim 2.

7. A plurality of the CPUs; A plurality of the first registers; A plurality of the second registers; And a plurality of the generation circuits provided in relation to the plurality of the CPUs, When each of the plurality of the generation circuits determines that the function branch has occurred due to the execution of an instruction by the associated CPU, the generation circuit adds the CPU number of the associated CPU to the function branch information and outputs the function branch information to which the CPU number is added. The semiconductor device according to claim 1.

8. The semiconductor device is a SoC (System On Chip) or an MPU (Micro Processing Unit). The semiconductor device according to claim 1.

9. The semiconductor device according to claim 1, An emulator that adds a timestamp to the function branch information output from the semiconductor device and outputs the function branch information to which the timestamp is added, And a debugger that displays an execution history of a function executed by the CPU based on the function branch information to which the timestamp is added and output from the emulator. A debug system.

10. A control method for a semiconductor device, comprising: The semiconductor device includes: A CPU (Central Processing Unit) that executes instructions included in a program, A first register that stores an address of an instruction currently being executed by the CPU, And a second register that stores an address of a return destination when a function branch occurs due to the execution of an instruction by the CPU. The control method includes: Determining whether or not the function branch has occurred based on values of the first register and the second register before and after the execution of the instruction by the CPU; And when it is determined that the function branch has occurred, outputting a value of the first register after the execution of the instruction by the CPU as function branch information indicating an address of a branch destination of the function. A control method for a semiconductor device.

11. The first register is a program counter. The second register is a link register that stores the return address when a function is called by execution of an instruction by the CPU, or an exception link register that stores the return address when an exception occurs by execution of an instruction by the CPU. The method for controlling a semiconductor device according to claim 10.

12. A debugging method executed by a debugging system, The debugging system includes: a CPU (Central Processing Unit) that executes instructions included in a program, a first register that stores the address of the instruction currently being executed by the CPU, and a second register that stores the return address when a function branch occurs by execution of an instruction by the CPU, a semiconductor device including the same, an emulator, and a debugger, The debugging method includes: the semiconductor device determining whether or not the function branch has occurred based on values of the first register and the second register before and after execution of an instruction by the CPU; when the semiconductor device determines that the function branch has occurred, outputting the value of the first register after execution of the instruction by the CPU as function branch information indicating the branch destination address of the function; the emulator adding a time stamp to the function branch information output from the semiconductor device and outputting the function branch information with the added time stamp; and the debugger displaying an execution history of the function executed by the CPU based on the function branch information with the added time stamp output from the emulator. Debugging method.

13. The first register is a program counter, The second register is a link register that stores the return address when a function is called by execution of an instruction by the CPU, or an exception link register that stores the return address when an exception occurs by execution of an instruction by the CPU. The debugging method according to claim 12.

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