Memory controller, and control method

Abstract

To suppress decrease in utilization efficiency of a memory.SOLUTION: A memory controller is connected to a memory that includes a plurality of bank groups each including a plurality of banks, the memory controller including: a hold circuit that holds a plurality of access requests to the memory; a read-write control circuit that generates read / write commands from each of the plurality of access requests such that banks of different bank groups are set as destinations of adjacent read or write commands; and a page control circuit that issues a page control command for an access request that is selected from the plurality of access requests. The page control circuit preferentially issues a page control command for an access request for which open / close states of pages of a plurality of banks that is set as destinations satisfy a predetermined condition.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory controller and a control method.

Background Art

[0002] Generally, DRAM is used as the main memory device of a computer system. With the higher functionality and performance of computer systems, the performance requirements for DRAM have increased, and various methods for memory controllers have been proposed to more effectively extract its performance.

[0003] DRAM is configured to have a plurality of bank groups each consisting of a plurality of banks, and there are those that improve the data transfer rate by operating prefetch independently between bank groups. In such DRAM, when read commands or write commands are continuously issued to banks in the same bank group, the interval between those commands needs to satisfy the timing constraints for ensuring the completion of the prefetch of the previous command. For this reason, a gap occurs in the data bus, which becomes a factor in reducing the memory utilization efficiency. Hereinafter, read commands and write commands are collectively referred to as read / write commands. In Patent Document 1, the memory controller issues adjacent read / write commands divided from one memory access request to banks in different bank groups to suppress a decrease in memory utilization efficiency.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In Patent Document 1, there is no mention of page control when issuing adjacent read commands / write commands split from one memory access request to banks in different bank groups. Even if adjacent read / write commands are issued to banks in different bank groups, if there is a gap between page control commands for a plurality of banks that are the access destinations of those commands, a redundant gap occurs between the commands and the memory utilization efficiency decreases. One of the objectives of the present disclosure is to solve such problems.

Means for Solving the Problems

[0006] A memory controller according to an aspect of the present invention is a memory controller connected to a memory having a plurality of bank groups each having a plurality of banks, holding means for holding a plurality of access requests to the memory, read / write control means for generating read / write commands so that adjacent read / write commands from each of the plurality of access requests are addressed to banks in different bank groups, page control means for issuing page control commands for an access request selected from the plurality of access requests, and the page control means preferentially issues page control commands for access requests in which the open / close states of pages of a plurality of banks that are destinations satisfy a predetermined condition.

Advantages of the Invention

[0007] According to the present invention, it is possible to suppress a decrease in memory utilization efficiency.

Brief Description of the Drawings

[0008]

Figure 1

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] <First Embodiment> FIG. 1 is a block diagram showing a configuration example of a memory controller 100 according to the first embodiment. The memory controller 100 is connected to a DRAM 110 and a bus master 120, and selects an arbitrary memory access request from a plurality of memory access requests and issues a command. The DRAM 110 is a memory having a plurality of bank groups each having a plurality of banks. In the present embodiment, the DRAM 110 will be described as having a configuration in which there are four bank groups each having four banks. However, the present disclosure does not limit the number of bank groups and the number of banks in a bank group, and it is sufficient that the number of bank groups is two or more and the number of banks in a bank group is one or more. The bus master 120 transmits a memory access request (including write data in the case of a write command) including address information to the memory controller 100. The memory controller 100 generates a DRAM command including a read / write command and a page control command based on the memory access request received from the bus master 120, and transmits it to the DRAM 110. Further, the memory controller 100 performs data transfer with the DRAM 110 based on the transmitted DRAM command.

[0011] Next, the configuration of the memory controller 100 will be described. The access holding circuit 101 is a buffer that holds a plurality of memory access requests from the bus master 120. The access holding circuit 101 of the present embodiment can hold m pieces (m≧2) of entry data. In this example, m = 4 will be described, but the present disclosure does not limit the number of m. FIG. 2(A) is a diagram showing a data configuration example of the entry data 200 held in the access holding circuit 101. Up to m pieces of the entry data 200 shown in FIG. 2(A) can be held in the access holding circuit 101. As shown in FIG. 2(A), the entry data 200 has fields of access type, target bank group, target bank, target page, target column, and remaining read / write command count. The access holding circuit 101 converts and holds the memory access request received from the bus master 120 so as to correspond to each field of the entry data 200. The information stored in each field is as follows.

[0012] (a) Access type field The access type of the memory access request stored in the entry. WRITE: The memory access request is a write (data writing). READ: The memory access request is a read (data reading). (b) Target bank group field The bank group address to which the memory access request stored in the entry accesses. (c) Target bank field The bank address to which the memory access request stored in the entry accesses. (d) Target page field The page address to which the memory access request stored in the entry accesses. (e) Target column field The starting column address to which the memory access request stored in the entry accesses. (f) Remaining read / write command count field The number of remaining DRAM read / write commands to be executed by the memory access request stored in the entry.

[0013] The access holding circuit 101 holds the entry data while maintaining the order in which the memory access requests are received from the bus master. When a new memory access request is stored in the access holding circuit 101, the access holding circuit 101 stores the corresponding entry data in order from the first entry. Also, when one entry data is deleted, the access holding circuit 101 shifts the entry data of the memory access information received after the deleted entry data to the entry on the head side. Then, the access holding circuit 101 stores a new memory access request from the bus master 120 in the entry following the last of the stored memory access requests. In this way, the entries are held in the access holding circuit 101 in the order in which they are held. On the other hand, when the read / write control circuit 102 and the page control circuit 103 read a memory access request from the access holding circuit 101, they can read from any entry.

[0014] Subsequently, the entry control signal input to the access holding circuit 101 will be described. FIG. 2(B) is a diagram showing an example of the data configuration of the entry control signal 210. The entry control signal 210 has an entry number field, a deletion field, and an update field. When 1 is set in the deletion field of the entry control signal 210, the access holding circuit 101 deletes the entry indicated by the entry number field. When 1 is set in the update field, the access holding circuit 101 updates the target bank group field and the target column field of the entry indicated by the entry number field to the bank group address and the first column address of the next read / write command. Also, at this time, the access holding circuit 101 updates the remaining read / write command count field to a value obtained by subtracting 1.

[0015] The bank group address and the first column address of the read / write command are calculated based on the address information of the entry and the memory map 300 shown in FIG. 3. The memory map 300 of the present embodiment assumes that the DRAM data has a 32-bit width and the burst length of the read / write command is 16. Also, since it is assumed that the data width of the memory access request is 8 bits / address, the 4 addresses represented by the lower 2 bits (addr[0] and addr[1]) of the memory access request address are not assigned to the DRAM address. To achieve a burst length of 16 with a 32-bit width, 32 addresses (column addresses [0] to [3]) are accessed in one read / write access. By assigning the bank group address [1] to the bit immediately above the column address [3], the first bit of the bank group address toggles in adjacent read / write commands. As a result, the read / write commands are issued to different bank groups. Note that the present disclosure is not dependent on the memory map 300 shown in FIG. 3, and any memory map may be used as long as adjacent read / write commands have different bank group addresses.

[0016] The read / write control circuit 102 can refer to all of the memory access requests stored in the access holding circuit 101. The read / write control circuit 102 selects an arbitrary memory access request from the memory access requests stored in the access holding circuit 101 for which the page to be accessed is open. Whether or not the page to be accessed by the memory access request is open is determined from the target bank group field, the target bank field, and the target page field of the entry data 200, and the bank state generated by the bank state management circuit 104. The read / write control circuit 102 generates a read / write command from the selected memory access request and outputs it to the command selector 105.

[0017] Next, the generation procedure of the entry control signal by the read / write control circuit 102 will be described. When the last read / write command executed by one memory access request is issued, the processing of the memory access request is completed. In this case, the read / write control circuit 102 generates an entry control signal (the deletion field is set to 1) instructing the access holding circuit 101 to delete the entry corresponding to the memory access request. On the other hand, when a non-last read / write command in the memory access request is issued, the read / write control circuit 102 generates an entry control signal to update the entry corresponding to the memory access request in the access holding circuit 101. However, when the last read / write command is issued, since the corresponding entry is to be deleted, there is no need to update the entry. Also, whether the issued read command or write command is the last one can be determined by whether the remaining read / write command count field of the entry data 200 is 1.

[0018] The page control circuit 103 can refer to all of the memory access requests stored in the access holding circuit 101. The page control circuit 103 generates page control commands such as an active command and a precharge command based on the memory access requests held by the access holding circuit 101 and the bank state output by the bank state management circuit 104. The generated page control commands are output to the command selector 105. Hereinafter, the active command will be described as the ACT command and the precharge command as the PRE command.

[0019] The bank state management circuit 104 updates the bank state based on the command issuance state input from the command selector 105. The command issuance state is composed of the command type (read, write) issued by the command selector 105 to the DRAM 110, and the bank group, bank, and page where the command was issued. The bank state includes information indicating whether a page is open for each bank constituting the DRAM 110 and the open page address.

[0020] The command selector 105 selects one from the read / write commands input from the read / write control circuit 102, the ACT command and the PRE command input from the page control circuit 103, and issues it to the DRAM 110. Although not described in this embodiment, commands such as refresh may be selected together. Further, the command selector 105 generates information on the command issue state from the command type of the command issued to the DRAM 110, and the bank group, bank, and page where the command was issued, and outputs it to the bank state management circuit 104.

[0021] FIG. 4 is a block diagram showing a configuration example of the page control circuit 103 in the first embodiment. The page control circuit 103 includes an ACT command issue request generation circuit (hereinafter, ACT request generation circuit 401) and an ACT command issue request selection circuit (hereinafter, ACT request selection circuit 402). Further, the page control circuit 103 includes a PRE command issue request generation circuit (hereinafter, PRE request generation circuit 403) and a PRE command issue request selection circuit (hereinafter, PRE request selection circuit 404).

[0022] The ACT request generation circuit 401 and the ACT request selection circuit 402 preferentially issue a page control command (ACT command) for a memory access request in which the open / closed states of pages in a plurality of destination banks satisfy a predetermined condition. For each of the memory access requests held by the access holding circuit 101, the ACT request generation circuit 401 generates an ACT command issuance request based on the bank state provided by the bank state management circuit 104. Further, the ACT request generation circuit 401 determines whether or not the generated ACT command issuance request should be preferentially selected by the ACT request selection circuit 402 based on the bank state of the destination of the memory access request, and generates a priority ACT flag indicating the determination result. FIG. 5 is a flowchart showing the generation process of the ACT command issuance request in the present embodiment. Hereinafter, the operation of the ACT request generation circuit 401 will be described in more detail with reference to the flowchart of FIG. 5. The generation process of the ACT command issuance request is executed for each of the memory access requests held by the access holding circuit 101 in each cycle of the memory access.

[0023] The ACT request generation circuit 401 specifies the access destination bank of the memory access request based on the target bank group, target bank, remaining read / write command count of the memory access request, and the number n of banks to be sequentially accessed by the memory access request (S500). In the memory map 300 (FIG. 3) of the present embodiment, n = 2 because the memory access request alternately accesses two banks belonging to different bank groups. Therefore, for example, when the target bank group is 0, the target bank is 0, and the remaining read / write command count is 2 or more, the access destination banks are two banks indicated by (bank group address, bank address) = (0, 0) and (2, 0). Note that although n = 2 in the present embodiment, the present invention is not limited to this. That is, n does not limit the number of bank groups and the number of banks within the bank group, and may be 2 or more, not more than the number of bank groups, and a power of 2.

[0024] Next, the ACT request generation circuit 401 determines whether there is a bank in which all pages are closed among the n access destination banks (S501). If it is determined that there is no access destination bank in which all pages are closed (NO in S501), the ACT request generation circuit 401 does not generate an ACT command issuance request (S502). On the other hand, if it is determined that there is an access destination bank in which all pages are closed (YES in S501), the ACT request generation circuit 401 determines whether there is a bank that has opened the target page for the access destination bank (S503).

[0025] When it is determined that there is no access destination bank that has opened the target page (NO in S503), the ACT request generation circuit 401 generates a request to issue an ACT command to the access destination bank in a state where all pages are closed (S504). In this case, since there is no bank that has opened the target page for the access destination bank, even if the issuance of the ACT command is delayed, no redundant gap occurs between the read / write commands. Therefore, the ACT request generation circuit 401 de-asserts the priority ACT flag associated with the generated ACT command issuance request in order to notify the ACT request selection circuit 402 that it is not necessary to prioritize this ACT command (S504). On the other hand, when it is determined that there is an access destination bank that has opened the target page (YES in S503), the ACT request generation circuit 401 generates a request to issue an ACT command to the access destination bank in a state where all pages are closed (S505). In this case, among the access destination banks, there are a bank in a state where it is possible to issue an ACT command (a bank with all pages closed) and a bank in a state where the issuance of the ACT command is unnecessary (a bank with the target page opened). The ACT request generation circuit 401 generates a request to issue an ACT command to the bank in a state where it is possible to issue an ACT command. Also, in this way, among the access destination banks, there are a bank with the target page opened and a bank without it, and if the issuance of the ACT command to the bank without the target page opened is delayed, a redundant gap occurs between the read / write commands. Therefore, the ACT request generation circuit 401 asserts the priority ACT flag associated with the generated ACT command issuance request in order to notify the ACT request selection circuit 402 to prioritize the issuance of the ACT command (S505).

[0026] Note that when an ACT command issuance request is generated in S504 and S505, there may be multiple destination banks in a state where all pages are closed. In such a case, the ACT request generation circuit 401 generates an ACT command issuance request for the bank that is accessed earliest among those multiple destination banks. The bank that is accessed earliest can be determined, for example, from the target bank group and target bank of the entry data 200. More specifically, when the memory access request addresses increase sequentially, it is determined from the order of change of the destination banks indicated by the target bank group and target bank of the entry data 200. For example, in this embodiment, n = 2, and the bank group address [1] is used to access the bank groups alternately. Therefore, for example, when the target bank group of the entry data 200 is "10" and the target bank is "11", the bank that is accessed earliest is specified in the order of (1) and (2) below. (1) Bank "11" of bank group "10" (2) Bank "11" of bank group "00".

[0027] The ACT request selection circuit 402 selects one from the ACT command issuance requests generated by the ACT request generation circuit 401 and outputs it as an ACT command to the command selector 105. When multiple ACT command issuance requests are generated simultaneously, the ACT request selection circuit 402 preferentially selects the ACT command issuance request for which the priority ACT flag is asserted. If there are multiple ACT command issuance requests for which the priority ACT flag is asserted, the ACT request selection circuit 402 selects the ACT command issuance request for the memory access request that was held earliest in the access holding circuit 101 among them. As described above, in the access holding circuit 101, entries are held in the order in which they were held, and the memory access request that was held earliest can be easily determined.

[0028] According to the ACT command issuance control by the ACT request generation circuit 401 and the ACT request selection circuit 402 as described above, the ACT commands for one memory access request are issued in a consolidated manner. For example, when the number of banks sequentially accessed due to a memory access request is 2, it is necessary to issue two ACT commands for two different bank groups. According to the above-described ACT command issuance control, it is suppressed that an ACT command is issued to another bank group between the issuance of the first ACT command and the second ACT command due to a memory access request. Therefore, it is possible to suppress the occurrence of a redundant gap caused by a gap occurring between the first ACT command and the second ACT command, and the utilization efficiency of the memory is improved.

[0029] Also, by the PRE request generation circuit 403 and the PRE request selection circuit 404, a page control command (PRE command) for a memory access request in which the open / close states of the pages of a plurality of destination banks satisfy a predetermined condition is preferentially issued. The PRE request generation circuit 403 generates a PRE command issuance request for each of the memory access requests held by the access holding circuit 101 based on the bank state provided from the bank state management circuit 104. Further, the PRE request generation circuit 403 determines whether or not the generated PRE command issuance request should be preferentially selected by the PRE request selection circuit 404 based on the bank state of the destination of the memory access request, and generates a priority PRE flag indicating the determination result. FIG. 6 is a flowchart showing the generation process of the PRE command issuance request in the present embodiment. Hereinafter, the operation of the PRE request generation circuit 403 will be described in detail with reference to the flowchart of FIG. 6. Note that the generation process of the PRE command issuance request is executed for each of the memory access requests held by the access holding circuit 101 for each memory access cycle.

[0030] The PRE request generation circuit 403 identifies the destination bank of the memory access request based on the target bank group of the memory access request, the target bank, the remaining number of read / write commands, and the number n of banks to be sequentially accessed by the memory access request (S600). The method for identifying the destination bank is the same as the generation process of the ACT command issuance request described above (Figure 5).

[0031] The PRE request generation circuit 403 determines whether there is a bank that has opened a page other than the target page for the destination bank (S601). If it is determined that there is no access destination bank that has opened a page other than the target page (NO in S601), the PRE request generation circuit 403 does not generate a PRE command issuance request (S602). If it is determined that there is an access destination bank that has opened a page other than the target page (YES in S602), the PRE request generation circuit 403 determines whether there is an access destination bank in a state where all pages are closed or the target page is open (S603).

[0032] If it is determined that there is no access destination bank with all pages closed or with the target page open (NO in S603), the PRE request generation circuit 403 generates a PRE command issuance request. In this case, even if the issuance of the PRE command is delayed, no redundant gap occurs between read / write commands. Therefore, in order to notify the PRE request selection circuit 404 that it is not necessary to prioritize the issuance of the PRE command, the priority PRE flag related to the PRE command issuance request is de-asserted (S604). On the other hand, if there is an access destination bank with all pages closed or with the target page open (YES in S603), the PRE request generation circuit 403 generates a PRE command issuance request (S605). In this case, among the access destination banks, there are banks that require the issuance of a PRE command (banks with pages other than the target page open) and banks that do not require the issuance of a PRE command (banks with all pages closed and banks with the target page open). The PRE request generation circuit 403 generates a PRE command issuance request for the banks that require the issuance of a PRE command. Also, when there are banks that require a PRE command and banks that do not in the access destination bank like this, if the issuance of the PRE command to the banks that require the PRE command is delayed, a redundant gap occurs between read / write commands. Therefore, the PRE request generation circuit 403 asserts the priority PRE flag related to the PRE command issuance request in order to notify the PRE request selection circuit 404 to prioritize the PRE command issuance request (S605).

[0033] Note that when generating a PRE command issuance request in S604 and S605, if pages other than the target page are open in multiple banks among the access destination banks, a PRE command issuance request is generated for the bank that is accessed earliest among those banks. Regarding the bank that is accessed earliest, it is as described above with respect to S504 and S505.

[0034] The PRE request selection circuit 404 selects one from the PRE command issuance requests generated by the PRE request generation circuit 403 and outputs it as a PRE command to the command selector 105. When a plurality of PRE command issuance requests are generated simultaneously, the PRE request selection circuit 404 preferentially selects the PRE command issuance request for which the priority PRE flag is asserted. If there are a plurality of PRE command issuance requests for which the priority PRE flag is asserted, the PRE request selection circuit 404 selects the PRE command issuance request for the memory access request that was stored in the access holding circuit 101 earliest among them.

[0035] According to the PRE command issuance control by the PRE request generation circuit 403 and the PRE request selection circuit 404 as described above, the PRE commands necessary for issuing an ACT command for one memory access request are issued in a consolidated manner. For example, when the number of banks sequentially accessed by a memory access request is 2, it is necessary to close the two banks. According to the above-described PRE command issuance control, the PRE commands for closing the two banks are issued in a consolidated manner. As a result, the issuance of the first ACT command and the second ACT command due to the memory access request can be made continuous, the occurrence of a redundant gap caused by an interval occurring between those ACT commands can be suppressed, and the utilization efficiency of the memory is improved.

[0036] As described above, according to the first embodiment, when adjacent read / write commands divided from one memory access request are issued to banks in different bank groups, page control for the access destination bank of the read / write commands is executed intensively. For this reason, a decrease in memory utilization efficiency can be suppressed.

[0037] <Second Embodiment> The second embodiment solves the problem that the memory access efficiency decreases because the issuance of read / write commands is delayed due to the selection of a memory access request to a bank group during prefetch execution. FIG. 7 is a block diagram showing a configuration example of the memory controller 100a according to the second embodiment. The same components as those in the first embodiment (FIG. 1) are denoted by the same reference numerals. The read / write control circuit 102a of the second embodiment uses the command issuance state input from the command selector 105 to determine whether each bank group is in the middle of prefetch execution, and operates so as not to select a memory access request that requires waiting for prefetch completion. As a result, the selection of a memory access request to a bank group during prefetch execution is avoided, and a decrease in memory utilization efficiency is suppressed.

[0038] FIG. 8 is a block diagram showing a configuration example of the read / write control circuit 102 according to the second embodiment. The read / write control circuit 102a includes a page open determination circuit 801, a priority access type determination circuit 802, a bank group prefetch determination circuit (hereinafter referred to as the prefetch determination circuit 803), a memory access request selection circuit 804, and timers 805 to 808. The timers 805 to 808 correspond to the bank groups 0 to 3 of the DRAM 110.

[0039] The page open determination circuit 801 determines whether the target bank of the target bank group has opened the target page for each of the memory access requests stored in the access holding circuit 101 based on the bank state. Then, the page open determination circuit 801 outputs only the memory access requests for which the target page is open among the memory access requests stored in the access holding circuit 101 to the priority access type determination circuit 802, and masks the other memory access requests.

[0040] The priority access type determination circuit 802 determines whether the access type of each memory access request output by the page open determination circuit 801 corresponds to the priority access type. The priority access type is generated by the priority access type determination circuit 802 based on the memory access requests stored in the access holding circuit 101 and the bank state, and indicates which of the read command and the write command is to be issued preferentially. The priority access type determination circuit 802 outputs only the memory access requests corresponding to the priority access type to the prefetch determination circuit 803 and masks the other memory access requests.

[0041] FIG. 9 is a flowchart showing an example of the determination process of the priority access type by the priority access type determination circuit 802. The priority access type determination circuit 802 determines the priority access type according to this flowchart every cycle. Also, when there is no access to the access holding circuit 101, the read is set as the priority access type.

[0042] In S901 to S903, the priority access type determination circuit 802 determines whether there is a read or write memory access request in the access holding circuit 101. If neither read nor write exists (NO in S901), the priority access type determination circuit 802 sets "read" as the priority access type (S912). Also, when only a read memory access request exists in the access holding circuit 101 (YES in S901, YES in S902), the priority access type determination circuit 802 sets "read" as the priority access type (S132). On the other hand, when only a write memory access request is held in the access holding circuit 101 (YES in S903), the priority access type determination circuit 802 sets "write" as the priority access type (S911).

[0043] When there are both read and write memory access requests to the access holding circuit 101 (NO in S903), the priority access type determination circuit 802 determines whether the current priority access type is read or write (S904). Note that the current priority access type is the access type (read or write) determined to have priority in the previous cycle. When the current priority access type is "read" (YES in S904), it is determined whether there is an access in the same direction as the priority access type (here, "read") and the target page has already been opened (S905). On the other hand, when the priority access type is "write" (NO in S904), it is determined whether there is an access in the same direction as the priority access type (here, "write") and the target page has already been opened (S906). If there is a corresponding access in each case (YES in S905 or S906), the priority access type is not changed (S907, S909). On the other hand, if there is no corresponding access (NO in S905 or S906), the priority access type is changed (S908, S910). The priority access type is determined as described above.

[0044] When the command issuance state output from the command selector 105 indicates the issuance of a read / write command to bank group 0, the timer 805 sets the period during which a read / write command cannot be issued to the same bank group by the prefetch operation. The value of the timer 805 is decremented over time and stops at 0 except during the setting. The timers 806 to 808 perform the same operation as the timer 805 for the corresponding bank groups 1 to 3, respectively.

[0045] The prefetch determination circuit 803 determines, for each of the memory access requests output by the priority access type determination circuit 802, whether a prefetch completion wait for the target bank group is necessary. Whether a prefetch completion wait for the target bank group is necessary is determined based on whether the values of the timers 805 to 808 corresponding to the target bank group of the memory access request are non-zero. The prefetch determination circuit 803 outputs only the memory access requests for which a prefetch completion wait for the target bank group does not occur to the memory access request selection circuit 804, and masks the memory access requests for which a prefetch completion wait occurs.

[0046] The memory access request selection circuit 804 selects an arbitrary memory access request from the memory access requests output by the prefetch determination circuit 803. Then, it generates a read command or a write command for the selected memory access request and outputs it to the command selector 105.

[0047] As described above, according to the second embodiment, it is possible to suppress a decrease in memory utilization efficiency by not selecting memory access requests that require a prefetch completion wait for the bank group.

[0048] As described above, according to the memory controller of the present disclosure, when issuing adjacent read / write commands from one memory access request to banks in different bank groups, page control for the banks that are the destinations of the read / write commands is executed intensively. For this reason, a decrease in the memory utilization efficiency of the DRAM is suppressed. Further, the memory controller of the present disclosure can be used in various memory controllers that are connected to a DRAM and select an arbitrary memory access request from a plurality of memory access requests and issue a command.

[0049] The disclosure of this specification includes the following memory controller and its control method. (Item 1) A memory controller connected to a memory having a plurality of bank groups each having a plurality of banks, Holding means for holding a plurality of access requests to the memory; Read / write control means for generating a read / write command from each of the plurality of access requests so that the banks of different bank groups with adjacent read / write commands are the destinations; Page control means for issuing a page control command for an access request selected from the plurality of access requests, and comprising: The page control means preferentially issues a page control command for an access request in which the open / close states of the pages of a plurality of destination banks satisfy a predetermined condition. A memory controller characterized by this. (Item 2) The page control means preferentially issues a page control command for an access request including a bank in a state where the page control command can be issued and a bank in a state where the issuance of the page control command is unnecessary as destinations. The memory controller according to Item 1, characterized by this. (Item 3) The page control command is an active command, The bank in a state where the page control command can be issued is a bank that has closed all pages, The bank in a state where the issuance of the page control command is unnecessary is a bank that has opened the target page of the read / write command generated from the access request. The memory controller according to Item 2, characterized by this. (Item 4) The page control means preferentially issues a page control command for an access request including a bank in a state where the issuance of the page control command is necessary and a bank in a state where the issuance of the page control command is unnecessary as destinations. The memory controller according to any one of Items 1 to 3, characterized by this. (Item 5) The page control command is a precharge command, The bank in a state where it is necessary to issue the page control command is a bank that has opened a page different from the target page of the read / write command generated from the access request. The memory controller according to item 4, wherein the bank in a state where it is not necessary to issue the page control command is a bank that has not opened a page different from the target page. (Item 6) When there are a plurality of page control commands generated from one access request in which the states of a plurality of destination banks satisfy the predetermined conditions, the page control means preferentially issues the page control command for the bank that is accessed earliest among the plurality of banks. The memory controller according to any one of items 1 to 5. (Item 7) When there are two or more access requests in which the states of a plurality of destination banks satisfy the predetermined conditions, the page control means preferentially issues the page control command generated from the access request that is held earliest by the holding means among the plurality of access requests. The memory controller according to any one of items 1 to 6. (Item 8) The read / write control means generates a read / write command for an access request selected from the remaining access requests excluding the access requests including the bank group in which prefetch is being executed as the destination among the plurality of access requests. The memory controller according to any one of items 1 to 7. (Item 9) The read / write control means determines which of the read and write commands to give priority to based on the access type of the plurality of access requests and the state of the bank that is the destination of the plurality of access requests. The memory controller according to any one of items 1 to 8. (Item 10) A control method for a memory controller connected to a memory having a plurality of bank groups each having a plurality of banks, A holding step of holding a plurality of access requests to the memory in a holding circuit; A read / write control step of generating a read / write command from each of the plurality of access requests so that a bank in a different bank group with an adjacent read / write command is the destination; A page control step of issuing a page control command for an access request selected from the plurality of access requests, and comprising: In the page control step, a page control command for an access request in which the open / close states of pages of a plurality of destination banks satisfy a predetermined condition is preferentially issued. A control method for a memory controller, characterized by this.

[0050] The invention is not limited to the above embodiments, and various changes and modifications are possible without departing from the spirit and scope of the invention. Therefore, claims are attached to disclose the scope of the invention.

Explanation of reference numerals

[0051] 100, 100a: Memory controller, 101: Access holding circuit, 102, 102a: Read / write control circuit, 103: Page control circuit, 104: Bank state management circuit, 105: Command selector, 110: DRAM, 120: Bus master

Claims

1. A memory controller connected to a memory having a plurality of bank groups each having a plurality of banks, comprising: holding means for holding a plurality of access requests to the memory; read / write control means for generating a read / write command from each of the plurality of access requests such that the destination is a bank in a different bank group where adjacent read / write commands are different; page control means for issuing a page control command for an access request selected from the plurality of access requests; wherein the page control means preferentially issues a page control command for an access request in which the open / close states of pages of a plurality of destination banks satisfy a predetermined condition.

2. The memory controller according to claim 1, wherein the page control means preferentially issues a page control command for an access request including a bank in a state where the page control command can be issued and a bank in a state where issuance of the page control command is unnecessary as destinations.

3. The page control command is an active command, the bank in a state where the page control command can be issued is a bank in which all pages are closed, and the bank in a state where issuance of the page control command is unnecessary is a bank in which the target page of the read / write command generated from the access request is open.

4. The memory controller according to claim 1, wherein the page control means preferentially issues a page control command for an access request including a bank in a state where issuance of the page control command is necessary and a bank in a state where issuance of the page control command is unnecessary as destinations.

5. The page control command is a precharge command, the bank in a state where issuance of the page control command is necessary is a bank in which a page different from the target page of the read / write command generated from the access request is open, and the bank in a state where issuance of the page control command is unnecessary is a bank in which a page different from the target page is not open.

6. When there are a plurality of page control commands generated from one access request in which the states of a plurality of destination banks satisfy the predetermined conditions, the page control means issues a page control command for the bank that is accessed earliest among the plurality of banks, giving priority thereto. The memory controller according to claim 1, characterized in that.

7. When there are two or more access requests in which the states of a plurality of destination banks satisfy the predetermined conditions, the page control means issues a page control command generated from the access request that was held earliest by the holding means among the plurality of access requests, giving priority thereto. The memory controller according to claim 1, characterized in that.

8. The read / write control means generates a read / write command for an access request selected from the remaining access requests excluding the access request that includes a bank group in which prefetch is being executed as a destination among the plurality of access requests. The memory controller according to claim 1, characterized in that.

9. The read / write control means determines which of the read and write commands to give priority to based on the access type of the plurality of access requests and the state of the bank that is the destination of the plurality of access requests. The memory controller according to claim 1, characterized in that.

10. A control method for a memory controller connected to a memory having a plurality of bank groups each having a plurality of banks, comprising: a holding step of holding a plurality of access requests to the memory in a holding circuit; a read / write control step of generating a read / write command from each of the plurality of access requests so that the destination is a bank in a bank group where adjacent read / write commands are different; a page control step of issuing a page control command for an access request selected from the plurality of access requests; and In the page control step, a page control command for an access request in which the open / close state of the pages of a plurality of destination banks satisfies a predetermined condition is issued with priority. A control method for a memory controller, characterized in that.

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