Delay circuit, control device, and driving system

Abstract

To suppress the change in driving time of a driving target even if power source voltage varies.SOLUTION: A delay circuit 10 includes an inverter 11, a resistor element R1 having one end connected to an output end of the inverter 11, NMOS transistors 12 and 13, and a resistor element R2 having one end connected to the power source voltage. To the inverter 11, a pulse signal Vin for generating a control signal is input from a logic circuit 20. The NMOS transistor 12 has a gate terminal connected to the other end of the resistor element R1 and a drain terminal and a source terminal connected to a ground potential, thereby forming a MOS capacitor. The NMOS transistor 13 has a gate terminal connected to the other end of the resistor element R1, a source terminal connected to a ground potential, and a drain terminal connected to the other end of the resistor element R2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a delay circuit, a control device, and a drive system.

Background Art

[0002] In a drive circuit that drives a drive target, control may be performed to drive the drive target based on the pulse period in a control signal input from the outside. In such a case, if a pulse signal with a constant pulse period is generated by a logic circuit and output as a control signal, the drive time of the drive target cannot be adjusted to an optimal time.

[0003] Therefore, in a logic circuit, a pulse signal for generating a control signal is input to a delay circuit, and the control signal is generated based on the delayed pulse signal, so as to adjust and optimize the pulse period of the control signal.

[0004] As a configuration of a delay circuit for delaying a pulse signal in this way, a delay circuit using a CR circuit composed of a capacitor and a resistor element may be used (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the delay circuit disclosed in Patent Document 1, the output of the CR circuit is inverted by an inverter. In this delay circuit, due to the charging and discharging of the CR circuit, the rising waveform of the signal input to the inverter is distorted or rounded, resulting in a delay in the time until the logic threshold of the inverter is reached and a transition time occurs. As a result, the pulse signal output from the inverter is delayed from the input pulse signal.

[0007] Here, the relationship between the capacitance value C of the capacitive element, the charge voltage V of this capacitive element, the current I, and the transition time t at which the output logic of the inverter transitions is V = It / C. That is, when the capacitance value C of the capacitive element is constant, the main factor for the change in the transition time t is the current value of the current I.

[0008] However, in the delay circuit with the circuit configuration as described above, the current value of the current I changes depending on the height of the power supply voltage. Specifically, when the power supply voltage is high, the current value of the current I also increases, and when the power supply voltage is low, the current value of the current I also decreases. Thus, since the current value of the current I changes due to the fluctuation of the power supply voltage, the transition time t of the inverter also changes, and as a result, the delay time also changes.

[0009] Therefore, if a pulse signal is delayed using such a delay circuit to generate a control signal and output it to a drive circuit, the drive time of the drive target will change due to the fluctuation of the power supply voltage.

[0010] An object of the present invention is to provide a delay circuit, a control device, and a drive system capable of suppressing changes in the drive time of a drive target even when the power supply voltage fluctuates.

Means for Solving the Problems

[0011] To solve the above problems, the delay circuit of the present invention includes a first inverter to which a pulse signal for generating a control signal for controlling a drive circuit for driving a drive target is input, a resistive element having one end connected to the output terminal of the first inverter, A MOS capacitor connected to the other end of the resistance element, A second inverter connected to the MOS capacitor.

[0012] In addition, in order to solve the above problems, another delay circuit of the present invention is a delay circuit configured to be connectable to a logic circuit that outputs a control signal for controlling a drive circuit for driving a drive target, A first inverter to which a pulse signal for generating the control signal is input from the logic circuit, A resistance element having one end connected to the output end of the first inverter, A MOS capacitor connected to the other end of the resistance element, A second inverter connected to the MOS capacitor.

[0013] Furthermore, in order to solve the above problems, a control device of the present invention includes a logic circuit that outputs a control signal for controlling a drive circuit for driving a drive target, A first inverter to which a pulse signal for generating the control signal is input from the logic circuit, a resistance element having one end connected to the output end of the first inverter, a MOS capacitor connected to the other end of the resistance element, and a second inverter connected to the MOS capacitor, and a delay circuit having the same, The pulse period of the control signal is adjusted by delaying the pulse signal output from the logic circuit in the delay circuit.

[0014] Furthermore, in order to solve the above problems, a drive system of the present invention includes a drive circuit that drives a drive target, A logic circuit that outputs a control signal for controlling the drive circuit, A first inverter to which a pulse signal for generating the control signal is input from the logic circuit, a resistance element having one end connected to the output end of the first inverter, a MOS capacitor connected to the other end of the resistance element, and a second inverter connected to the MOS capacitor, and a delay circuit having the same, The pulse signal output from the logic circuit is delayed in the delay circuit, thereby adjusting the pulse width of the control signal.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Modes for Carrying Out the Invention

[0016] Next, embodiments of the present invention will be described in detail with reference to the drawings.

[0017] [First Embodiment] The configuration of the drive system according to the first embodiment of the present invention is shown in the block diagram of FIG. 1.

[0018] The drive system of this embodiment is composed of, for example, a drive circuit 30 that drives a drive target 40 such as a motor, and a control device 50.

[0019] The control device 50 includes a delay circuit 10 and a logic circuit 20.

[0020] The logic circuit 20 outputs a control signal for controlling the drive circuit 30. Specifically, the logic circuit 20 is a circuit that outputs a pulse signal of a specific period as a control signal to the drive circuit 30. The drive circuit 30 drives the drive target 40 only during the period when the control signal output from the logic circuit 20 is at a high level.

[0021] The delay circuit 10 is a delay circuit configured to be connectable to a logic circuit 20 that outputs a control signal for controlling the drive circuit 30. The delay circuit 10 includes an inverter 11, a resistor element R1 having one end connected to the output terminal of the inverter 11, NMOS transistors (N-channel MOSFETs (MOS Field Effect Transistors)) 12 and 13, and a resistor element R2 having one end connected to the power supply voltage.

[0022] A pulse signal Vin for generating a control signal is input from the logic circuit 20 to the inverter 11.

[0023] The gate terminal of the NMOS transistor 12 is connected to the other end of the resistor element R1, and the drain terminal and the source terminal are connected to the ground potential. Due to such a circuit configuration, the NMOS transistor 12 forms a MOS (Metal Oxide Semiconductor) capacitor. That is, the MOS capacitor formed by this NMOS transistor 12 is connected to the other end of the resistor element R1.

[0024] Here, a MOS capacitor is a capacitor that uses the gate capacitance formed by the gate oxide film as a capacitive element when the drain terminal and the source terminal of the MOSFET are at the same potential.

[0025] The terminal of the MOS capacitor formed by this NMOS transistor 12 that is not connected to the resistor element R1 is connected to the ground potential.

[0026] The gate terminal of the NMOS transistor 13 is connected to the other end of the resistor element R1, the source terminal is connected to the ground potential, and the drain terminal is connected to the other end of the resistor element R2.

[0027] Here, the NMOS transistor 13 and the resistor element R2 form an inverter, and this inverter is connected to the MOS capacitor formed by the NMOS transistor 12.

[0028] The pulse signal Vin output from the logic circuit 20 is logically inverted by the inverter 11, then passes through a CR circuit composed of a resistor element R1 and a MOS capacitor composed of an NMOS transistor 12, and is logically determined again by an inverter composed of an NMOS transistor 13 and a resistor element R2, and is fed back to the logic circuit 20 as a pulse signal Vout.

[0029] An example of the operation waveform in the control device 50 of the present embodiment shown in FIG. 1 is shown in the timing chart of FIG. 2.

[0030] In the logic circuit 20, for example, a control signal is generated by performing a logical sum operation between the pulse signal Vin before delay by the delay circuit 10 and the pulse signal Vout after delay by the delay circuit 10.

[0031] As can be seen with reference to FIG. 2, the control signal output from the logic circuit 20 is a signal in which the high-level period is longer by the delay time of the delay circuit 10 with respect to the pulse signal Vin output to the delay circuit 10. That is, in the control device 50, the pulse period of the control signal is adjusted by delaying the pulse signal Vin output from the logic circuit 20 in the delay circuit 10.

[0032] In addition, when the pulse period of the control signal cannot be adjusted to an optimal time with only one delay time in the delay circuit 10, the pulse signal Vout fed back from the delay circuit 10 is output again as the pulse signal Vin to the delay circuit 10. By doing so, it is also possible to adjust the pulse period of the control signal output to the drive circuit 30 to an optimal time.

[0033] As described above, when the pulse signal Vin is applied to the delay circuit 10, this pulse signal is applied to the gate terminal of the NMOS transistor 12 via the inverter 11 and the resistor element R1. At this time, a current starts to flow through the MOS capacitor formed by the NMOS transistor 12 and the voltage starts to be charged. Here, the current I flowing through the MOS capacitor gradually decreases as the charge voltage of the MOS capacitor increases.

[0034] And the relationship between the capacitance value C of the MOS capacitor formed by the NMOS transistor 12, the charge voltage V of this MOS capacitor, the current I, and the transition time t until the gate voltage of the NMOS transistor 13 reaches the threshold voltage is V = It / C as described above. That is, when the capacitance value C is constant, the main factor for the change in the transition time t is the current value of the current I. And the current value of the current I is determined by the driving ability of the inverter 11. The higher the power supply voltage, the greater the driving ability of the inverter 11. That is, the higher the power supply voltage, the larger the current value of the current I and the shorter the transition time t.

[0035] Here, the capacitance value of a general capacitive element such as a capacitor is constant regardless of the magnitude of the power supply voltage. Therefore, when a general capacitive element such as a capacitor is used instead of the MOS capacitor formed by the NMOS transistor 12, the transition time t from when the pulse signal Vin is input until the logic state of the NMOS transistor 13 changes will be greatly affected by the fluctuation of the power supply voltage.

[0036] However, the capacitance value of a MOS capacitor composed of MOS transistors has the characteristic of changing depending on the height of the applied gate voltage. Specifically, the MOS capacitor has the characteristic that the capacitance value increases when the gate voltage is high and the capacitance value decreases when the gate voltage is low. Therefore, when a MOS capacitor is used as the capacitive element of the CR circuit as in this embodiment, when the power supply voltage increases, the current I also increases, but the capacitance value of the capacitive element also increases. Conversely, when a MOS capacitor is used as the capacitive element of the CR circuit, when the power supply voltage decreases, the current I decreases, but the capacitance value of the capacitive element also decreases.

[0037] As a result, an effect can be obtained in which the change in the capacitance value of the MOS capacitor cancels out the change in the power supply voltage. That is, by adopting a configuration in which a MOS capacitor is used as the capacitive element in the delay circuit 10, it is possible to suppress a change in the delay time of the delay circuit 10 due to a change in the power supply voltage.

[0038] Therefore, according to the drive system of this embodiment, even when the power supply voltage fluctuates, it is possible to suppress a change in the drive time of the drive target 40.

[0039] [Second Embodiment] The configuration of the drive system according to the second embodiment of the present invention is shown in the block diagram of FIG. 3.

[0040] The drive system of this embodiment has a configuration in which the control device 50 is replaced with a control device 50A with respect to the drive system of the first embodiment shown in FIG. 1. And the control device 50A has a configuration in which the delay circuit 10 is replaced with a delay circuit 10A with respect to the control device 50.

[0041] And the delay circuit 10A in this embodiment has a configuration in which the NMOS transistor 12 is deleted and a PMOS transistor (P-channel MOSFET) 14 is added with respect to the delay circuit 10 shown in FIG. 1.

[0042] The PMOS transistor 14 has its gate terminal connected to the other end of the resistor element R1, and its drain terminal and source terminal are connected to the power supply voltage. Due to such a circuit configuration, the PMOS transistor 14 constitutes a MOS capacitor. That is, the MOS capacitor constituted by this PMOS transistor 14 is connected to the resistor element R1, and the terminal on the side not connected to the resistor element R1 is connected to the power supply voltage. That is, the MOS capacitor constituted by the PMOS transistor 14 is connected between the other end of the resistor element R1 and the power supply voltage.

[0043] Also in the delay circuit 10A of the present embodiment, the pulse signal Vin output from the logic circuit 20 is logically inverted by the inverter 11, then passes through a CR circuit composed of the resistor element R1 and the MOS capacitor constituted by the PMOS transistor 14, and is logically determined again by an inverter composed of the NMOS transistor 13 and the resistor element R2, and is fed back to the logic circuit 20 as the pulse signal Vout.

[0044] Therefore, also in the delay circuit 10A of the present embodiment, an effect can be obtained in which the change in the capacitance value of the MOS capacitor cancels out the change in the power supply voltage. That is, by adopting a configuration in which a MOS capacitor is used as the capacitive element in the delay circuit 10A, it is possible to suppress the change in the delay time of the delay circuit 10A due to the change in the power supply voltage.

[0045] Therefore, also by the drive system of the present embodiment, similar to the drive system of the first embodiment described above, even when the power supply voltage fluctuates, it is possible to suppress the change in the drive time of the drive target 40.

[0046] [Third Embodiment] The configuration of the drive system according to the third embodiment of the present invention is shown in the block diagram of FIG. 4.

[0047] The drive system of this embodiment has a configuration in which the control device 50 is replaced with the control device 50B with respect to the drive system of the first embodiment shown in FIG. 1. And the control device 50B has a configuration in which the delay circuit 10 is replaced with the delay circuit 10B with respect to the control device 50.

[0048] And the delay circuit 10B in this embodiment has a configuration in which a PMOS transistor 14 is added with respect to the delay circuit 10 shown in FIG. 1.

[0049] In the first embodiment described above, a MOS capacitor formed by the NMOS transistor 12 is connected between the other end of the resistance element R1 and the ground potential, and in the second embodiment, a MOS capacitor formed by the PMOS transistor 14 is connected between the other end of the resistance element R1 and the power supply voltage.

[0050] On the other hand, in the delay circuit 10B of this embodiment, a MOS capacitor formed by the NMOS transistor 12 is connected between the other end of the resistance element R1 and the ground potential, and a MOS capacitor formed by the PMOS transistor 14 is also connected between the other end of the resistance element R1 and the power supply voltage.

[0051] Thus, the delay circuit 10B in this embodiment has a circuit configuration further including a MOS capacitor formed by the PMOS transistor 14 connected between the other end of the resistance element R1 and the power supply voltage with respect to the delay circuit 10 in the first embodiment. Also, the delay circuit 10B in this embodiment has a circuit configuration further including a MOS capacitor formed by the NMOS transistor 12 connected between the other end of the resistance element R1 and the ground potential with respect to the delay circuit 10A in the second embodiment.

[0052] Even with a circuit configuration in which MOS capacitors are provided on both sides between the other end of the resistor element R1 and the power supply voltage and the ground potential, like the delay circuit 10B of the present embodiment, similar to the drive systems of the first and second embodiments described above, it is possible to suppress changes in the drive time of the drive target 40 even when the power supply voltage fluctuates.

Explanation of Signs

[0053] 10, 10A, 10B Delay circuit 11 Inverter 12 NMOS transistor 13 NMOS transistor 14 PMOS transistor 20 Logic circuit 30 Drive circuit 40 Drive target 50, 50A, 50B Control device R1, R2 Resistor element

Claims

1. A first inverter to which a pulse signal for generating a control signal for controlling a drive circuit for driving a drive target is input; A resistance element having one end connected to the output terminal of the first inverter; A MOS capacitor connected to the other end of the resistance element; A second inverter connected to the MOS capacitor; A delay circuit comprising:

2. A delay circuit configured to be connectable to a logic circuit that outputs a control signal for controlling a drive circuit for driving a drive target, A first inverter to which a pulse signal for generating the control signal is input from the logic circuit; A resistance element having one end connected to the output terminal of the first inverter; A MOS capacitor connected to the other end of the resistance element; A second inverter connected to the MOS capacitor; A delay circuit comprising:

3. A terminal of the MOS capacitor on the side not connected to the resistance element is connected to the ground potential, The delay circuit according to claim 1 or 2, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the power supply voltage.

4. A terminal of the MOS capacitor on the side not connected to the resistance element is connected to the power supply voltage, The delay circuit according to claim 1 or 2, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the ground potential.

5. A logic circuit that outputs a control signal for controlling a drive circuit for driving a drive target; A first inverter to which a pulse signal for generating the control signal is input from the logic circuit, a resistance element having one end connected to the output terminal of the first inverter, a MOS capacitor connected to the other end of the resistance element, and a second inverter connected to the MOS capacitor; and a delay circuit having the same, A control device, wherein the pulse period of the control signal is adjusted by delaying the pulse signal output from the logic circuit in the delay circuit.

6. A terminal of the MOS capacitor on the side not connected to the resistance element is connected to the ground potential, The control device according to claim 5, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the power supply voltage.

7. A terminal of the MOS capacitor on the side not connected to the resistance element is connected to the ground potential, The control device according to claim 5, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the power supply voltage.

8. ​ The terminal of the MOS capacitor on the side not connected to the resistance element is connected to the power supply voltage, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the ground potential, The control device according to claim 5.

8. A drive circuit for driving a drive target, A logic circuit that outputs a control signal for controlling the drive circuit, a first inverter to which a pulse signal for generating the control signal is input from the logic circuit, a resistance element having one end connected to the output terminal of the first inverter, a MOS capacitor connected to the other end of the resistance element, and a second inverter connected to the MOS capacitor. A delay circuit having, The pulse period of the control signal is adjusted by delaying the pulse signal output from the logic circuit in the delay circuit, A drive system.

9. The terminal of the MOS capacitor on the side not connected to the resistance element is connected to the ground potential, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the power supply voltage, The drive system according to claim 8.

10. The terminal of the MOS capacitor on the side not connected to the resistance element is connected to the power supply voltage, further comprising another MOS capacitor different from the MOS capacitor, connected between the other end of the resistance element and the ground potential, The drive system according to claim 8.

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