Qubit device and qubit device fabrication method

Abstract

To suppress increase in the number of wiring lines that accompanies a multi-bit configuration of qubits.SOLUTION: A quantum bit device includes a first qubit substrate, a second qubit substrate, and a first relay substrate provided between the first qubit substrate and the second qubit substrate. The first qubit substrate includes a first qubit, a first control electrode, and a first read-out electrode. The second qubit substrate includes a second qubit, a second control electrode, and a second read-out electrode. The first relay substrate includes: a first control line that is connected to the first control electrode, and transmits a control signal that controls the first qubit; a read-out line that is a line connected to both first and second read-out electrodes, and that transmits a response signal indicating a state of the first qubit or the second qubit; a first access electrode connected to the first control line; and a second access electrode connected to the read-out line.SELECTED DRAWING: Figure 5A

Description

Technical Field

[0001] The disclosed technology relates to a qubit device and a method for manufacturing a qubit device.

Background Art

[0002] As technologies related to qubit devices, the following technologies are known. For example, Patent Document 1 describes a quantum chip including a first substrate and a second substrate provided opposite to each other, and a plurality of connectors connected between the first substrate and the second substrate. A plurality of sets of coupled qubits and a first controller are provided on the surface of the first substrate facing the second substrate, and a plurality of control signal transmission units are provided on the surface of the second substrate facing the first substrate. The connectors connect the first controller and the control signal transmission units one-to-one.

[0003] Patent Document 2 describes a system including an auxiliary qubit chip including a plurality of auxiliary qubits and a data qubit chip including a plurality of data qubits. This system has an interposer coupled to the auxiliary qubit chip and the data qubit chip and including a plurality of superconducting structures.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] As a qubit constituting a qubit device such as a quantum computing device, one using a transmon is known. A transmon has a configuration in which a superconducting Josephson element and a capacitor are connected in parallel, and performs quantum computing using non-linear energy. In order to realize quantum computing using qubits, it is necessary to input a control signal for controlling the qubits and read out a response signal indicating the state of the qubits. That is, the qubit device needs to include a wiring for transmitting the control signal and a wiring for transmitting the response signal. When the number of wirings increases with the multi-bitization of qubits, it becomes necessary to arrange a plurality of wirings three-dimensionally, which complicates the manufacturing process and also causes crosstalk.

[0006] The disclosed technology has been made in view of the above points, and aims to suppress the number of wirings that increases with the multi-bitization of qubits.

Means for Solving the Problem

[0007] The qubit device according to the disclosed technology includes a first qubit substrate, a second qubit substrate, and a first relay substrate provided between the first qubit substrate and the second qubit substrate. The first qubit substrate has a first qubit, a first control electrode, and a first readout electrode. The second qubit substrate has a second qubit, a second control electrode, and a second readout electrode. The first relay substrate is connected to the first control electrode, and includes a first control wiring for transmitting a control signal for controlling the first qubit, a wiring connected to both the first readout electrode and the second readout electrode, and through which a response signal indicating the state of the first qubit or the second qubit is transmitted, a first access electrode connected to the first control wiring, and a second access electrode connected to the readout wiring.

Effect of the Invention

[0008] According to the disclosed technology, it is possible to suppress the number of wirings that increases with the multi-bitization of qubits.

Brief Description of the Drawings

[0009]

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[0010] Hereinafter, an example of the disclosed embodiment will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and duplicate descriptions are omitted.

[0011] FIG. 1 is an equivalent circuit diagram showing an example of the configuration of an arithmetic unit 100 that constitutes a qubit device according to an embodiment of the disclosed technology. In the qubit device, a plurality of arithmetic units 100 are integrated. The arithmetic unit 100 has a qubit 1, a resonator 2, and a filter 3, respectively.

[0012] The qubit 1 is an element that forms a coherent two-level system using superconductivity and performs quantum operations using non-linear energy. The qubit 1 has a transmon qubit circuit in which a superconducting Josephson element 4 and a capacitor 5 are connected in parallel. The superconducting Josephson element 4 has a pair of superconductors that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator with a thickness of about several nm sandwiched between the pair of superconductors. The superconductor may be, for example, aluminum, and the insulator may be, for example, aluminum oxide.

[0013] The resonator 2 is connected to the qubit 1 via the capacitor 10. When the resonator 2 interacts with the qubit 1, a response signal indicating the state of the qubit 1 is read out. The resonator 2 has a resonant circuit in which a superconducting inductor 6 and a capacitor 7 are connected in parallel. The filter 3 is connected to the resonator 2 via the capacitor 11. The filter 3 removes the noise components included in the response signal indicating the state of the qubit 1. The filter 3, like the resonator 2, has a resonant circuit in which a superconducting inductor 8 and a capacitor 9 are connected in parallel.

[0014] The control electrode 21, the ground electrode 22, and the readout electrode 23 are connected to the arithmetic unit 100. A control signal for controlling the qubit 1 is input to the control electrode 21. The quantum state of the qubit 1 is controlled by the control signal input to the control electrode 21. The response signal indicating the quantum state of the qubit 1 is read out from the readout electrode 23. An external ground potential is applied to the ground electrode 22. The ground potential applied to the ground electrode 22 is supplied to each part of the arithmetic unit 100.

[0015] The qubit device has a qubit substrate provided with a plurality of arithmetic units 100. FIG. 2 is a plan view showing an example of the configuration of the qubit substrate 30 constituting the qubit device according to the embodiment of the disclosed technology. The qubit substrate 30 has a plurality of unit structures 101 each including four arithmetic units 100.

[0016] FIG. 3 is an enlarged view showing one of the plurality of unit structures 101 shown in FIG. 2. The four qubits 1 constituting one unit structure 101 are arranged at positions corresponding to the four vertices of a square, and a readout electrode 23 is arranged at the center of the square. One readout electrode 23 is shared by four operation units 100. Resonators 2 and filters 3 are provided on each path from the four qubits 1 toward the readout electrode 23. Each qubit 1 is connected to another adjacent qubit 1 via a capacitor 31. Thereby, each qubit creates an entangled state with another adjacent qubit 1 to perform a quantum operation.

[0017] FIG. 4 is a perspective view schematically showing the configuration of a qubit device 200 according to an embodiment of the disclosed technology. The qubit device 200 is configured by alternately laminating qubit substrates and relay substrates. FIG. 4 shows a configuration in which qubit substrates 30A and 30B are laminated with a relay substrate 40A interposed therebetween. Among the qubits 1 provided on the qubit substrates 30A and 30B, those adjacent in the lamination direction are connected to each other via a coupling element 41 provided on the relay substrate 40A. The coupling element 41 may be any element that can electrically connect the upper and lower qubits, and a capacitor, a junction, an inductive coil, etc. may be used. Also, among the readout electrodes 23 provided on the qubit substrates 30A and 30B, those adjacent in the lamination direction are respectively connected to a readout wiring 48 provided on the relay substrate 40A. That is, a response signal read from each of the four qubits 1 included in the unit structure 101 provided on the qubit substrate 30A and a response signal read from each of the four qubits 1 included in the unit structure 101 provided on the qubit substrate 30B are multiplexed and transmitted on one readout wiring 48.

[0018] FIG. 5A and FIG. 5B are cross-sectional views showing an example of the configuration of the quantum bit device 200 according to an embodiment of the disclosed technology. The cross-sections shown in FIGS. 5A and 5B correspond to the cross-section along line 5-5 in FIG. 4. FIG. 5A shows the quantum bit substrate and the relay substrate disassembled, and FIG. 5B shows the state in which the quantum bit substrate and the relay substrate are joined together.

[0019] FIGS. 5A and 5B illustrate a configuration including two quantum bit substrates 30A and 30B and one relay substrate 40A. The relay substrate 40A is provided between the quantum bit substrates 30A and 30B. Hereinafter, when the quantum bit substrates 30A and 30B are not distinguished or are collectively referred to, they are denoted as the quantum bit substrate 30.

[0020] The quantum bit substrate 30 has, for example, a silicon substrate as the base material 32. On the first surface S1 of the base material 32, a quantum bit 1, a resonator 2, and a filter 3 are provided, and on the second surface S2 of the base material 32, a control electrode 21 is provided. The control electrode 21 is disposed directly below the quantum bit 1. The control signal input to the control electrode 21 acts on the quantum bit 1 through the base material 32.

[0021] The readout electrode 23 has a through-electrode structure that penetrates the base material 32. The response signal read from the quantum bit 1 through the resonator 2 and the filter 3 is drawn out to the second surface S2 of the base material 32 by the readout electrode 23 of the through-electrode structure. In the vicinity of the quantum bit 1, a connection electrode 24 electrically connected to the quantum bit 1 is provided. Each of the connection electrodes 24 has a through-electrode structure. A conductive path electrically connected to the quantum bit 1 is drawn out to the second surface S2 of the base material 32 by the connection electrode 24 of the through-electrode structure. This electrical connection may be a direct connection or an indirect connection such as inductive coupling or capacitive coupling.

[0022] Note that the qubit substrate 30A is an example of the "first qubit substrate" in the disclosed technology. The qubit substrate 30B is an example of the "second qubit substrate" in the disclosed technology. The qubit 1 provided on the qubit substrate 30A is an example of the "first qubit" in the disclosed technology. The qubit 1 provided on the qubit substrate 30B is an example of the "second qubit" in the disclosed technology. The control electrode 21 provided on the qubit substrate 30A is an example of the "first control electrode" in the disclosed technology. The control electrode 21 provided on the qubit substrate 30B is an example of the "second control electrode" in the disclosed technology. The readout electrode 23 provided on the qubit substrate 30A is an example of the "first readout electrode" in the disclosed technology. The readout electrode 23 provided on the qubit substrate 30B is an example of the "second readout electrode" in the disclosed technology.

[0023] The relay substrate 40A has, for example, low-temperature co-fired ceramics (LTCC) or high-temperature co-fired ceramics (HTCC) as the base material 42. The relay substrate 40A has a pair of capacitor electrodes 43a and 43b provided at positions corresponding to the formation positions of the connection electrodes 24 of the qubit substrate 30. The capacitor electrodes 43a and 43b face each other with the base material 42 interposed therebetween. The relay substrate 40A has a capacitor 41a which is an example of the coupling element 41 formed inside the base material 42. One end of the capacitor 41a is connected to the capacitor electrode 43a, and the other end of the capacitor 41a is connected to the capacitor electrode 43b. In this embodiment, the capacitor 41a is used as an example of the coupling element 41, but any element that functions as a coupling element may be used, such as a junction or a dielectric coil.

[0024] The relay substrate 40A has control wiring electrodes 45 provided at positions corresponding to the formation positions of the control electrodes 21 of the qubit substrates 30A and 30B, respectively. The relay substrate 40A has control wirings 46A and 46B formed inside the base material 42. The control wirings 46A and 46B are each connected to the control wiring electrode 45. The control wiring 46A is connected to the control electrode 21 of the qubit substrate 30A via the control wiring electrode 45. A control signal for controlling the qubit 1 provided on the qubit substrate 30A is transmitted to the control wiring 46A. The control wiring 46B is connected to the control electrode 21 of the qubit substrate 30B via the control wiring electrode 45. A control signal for controlling the qubit 1 provided on the qubit substrate 30B is transmitted to the control wiring 46B.

[0025] The relay substrate 40A has readout wiring electrodes 47 provided at positions corresponding to the formation positions of the readout electrodes 23 of the qubit substrates 30A and 30B. The relay substrate 40A has a readout wiring 48 connected to the readout wiring electrode 47.

[0026] The qubit substrate 30A is laminated on one surface side of the relay substrate 40A, and the qubit substrate 30B is laminated on the other surface side of the relay substrate 40A. The connection electrode 24 of the qubit substrate 30A is joined to the capacitor electrode 43a of the relay substrate 40A via a bump 49. The connection electrode 24 of the qubit substrate 30B is joined to the capacitor electrode 43b of the relay substrate 40A via a bump 49. Thereby, the qubit 1 provided on the qubit substrate 30A and the qubit 1 provided on the qubit substrate 30B are connected to each other via the capacitor 41a provided on the relay substrate 40A.

[0027] The control electrode 21 of the qubit substrate 30A is joined to the control wiring electrode 45 of the relay substrate 40A via the bump 49. As a result, the control electrode 21 of the qubit substrate 30A is connected to the control wiring 46A provided on the relay substrate 40A. Similarly, the control electrode 21 of the qubit substrate 30B is joined to the control wiring electrode 45 of the relay substrate 40A via the bump 49. As a result, the control electrode 21 of the qubit substrate 30B is connected to the control wiring 46B provided on the relay substrate 40A.

[0028] The readout electrode 23 of the qubit substrate 30A is joined to the readout wiring electrode 47 of the relay substrate 40A via the bump 49. Similarly, the readout electrode 23 of the qubit substrate 30B is joined to the readout wiring electrode 47 of the relay substrate 40A via the bump 49. As a result, the readout wiring 48 of the relay substrate 40A is connected to both the readout electrode 23 of the qubit substrate 30A and the readout electrode 23 of the qubit substrate 30B. That is, it is possible to read out both the response signal indicating the state of the qubit 1 provided on the qubit substrate 30A and the response signal indicating the state of the qubit 1 provided on the qubit substrate 30B from the readout wiring 48. Therefore, the response signals read from each of the four qubits 1 included in the unit structure 101 provided on the qubit substrate 30A and the response signals read from each of the four qubits 1 included in the unit structure 101 provided on the qubit substrate 30B are multiplexed and transmitted on one readout wiring 48.

[0029] Note that the relay substrate 40A is an example of the "first relay substrate" in the disclosed technology. The control wiring 46A is an example of the "first control wiring" in the disclosed technology. The control wiring 46B is an example of the "second control wiring" in the disclosed technology. The readout wiring 48 is an example of the "readout wiring" in the disclosed technology.

[0030] FIG. 6A is a plan view showing an example of the configuration of a capacitor 41a, which is an example of a coupling element 41 provided on the relay substrate 40A. The capacitor 41a may include a pair of conductors 50a and 50b provided with a gap in a wiring layer inside the base material 42. A capacitor is formed by interposing the base material 42, which is an insulator, between the conductor 50a and the conductor 50b. The conductor 50a is connected to the capacitor electrode 43a via a via (not shown), and the conductor 50b is connected to the capacitor electrode 43b via a via (not shown). The conductors 50a and 50b may have a comb-tooth pattern as shown in FIG. 6A in order to ensure the capacitance of the capacitor 41a.

[0031] FIG. 6B is a cross-sectional view showing an example of another configuration of the capacitor 41a provided on the relay substrate 40A. The capacitor 41a may include a conductor 50c provided on one surface of the base material 42 and a conductor 50d provided at a position facing the conductor 50c on the other surface of the base material 42. A capacitor is formed by interposing the base material 42, which is an insulator, between the conductor 50c and the conductor 50d. By using the base material 42 having a high dielectric constant, it is possible to form a capacitor 41a having a large capacitance even with a small area. Note that the conductor 50c may also serve as the capacitor electrode 43a, and the conductor 50d may also serve as the capacitor electrode 43b.

[0032] FIG. 6C is a cross-sectional view showing an example of another configuration of the capacitor 41a. The capacitor 41a may be formed by providing gaps between the connection electrode 24 of the qubit substrate 30A and the capacitor electrode 43a of the relay substrate 40A and between the connection electrode 24 of the qubit substrate 30B and the capacitor electrode 43b of the relay substrate 40A, respectively. In this case, the capacitor electrodes 43a and 43b are electrically connected to each other by vias 51 penetrating the base material 42. By forming the capacitor 41a using a vacuum gap, it is possible to suppress the charge leakage of the capacitor 41a and increase the Q value. Note that a spacer (not shown) may be provided between the qubit substrates 30A and 30B and the relay substrate 40A in order to form the gap.

[0033] FIG. 7 is a plan view showing an example of the configuration of the qubit device 200. FIG. 8 is a plan view showing an enlarged part of FIG. 7. FIG. 9 is a cross-sectional view taken along line 9-9 in FIG. 8. FIG. 10 is a cross-sectional view taken along line 10-10 in FIG. 8.

[0034] The size of the relay substrate 40A is made larger than that of the qubit substrate 30A. Therefore, the relay substrate 40A has a portion that protrudes outward in the plane direction beyond the outer edge of the qubit substrate 30A. The size of the qubit substrate 30B is substantially the same as that of the relay substrate 40A.

[0035] The control wirings 46A, 46B and the readout wiring 48 provided inside the relay substrate 40A each extend to a portion of the relay substrate 40A that protrudes outward in the plane direction beyond the outer edge of the qubit substrate 30A. A plurality of input electrodes 60A, 60B and a plurality of output electrodes 61 are provided on the surface of the protruding portion of the relay substrate 40A. The plurality of input electrodes 60A correspond to the respective control wirings 46A, and the plurality of input electrodes 60B correspond to the respective control wirings 46B. The plurality of output electrodes 61 correspond to the respective readout wirings 48. As shown in FIG. 9, one end of the readout wiring 48 is connected to the corresponding readout wiring electrode 47 via vias 63a, 63b, and the other end is connected to the corresponding output electrode 61 via via 63c. As shown in FIG. 10, one end of the control wiring 46A is connected to the corresponding control wiring electrode 45 via via 62a, and the other end is connected to the corresponding input electrode 60A via via 62b. One end of the control wiring 46B is connected to the corresponding control wiring electrode 45 via via 62c, and the other end is connected to the corresponding input electrode 60B via via 62d.

[0036] Control signals for controlling the quantum bits 1 provided on the quantum bit substrate 30A are input to the input electrodes 60A. The control signals input to the input electrodes 60A are supplied to the control electrodes 21 provided on the quantum bit substrate 30A via the control wiring 46A. Similarly, control signals for controlling the quantum bits 1 provided on the quantum bit substrate 30B are input to the input electrodes 60B. The control signals input to the input electrodes 60B are supplied to the control electrodes 21 provided on the quantum bit substrate 30B via the control wiring 46B. Response signals indicating the states of the quantum bits 1 provided on each of the quantum bit substrates 30A and 30B are output from the output electrode 61 via the readout wiring 48 provided on the relay substrate 40A.

[0037] In this way, it is possible to access the quantum bits 1 provided on each of the quantum bit substrates 30A and 30B via the input electrodes 60A, 60B and the output electrode 61 provided on the relay substrate 40A. By providing the input electrodes 60A, 60B and the output electrode 61 in a portion of the relay substrate 40A that protrudes outward in the planar direction beyond the outer edge of the quantum bit substrate 30A, external access to the quantum bits 1 provided on the quantum bit substrates 30A and 30B becomes easy.

[0038] The relay substrate 40A and the quantum bit substrate 30B are joined to each other via a dummy joint portion 70 in a portion that protrudes outward in the planar direction beyond the outer edge of the quantum bit substrate 30A. The dummy joint portion 70 is for the purpose of mechanical connection between the substrates and is a joint portion that does not form an electrical connection. This makes it possible to suppress the risk of a decrease in the connectivity between the substrates due to the bending of each substrate or damage to the joint portion.

[0039] The input electrodes 60A, 60B and the output electrode 61 only need to be provided in a portion of the relay substrate 40A that protrudes outward in the planar direction beyond the outer edge of the quantum bit substrate 30A, and the arrangement of these electrodes can be determined as appropriate. Note that the input electrode 60A is an example of the "first access electrode" in the disclosed technology. The output electrode 61 is an example of the "second access electrode" in the disclosed technology.

[0040] Hereinafter, a method for manufacturing the quantum bit device 200 will be described. FIGS. 11A to 11H are cross-sectional views showing an example of a method for manufacturing the quantum bit substrate 30. First, a base material 32 of the quantum bit substrate 30 is prepared. As the base material 32, for example, a silicon substrate having a thickness of about 300 μm can be used (FIG. 11A). Next, a conductive film 80 having a thickness of about 100 nm is formed on both surfaces of the base material 32 by, for example, a sputtering method, plasma CVD (Chemical Vapor Deposition), or an ion plating method. For example, TiN can be used as the material of the conductive film 80 (FIG. 11B). Next, a resist mask (not shown) is formed on the surface of the conductive film 80, and the conductive film 80 is patterned by partially etching the conductive film 80 through this resist mask. Thereby, the resonator 2, the filter 3, the control electrode 21, and the connection electrode 24 are formed (FIG. 11C).

[0041] Next, a quantum bit 1 is formed on the surface of the base material 32 (FIG. 11D). The superconducting Josephson element constituting the quantum bit 1 is formed, for example, by a process of forming a first electrode (not shown) containing Al on the surface of the base material 32 by a vapor deposition method, a process of forming an extremely thin oxide film (not shown) having a thickness of about several nm on the surface of the first electrode using O2 gas, and a process of forming a second electrode (not shown) containing Al on the surface of the oxide film by a vapor deposition method. The patterning of the first electrode and the second electrode may be performed, for example, by a lift-off method using a patterned resist mask (not shown). In this case, the opening pattern of the resist mask is formed in a cross shape including a first straight portion along a first direction and a second straight portion along a second direction orthogonal to the first direction, and the first electrode may be formed in a portion corresponding to the first straight portion by performing vapor deposition while tilting with the first direction as the rotation axis. Subsequently, the second electrode may be formed in a portion corresponding to the second straight portion by performing vapor deposition while tilting with the second direction as the rotation axis. According to the above method, it becomes possible to pattern the first electrode and the second electrode with a single resist mask.

[0042] Next, a protective film 81 covering the surface of the quantum bit 1 is formed, for example, by a CVD method. For example, SiO2 can be used as the material of the protective film 81. Then, the protective film 81 is patterned using photolithography technology (Fig. 11E). Next, through holes 82 are formed at the formation positions of the connection electrodes 24 and the readout electrodes 23 of the base material 32, respectively, for example, by a Deep-RIE (Reactive Ion Etching) method (Fig. 11F). Next, a conductive film covering the inner wall of the through hole 82 and the periphery of the opening end of the through hole 82 is formed, for example, by a vapor deposition method. For example, Al can be used as the material of the conductive film. Then, the conductive film is patterned, for example, by a lift-off method. Thereby, the readout electrode 23 is formed (Fig. 11G). Next, the protective film 81 covering the quantum bit 1 is removed by etching using, for example, hydrofluoric acid vapor (Fig. 11H). Through the above steps, the quantum bit substrate 30 is completed.

[0043] The relay substrate 40A can be manufactured, for example, using a known manufacturing process of an LTCC multilayer substrate. The details of the manufacturing method of the relay substrate 40A will be omitted.

[0044] Hereinafter, the bonding of the quantum bit substrates 30A and 30B and the relay substrate 40A will be described with reference to Figs. 5A and 5B. Bumps 49 are respectively formed on the surfaces of the capacitor electrodes 43a, 43b, the control wiring electrode 45, and the readout wiring electrode 47 of the relay substrate 40A. For example, In can be used as the material of the bumps 49. The bumps 49 are patterned, for example, by a lift-off method.

[0045] Next, the qubit substrate 30A and the relay substrate 40A are joined via the bumps 49, and further, the qubit substrate 30B and the relay substrate 40A are joined via the bumps 49. Specifically, the connection electrode 24 of the qubit substrate 30A and the capacitor electrode 43a of the relay substrate 40A, the control electrode 21 of the qubit substrate 30A and the control wiring electrode 45 of the relay substrate 40A, and the readout electrode 23 of the qubit substrate 30A and the readout wiring electrode 47 of the relay substrate 40A are joined via the bumps 49, respectively. Thereby, the qubit substrate 30A and the relay substrate 40A are joined. Next, the connection electrode 24 of the qubit substrate 30B and the capacitor electrode 43b of the relay substrate 40A, the control electrode 21 of the qubit substrate 30B and the control wiring electrode 45 of the relay substrate 40A, and the readout electrode 23 of the qubit substrate 30B and the readout wiring electrode 47 of the relay substrate 40A are joined via the bumps 49, respectively. Thereby, the qubit substrate 30B and the relay substrate 40A are joined. The control electrode 21 of the qubit substrate 30A is connected to the control wiring 46A of the relay substrate 40A, and the control electrode 21 of the qubit substrate 30B is connected to the control wiring 46B of the relay substrate 40A. The readout electrodes 23 of the qubit substrates 30A and 30B are connected to the common readout wiring 48 of the relay substrate 40A. The qubit 1 provided on the qubit substrate 30A and the qubit 1 provided on the qubit substrate 30B are connected to each other via the capacitor 41a provided on the relay substrate 40A.

[0046] For example, an ultrasonic bonding method can be used for joining between the electrodes of the qubit substrates 30A and 30B and the relay substrate 40A. Note that the adjacent substrates may be joined together in a lump with the relay substrate 40A sandwiched between the qubit substrate 30A and the qubit substrate 30B.

[0047] FIG. 12 is a cross-sectional view showing an example of the configuration of a qubit device 200 in which the number of stacked qubit substrates is increased. FIG. 12 illustrates a configuration including four qubit substrates 30A, 30B, 30C, 30D and relay substrates 40A, 40B, 40C respectively provided between these qubit substrates.

[0048] The relay substrate 40C has control wirings 46A, 46B, and a readout wiring 48, similar to the relay substrate 40A. The control wiring 46A of the relay substrate 40C is connected to the control electrode 21 of the qubit substrate 30C, and the control wiring 46B of the relay substrate 40C is connected to the control electrode 21 of the qubit substrate 30D. The readout wiring 48 of the relay substrate 40C is connected to both the readout electrode 23 of the qubit substrate 30C and the readout electrode 23 of the qubit substrate 30D.

[0049] The relay substrate 40B is used for joining a first set including the qubit substrate 30A, the relay substrate 40A, and the qubit substrate 30B, and a second set including the qubit substrate 30C, the relay substrate 40C, and the qubit substrate 30D. The relay substrate 40B has capacitor electrodes 43a, 43b. The capacitor electrode 43a of the relay substrate 40B is connected to the connection electrode 24 of the qubit substrate 30B. The capacitor electrode 43b of the relay substrate 40B is connected to the connection electrode 24 of the qubit substrate 30C. Thereby, among the qubits 1 provided on the qubit substrates 30B and 30C, those adjacent in the stacking direction are connected to each other via the capacitor 41a provided on the relay substrate 40B.

[0050] As described above, the qubit device 200 according to the embodiment of the disclosed technology includes the qubit substrate 30A, the qubit substrate 30B, and the relay substrate 40A provided between these substrates. The qubit substrates 30A and 30B each have a qubit 1, a control electrode 21, and a readout electrode 23. The relay substrate 40A has a control wiring 46A through which a control signal for controlling the qubit 1 provided on the qubit substrate 30A is transmitted. The relay substrate 40A has a readout wiring 48 connected to both the readout electrode 23 of the qubit substrate 30A and the readout electrode 23 of the qubit substrate 30B. The relay substrate 40A has input electrodes 60A and 60B respectively connected to the control wirings 46A and 46B, and an output electrode 61 connected to the readout wiring 48.

[0051] According to the quantum bit device 200 related to the disclosed technology, on one readout wiring 48, a response signal indicating the state of the quantum bit 1 provided on the quantum bit substrate 30A and a response signal indicating the state of the quantum bit 1 provided on the quantum bit substrate 30B are multiplexed and transmitted. Thereby, it becomes possible to suppress the number of wirings that increases with the multi-bitization of quantum bits.

[0052] Also, the relay substrate 40A has a capacitor 41a for capacitively coupling the quantum bit 1 provided on the quantum bit substrate 30A and the quantum bit 1 provided on the quantum bit substrate 30B. The quantum bits 1 provided on the different quantum bit substrates 30A and 30B are connected to each other via the capacitor 41a provided on the relay substrate 40A. That is, the quantum bits provided on each quantum bit substrate are connected to other quantum bits adjacent not only in the plane direction of the quantum bit substrate but also in the stacking direction of the substrates via capacitors. Thereby, it becomes possible to achieve multi-bitization without being restricted by the layout of the quantum bit substrate. As a result, it is possible to increase the combination of quantum bit gates including a plurality of quantum bits, and it becomes possible to improve the computing performance in the quantum device.

[0053] Here, FIGS. 13A, 13B, 13C, and 13D are plan views showing an example of the layout of the quantum bit 1 and the readout electrode 23 when the quantum bits are arranged on a plane. FIG. 13A shows a layout in which the quantum bits 1 are arranged at the vertices of a triangle and the readout electrode 23 is arranged at the center of the triangle. According to this layout, the degree is 6 and the multiplicity is 3. FIG. 13B shows a layout in which the quantum bits 1 are arranged at the vertices of a quadrilateral and the readout electrode 23 is arranged at the center of the quadrilateral. According to this layout, the degree is 4 and the multiplicity is 4. FIG. 13C shows a layout in which the quantum bits 1 are arranged at the vertices of a hexagon and the readout electrode 23 is arranged at the center of the hexagon. According to this layout, the degree is 3 and the multiplicity is 6. FIG. 13D shows a layout in which the quantum bits 1 are arranged at the vertices of an octagon and the readout electrode 23 is arranged at the center of the octagon. According to this layout, the degree is 3 and the multiplicity is 8.

[0054] The degree is the number of other quantum bits to which one quantum bit is coupled. The larger the degree, the more quantum gates can be formed starting from one quantum bit. The multiplicity is the number of quantum bits connected to one readout wiring. The larger the multiplicity, the more possible it is to suppress the number of readout wirings. When the quantum bits are arranged on a plane, the number of quantum bits surrounding the readout electrode 23 becomes the multiplicity. When the multiplicity is increased, the degree tends to decrease. That is, when the quantum bits 1 are arranged on a plane, it is difficult to increase both the degree and the multiplicity.

[0055] On the other hand, according to the quantum bit device 200 according to the embodiment of the disclosed technology, as shown in FIG. 14, the degree can be 6 and the multiplicity can be 8, and it is possible to increase both the degree and the multiplicity. However, connecting the upper and lower quantum bits via the coupling elements of the relay substrate is not essential in the present invention, and a structure with a degree of 4 and a multiplicity of 8 may be adopted as in other embodiments described later.

[0056] FIG. 15 is a diagram showing an example of the relationship of the arrangement of the unit structures 101 formed on each qubit substrate. As shown in FIG. 15, between qubit substrates adjacent to each other with the relay substrate interposed therebetween, the unit structures 101 may be arranged at positions shifted from each other in the planar direction. FIG. 15 exemplifies a configuration in which the unit structure 101 provided on the qubit substrate 30B is arranged at a position shifted in the planar direction with respect to the unit structures 101 respectively provided on the qubit substrates 30A and 30C. Thereby, between qubit substrates adjacent to each other with the relay substrate interposed therebetween, since the positions of the resonator 2, the filter 3, and the readout electrode 23 are shifted from each other, it becomes possible to suppress crosstalk.

[0057] In this case, it is preferable that the wiring lengths from each of the readout electrodes 23 connected to the common readout wiring 48 to the output electrode 61 are the same. In the example shown in FIG. 15, the wiring lengths from each of the readout electrodes 23 provided on the qubit substrates 30A and 30B to the output electrode 61 via the common readout wiring 48 are made equal to each other. Thereby, it becomes possible to make the attenuation amounts and phases of the response signals read from each qubit 1 uniform.

[0058] FIG. 16 is a plan view showing the configuration of a qubit device 200A according to another embodiment of the disclosed technology. FIG. 17 is a cross-sectional view taken along line 17-17 in FIG. 16. In FIG. 17, the readout wiring and the control wiring provided on the relay substrate 40A are omitted. The qubit device 200A has a plurality of qubit substrates 30 including the qubit substrates 30A and 30X provided on one surface side of the relay substrate 40A. Further, the qubit device 200B has a plurality of qubit substrates 30 including the qubit substrates 30B and 30Y provided on the other surface side of the relay substrate 40A.

[0059] The relay substrate 40A has a plurality of capacitors 90 provided on one surface and the other surface. The capacitors 90 form capacitive coupling between qubits provided on different qubit substrates mounted on the same surface of the relay substrate 40A. For example, the capacitors 90 provided on one surface of the relay substrate 40A form capacitive coupling between the qubits 1 provided on the qubit substrates 30A and 30X, respectively. The capacitors 90 provided on the other surface of the relay substrate 40A form capacitive coupling between the qubits 1 provided on the qubit substrates 30B and 30Y, respectively. According to the qubit device 200B according to the present embodiment, since a plurality of qubit substrates 30 are juxtaposed with respect to one relay substrate 40A, further multi-bit expansion can be achieved.

[0060] FIGS. 18A and 18B are cross-sectional views showing an example of the configuration of a qubit device 200B according to another embodiment of the disclosed technology. FIG. 18A shows a disassembled view of the qubit substrate and the relay substrate, and FIG. 18B shows a state in which the qubit substrate and the relay substrate are joined. The qubit device 200B has qubit substrates 30A, 30B and relay substrates 40A, 40B. The relay substrate 40A is provided between the qubit substrate 30A and the qubit substrate 30B, and the qubit substrate 30B is provided between the relay substrate 40A and the relay substrate 40B.

[0061] In the qubit device 200 shown in FIGS. 5A and 5B, both the control wiring 46A connected to the control electrode 21 of the qubit substrate 30A and the control wiring 46B connected to the control electrode 21 of the qubit substrate 30B were provided on the relay substrate 40A. On the other hand, in the qubit device 200B according to the present embodiment, the control wiring 46A is provided on the relay substrate 40A, and the control wiring 46B is provided on the relay substrate 40B. In this way, by dispersing and arranging the control wirings 46A and 46B connected to the control electrodes 21 of the different qubit substrates 30A and 30B on the different relay substrates 40A and 40B, the wiring density on one relay substrate can be suppressed, and the design and manufacture of the relay substrate can be facilitated. Note that the relay substrate 40B is an example of the "second relay substrate" in the disclosed technology.

[0062] FIG. 19A is a perspective view schematically showing the configuration of a qubit device 200C according to another embodiment of the disclosed technology, and FIG. 19B is a cross-sectional view of the qubit device 200C. In FIG. 19B, the readout wiring and the control wiring provided on the relay substrate 40A are omitted. The qubit device 200C is different from the above-described qubit device 200A (see FIGS. 16 and 17) in that it does not have a coupling element that connects adjacent qubits in the stacking direction. According to the qubit device 200C, the degree can be 4 and the multiplicity can be 8, and it is possible to increase only the multiplicity without increasing both the degree and the multiplicity.

[0063] Regarding the above embodiments, the following additional remarks are further disclosed. (Additional Remark 1) A qubit device (200, FIG. 5A) including a first qubit substrate (30A, FIG. 5A), a second qubit substrate (30B, FIG. 5A), and a first relay substrate (40A, FIG. 5A) provided between the first qubit substrate and the second qubit substrate, The first qubit substrate has a first qubit (1, FIG. 5A), a first control electrode (21, FIG. 5A), and a first readout electrode (23, FIG. 5A). The second qubit substrate has a second qubit (1, FIG. 5A), a second control electrode (21, FIG. 5A), and a second readout electrode (23, FIG. 5A), The first relay substrate, A first control wiring (46A, FIG. 5A) connected to the first control electrode and through which a control signal for controlling the first qubit is transmitted; A wiring connected to both the first readout electrode and the second readout electrode, and through which a response signal indicating the state of the first qubit or the second qubit is transmitted (readout wiring 48, FIG. 5A); A first access electrode (60A, FIG. 10) connected to the first control wiring; A second access electrode (61, FIG. 9) connected to the readout wiring; A qubit device having the above.

[0064] (Appendix 2) The first relay substrate has a capacitor (41, FIG. 5A) for capacitively coupling the first qubit and the second qubit. The qubit device according to Appendix 1.

[0065] (Appendix 3) The size of the first relay substrate is larger than the size of the first qubit substrate. The qubit device according to Appendix 1 or Appendix 2.

[0066] (Appendix 4) The first access electrode and the second access electrode are provided at a portion of the first relay substrate that protrudes outward in the planar direction beyond the outer edge of the first qubit substrate. The qubit device according to Appendix 3.

[0067] (Appendix 5) The first readout electrode and the second readout electrode are arranged at positions shifted from each other in the planar direction. The qubit device according to any one of Appendices 1 to 4.

[0068] (Appendix 6) The wiring length from the first readout electrode to the second access electrode is the same as the wiring length from the second readout electrode to the second access electrode. The quantum bit device according to any one of Appendices 1 to 5.

[0069] (Appendix 7) The first relay substrate has a capacitor for forming a capacitive coupling between quantum bits provided on different quantum bit substrates mounted on the same surface of the first relay substrate. The quantum bit device according to any one of Appendices 1 to 6.

[0070] (Appendix 8) The first relay substrate further includes a second control wiring (46B, FIG. 5A) connected to the second control electrode and through which a control signal for controlling the second quantum bit is transmitted. The quantum bit device according to any one of Appendices 1 to 7.

[0071] (Appendix 9) The quantum bit device further includes a second relay substrate (40B, FIG. 18A) having a second control wiring (46B, FIG. 5A) connected to the second control electrode and through which a control signal for controlling the second quantum bit is transmitted. The quantum bit device according to any one of Appendices 1 to 7.

[0072] (Appendix 10) In a quantum bit device including a first quantum bit substrate, a second quantum bit substrate, and a first relay substrate having a first surface and a second surface provided between the first quantum bit substrate and the second quantum bit substrate, a step of bonding the first surface of the first quantum bit substrate and the first relay substrate; a step of bonding the second surface of the second quantum bit substrate and the first relay substrate; and the first quantum bit substrate has a first quantum bit, a first control electrode, and a first readout electrode. The second qubit substrate has a second qubit, a second control electrode, and a second readout electrode, The first relay substrate, A first control wiring through which a control signal for controlling the first qubit is transmitted, A readout wiring through which a response signal indicating the state of the first qubit or the second qubit is transmitted, A first access electrode connected to the first control wiring, A second access electrode connected to the readout wiring, And has, Connecting the first control electrode and the first control wiring, Connecting both the first readout electrode and the second readout electrode to the readout wiring Manufacturing method.

[0073] (Appendix 11) The first relay substrate has a capacitor for capacitively coupling the first qubit and the second qubit The manufacturing method according to Appendix 10.

[0074] (Appendix 12) The size of the first relay substrate is larger than the size of the first qubit substrate The manufacturing method according to Appendix 10 or Appendix 11.

[0075] (Appendix 13) The first access electrode and the second access electrode are provided in a portion of the first relay substrate that protrudes outward in the plane direction beyond the outer edge of the first qubit substrate The manufacturing method according to Appendix 12.

[0076] (Appendix 14) The first readout electrode and the second readout electrode are arranged at positions shifted from each other in the plane direction The manufacturing method according to any one of Appendix 10 to Appendix 13.

[0077] (Appendix 15) The wiring length from the first read electrode to the second access electrode is the same as the wiring length from the second read electrode to the second access electrode. The manufacturing method according to any one of Appendices 10 to 14.

[0078] (Appendix 16) The first relay substrate has a capacitor for forming a capacitive coupling between qubits provided on different qubit substrates mounted on the same surface of the first relay substrate. The manufacturing method according to any one of Appendices 10 to 15.

[0079] (Appendix 17) The first relay substrate further includes a second control wiring connected to the second control electrode and through which a control signal for controlling the second qubit is transmitted. The manufacturing method according to any one of Appendices 10 to 16.

[0080] (Appendix 18) It further has a second relay substrate having a second control wiring connected to the second control electrode and through which a control signal for controlling the second qubit is transmitted. The manufacturing method according to any one of Appendices 10 to 16.

Explanation of Reference Numerals

[0081] 1 Qubit 21 Control Electrode 23 Read Electrode 24 Connection Electrode 30, 30A, 30B, 30C, 30D Qubit Substrate 40A, 40B, 40C Relay Substrate 41 Coupling Element 46A, 46B Control Wiring 48 Read Wiring 60A, 60B Input Electrode 61 Output Electrode 70 Junction 90 Capacitor 200, 200A, 200B, 200C Qubit Device

Claims

1. A qubit device comprising a first qubit substrate, a second qubit substrate, and a first relay substrate provided between the first qubit substrate and the second qubit substrate, wherein the first qubit substrate has a first qubit, a first control electrode, and a first readout electrode, the second qubit substrate has a second qubit, a second control electrode, and a second readout electrode, and the first relay substrate has a first control wiring connected to the first control electrode and through which a control signal for controlling the first qubit is transmitted, a readout wiring connected to both the first readout electrode and the second readout electrode and through which a response signal indicating the state of the first qubit or the second qubit is transmitted, a first access electrode connected to the first control wiring, and a second access electrode connected to the readout wiring. A qubit device having the above components.

2. The first relay substrate has a capacitor for capacitively coupling the first qubit and the second qubit. The qubit device according to claim 1.

3. The size of the first relay substrate is larger than the size of the first qubit substrate. The qubit device according to claim 1.

4. The first access electrode and the second access electrode are provided at a portion of the first relay substrate that protrudes outward in the planar direction beyond the outer edge of the first qubit substrate. The qubit device according to claim 3.

5. The first readout electrode and the second readout electrode are arranged at positions shifted from each other in the planar direction. The qubit device according to claim 1.

6. The wiring length from the first readout electrode to the second access electrode is the same as the wiring length from the second readout electrode to the second access electrode. The qubit device according to claim 1.

7. The first relay substrate has a capacitor for forming a capacitive coupling between qubits provided on different qubit substrates mounted on the same surface of the first relay substrate. The qubit device according to claim 1.

8. The first relay substrate further includes a second control wiring connected to the second control electrode and through which a control signal for controlling the second qubit is transmitted. The qubit device according to claim 1.

9. It further has a second relay substrate having a second control wiring connected to the second control electrode and through which a control signal for controlling the second qubit is transmitted. The qubit device according to claim 1.

10. In a qubit device including a first qubit substrate, a second qubit substrate, and a first relay substrate having a first surface and a second surface provided between the first qubit substrate and the second qubit substrate, a step of bonding the first surface of the first qubit substrate and the first relay substrate; a step of bonding the second surface of the second qubit substrate and the first relay substrate; having the first qubit substrate has a first qubit, a first control electrode, and a first readout electrode; the second qubit substrate has a second qubit, a second control electrode, and a second readout electrode; the first relay substrate has a first control wiring through which a control signal for controlling the first qubit is transmitted; a readout wiring through which a response signal indicating the state of the first qubit or the second qubit is transmitted; a first access electrode connected to the first control wiring; a second access electrode connected to the readout wiring; having connecting the first control electrode and the first control wiring; connecting both the first readout electrode and the second readout electrode to the readout wiring Manufacturing method.

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